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authorMark Rutland <mark.rutland@arm.com>2013-07-18 17:20:33 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2013-07-26 12:01:17 +0100
commit8fbac214e5c594a0c2fe78c14adf2cdbb1febc92 (patch)
tree0f331dcd30fb4110f10afe7cde11bc40b8f83ada /arch/arm/include/asm/virt.h
parentab8d46c0609843a83aef3f486365ca5e7c21d537 (diff)
downloadblackbird-op-linux-8fbac214e5c594a0c2fe78c14adf2cdbb1febc92.tar.gz
blackbird-op-linux-8fbac214e5c594a0c2fe78c14adf2cdbb1febc92.zip
ARM: 7787/1: virt: ensure visibility of __boot_cpu_mode
Secondary CPUs write to __boot_cpu_mode with caches disabled, and thus a cached value of __boot_cpu_mode may be incoherent with that in memory. This could lead to a failure to detect mismatched boot modes. This patch adds flushing to ensure that writes by secondaries to __boot_cpu_mode are made visible before we test against it. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Dave Martin <Dave.Martin@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Christoffer Dall <cdall@cs.columbia.edu> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include/asm/virt.h')
-rw-r--r--arch/arm/include/asm/virt.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h
index 50af92bac737..4371f45c5784 100644
--- a/arch/arm/include/asm/virt.h
+++ b/arch/arm/include/asm/virt.h
@@ -29,6 +29,7 @@
#define BOOT_CPU_MODE_MISMATCH PSR_N_BIT
#ifndef __ASSEMBLY__
+#include <asm/cacheflush.h>
#ifdef CONFIG_ARM_VIRT_EXT
/*
@@ -41,10 +42,21 @@
*/
extern int __boot_cpu_mode;
+static inline void sync_boot_mode(void)
+{
+ /*
+ * As secondaries write to __boot_cpu_mode with caches disabled, we
+ * must flush the corresponding cache entries to ensure the visibility
+ * of their writes.
+ */
+ sync_cache_r(&__boot_cpu_mode);
+}
+
void __hyp_set_vectors(unsigned long phys_vector_base);
unsigned long __hyp_get_vectors(void);
#else
#define __boot_cpu_mode (SVC_MODE)
+#define sync_boot_mode()
#endif
#ifndef ZIMAGE
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