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| author | Catalin Marinas <catalin.marinas@arm.com> | 2013-03-26 23:35:04 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2013-04-03 16:45:49 +0100 |
| commit | 93dc68876b608da041fe40ed39424b0fcd5aa2fb (patch) | |
| tree | dcd4dc84c5a0da7ce4c1581b3ee6f81fdb969765 /arch/arm/include/asm/tlbflush.h | |
| parent | 6e7aceeb7c70b9ebad79bcfe91fcf738826e8e6d (diff) | |
| download | blackbird-op-linux-93dc68876b608da041fe40ed39424b0fcd5aa2fb.tar.gz blackbird-op-linux-93dc68876b608da041fe40ed39424b0fcd5aa2fb.zip | |
ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)
On Cortex-A15 (r0p0..r3p2) the TLBI/DSB are not adequately shooting down
all use of the old entries. This patch implements the erratum workaround
which consists of:
1. Dummy TLBIMVAIS and DSB on the CPU doing the TLBI operation.
2. Send IPI to the CPUs that are running the same mm (and ASID) as the
one being invalidated (or all the online CPUs for global pages).
3. CPU receiving the IPI executes a DMB and CLREX (part of the exception
return code already).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include/asm/tlbflush.h')
| -rw-r--r-- | arch/arm/include/asm/tlbflush.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 4db8c8820f0d..9e9c041358ca 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -450,6 +450,21 @@ static inline void local_flush_bp_all(void) isb(); } +#ifdef CONFIG_ARM_ERRATA_798181 +static inline void dummy_flush_tlb_a15_erratum(void) +{ + /* + * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0. + */ + asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); + dsb(); +} +#else +static inline void dummy_flush_tlb_a15_erratum(void) +{ +} +#endif + /* * flush_pmd_entry * |
