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| author | Will Deacon <will.deacon@arm.com> | 2015-03-06 11:54:09 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2015-03-24 15:07:57 +0000 |
| commit | 9fd85eb502a78bd812db58bd1f668b2a06ee30a5 (patch) | |
| tree | 81e8e9ea897a7ab9aa32e7bbfc56ca62423b119e /arch/arm/configs/sama5_defconfig | |
| parent | e429817b401f095ac483fcb02524b01faf45dad6 (diff) | |
| download | blackbird-op-linux-9fd85eb502a78bd812db58bd1f668b2a06ee30a5.tar.gz blackbird-op-linux-9fd85eb502a78bd812db58bd1f668b2a06ee30a5.zip | |
ARM: pmu: add support for interrupt-affinity property
Historically, the PMU devicetree bindings have expected SPIs to be
listed in order of *logical* CPU number. This is problematic for
bootloaders, especially when the boot CPU (logical ID 0) isn't listed
first in the devicetree.
This patch adds a new optional property, interrupt-affinity, to the
PMU node which allows the interrupt affinity to be described using
a list of phandled to CPU nodes, with each entry in the list
corresponding to the SPI at the same index in the interrupts property.
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/configs/sama5_defconfig')
0 files changed, 0 insertions, 0 deletions
