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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-12-04 16:13:29 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-12-14 19:21:42 +0000
commitff2e27ae0b17f53a6a289c87d325f706598f3788 (patch)
tree1288f491bce11b3d8a6d48604fd00d68bea6eb98 /arch/arm/common
parent384895330e0f3954d9478fd0853145f9c169df12 (diff)
downloadblackbird-op-linux-ff2e27ae0b17f53a6a289c87d325f706598f3788.tar.gz
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ARM: GIC: consolidate gic_cpu_base_addr to common GIC code
Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/common')
-rw-r--r--arch/arm/common/gic.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index dd0d18d560ac..9105d48c02de 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -35,6 +35,9 @@
static DEFINE_SPINLOCK(irq_controller_lock);
+/* Address of GIC 0 CPU interface */
+void __iomem *gic_cpu_base_addr;
+
struct gic_chip_data {
unsigned int irq_offset;
void __iomem *dist_base;
@@ -317,6 +320,8 @@ static void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
void __iomem *dist_base, void __iomem *cpu_base)
{
+ if (gic_nr == 0)
+ gic_cpu_base_addr = cpu_base;
gic_dist_init(gic_nr, dist_base, irq_start);
gic_cpu_init(gic_nr, cpu_base);
}
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