diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2015-10-01 19:57:49 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2015-10-07 10:55:54 +0100 |
| commit | 79d05ec96a768d37781f7c98489eea58de3e2348 (patch) | |
| tree | 07e685f0f24d7231824310e9926e488b13b6d9c5 /arch/arm/boot/dts/sun8i-a23-a33.dtsi | |
| parent | a2f1a680115c527972ead1b89de4a31176d3c2c6 (diff) | |
| download | blackbird-op-linux-79d05ec96a768d37781f7c98489eea58de3e2348.tar.gz blackbird-op-linux-79d05ec96a768d37781f7c98489eea58de3e2348.zip | |
ARM: dts: sun8i: Add Reduced Serial Bus controller device node to A23/A33 dtsi
This patch adds a device node for the Reduced Serial Bus (RSB)
controller and the defacto pinmux setting to the A23/A33 dtsi.
Since there is only one possible pinmux setting for RSB, just
set it in the dtsi.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-a23-a33.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun8i-a23-a33.dtsi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 04bccad977ee..828aaf52c342 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -651,6 +651,13 @@ #size-cells = <0>; #gpio-cells = <3>; + r_rsb_pins: r_rsb { + allwinner,pins = "PL0", "PL1"; + allwinner,function = "s_rsb"; + allwinner,drive = <SUN4I_PINCTRL_20_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + r_uart_pins_a: r_uart@0 { allwinner,pins = "PL2", "PL3"; allwinner,function = "s_uart"; @@ -658,5 +665,19 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; }; + + r_rsb: rsb@01f03400 { + compatible = "allwinner,sun8i-a23-rsb"; + reg = <0x01f03400 0x400>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&apb0_gates 3>; + clock-frequency = <3000000>; + resets = <&apb0_rst 3>; + pinctrl-names = "default"; + pinctrl-0 = <&r_rsb_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; }; }; |
