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author | Stephen Boyd <sboyd@codeaurora.org> | 2014-01-16 17:25:03 -0800 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2014-01-31 14:58:51 -0800 |
commit | 3933d267835c8b0fd2892e2b851f9b2a3991f6c8 (patch) | |
tree | f50b1a62b772e3a125cda4599dddabbfdf04456b /arch/arm/boot/dts/qcom-msm8974.dtsi | |
parent | de70af494c468c107eedf90090eb74d6ccf30c4c (diff) | |
download | blackbird-op-linux-3933d267835c8b0fd2892e2b851f9b2a3991f6c8.tar.gz blackbird-op-linux-3933d267835c8b0fd2892e2b851f9b2a3991f6c8.zip |
ARM: dts: msm: Add clock controller nodes and hook into uart
Add the necessary DT nodes to probe the clock controllers on MSM
devices as well as hook up the uart nodes to the clock
controllers. This should allow us to boot to a serial console on
all DT enabled MSM platforms.
Cc: David Brown <davidb@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/qcom-msm8974.dtsi')
-rw-r--r-- | arch/arm/boot/dts/qcom-msm8974.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 6ac94967d2d3..9e5dadb101eb 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -2,6 +2,8 @@ #include "skeleton.dtsi" +#include <dt-bindings/clock/qcom,gcc-msm8974.h> + / { model = "Qualcomm MSM8974"; compatible = "qcom,msm8974"; @@ -93,5 +95,27 @@ compatible = "qcom,pshold"; reg = <0xfc4ab000 0x4>; }; + + gcc: clock-controller@fc400000 { + compatible = "qcom,gcc-msm8974"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0xfc400000 0x4000>; + }; + + mmcc: clock-controller@fd8c0000 { + compatible = "qcom,mmcc-msm8974"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0xfd8c0000 0x6000>; + }; + + serial@f991e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991e000 0x1000>; + interrupts = <0 108 0x0>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + }; }; }; |