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authorBeniamino Galvani <b.galvani@gmail.com>2014-11-18 15:30:35 +0100
committerCarlo Caione <carlo@caione.org>2014-11-18 16:36:14 +0100
commit550ab390d7c60b85cd896cf03a34f8eae8a65d69 (patch)
treef880749d8051fb56356de52ba330a4194a5c546d /arch/arm/boot/dts/meson6.dtsi
parentaeff05a39a5a9b9a41fe96ef4f4246cef5fb2f4a (diff)
downloadblackbird-op-linux-550ab390d7c60b85cd896cf03a34f8eae8a65d69.tar.gz
blackbird-op-linux-550ab390d7c60b85cd896cf03a34f8eae8a65d69.zip
ARM: meson: DTS: enable L2 cache
This enables the L2 cache controller available in Amlogic SoCs. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Carlo Caione <carlo@caione.org>
Diffstat (limited to 'arch/arm/boot/dts/meson6.dtsi')
-rw-r--r--arch/arm/boot/dts/meson6.dtsi2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index 4ba49127779f..8b33be15af94 100644
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -60,12 +60,14 @@
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
reg = <0x200>;
};
cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
reg = <0x201>;
};
};
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