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| author | Shawn Guo <shawn.guo@linaro.org> | 2013-07-11 13:58:36 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-08-22 23:29:11 +0800 |
| commit | c56009b2f6134e5943a03cf26e4d7fce9745d56b (patch) | |
| tree | bd792350bb8bea866bf45c36ec18df64e8c9b5d2 /arch/arm/boot/dts/imx6q-arm2.dts | |
| parent | 51056d9cff64ba1347a20476c840e943576f0283 (diff) | |
| download | blackbird-op-linux-c56009b2f6134e5943a03cf26e4d7fce9745d56b.tar.gz blackbird-op-linux-c56009b2f6134e5943a03cf26e4d7fce9745d56b.zip | |
ARM: dts: imx: share pad macro names between imx6q and imx6dl
The imx6q and imx6dl are two pin-to-pin compatible SoCs. The same board
design can work with either chip plugged into the socket, e.g. sabresd
and sabreauto boards.
We currently define pin groups in imx6q.dtsi and imx6dl.dtsi
respectively because the pad macro names are different between two
chips. This brings a maintenance burden on having the same label point
to the same pin group defined in two places.
The patch replaces prefix MX6Q_ and MX6DL_ with MX6QDL_ for both SoCs
pad macro names. Then the pin groups becomes completely common between
imx6q and imx6dl and can just be moved into imx6qdl.dtsi, so that the
long term maintenance of imx6q/dt pin settings becomes easier.
Unfortunately, the change brings some dramatic diff stat, but it's all
about DTS file, and the ultimate net diff stat is good.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q-arm2.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx6q-arm2.dts | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index e7e3b566cce9..9b17393f24ec 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -57,7 +57,7 @@ hog { pinctrl_hog: hoggrp { fsl,pins = < - MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000 + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 >; }; }; @@ -65,8 +65,8 @@ arm2 { pinctrl_usdhc3_arm2: usdhc3grp-arm2 { fsl,pins = < - MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 - MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 >; }; }; |
