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authorArnd Bergmann <arnd@arndb.de>2011-09-20 22:15:55 +0200
committerArnd Bergmann <arnd@arndb.de>2011-09-20 22:15:55 +0200
commitda1c5afee092a2b51136ac3bf20c68bfff2924be (patch)
treefa71b9e3af25c870012a22e4cb72547f9aafcfd0 /arch/arm/Kconfig
parent1fdb4888e45f1413972a8e9da55f3ffc08b9abcb (diff)
parent4c59de052e7167a3bcf3f32c5ea4c9a5ef07386a (diff)
downloadblackbird-op-linux-da1c5afee092a2b51136ac3bf20c68bfff2924be.tar.gz
blackbird-op-linux-da1c5afee092a2b51136ac3bf20c68bfff2924be.zip
Merge branch 'samsung/cleanup' into next/cleanup
Diffstat (limited to 'arch/arm/Kconfig')
-rw-r--r--arch/arm/Kconfig12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6c7eb9c080fd..9f1ff5c94bef 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1272,6 +1272,18 @@ config ARM_ERRATA_754327
This workaround defines cpu_relax() as smp_mb(), preventing correctly
written polling loops from denying visibility of updates to memory.
+config ARM_ERRATA_364296
+ bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
+ depends on CPU_V6 && !SMP
+ help
+ This options enables the workaround for the 364296 ARM1136
+ r0p2 erratum (possible cache data corruption with
+ hit-under-miss enabled). It sets the undocumented bit 31 in
+ the auxiliary control register and the FI bit in the control
+ register, thus disabling hit-under-miss without putting the
+ processor into full low interrupt latency mode. ARM11MPCore
+ is not affected.
+
endmenu
source "arch/arm/common/Kconfig"
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