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authorArnd Bergmann <arnd@arndb.de>2012-05-14 15:33:42 +0200
committerArnd Bergmann <arnd@arndb.de>2012-05-14 15:33:42 +0200
commitd2819f80d465672b09c2f4cb52303b7f951c4d0f (patch)
treeaa0262703e86b97ad1460c722e78d7233e24e3bb /Documentation
parent5df33a62c4a028d6fc7f2dcc159827d09b7334b8 (diff)
parent366695ff706669d40459174b1cbb78fca42f4e06 (diff)
downloadblackbird-op-linux-d2819f80d465672b09c2f4cb52303b7f951c4d0f.tar.gz
blackbird-op-linux-d2819f80d465672b09c2f4cb52303b7f951c4d0f.zip
Merge branch 'spear/pinctrl' into spear/clock
Conflicts: arch/arm/mach-spear3xx/Makefile arch/arm/mach-spear3xx/clock.c arch/arm/mach-spear3xx/include/mach/generic.h arch/arm/mach-spear6xx/clock.c arch/arm/plat-spear/Makefile drivers/pinctrl/core.c This resolves some annoying merge conflicts. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/arm/SPEAr/overview.txt13
-rw-r--r--Documentation/devicetree/bindings/arm/spear.txt18
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt95
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt1628
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt918
-rw-r--r--Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt132
-rw-r--r--Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt132
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt128
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt108
-rw-r--r--Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt5
-rw-r--r--Documentation/driver-model/devres.txt4
-rw-r--r--Documentation/pinctrl.txt94
12 files changed, 3221 insertions, 54 deletions
diff --git a/Documentation/arm/SPEAr/overview.txt b/Documentation/arm/SPEAr/overview.txt
index 253a35c6f782..28a9af953b9d 100644
--- a/Documentation/arm/SPEAr/overview.txt
+++ b/Documentation/arm/SPEAr/overview.txt
@@ -17,14 +17,14 @@ Introduction
SPEAr (Platform)
- SPEAr3XX (3XX SOC series, based on ARM9)
- SPEAr300 (SOC)
- - SPEAr300_EVB (Evaluation Board)
+ - SPEAr300 Evaluation Board
- SPEAr310 (SOC)
- - SPEAr310_EVB (Evaluation Board)
+ - SPEAr310 Evaluation Board
- SPEAr320 (SOC)
- - SPEAr320_EVB (Evaluation Board)
+ - SPEAr320 Evaluation Board
- SPEAr6XX (6XX SOC series, based on ARM9)
- SPEAr600 (SOC)
- - SPEAr600_EVB (Evaluation Board)
+ - SPEAr600 Evaluation Board
- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
- SPEAr1300 (SOC)
@@ -51,10 +51,11 @@ Introduction
Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
- mach-spear* also contains board specific files for each machine type.
+ mach-spear* doesn't contains board specific files as they fully support
+ Flattened Device Tree.
Document Author
---------------
- Viresh Kumar, (c) 2010 ST Microelectronics
+ Viresh Kumar <viresh.kumar@st.com>, (c) 2010-2012 ST Microelectronics
diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
index f8e54f092328..aa5f355cc947 100644
--- a/Documentation/devicetree/bindings/arm/spear.txt
+++ b/Documentation/devicetree/bindings/arm/spear.txt
@@ -6,3 +6,21 @@ Boards with the ST SPEAr600 SoC shall have the following properties:
Required root node property:
compatible = "st,spear600";
+
+Boards with the ST SPEAr300 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear300";
+
+Boards with the ST SPEAr310 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear310";
+
+Boards with the ST SPEAr320 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear320";
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
new file mode 100644
index 000000000000..ab19e6bc7d3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
@@ -0,0 +1,95 @@
+* Freescale IOMUX Controller (IOMUXC) for i.MX
+
+The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
+to share one PAD to several functional blocks. The sharing is done by
+multiplexing the PAD input/output signals. For each PAD there are up to
+8 muxing options (called ALT modes). Since different modules require
+different PAD settings (like pull up, keeper, etc) the IOMUXC controls
+also the PAD settings parameters.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Freescale IMX pin configuration node is a node of a group of pins which can be
+used for a specific device or function. This node represents both mux and config
+of the pins in that group. The 'mux' selects the function mode(also named mux
+mode) this pin can work on and the 'config' configures various pad settings
+such as pull-up, open drain, drive strength, etc.
+
+Required properties for iomux controller:
+- compatible: "fsl,<soc>-iomuxc"
+ Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
+
+Required properties for pin configuration node:
+- fsl,pins: two integers array, represents a group of pins mux and config
+ setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+ pin working on a specific function, CONFIG is the pad setting value like
+ pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid
+ pins and functions of each SoC.
+
+Bits used for CONFIG:
+NO_PAD_CTL(1 << 31): indicate this pin does not need config.
+
+SION(1 << 30): Software Input On Field.
+Force the selected mux mode input path no matter of MUX_MODE functionality.
+By default the input path is determined by functionality of the selected
+mux mode (regular).
+
+Other bits are used for PAD setting.
+Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
+of bits definitions.
+
+NOTE:
+Some requirements for using fsl,imx-pinctrl binding:
+1. We have pin function node defined under iomux controller node to represent
+ what pinmux functions this SoC supports.
+2. The pin configuration node intends to work on a specific function should
+ to be defined under that specific function node.
+ The function node's name should represent well about what function
+ this group of pins in this pin configuration node are working on.
+3. The driver can use the function node's name and pin configuration node's
+ name describe the pin function and group hierarchy.
+ For example, Linux IMX pinctrl driver takes the function node's name
+ as the function name and pin configuration node's name as group name to
+ create the map table.
+4. Each pin configuration node should have a phandle, devices can set pins
+ configurations by referring to the phandle of that pin configuration node.
+
+Examples:
+usdhc@0219c000 { /* uSDHC4 */
+ fsl,card-wired;
+ vmmc-supply = <&reg_3p3v>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4_1>;
+};
+
+iomuxc@020e0000 {
+ compatible = "fsl,imx6q-iomuxc";
+ reg = <0x020e0000 0x4000>;
+
+ /* shared pinctrl settings */
+ usdhc4 {
+ pinctrl_usdhc4_1: usdhc4grp-1 {
+ fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+ 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
+ 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+ 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+ 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+ 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+ 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
+ 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
+ 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
+ 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+ };
+ };
+ ....
+};
+Refer to the IOMUXC controller chapter in imx6q datasheet,
+0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
+80Ohm driver strength and Fast Slew Rate.
+User should refer to each SoC spec to set the correct value.
+
+TODO: when dtc macro support is available, we can change above raw data
+to dt macro which can get better readability in dts file.
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
new file mode 100644
index 000000000000..82b43f915857
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
@@ -0,0 +1,1628 @@
+* Freescale IMX6Q IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx6q-iomuxc"
+- fsl,pins: two integers array, represents a group of pins mux and config
+ setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+ pin working on a specific function, CONFIG is the pad setting value like
+ pull-up for this pin. Please refer to imx6q datasheet for the valid pad
+ config settings.
+
+CONFIG bits definition:
+PAD_CTL_HYS (1 << 16)
+PAD_CTL_PUS_100K_DOWN (0 << 14)
+PAD_CTL_PUS_47K_UP (1 << 14)
+PAD_CTL_PUS_100K_UP (2 << 14)
+PAD_CTL_PUS_22K_UP (3 << 14)
+PAD_CTL_PUE (1 << 13)
+PAD_CTL_PKE (1 << 12)
+PAD_CTL_ODE (1 << 11)
+PAD_CTL_SPEED_LOW (1 << 6)
+PAD_CTL_SPEED_MED (2 << 6)
+PAD_CTL_SPEED_HIGH (3 << 6)
+PAD_CTL_DSE_DISABLE (0 << 3)
+PAD_CTL_DSE_240ohm (1 << 3)
+PAD_CTL_DSE_120ohm (2 << 3)
+PAD_CTL_DSE_80ohm (3 << 3)
+PAD_CTL_DSE_60ohm (4 << 3)
+PAD_CTL_DSE_48ohm (5 << 3)
+PAD_CTL_DSE_40ohm (6 << 3)
+PAD_CTL_DSE_34ohm (7 << 3)
+PAD_CTL_SRE_FAST (1 << 0)
+PAD_CTL_SRE_SLOW (0 << 0)
+
+See below for available PIN_FUNC_ID for imx6q:
+MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 0
+MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 1
+MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 2
+MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS 3
+MX6Q_PAD_SD2_DAT1__KPP_COL_7 4
+MX6Q_PAD_SD2_DAT1__GPIO_1_14 5
+MX6Q_PAD_SD2_DAT1__CCM_WAIT 6
+MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 7
+MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 8
+MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 9
+MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 10
+MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD 11
+MX6Q_PAD_SD2_DAT2__KPP_ROW_6 12
+MX6Q_PAD_SD2_DAT2__GPIO_1_13 13
+MX6Q_PAD_SD2_DAT2__CCM_STOP 14
+MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 15
+MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 16
+MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 17
+MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD 18
+MX6Q_PAD_SD2_DAT0__KPP_ROW_7 19
+MX6Q_PAD_SD2_DAT0__GPIO_1_15 20
+MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT 21
+MX6Q_PAD_SD2_DAT0__TESTO_2 22
+MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA 23
+MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC 24
+MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK 25
+MX6Q_PAD_RGMII_TXC__GPIO_6_19 26
+MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 27
+MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT 28
+MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY 29
+MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 30
+MX6Q_PAD_RGMII_TD0__GPIO_6_20 31
+MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 32
+MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG 33
+MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 34
+MX6Q_PAD_RGMII_TD1__GPIO_6_21 35
+MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 36
+MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP 37
+MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA 38
+MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 39
+MX6Q_PAD_RGMII_TD2__GPIO_6_22 40
+MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 41
+MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP 42
+MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK 43
+MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 44
+MX6Q_PAD_RGMII_TD3__GPIO_6_23 45
+MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 46
+MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA 47
+MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 48
+MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 49
+MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 50
+MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY 51
+MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 52
+MX6Q_PAD_RGMII_RD0__GPIO_6_25 53
+MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 54
+MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE 55
+MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 56
+MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 57
+MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 58
+MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT 59
+MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL 60
+MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 61
+MX6Q_PAD_RGMII_RD1__GPIO_6_27 62
+MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 63
+MX6Q_PAD_RGMII_RD1__SJC_FAIL 64
+MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA 65
+MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 66
+MX6Q_PAD_RGMII_RD2__GPIO_6_28 67
+MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 68
+MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK 69
+MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 70
+MX6Q_PAD_RGMII_RD3__GPIO_6_29 71
+MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 72
+MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE 73
+MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC 74
+MX6Q_PAD_RGMII_RXC__GPIO_6_30 75
+MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 76
+MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 77
+MX6Q_PAD_EIM_A25__ECSPI4_SS1 78
+MX6Q_PAD_EIM_A25__ECSPI2_RDY 79
+MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 80
+MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 81
+MX6Q_PAD_EIM_A25__GPIO_5_2 82
+MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 83
+MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 84
+MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 85
+MX6Q_PAD_EIM_EB2__ECSPI1_SS0 86
+MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK 87
+MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 88
+MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 89
+MX6Q_PAD_EIM_EB2__GPIO_2_30 90
+MX6Q_PAD_EIM_EB2__I2C2_SCL 91
+MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 92
+MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 93
+MX6Q_PAD_EIM_D16__ECSPI1_SCLK 94
+MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 95
+MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 96
+MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 97
+MX6Q_PAD_EIM_D16__GPIO_3_16 98
+MX6Q_PAD_EIM_D16__I2C2_SDA 99
+MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 100
+MX6Q_PAD_EIM_D17__ECSPI1_MISO 101
+MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 102
+MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 103
+MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT 104
+MX6Q_PAD_EIM_D17__GPIO_3_17 105
+MX6Q_PAD_EIM_D17__I2C3_SCL 106
+MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 107
+MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 108
+MX6Q_PAD_EIM_D18__ECSPI1_MOSI 109
+MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 110
+MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 111
+MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 112
+MX6Q_PAD_EIM_D18__GPIO_3_18 113
+MX6Q_PAD_EIM_D18__I2C3_SDA 114
+MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 115
+MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 116
+MX6Q_PAD_EIM_D19__ECSPI1_SS1 117
+MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 118
+MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 119
+MX6Q_PAD_EIM_D19__UART1_CTS 120
+MX6Q_PAD_EIM_D19__GPIO_3_19 121
+MX6Q_PAD_EIM_D19__EPIT1_EPITO 122
+MX6Q_PAD_EIM_D19__PL301_PER1_HRESP 123
+MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 124
+MX6Q_PAD_EIM_D20__ECSPI4_SS0 125
+MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 126
+MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 127
+MX6Q_PAD_EIM_D20__UART1_RTS 128
+MX6Q_PAD_EIM_D20__GPIO_3_20 129
+MX6Q_PAD_EIM_D20__EPIT2_EPITO 130
+MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 131
+MX6Q_PAD_EIM_D21__ECSPI4_SCLK 132
+MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 133
+MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 134
+MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC 135
+MX6Q_PAD_EIM_D21__GPIO_3_21 136
+MX6Q_PAD_EIM_D21__I2C1_SCL 137
+MX6Q_PAD_EIM_D21__SPDIF_IN1 138
+MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 139
+MX6Q_PAD_EIM_D22__ECSPI4_MISO 140
+MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 141
+MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 142
+MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR 143
+MX6Q_PAD_EIM_D22__GPIO_3_22 144
+MX6Q_PAD_EIM_D22__SPDIF_OUT1 145
+MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE 146
+MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 147
+MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 148
+MX6Q_PAD_EIM_D23__UART3_CTS 149
+MX6Q_PAD_EIM_D23__UART1_DCD 150
+MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 151
+MX6Q_PAD_EIM_D23__GPIO_3_23 152
+MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 153
+MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 154
+MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 155
+MX6Q_PAD_EIM_EB3__ECSPI4_RDY 156
+MX6Q_PAD_EIM_EB3__UART3_RTS 157
+MX6Q_PAD_EIM_EB3__UART1_RI 158
+MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 159
+MX6Q_PAD_EIM_EB3__GPIO_2_31 160
+MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 161
+MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 162
+MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 163
+MX6Q_PAD_EIM_D24__ECSPI4_SS2 164
+MX6Q_PAD_EIM_D24__UART3_TXD 165
+MX6Q_PAD_EIM_D24__ECSPI1_SS2 166
+MX6Q_PAD_EIM_D24__ECSPI2_SS2 167
+MX6Q_PAD_EIM_D24__GPIO_3_24 168
+MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS 169
+MX6Q_PAD_EIM_D24__UART1_DTR 170
+MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 171
+MX6Q_PAD_EIM_D25__ECSPI4_SS3 172
+MX6Q_PAD_EIM_D25__UART3_RXD 173
+MX6Q_PAD_EIM_D25__ECSPI1_SS3 174
+MX6Q_PAD_EIM_D25__ECSPI2_SS3 175
+MX6Q_PAD_EIM_D25__GPIO_3_25 176
+MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC 177
+MX6Q_PAD_EIM_D25__UART1_DSR 178
+MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 179
+MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 180
+MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 181
+MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 182
+MX6Q_PAD_EIM_D26__UART2_TXD 183
+MX6Q_PAD_EIM_D26__GPIO_3_26 184
+MX6Q_PAD_EIM_D26__IPU1_SISG_2 185
+MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 186
+MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 187
+MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 188
+MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 189
+MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 190
+MX6Q_PAD_EIM_D27__UART2_RXD 191
+MX6Q_PAD_EIM_D27__GPIO_3_27 192
+MX6Q_PAD_EIM_D27__IPU1_SISG_3 193
+MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 194
+MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 195
+MX6Q_PAD_EIM_D28__I2C1_SDA 196
+MX6Q_PAD_EIM_D28__ECSPI4_MOSI 197
+MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 198
+MX6Q_PAD_EIM_D28__UART2_CTS 199
+MX6Q_PAD_EIM_D28__GPIO_3_28 200
+MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 201
+MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 202
+MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 203
+MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 204
+MX6Q_PAD_EIM_D29__ECSPI4_SS0 205
+MX6Q_PAD_EIM_D29__UART2_RTS 206
+MX6Q_PAD_EIM_D29__GPIO_3_29 207
+MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 208
+MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 209
+MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 210
+MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 211
+MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 212
+MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 213
+MX6Q_PAD_EIM_D30__UART3_CTS 214
+MX6Q_PAD_EIM_D30__GPIO_3_30 215
+MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC 216
+MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 217
+MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 218
+MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 219
+MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 220
+MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 221
+MX6Q_PAD_EIM_D31__UART3_RTS 222
+MX6Q_PAD_EIM_D31__GPIO_3_31 223
+MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR 224
+MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 225
+MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 226
+MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 227
+MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 228
+MX6Q_PAD_EIM_A24__IPU2_SISG_2 229
+MX6Q_PAD_EIM_A24__IPU1_SISG_2 230
+MX6Q_PAD_EIM_A24__GPIO_5_4 231
+MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 232
+MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 233
+MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 234
+MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 235
+MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 236
+MX6Q_PAD_EIM_A23__IPU2_SISG_3 237
+MX6Q_PAD_EIM_A23__IPU1_SISG_3 238
+MX6Q_PAD_EIM_A23__GPIO_6_6 239
+MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 240
+MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 241
+MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 242
+MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 243
+MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 244
+MX6Q_PAD_EIM_A22__GPIO_2_16 245
+MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 246
+MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 247
+MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 248
+MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 249
+MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 250
+MX6Q_PAD_EIM_A21__RESERVED_RESERVED 251
+MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 252
+MX6Q_PAD_EIM_A21__GPIO_2_17 253
+MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 254
+MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 255
+MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 256
+MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 257
+MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 258
+MX6Q_PAD_EIM_A20__RESERVED_RESERVED 259
+MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 260
+MX6Q_PAD_EIM_A20__GPIO_2_18 261
+MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 262
+MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 263
+MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 264
+MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 265
+MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 266
+MX6Q_PAD_EIM_A19__RESERVED_RESERVED 267
+MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 268
+MX6Q_PAD_EIM_A19__GPIO_2_19 269
+MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 270
+MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 271
+MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 272
+MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 273
+MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 274
+MX6Q_PAD_EIM_A18__RESERVED_RESERVED 275
+MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 276
+MX6Q_PAD_EIM_A18__GPIO_2_20 277
+MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 278
+MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 279
+MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 280
+MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 281
+MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 282
+MX6Q_PAD_EIM_A17__RESERVED_RESERVED 283
+MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 284
+MX6Q_PAD_EIM_A17__GPIO_2_21 285
+MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 286
+MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 287
+MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 288
+MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 289
+MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 290
+MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 291
+MX6Q_PAD_EIM_A16__GPIO_2_22 292
+MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 293
+MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 294
+MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 295
+MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 296
+MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 297
+MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 298
+MX6Q_PAD_EIM_CS0__GPIO_2_23 299
+MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 300
+MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 301
+MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 302
+MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 303
+MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 304
+MX6Q_PAD_EIM_CS1__GPIO_2_24 305
+MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 306
+MX6Q_PAD_EIM_OE__WEIM_WEIM_OE 307
+MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 308
+MX6Q_PAD_EIM_OE__ECSPI2_MISO 309
+MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 310
+MX6Q_PAD_EIM_OE__GPIO_2_25 311
+MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 312
+MX6Q_PAD_EIM_RW__WEIM_WEIM_RW 313
+MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 314
+MX6Q_PAD_EIM_RW__ECSPI2_SS0 315
+MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 316
+MX6Q_PAD_EIM_RW__GPIO_2_26 317
+MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 318
+MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 319
+MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA 320
+MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 321
+MX6Q_PAD_EIM_LBA__ECSPI2_SS1 322
+MX6Q_PAD_EIM_LBA__GPIO_2_27 323
+MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 324
+MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 325
+MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 326
+MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 327
+MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 328
+MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 329
+MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY 330
+MX6Q_PAD_EIM_EB0__GPIO_2_28 331
+MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 332
+MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 333
+MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 334
+MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 335
+MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 336
+MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 337
+MX6Q_PAD_EIM_EB1__GPIO_2_29 338
+MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 339
+MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 340
+MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 341
+MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 342
+MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 343
+MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 344
+MX6Q_PAD_EIM_DA0__GPIO_3_0 345
+MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 346
+MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 347
+MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 348
+MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 349
+MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 350
+MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 351
+MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE 352
+MX6Q_PAD_EIM_DA1__GPIO_3_1 353
+MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 354
+MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 355
+MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 356
+MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 357
+MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 358
+MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 359
+MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE 360
+MX6Q_PAD_EIM_DA2__GPIO_3_2 361
+MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 362
+MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 363
+MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 364
+MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 365
+MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 366
+MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 367
+MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ 368
+MX6Q_PAD_EIM_DA3__GPIO_3_3 369
+MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 370
+MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 371
+MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 372
+MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 373
+MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 374
+MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 375
+MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN 376
+MX6Q_PAD_EIM_DA4__GPIO_3_4 377
+MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 378
+MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 379
+MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 380
+MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 381
+MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 382
+MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 383
+MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP 384
+MX6Q_PAD_EIM_DA5__GPIO_3_5 385
+MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 386
+MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 387
+MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 388
+MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 389
+MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 390
+MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 391
+MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN 392
+MX6Q_PAD_EIM_DA6__GPIO_3_6 393
+MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 394
+MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 395
+MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 396
+MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 397
+MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 398
+MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 399
+MX6Q_PAD_EIM_DA7__GPIO_3_7 400
+MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 401
+MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 402
+MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 403
+MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 404
+MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 405
+MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 406
+MX6Q_PAD_EIM_DA8__GPIO_3_8 407
+MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 408
+MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 409
+MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 410
+MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 411
+MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 412
+MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 413
+MX6Q_PAD_EIM_DA9__GPIO_3_9 414
+MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 415
+MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 416
+MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 417
+MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 418
+MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 419
+MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 420
+MX6Q_PAD_EIM_DA10__GPIO_3_10 421
+MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 422
+MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 423
+MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 424
+MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 425
+MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 426
+MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 427
+MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 428
+MX6Q_PAD_EIM_DA11__GPIO_3_11 429
+MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 430
+MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 431
+MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 432
+MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 433
+MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 434
+MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 435
+MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 436
+MX6Q_PAD_EIM_DA12__GPIO_3_12 437
+MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 438
+MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 439
+MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 440
+MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 441
+MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK 442
+MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 443
+MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 444
+MX6Q_PAD_EIM_DA13__GPIO_3_13 445
+MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 446
+MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 447
+MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 448
+MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 449
+MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK 450
+MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 451
+MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 452
+MX6Q_PAD_EIM_DA14__GPIO_3_14 453
+MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 454
+MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 455
+MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 456
+MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 457
+MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 458
+MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 459
+MX6Q_PAD_EIM_DA15__GPIO_3_15 460
+MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 461
+MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 462
+MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT 463
+MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B 464
+MX6Q_PAD_EIM_WAIT__GPIO_5_0 465
+MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 466
+MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 467
+MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK 468
+MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 469
+MX6Q_PAD_EIM_BCLK__GPIO_6_31 470
+MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 471
+MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK 472
+MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK 473
+MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 474
+MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 475
+MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 476
+MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 477
+MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 478
+MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 479
+MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 480
+MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 481
+MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 482
+MX6Q_PAD_DI0_PIN15__GPIO_4_17 483
+MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 484
+MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 485
+MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 486
+MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 487
+MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 488
+MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 489
+MX6Q_PAD_DI0_PIN2__GPIO_4_18 490
+MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 491
+MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 492
+MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 493
+MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 494
+MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 495
+MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 496
+MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 497
+MX6Q_PAD_DI0_PIN3__GPIO_4_19 498
+MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 499
+MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 500
+MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 501
+MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 502
+MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 503
+MX6Q_PAD_DI0_PIN4__USDHC1_WP 504
+MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 505
+MX6Q_PAD_DI0_PIN4__GPIO_4_20 506
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+MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 819
+MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 820
+MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS 821
+MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET 822
+MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 823
+MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 824
+MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 825
+MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 826
+MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 827
+MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 828
+MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 829
+MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 830
+MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 831
+MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE 832
+MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 833
+MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 834
+MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 835
+MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 836
+MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 837
+MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 838
+MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 839
+MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 840
+MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 841
+MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 842
+MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 843
+MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 844
+MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 845
+MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 846
+MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 847
+MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 848
+MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 849
+MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 850
+MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 851
+MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 852
+MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 853
+MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 854
+MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 855
+MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 856
+MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 857
+MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 858
+MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 859
+MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 860
+MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 861
+MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 862
+MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 863
+MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 864
+MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 865
+MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 866
+MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 867
+MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 868
+MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 869
+MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 870
+MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 871
+MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 872
+MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 873
+MX6Q_PAD_KEY_COL0__ENET_RDATA_3 874
+MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC 875
+MX6Q_PAD_KEY_COL0__KPP_COL_0 876
+MX6Q_PAD_KEY_COL0__UART4_TXD 877
+MX6Q_PAD_KEY_COL0__GPIO_4_6 878
+MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT 879
+MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST 880
+MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 881
+MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 882
+MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 883
+MX6Q_PAD_KEY_ROW0__KPP_ROW_0 884
+MX6Q_PAD_KEY_ROW0__UART4_RXD 885
+MX6Q_PAD_KEY_ROW0__GPIO_4_7 886
+MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT 887
+MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 888
+MX6Q_PAD_KEY_COL1__ECSPI1_MISO 889
+MX6Q_PAD_KEY_COL1__ENET_MDIO 890
+MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 891
+MX6Q_PAD_KEY_COL1__KPP_COL_1 892
+MX6Q_PAD_KEY_COL1__UART5_TXD 893
+MX6Q_PAD_KEY_COL1__GPIO_4_8 894
+MX6Q_PAD_KEY_COL1__USDHC1_VSELECT 895
+MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 896
+MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 897
+MX6Q_PAD_KEY_ROW1__ENET_COL 898
+MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 899
+MX6Q_PAD_KEY_ROW1__KPP_ROW_1 900
+MX6Q_PAD_KEY_ROW1__UART5_RXD 901
+MX6Q_PAD_KEY_ROW1__GPIO_4_9 902
+MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT 903
+MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 904
+MX6Q_PAD_KEY_COL2__ECSPI1_SS1 905
+MX6Q_PAD_KEY_COL2__ENET_RDATA_2 906
+MX6Q_PAD_KEY_COL2__CAN1_TXCAN 907
+MX6Q_PAD_KEY_COL2__KPP_COL_2 908
+MX6Q_PAD_KEY_COL2__ENET_MDC 909
+MX6Q_PAD_KEY_COL2__GPIO_4_10 910
+MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP 911
+MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 912
+MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 913
+MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 914
+MX6Q_PAD_KEY_ROW2__CAN1_RXCAN 915
+MX6Q_PAD_KEY_ROW2__KPP_ROW_2 916
+MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT 917
+MX6Q_PAD_KEY_ROW2__GPIO_4_11 918
+MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 919
+MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 920
+MX6Q_PAD_KEY_COL3__ECSPI1_SS3 921
+MX6Q_PAD_KEY_COL3__ENET_CRS 922
+MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 923
+MX6Q_PAD_KEY_COL3__KPP_COL_3 924
+MX6Q_PAD_KEY_COL3__I2C2_SCL 925
+MX6Q_PAD_KEY_COL3__GPIO_4_12 926
+MX6Q_PAD_KEY_COL3__SPDIF_IN1 927
+MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 928
+MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT 929
+MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK 930
+MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 931
+MX6Q_PAD_KEY_ROW3__KPP_ROW_3 932
+MX6Q_PAD_KEY_ROW3__I2C2_SDA 933
+MX6Q_PAD_KEY_ROW3__GPIO_4_13 934
+MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT 935
+MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 936
+MX6Q_PAD_KEY_COL4__CAN2_TXCAN 937
+MX6Q_PAD_KEY_COL4__IPU1_SISG_4 938
+MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC 939
+MX6Q_PAD_KEY_COL4__KPP_COL_4 940
+MX6Q_PAD_KEY_COL4__UART5_RTS 941
+MX6Q_PAD_KEY_COL4__GPIO_4_14 942
+MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 943
+MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 944
+MX6Q_PAD_KEY_ROW4__CAN2_RXCAN 945
+MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 946
+MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 947
+MX6Q_PAD_KEY_ROW4__KPP_ROW_4 948
+MX6Q_PAD_KEY_ROW4__UART5_CTS 949
+MX6Q_PAD_KEY_ROW4__GPIO_4_15 950
+MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 951
+MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 952
+MX6Q_PAD_GPIO_0__CCM_CLKO 953
+MX6Q_PAD_GPIO_0__KPP_COL_5 954
+MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK 955
+MX6Q_PAD_GPIO_0__EPIT1_EPITO 956
+MX6Q_PAD_GPIO_0__GPIO_1_0 957
+MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR 958
+MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 959
+MX6Q_PAD_GPIO_1__ESAI1_SCKR 960
+MX6Q_PAD_GPIO_1__WDOG2_WDOG_B 961
+MX6Q_PAD_GPIO_1__KPP_ROW_5 962
+MX6Q_PAD_GPIO_1__PWM2_PWMO 963
+MX6Q_PAD_GPIO_1__GPIO_1_1 964
+MX6Q_PAD_GPIO_1__USDHC1_CD 965
+MX6Q_PAD_GPIO_1__SRC_TESTER_ACK 966
+MX6Q_PAD_GPIO_9__ESAI1_FSR 967
+MX6Q_PAD_GPIO_9__WDOG1_WDOG_B 968
+MX6Q_PAD_GPIO_9__KPP_COL_6 969
+MX6Q_PAD_GPIO_9__CCM_REF_EN_B 970
+MX6Q_PAD_GPIO_9__PWM1_PWMO 971
+MX6Q_PAD_GPIO_9__GPIO_1_9 972
+MX6Q_PAD_GPIO_9__USDHC1_WP 973
+MX6Q_PAD_GPIO_9__SRC_EARLY_RST 974
+MX6Q_PAD_GPIO_3__ESAI1_HCKR 975
+MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 976
+MX6Q_PAD_GPIO_3__I2C3_SCL 977
+MX6Q_PAD_GPIO_3__ANATOP_24M_OUT 978
+MX6Q_PAD_GPIO_3__CCM_CLKO2 979
+MX6Q_PAD_GPIO_3__GPIO_1_3 980
+MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC 981
+MX6Q_PAD_GPIO_3__MLB_MLBCLK 982
+MX6Q_PAD_GPIO_6__ESAI1_SCKT 983
+MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 984
+MX6Q_PAD_GPIO_6__I2C3_SDA 985
+MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 986
+MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB 987
+MX6Q_PAD_GPIO_6__GPIO_1_6 988
+MX6Q_PAD_GPIO_6__USDHC2_LCTL 989
+MX6Q_PAD_GPIO_6__MLB_MLBSIG 990
+MX6Q_PAD_GPIO_2__ESAI1_FST 991
+MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 992
+MX6Q_PAD_GPIO_2__KPP_ROW_6 993
+MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 994
+MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 995
+MX6Q_PAD_GPIO_2__GPIO_1_2 996
+MX6Q_PAD_GPIO_2__USDHC2_WP 997
+MX6Q_PAD_GPIO_2__MLB_MLBDAT 998
+MX6Q_PAD_GPIO_4__ESAI1_HCKT 999
+MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 1000
+MX6Q_PAD_GPIO_4__KPP_COL_7 1001
+MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 1002
+MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1003
+MX6Q_PAD_GPIO_4__GPIO_1_4 1004
+MX6Q_PAD_GPIO_4__USDHC2_CD 1005
+MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA 1006
+MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 1007
+MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 1008
+MX6Q_PAD_GPIO_5__KPP_ROW_7 1009
+MX6Q_PAD_GPIO_5__CCM_CLKO 1010
+MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1011
+MX6Q_PAD_GPIO_5__GPIO_1_5 1012
+MX6Q_PAD_GPIO_5__I2C3_SCL 1013
+MX6Q_PAD_GPIO_5__CHEETAH_EVENTI 1014
+MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 1015
+MX6Q_PAD_GPIO_7__ECSPI5_RDY 1016
+MX6Q_PAD_GPIO_7__EPIT1_EPITO 1017
+MX6Q_PAD_GPIO_7__CAN1_TXCAN 1018
+MX6Q_PAD_GPIO_7__UART2_TXD 1019
+MX6Q_PAD_GPIO_7__GPIO_1_7 1020
+MX6Q_PAD_GPIO_7__SPDIF_PLOCK 1021
+MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE 1022
+MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 1023
+MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT 1024
+MX6Q_PAD_GPIO_8__EPIT2_EPITO 1025
+MX6Q_PAD_GPIO_8__CAN1_RXCAN 1026
+MX6Q_PAD_GPIO_8__UART2_RXD 1027
+MX6Q_PAD_GPIO_8__GPIO_1_8 1028
+MX6Q_PAD_GPIO_8__SPDIF_SRCLK 1029
+MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK 1030
+MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 1031
+MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 1032
+MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT 1033
+MX6Q_PAD_GPIO_16__USDHC1_LCTL 1034
+MX6Q_PAD_GPIO_16__SPDIF_IN1 1035
+MX6Q_PAD_GPIO_16__GPIO_7_11 1036
+MX6Q_PAD_GPIO_16__I2C3_SDA 1037
+MX6Q_PAD_GPIO_16__SJC_DE_B 1038
+MX6Q_PAD_GPIO_17__ESAI1_TX0 1039
+MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 1040
+MX6Q_PAD_GPIO_17__CCM_PMIC_RDY 1041
+MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 1042
+MX6Q_PAD_GPIO_17__SPDIF_OUT1 1043
+MX6Q_PAD_GPIO_17__GPIO_7_12 1044
+MX6Q_PAD_GPIO_17__SJC_JTAG_ACT 1045
+MX6Q_PAD_GPIO_18__ESAI1_TX1 1046
+MX6Q_PAD_GPIO_18__ENET_RX_CLK 1047
+MX6Q_PAD_GPIO_18__USDHC3_VSELECT 1048
+MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 1049
+MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK 1050
+MX6Q_PAD_GPIO_18__GPIO_7_13 1051
+MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 1052
+MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST 1053
+MX6Q_PAD_GPIO_19__KPP_COL_5 1054
+MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 1055
+MX6Q_PAD_GPIO_19__SPDIF_OUT1 1056
+MX6Q_PAD_GPIO_19__CCM_CLKO 1057
+MX6Q_PAD_GPIO_19__ECSPI1_RDY 1058
+MX6Q_PAD_GPIO_19__GPIO_4_5 1059
+MX6Q_PAD_GPIO_19__ENET_TX_ER 1060
+MX6Q_PAD_GPIO_19__SRC_INT_BOOT 1061
+MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 1062
+MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 1063
+MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 1064
+MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 1065
+MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 1066
+MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO 1067
+MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 1068
+MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 1069
+MX6Q_PAD_CSI0_MCLK__CCM_CLKO 1070
+MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 1071
+MX6Q_PAD_CSI0_MCLK__GPIO_5_19 1072
+MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 1073
+MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL 1074
+MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN 1075
+MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 1076
+MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 1077
+MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 1078
+MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 1079
+MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 1080
+MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK 1081
+MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 1082
+MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 1083
+MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 1084
+MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 1085
+MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 1086
+MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 1087
+MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 1088
+MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 1089
+MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 1090
+MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 1091
+MX6Q_PAD_CSI0_DAT4__KPP_COL_5 1092
+MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 1093
+MX6Q_PAD_CSI0_DAT4__GPIO_5_22 1094
+MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 1095
+MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 1096
+MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 1097
+MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 1098
+MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 1099
+MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 1100
+MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 1101
+MX6Q_PAD_CSI0_DAT5__GPIO_5_23 1102
+MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 1103
+MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 1104
+MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 1105
+MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 1106
+MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 1107
+MX6Q_PAD_CSI0_DAT6__KPP_COL_6 1108
+MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 1109
+MX6Q_PAD_CSI0_DAT6__GPIO_5_24 1110
+MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 1111
+MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 1112
+MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 1113
+MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 1114
+MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 1115
+MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 1116
+MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 1117
+MX6Q_PAD_CSI0_DAT7__GPIO_5_25 1118
+MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 1119
+MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 1120
+MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 1121
+MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 1122
+MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 1123
+MX6Q_PAD_CSI0_DAT8__KPP_COL_7 1124
+MX6Q_PAD_CSI0_DAT8__I2C1_SDA 1125
+MX6Q_PAD_CSI0_DAT8__GPIO_5_26 1126
+MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 1127
+MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 1128
+MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 1129
+MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 1130
+MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 1131
+MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 1132
+MX6Q_PAD_CSI0_DAT9__I2C1_SCL 1133
+MX6Q_PAD_CSI0_DAT9__GPIO_5_27 1134
+MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 1135
+MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 1136
+MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 1137
+MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 1138
+MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 1139
+MX6Q_PAD_CSI0_DAT10__UART1_TXD 1140
+MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 1141
+MX6Q_PAD_CSI0_DAT10__GPIO_5_28 1142
+MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 1143
+MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 1144
+MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 1145
+MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 1146
+MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 1147
+MX6Q_PAD_CSI0_DAT11__UART1_RXD 1148
+MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 1149
+MX6Q_PAD_CSI0_DAT11__GPIO_5_29 1150
+MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 1151
+MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 1152
+MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 1153
+MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 1154
+MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 1155
+MX6Q_PAD_CSI0_DAT12__UART4_TXD 1156
+MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 1157
+MX6Q_PAD_CSI0_DAT12__GPIO_5_30 1158
+MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 1159
+MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 1160
+MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 1161
+MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 1162
+MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 1163
+MX6Q_PAD_CSI0_DAT13__UART4_RXD 1164
+MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 1165
+MX6Q_PAD_CSI0_DAT13__GPIO_5_31 1166
+MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 1167
+MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 1168
+MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 1169
+MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 1170
+MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 1171
+MX6Q_PAD_CSI0_DAT14__UART5_TXD 1172
+MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 1173
+MX6Q_PAD_CSI0_DAT14__GPIO_6_0 1174
+MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 1175
+MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 1176
+MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 1177
+MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 1178
+MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 1179
+MX6Q_PAD_CSI0_DAT15__UART5_RXD 1180
+MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 1181
+MX6Q_PAD_CSI0_DAT15__GPIO_6_1 1182
+MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 1183
+MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 1184
+MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 1185
+MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 1186
+MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 1187
+MX6Q_PAD_CSI0_DAT16__UART4_RTS 1188
+MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 1189
+MX6Q_PAD_CSI0_DAT16__GPIO_6_2 1190
+MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 1191
+MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 1192
+MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 1193
+MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 1194
+MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 1195
+MX6Q_PAD_CSI0_DAT17__UART4_CTS 1196
+MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 1197
+MX6Q_PAD_CSI0_DAT17__GPIO_6_3 1198
+MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 1199
+MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 1200
+MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 1201
+MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 1202
+MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 1203
+MX6Q_PAD_CSI0_DAT18__UART5_RTS 1204
+MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 1205
+MX6Q_PAD_CSI0_DAT18__GPIO_6_4 1206
+MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 1207
+MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 1208
+MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 1209
+MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 1210
+MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 1211
+MX6Q_PAD_CSI0_DAT19__UART5_CTS 1212
+MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 1213
+MX6Q_PAD_CSI0_DAT19__GPIO_6_5 1214
+MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 1215
+MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 1216
+MX6Q_PAD_JTAG_TMS__SJC_TMS 1217
+MX6Q_PAD_JTAG_MOD__SJC_MOD 1218
+MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB 1219
+MX6Q_PAD_JTAG_TDI__SJC_TDI 1220
+MX6Q_PAD_JTAG_TCK__SJC_TCK 1221
+MX6Q_PAD_JTAG_TDO__SJC_TDO 1222
+MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 1223
+MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 1224
+MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 1225
+MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 1226
+MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 1227
+MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 1228
+MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 1229
+MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 1230
+MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 1231
+MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 1232
+MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 1233
+MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM 1234
+MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ 1235
+MX6Q_PAD_POR_B__SRC_POR_B 1236
+MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 1237
+MX6Q_PAD_RESET_IN_B__SRC_RESET_B 1238
+MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 1239
+MX6Q_PAD_TEST_MODE__TCU_TEST_MODE 1240
+MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 1241
+MX6Q_PAD_SD3_DAT7__UART1_TXD 1242
+MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 1243
+MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 1244
+MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 1245
+MX6Q_PAD_SD3_DAT7__GPIO_6_17 1246
+MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 1247
+MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV 1248
+MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 1249
+MX6Q_PAD_SD3_DAT6__UART1_RXD 1250
+MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 1251
+MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 1252
+MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 1253
+MX6Q_PAD_SD3_DAT6__GPIO_6_18 1254
+MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 1255
+MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 1256
+MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 1257
+MX6Q_PAD_SD3_DAT5__UART2_TXD 1258
+MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 1259
+MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 1260
+MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 1261
+MX6Q_PAD_SD3_DAT5__GPIO_7_0 1262
+MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 1263
+MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 1264
+MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 1265
+MX6Q_PAD_SD3_DAT4__UART2_RXD 1266
+MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 1267
+MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 1268
+MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 1269
+MX6Q_PAD_SD3_DAT4__GPIO_7_1 1270
+MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 1271
+MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 1272
+MX6Q_PAD_SD3_CMD__USDHC3_CMD 1273
+MX6Q_PAD_SD3_CMD__UART2_CTS 1274
+MX6Q_PAD_SD3_CMD__CAN1_TXCAN 1275
+MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 1276
+MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 1277
+MX6Q_PAD_SD3_CMD__GPIO_7_2 1278
+MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 1279
+MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 1280
+MX6Q_PAD_SD3_CLK__USDHC3_CLK 1281
+MX6Q_PAD_SD3_CLK__UART2_RTS 1282
+MX6Q_PAD_SD3_CLK__CAN1_RXCAN 1283
+MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 1284
+MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 1285
+MX6Q_PAD_SD3_CLK__GPIO_7_3 1286
+MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 1287
+MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 1288
+MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 1289
+MX6Q_PAD_SD3_DAT0__UART1_CTS 1290
+MX6Q_PAD_SD3_DAT0__CAN2_TXCAN 1291
+MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 1292
+MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 1293
+MX6Q_PAD_SD3_DAT0__GPIO_7_4 1294
+MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 1295
+MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 1296
+MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 1297
+MX6Q_PAD_SD3_DAT1__UART1_RTS 1298
+MX6Q_PAD_SD3_DAT1__CAN2_RXCAN 1299
+MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 1300
+MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 1301
+MX6Q_PAD_SD3_DAT1__GPIO_7_5 1302
+MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 1303
+MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 1304
+MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 1305
+MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 1306
+MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 1307
+MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 1308
+MX6Q_PAD_SD3_DAT2__GPIO_7_6 1309
+MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 1310
+MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 1311
+MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 1312
+MX6Q_PAD_SD3_DAT3__UART3_CTS 1313
+MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 1314
+MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 1315
+MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 1316
+MX6Q_PAD_SD3_DAT3__GPIO_7_7 1317
+MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 1318
+MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 1319
+MX6Q_PAD_SD3_RST__USDHC3_RST 1320
+MX6Q_PAD_SD3_RST__UART3_RTS 1321
+MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 1322
+MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 1323
+MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 1324
+MX6Q_PAD_SD3_RST__GPIO_7_8 1325
+MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 1326
+MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 1327
+MX6Q_PAD_NANDF_CLE__RAWNAND_CLE 1328
+MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 1329
+MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 1330
+MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 1331
+MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 1332
+MX6Q_PAD_NANDF_CLE__GPIO_6_7 1333
+MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 1334
+MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 1335
+MX6Q_PAD_NANDF_ALE__RAWNAND_ALE 1336
+MX6Q_PAD_NANDF_ALE__USDHC4_RST 1337
+MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 1338
+MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 1339
+MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 1340
+MX6Q_PAD_NANDF_ALE__GPIO_6_8 1341
+MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 1342
+MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 1343
+MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN 1344
+MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 1345
+MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 1346
+MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 1347
+MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 1348
+MX6Q_PAD_NANDF_WP_B__GPIO_6_9 1349
+MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 1350
+MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 1351
+MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 1352
+MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 1353
+MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 1354
+MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 1355
+MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 1356
+MX6Q_PAD_NANDF_RB0__GPIO_6_10 1357
+MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 1358
+MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 1359
+MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N 1360
+MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 1361
+MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 1362
+MX6Q_PAD_NANDF_CS0__GPIO_6_11 1363
+MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 1364
+MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N 1365
+MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT 1366
+MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT 1367
+MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 1368
+MX6Q_PAD_NANDF_CS1__GPIO_6_14 1369
+MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT 1370
+MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N 1371
+MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 1372
+MX6Q_PAD_NANDF_CS2__ESAI1_TX0 1373
+MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE 1374
+MX6Q_PAD_NANDF_CS2__CCM_CLKO2 1375
+MX6Q_PAD_NANDF_CS2__GPIO_6_15 1376
+MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 1377
+MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N 1378
+MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 1379
+MX6Q_PAD_NANDF_CS3__ESAI1_TX1 1380
+MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 1381
+MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 1382
+MX6Q_PAD_NANDF_CS3__GPIO_6_16 1383
+MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 1384
+MX6Q_PAD_NANDF_CS3__TPSMP_CLK 1385
+MX6Q_PAD_SD4_CMD__USDHC4_CMD 1386
+MX6Q_PAD_SD4_CMD__RAWNAND_RDN 1387
+MX6Q_PAD_SD4_CMD__UART3_TXD 1388
+MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 1389
+MX6Q_PAD_SD4_CMD__GPIO_7_9 1390
+MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR 1391
+MX6Q_PAD_SD4_CLK__USDHC4_CLK 1392
+MX6Q_PAD_SD4_CLK__RAWNAND_WRN 1393
+MX6Q_PAD_SD4_CLK__UART3_RXD 1394
+MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 1395
+MX6Q_PAD_SD4_CLK__GPIO_7_10 1396
+MX6Q_PAD_NANDF_D0__RAWNAND_D0 1397
+MX6Q_PAD_NANDF_D0__USDHC1_DAT4 1398
+MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 1399
+MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 1400
+MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 1401
+MX6Q_PAD_NANDF_D0__GPIO_2_0 1402
+MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 1403
+MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 1404
+MX6Q_PAD_NANDF_D1__RAWNAND_D1 1405
+MX6Q_PAD_NANDF_D1__USDHC1_DAT5 1406
+MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 1407
+MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 1408
+MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 1409
+MX6Q_PAD_NANDF_D1__GPIO_2_1 1410
+MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 1411
+MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 1412
+MX6Q_PAD_NANDF_D2__RAWNAND_D2 1413
+MX6Q_PAD_NANDF_D2__USDHC1_DAT6 1414
+MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 1415
+MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 1416
+MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 1417
+MX6Q_PAD_NANDF_D2__GPIO_2_2 1418
+MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 1419
+MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 1420
+MX6Q_PAD_NANDF_D3__RAWNAND_D3 1421
+MX6Q_PAD_NANDF_D3__USDHC1_DAT7 1422
+MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 1423
+MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 1424
+MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 1425
+MX6Q_PAD_NANDF_D3__GPIO_2_3 1426
+MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 1427
+MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 1428
+MX6Q_PAD_NANDF_D4__RAWNAND_D4 1429
+MX6Q_PAD_NANDF_D4__USDHC2_DAT4 1430
+MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 1431
+MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 1432
+MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 1433
+MX6Q_PAD_NANDF_D4__GPIO_2_4 1434
+MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 1435
+MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 1436
+MX6Q_PAD_NANDF_D5__RAWNAND_D5 1437
+MX6Q_PAD_NANDF_D5__USDHC2_DAT5 1438
+MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 1439
+MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 1440
+MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 1441
+MX6Q_PAD_NANDF_D5__GPIO_2_5 1442
+MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 1443
+MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 1444
+MX6Q_PAD_NANDF_D6__RAWNAND_D6 1445
+MX6Q_PAD_NANDF_D6__USDHC2_DAT6 1446
+MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 1447
+MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 1448
+MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 1449
+MX6Q_PAD_NANDF_D6__GPIO_2_6 1450
+MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 1451
+MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 1452
+MX6Q_PAD_NANDF_D7__RAWNAND_D7 1453
+MX6Q_PAD_NANDF_D7__USDHC2_DAT7 1454
+MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 1455
+MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 1456
+MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 1457
+MX6Q_PAD_NANDF_D7__GPIO_2_7 1458
+MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 1459
+MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 1460
+MX6Q_PAD_SD4_DAT0__RAWNAND_D8 1461
+MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 1462
+MX6Q_PAD_SD4_DAT0__RAWNAND_DQS 1463
+MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 1464
+MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 1465
+MX6Q_PAD_SD4_DAT0__GPIO_2_8 1466
+MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 1467
+MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 1468
+MX6Q_PAD_SD4_DAT1__RAWNAND_D9 1469
+MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 1470
+MX6Q_PAD_SD4_DAT1__PWM3_PWMO 1471
+MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 1472
+MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 1473
+MX6Q_PAD_SD4_DAT1__GPIO_2_9 1474
+MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 1475
+MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 1476
+MX6Q_PAD_SD4_DAT2__RAWNAND_D10 1477
+MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 1478
+MX6Q_PAD_SD4_DAT2__PWM4_PWMO 1479
+MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 1480
+MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 1481
+MX6Q_PAD_SD4_DAT2__GPIO_2_10 1482
+MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 1483
+MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 1484
+MX6Q_PAD_SD4_DAT3__RAWNAND_D11 1485
+MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 1486
+MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 1487
+MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 1488
+MX6Q_PAD_SD4_DAT3__GPIO_2_11 1489
+MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 1490
+MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 1491
+MX6Q_PAD_SD4_DAT4__RAWNAND_D12 1492
+MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 1493
+MX6Q_PAD_SD4_DAT4__UART2_RXD 1494
+MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 1495
+MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 1496
+MX6Q_PAD_SD4_DAT4__GPIO_2_12 1497
+MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 1498
+MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 1499
+MX6Q_PAD_SD4_DAT5__RAWNAND_D13 1500
+MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 1501
+MX6Q_PAD_SD4_DAT5__UART2_RTS 1502
+MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 1503
+MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 1504
+MX6Q_PAD_SD4_DAT5__GPIO_2_13 1505
+MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 1506
+MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 1507
+MX6Q_PAD_SD4_DAT6__RAWNAND_D14 1508
+MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 1509
+MX6Q_PAD_SD4_DAT6__UART2_CTS 1510
+MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 1511
+MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 1512
+MX6Q_PAD_SD4_DAT6__GPIO_2_14 1513
+MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 1514
+MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 1515
+MX6Q_PAD_SD4_DAT7__RAWNAND_D15 1516
+MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 1517
+MX6Q_PAD_SD4_DAT7__UART2_TXD 1518
+MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 1519
+MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 1520
+MX6Q_PAD_SD4_DAT7__GPIO_2_15 1521
+MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 1522
+MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 1523
+MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 1524
+MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 1525
+MX6Q_PAD_SD1_DAT1__PWM3_PWMO 1526
+MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 1527
+MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 1528
+MX6Q_PAD_SD1_DAT1__GPIO_1_17 1529
+MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 1530
+MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 1531
+MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 1532
+MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 1533
+MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS 1534
+MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 1535
+MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 1536
+MX6Q_PAD_SD1_DAT0__GPIO_1_16 1537
+MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 1538
+MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 1539
+MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 1540
+MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 1541
+MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 1542
+MX6Q_PAD_SD1_DAT3__PWM1_PWMO 1543
+MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B 1544
+MX6Q_PAD_SD1_DAT3__GPIO_1_21 1545
+MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB 1546
+MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 1547
+MX6Q_PAD_SD1_CMD__USDHC1_CMD 1548
+MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 1549
+MX6Q_PAD_SD1_CMD__PWM4_PWMO 1550
+MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 1551
+MX6Q_PAD_SD1_CMD__GPIO_1_18 1552
+MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 1553
+MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 1554
+MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 1555
+MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 1556
+MX6Q_PAD_SD1_DAT2__PWM2_PWMO 1557
+MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B 1558
+MX6Q_PAD_SD1_DAT2__GPIO_1_19 1559
+MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB 1560
+MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 1561
+MX6Q_PAD_SD1_CLK__USDHC1_CLK 1562
+MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 1563
+MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT 1564
+MX6Q_PAD_SD1_CLK__GPT_CLKIN 1565
+MX6Q_PAD_SD1_CLK__GPIO_1_20 1566
+MX6Q_PAD_SD1_CLK__PHY_DTB_0 1567
+MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 1568
+MX6Q_PAD_SD2_CLK__USDHC2_CLK 1569
+MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 1570
+MX6Q_PAD_SD2_CLK__KPP_COL_5 1571
+MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1572
+MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 1573
+MX6Q_PAD_SD2_CLK__GPIO_1_10 1574
+MX6Q_PAD_SD2_CLK__PHY_DTB_1 1575
+MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 1576
+MX6Q_PAD_SD2_CMD__USDHC2_CMD 1577
+MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 1578
+MX6Q_PAD_SD2_CMD__KPP_ROW_5 1579
+MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1580
+MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 1581
+MX6Q_PAD_SD2_CMD__GPIO_1_11 1582
+MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 1583
+MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 1584
+MX6Q_PAD_SD2_DAT3__KPP_COL_6 1585
+MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC 1586
+MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 1587
+MX6Q_PAD_SD2_DAT3__GPIO_1_12 1588
+MX6Q_PAD_SD2_DAT3__SJC_DONE 1589
+MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 1590
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
new file mode 100644
index 000000000000..f7e8e8f4d9a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
@@ -0,0 +1,918 @@
+* Freescale MXS Pin Controller
+
+The pins controlled by mxs pin controller are organized in banks, each bank
+has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
+function is GPIO. The configuration on the pins includes drive strength,
+voltage and pull-up.
+
+Required properties:
+- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
+- reg: Should contain the register physical address and length for the
+ pin controller.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+The node of mxs pin controller acts as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for
+a group of pins, and only affects those parameters that are explicitly listed.
+In other words, a subnode that describes a drive strength parameter implies no
+information about pull-up. For this reason, even seemingly boolean values are
+actually tristates in this binding: unspecified, off, or on. Unspecified is
+represented as an absent property, and off/on are represented as integer
+values 0 and 1.
+
+Those subnodes under mxs pin controller node will fall into two categories.
+One is to set up a group of pins for a function, both mux selection and pin
+configurations, and it's called group node in the binding document. The other
+one is to adjust the pin configuration for some particular pins that need a
+different configuration than what is defined in group node. The binding
+document calls this type of node config node.
+
+On mxs, there is no hardware pin group. The pin group in this binding only
+means a group of pins put together for particular peripheral to work in
+particular function, like SSP0 functioning as mmc0-8bit. That said, the
+group node should include all the pins needed for one function rather than
+having these pins defined in several group nodes. It also means each of
+"pinctrl-*" phandle in client device node should only have one group node
+pointed in there, while the phandle can have multiple config node referenced
+there to adjust configurations for some pins in the group.
+
+Required subnode-properties:
+- fsl,pinmux-ids: An integer array. Each integer in the array specify a pin
+ with given mux function, with bank, pin and mux packed as below.
+
+ [15..12] : bank number
+ [11..4] : pin number
+ [3..0] : mux selection
+
+ This integer with mux selection packed is used as an entity by both group
+ and config nodes to identify a pin. The mux selection in the integer takes
+ effects only on group node, and will get ignored by driver with config node,
+ since config node is only meant to set up pin configurations.
+
+ Valid values for these integers are listed below.
+
+- reg: Should be the index of the group nodes for same function. This property
+ is required only for group nodes, and should not be present in any config
+ nodes.
+
+Optional subnode-properties:
+- fsl,drive-strength: Integer.
+ 0: 4 mA
+ 1: 8 mA
+ 2: 12 mA
+ 3: 16 mA
+- fsl,voltage: Integer.
+ 0: 1.8 V
+ 1: 3.3 V
+- fsl,pull-up: Integer.
+ 0: Disable the internal pull-up
+ 1: Enable the internal pull-up
+
+Examples:
+
+pinctrl@80018000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx28-pinctrl";
+ reg = <0x80018000 2000>;
+
+ mmc0_8bit_pins_a: mmc0-8bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x2000 0x2010 0x2020 0x2030
+ 0x2040 0x2050 0x2060 0x2070
+ 0x2080 0x2090 0x20a0>;
+ fsl,drive-strength = <1>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <1>;
+ };
+
+ mmc_cd_cfg: mmc-cd-cfg {
+ fsl,pinmux-ids = <0x2090>;
+ fsl,pull-up = <0>;
+ };
+
+ mmc_sck_cfg: mmc-sck-cfg {
+ fsl,pinmux-ids = <0x20a0>;
+ fsl,drive-strength = <2>;
+ fsl,pull-up = <0>;
+ };
+};
+
+In this example, group node mmc0-8bit defines a group of pins for mxs SSP0
+to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations
+applied on all these pins. And config nodes mmc-cd-cfg and mmc-sck-cfg are
+adjusting the configuration for pins card-detection and clock from what group
+node mmc0-8bit defines. Only the configuration properties to be adjusted need
+to be listed in the config nodes.
+
+Valid values for i.MX28 pinmux-id:
+
+pinmux id
+------ --
+MX28_PAD_GPMI_D00__GPMI_D0 0x0000
+MX28_PAD_GPMI_D01__GPMI_D1 0x0010
+MX28_PAD_GPMI_D02__GPMI_D2 0x0020
+MX28_PAD_GPMI_D03__GPMI_D3 0x0030
+MX28_PAD_GPMI_D04__GPMI_D4 0x0040
+MX28_PAD_GPMI_D05__GPMI_D5 0x0050
+MX28_PAD_GPMI_D06__GPMI_D6 0x0060
+MX28_PAD_GPMI_D07__GPMI_D7 0x0070
+MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
+MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
+MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
+MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130
+MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140
+MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150
+MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160
+MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170
+MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180
+MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190
+MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0
+MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0
+MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0
+MX28_PAD_LCD_D00__LCD_D0 0x1000
+MX28_PAD_LCD_D01__LCD_D1 0x1010
+MX28_PAD_LCD_D02__LCD_D2 0x1020
+MX28_PAD_LCD_D03__LCD_D3 0x1030
+MX28_PAD_LCD_D04__LCD_D4 0x1040
+MX28_PAD_LCD_D05__LCD_D5 0x1050
+MX28_PAD_LCD_D06__LCD_D6 0x1060
+MX28_PAD_LCD_D07__LCD_D7 0x1070
+MX28_PAD_LCD_D08__LCD_D8 0x1080
+MX28_PAD_LCD_D09__LCD_D9 0x1090
+MX28_PAD_LCD_D10__LCD_D10 0x10a0
+MX28_PAD_LCD_D11__LCD_D11 0x10b0
+MX28_PAD_LCD_D12__LCD_D12 0x10c0
+MX28_PAD_LCD_D13__LCD_D13 0x10d0
+MX28_PAD_LCD_D14__LCD_D14 0x10e0
+MX28_PAD_LCD_D15__LCD_D15 0x10f0
+MX28_PAD_LCD_D16__LCD_D16 0x1100
+MX28_PAD_LCD_D17__LCD_D17 0x1110
+MX28_PAD_LCD_D18__LCD_D18 0x1120
+MX28_PAD_LCD_D19__LCD_D19 0x1130
+MX28_PAD_LCD_D20__LCD_D20 0x1140
+MX28_PAD_LCD_D21__LCD_D21 0x1150
+MX28_PAD_LCD_D22__LCD_D22 0x1160
+MX28_PAD_LCD_D23__LCD_D23 0x1170
+MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180
+MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190
+MX28_PAD_LCD_RS__LCD_RS 0x11a0
+MX28_PAD_LCD_CS__LCD_CS 0x11b0
+MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0
+MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0
+MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0
+MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0
+MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000
+MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010
+MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020
+MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030
+MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040
+MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050
+MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060
+MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070
+MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080
+MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090
+MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0
+MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0
+MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0
+MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0
+MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0
+MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100
+MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110
+MX28_PAD_SSP2_MISO__SSP2_D0 0x2120
+MX28_PAD_SSP2_SS0__SSP2_D3 0x2130
+MX28_PAD_SSP2_SS1__SSP2_D4 0x2140
+MX28_PAD_SSP2_SS2__SSP2_D5 0x2150
+MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180
+MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190
+MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0
+MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0
+MX28_PAD_AUART0_RX__AUART0_RX 0x3000
+MX28_PAD_AUART0_TX__AUART0_TX 0x3010
+MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020
+MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030
+MX28_PAD_AUART1_RX__AUART1_RX 0x3040
+MX28_PAD_AUART1_TX__AUART1_TX 0x3050
+MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060
+MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070
+MX28_PAD_AUART2_RX__AUART2_RX 0x3080
+MX28_PAD_AUART2_TX__AUART2_TX 0x3090
+MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0
+MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0
+MX28_PAD_AUART3_RX__AUART3_RX 0x30c0
+MX28_PAD_AUART3_TX__AUART3_TX 0x30d0
+MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0
+MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0
+MX28_PAD_PWM0__PWM_0 0x3100
+MX28_PAD_PWM1__PWM_1 0x3110
+MX28_PAD_PWM2__PWM_2 0x3120
+MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140
+MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150
+MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160
+MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170
+MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180
+MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190
+MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0
+MX28_PAD_SPDIF__SPDIF_TX 0x31b0
+MX28_PAD_PWM3__PWM_3 0x31c0
+MX28_PAD_PWM4__PWM_4 0x31d0
+MX28_PAD_LCD_RESET__LCD_RESET 0x31e0
+MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000
+MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010
+MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020
+MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030
+MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040
+MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050
+MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060
+MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070
+MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080
+MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090
+MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0
+MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0
+MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0
+MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0
+MX28_PAD_ENET0_COL__ENET0_COL 0x40e0
+MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0
+MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100
+MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140
+MX28_PAD_EMI_D00__EMI_DATA0 0x5000
+MX28_PAD_EMI_D01__EMI_DATA1 0x5010
+MX28_PAD_EMI_D02__EMI_DATA2 0x5020
+MX28_PAD_EMI_D03__EMI_DATA3 0x5030
+MX28_PAD_EMI_D04__EMI_DATA4 0x5040
+MX28_PAD_EMI_D05__EMI_DATA5 0x5050
+MX28_PAD_EMI_D06__EMI_DATA6 0x5060
+MX28_PAD_EMI_D07__EMI_DATA7 0x5070
+MX28_PAD_EMI_D08__EMI_DATA8 0x5080
+MX28_PAD_EMI_D09__EMI_DATA9 0x5090
+MX28_PAD_EMI_D10__EMI_DATA10 0x50a0
+MX28_PAD_EMI_D11__EMI_DATA11 0x50b0
+MX28_PAD_EMI_D12__EMI_DATA12 0x50c0
+MX28_PAD_EMI_D13__EMI_DATA13 0x50d0
+MX28_PAD_EMI_D14__EMI_DATA14 0x50e0
+MX28_PAD_EMI_D15__EMI_DATA15 0x50f0
+MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100
+MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110
+MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120
+MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130
+MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140
+MX28_PAD_EMI_CLK__EMI_CLK 0x5150
+MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160
+MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170
+MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0
+MX28_PAD_EMI_A00__EMI_ADDR0 0x6000
+MX28_PAD_EMI_A01__EMI_ADDR1 0x6010
+MX28_PAD_EMI_A02__EMI_ADDR2 0x6020
+MX28_PAD_EMI_A03__EMI_ADDR3 0x6030
+MX28_PAD_EMI_A04__EMI_ADDR4 0x6040
+MX28_PAD_EMI_A05__EMI_ADDR5 0x6050
+MX28_PAD_EMI_A06__EMI_ADDR6 0x6060
+MX28_PAD_EMI_A07__EMI_ADDR7 0x6070
+MX28_PAD_EMI_A08__EMI_ADDR8 0x6080
+MX28_PAD_EMI_A09__EMI_ADDR9 0x6090
+MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0
+MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0
+MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0
+MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0
+MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0
+MX28_PAD_EMI_BA0__EMI_BA0 0x6100
+MX28_PAD_EMI_BA1__EMI_BA1 0x6110
+MX28_PAD_EMI_BA2__EMI_BA2 0x6120
+MX28_PAD_EMI_CASN__EMI_CASN 0x6130
+MX28_PAD_EMI_RASN__EMI_RASN 0x6140
+MX28_PAD_EMI_WEN__EMI_WEN 0x6150
+MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160
+MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170
+MX28_PAD_EMI_CKE__EMI_CKE 0x6180
+MX28_PAD_GPMI_D00__SSP1_D0 0x0001
+MX28_PAD_GPMI_D01__SSP1_D1 0x0011
+MX28_PAD_GPMI_D02__SSP1_D2 0x0021
+MX28_PAD_GPMI_D03__SSP1_D3 0x0031
+MX28_PAD_GPMI_D04__SSP1_D4 0x0041
+MX28_PAD_GPMI_D05__SSP1_D5 0x0051
+MX28_PAD_GPMI_D06__SSP1_D6 0x0061
+MX28_PAD_GPMI_D07__SSP1_D7 0x0071
+MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101
+MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111
+MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121
+MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131
+MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141
+MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151
+MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161
+MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171
+MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181
+MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191
+MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1
+MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1
+MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1
+MX28_PAD_LCD_D03__ETM_DA8 0x1031
+MX28_PAD_LCD_D04__ETM_DA9 0x1041
+MX28_PAD_LCD_D08__ETM_DA3 0x1081
+MX28_PAD_LCD_D09__ETM_DA4 0x1091
+MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141
+MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151
+MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161
+MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171
+MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181
+MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191
+MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1
+MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1
+MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1
+MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1
+MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1
+MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041
+MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051
+MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061
+MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071
+MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1
+MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1
+MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1
+MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1
+MX28_PAD_SSP2_SCK__AUART2_RX 0x2101
+MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111
+MX28_PAD_SSP2_MISO__AUART3_RX 0x2121
+MX28_PAD_SSP2_SS0__AUART3_TX 0x2131
+MX28_PAD_SSP2_SS1__SSP2_D1 0x2141
+MX28_PAD_SSP2_SS2__SSP2_D2 0x2151
+MX28_PAD_SSP3_SCK__AUART4_TX 0x2181
+MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191
+MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1
+MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1
+MX28_PAD_AUART0_RX__I2C0_SCL 0x3001
+MX28_PAD_AUART0_TX__I2C0_SDA 0x3011
+MX28_PAD_AUART0_CTS__AUART4_RX 0x3021
+MX28_PAD_AUART0_RTS__AUART4_TX 0x3031
+MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041
+MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051
+MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061
+MX28_PAD_AUART1_RTS__USB0_ID 0x3071
+MX28_PAD_AUART2_RX__SSP3_D1 0x3081
+MX28_PAD_AUART2_TX__SSP3_D2 0x3091
+MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1
+MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1
+MX28_PAD_AUART3_RX__CAN0_TX 0x30c1
+MX28_PAD_AUART3_TX__CAN0_RX 0x30d1
+MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1
+MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1
+MX28_PAD_PWM0__I2C1_SCL 0x3101
+MX28_PAD_PWM1__I2C1_SDA 0x3111
+MX28_PAD_PWM2__USB0_ID 0x3121
+MX28_PAD_SAIF0_MCLK__PWM_3 0x3141
+MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151
+MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161
+MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171
+MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181
+MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191
+MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1
+MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1
+MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001
+MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011
+MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021
+MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031
+MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041
+MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051
+MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061
+MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071
+MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081
+MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091
+MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1
+MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1
+MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1
+MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1
+MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1
+MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1
+MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122
+MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132
+MX28_PAD_GPMI_RDY0__USB0_ID 0x0142
+MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162
+MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172
+MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2
+MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2
+MX28_PAD_LCD_D00__ETM_DA0 0x1002
+MX28_PAD_LCD_D01__ETM_DA1 0x1012
+MX28_PAD_LCD_D02__ETM_DA2 0x1022
+MX28_PAD_LCD_D03__ETM_DA3 0x1032
+MX28_PAD_LCD_D04__ETM_DA4 0x1042
+MX28_PAD_LCD_D05__ETM_DA5 0x1052
+MX28_PAD_LCD_D06__ETM_DA6 0x1062
+MX28_PAD_LCD_D07__ETM_DA7 0x1072
+MX28_PAD_LCD_D08__ETM_DA8 0x1082
+MX28_PAD_LCD_D09__ETM_DA9 0x1092
+MX28_PAD_LCD_D10__ETM_DA10 0x10a2
+MX28_PAD_LCD_D11__ETM_DA11 0x10b2
+MX28_PAD_LCD_D12__ETM_DA12 0x10c2
+MX28_PAD_LCD_D13__ETM_DA13 0x10d2
+MX28_PAD_LCD_D14__ETM_DA14 0x10e2
+MX28_PAD_LCD_D15__ETM_DA15 0x10f2
+MX28_PAD_LCD_D16__ETM_DA7 0x1102
+MX28_PAD_LCD_D17__ETM_DA6 0x1112
+MX28_PAD_LCD_D18__ETM_DA5 0x1122
+MX28_PAD_LCD_D19__ETM_DA4 0x1132
+MX28_PAD_LCD_D20__ETM_DA3 0x1142
+MX28_PAD_LCD_D21__ETM_DA2 0x1152
+MX28_PAD_LCD_D22__ETM_DA1 0x1162
+MX28_PAD_LCD_D23__ETM_DA0 0x1172
+MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182
+MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192
+MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2
+MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2
+MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2
+MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2
+MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2
+MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2
+MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102
+MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112
+MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122
+MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132
+MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142
+MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152
+MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182
+MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192
+MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2
+MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2
+MX28_PAD_AUART0_RX__DUART_CTS 0x3002
+MX28_PAD_AUART0_TX__DUART_RTS 0x3012
+MX28_PAD_AUART0_CTS__DUART_RX 0x3022
+MX28_PAD_AUART0_RTS__DUART_TX 0x3032
+MX28_PAD_AUART1_RX__PWM_0 0x3042
+MX28_PAD_AUART1_TX__PWM_1 0x3052
+MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062
+MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072
+MX28_PAD_AUART2_RX__SSP3_D4 0x3082
+MX28_PAD_AUART2_TX__SSP3_D5 0x3092
+MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2
+MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2
+MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2
+MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2
+MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2
+MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2
+MX28_PAD_PWM0__DUART_RX 0x3102
+MX28_PAD_PWM1__DUART_TX 0x3112
+MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122
+MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142
+MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152
+MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162
+MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172
+MX28_PAD_I2C0_SCL__DUART_RX 0x3182
+MX28_PAD_I2C0_SDA__DUART_TX 0x3192
+MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2
+MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2
+MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002
+MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012
+MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022
+MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032
+MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052
+MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092
+MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2
+MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2
+MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2
+MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2
+MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2
+MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2
+MX28_PAD_GPMI_D00__GPIO_0_0 0x0003
+MX28_PAD_GPMI_D01__GPIO_0_1 0x0013
+MX28_PAD_GPMI_D02__GPIO_0_2 0x0023
+MX28_PAD_GPMI_D03__GPIO_0_3 0x0033
+MX28_PAD_GPMI_D04__GPIO_0_4 0x0043
+MX28_PAD_GPMI_D05__GPIO_0_5 0x0053
+MX28_PAD_GPMI_D06__GPIO_0_6 0x0063
+MX28_PAD_GPMI_D07__GPIO_0_7 0x0073
+MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103
+MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113
+MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123
+MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133
+MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143
+MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153
+MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163
+MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173
+MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183
+MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193
+MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3
+MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3
+MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3
+MX28_PAD_LCD_D00__GPIO_1_0 0x1003
+MX28_PAD_LCD_D01__GPIO_1_1 0x1013
+MX28_PAD_LCD_D02__GPIO_1_2 0x1023
+MX28_PAD_LCD_D03__GPIO_1_3 0x1033
+MX28_PAD_LCD_D04__GPIO_1_4 0x1043
+MX28_PAD_LCD_D05__GPIO_1_5 0x1053
+MX28_PAD_LCD_D06__GPIO_1_6 0x1063
+MX28_PAD_LCD_D07__GPIO_1_7 0x1073
+MX28_PAD_LCD_D08__GPIO_1_8 0x1083
+MX28_PAD_LCD_D09__GPIO_1_9 0x1093
+MX28_PAD_LCD_D10__GPIO_1_10 0x10a3
+MX28_PAD_LCD_D11__GPIO_1_11 0x10b3
+MX28_PAD_LCD_D12__GPIO_1_12 0x10c3
+MX28_PAD_LCD_D13__GPIO_1_13 0x10d3
+MX28_PAD_LCD_D14__GPIO_1_14 0x10e3
+MX28_PAD_LCD_D15__GPIO_1_15 0x10f3
+MX28_PAD_LCD_D16__GPIO_1_16 0x1103
+MX28_PAD_LCD_D17__GPIO_1_17 0x1113
+MX28_PAD_LCD_D18__GPIO_1_18 0x1123
+MX28_PAD_LCD_D19__GPIO_1_19 0x1133
+MX28_PAD_LCD_D20__GPIO_1_20 0x1143
+MX28_PAD_LCD_D21__GPIO_1_21 0x1153
+MX28_PAD_LCD_D22__GPIO_1_22 0x1163
+MX28_PAD_LCD_D23__GPIO_1_23 0x1173
+MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183
+MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193
+MX28_PAD_LCD_RS__GPIO_1_26 0x11a3
+MX28_PAD_LCD_CS__GPIO_1_27 0x11b3
+MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3
+MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3
+MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3
+MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3
+MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003
+MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013
+MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023
+MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033
+MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043
+MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053
+MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063
+MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073
+MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083
+MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093
+MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3
+MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3
+MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3
+MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3
+MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3
+MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103
+MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113
+MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123
+MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133
+MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143
+MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153
+MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183
+MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193
+MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3
+MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3
+MX28_PAD_AUART0_RX__GPIO_3_0 0x3003
+MX28_PAD_AUART0_TX__GPIO_3_1 0x3013
+MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023
+MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033
+MX28_PAD_AUART1_RX__GPIO_3_4 0x3043
+MX28_PAD_AUART1_TX__GPIO_3_5 0x3053
+MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063
+MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073
+MX28_PAD_AUART2_RX__GPIO_3_8 0x3083
+MX28_PAD_AUART2_TX__GPIO_3_9 0x3093
+MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3
+MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3
+MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3
+MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3
+MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3
+MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3
+MX28_PAD_PWM0__GPIO_3_16 0x3103
+MX28_PAD_PWM1__GPIO_3_17 0x3113
+MX28_PAD_PWM2__GPIO_3_18 0x3123
+MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143
+MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153
+MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163
+MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173
+MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183
+MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193
+MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3
+MX28_PAD_SPDIF__GPIO_3_27 0x31b3
+MX28_PAD_PWM3__GPIO_3_28 0x31c3
+MX28_PAD_PWM4__GPIO_3_29 0x31d3
+MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3
+MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003
+MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013
+MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023
+MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033
+MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043
+MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053
+MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063
+MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073
+MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083
+MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093
+MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3
+MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3
+MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3
+MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3
+MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3
+MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3
+MX28_PAD_ENET_CLK__GPIO_4_16 0x4103
+MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143
+
+Valid values for i.MX23 pinmux-id:
+
+pinmux id
+------ --
+MX23_PAD_GPMI_D00__GPMI_D00 0x0000
+MX23_PAD_GPMI_D01__GPMI_D01 0x0010
+MX23_PAD_GPMI_D02__GPMI_D02 0x0020
+MX23_PAD_GPMI_D03__GPMI_D03 0x0030
+MX23_PAD_GPMI_D04__GPMI_D04 0x0040
+MX23_PAD_GPMI_D05__GPMI_D05 0x0050
+MX23_PAD_GPMI_D06__GPMI_D06 0x0060
+MX23_PAD_GPMI_D07__GPMI_D07 0x0070
+MX23_PAD_GPMI_D08__GPMI_D08 0x0080
+MX23_PAD_GPMI_D09__GPMI_D09 0x0090
+MX23_PAD_GPMI_D10__GPMI_D10 0x00a0
+MX23_PAD_GPMI_D11__GPMI_D11 0x00b0
+MX23_PAD_GPMI_D12__GPMI_D12 0x00c0
+MX23_PAD_GPMI_D13__GPMI_D13 0x00d0
+MX23_PAD_GPMI_D14__GPMI_D14 0x00e0
+MX23_PAD_GPMI_D15__GPMI_D15 0x00f0
+MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100
+MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110
+MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
+MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130
+MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140
+MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150
+MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160
+MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170
+MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180
+MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190
+MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0
+MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0
+MX23_PAD_AUART1_RX__AUART1_RX 0x01c0
+MX23_PAD_AUART1_TX__AUART1_TX 0x01d0
+MX23_PAD_I2C_SCL__I2C_SCL 0x01e0
+MX23_PAD_I2C_SDA__I2C_SDA 0x01f0
+MX23_PAD_LCD_D00__LCD_D00 0x1000
+MX23_PAD_LCD_D01__LCD_D01 0x1010
+MX23_PAD_LCD_D02__LCD_D02 0x1020
+MX23_PAD_LCD_D03__LCD_D03 0x1030
+MX23_PAD_LCD_D04__LCD_D04 0x1040
+MX23_PAD_LCD_D05__LCD_D05 0x1050
+MX23_PAD_LCD_D06__LCD_D06 0x1060
+MX23_PAD_LCD_D07__LCD_D07 0x1070
+MX23_PAD_LCD_D08__LCD_D08 0x1080
+MX23_PAD_LCD_D09__LCD_D09 0x1090
+MX23_PAD_LCD_D10__LCD_D10 0x10a0
+MX23_PAD_LCD_D11__LCD_D11 0x10b0
+MX23_PAD_LCD_D12__LCD_D12 0x10c0
+MX23_PAD_LCD_D13__LCD_D13 0x10d0
+MX23_PAD_LCD_D14__LCD_D14 0x10e0
+MX23_PAD_LCD_D15__LCD_D15 0x10f0
+MX23_PAD_LCD_D16__LCD_D16 0x1100
+MX23_PAD_LCD_D17__LCD_D17 0x1110
+MX23_PAD_LCD_RESET__LCD_RESET 0x1120
+MX23_PAD_LCD_RS__LCD_RS 0x1130
+MX23_PAD_LCD_WR__LCD_WR 0x1140
+MX23_PAD_LCD_CS__LCD_CS 0x1150
+MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160
+MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170
+MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180
+MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190
+MX23_PAD_PWM0__PWM0 0x11a0
+MX23_PAD_PWM1__PWM1 0x11b0
+MX23_PAD_PWM2__PWM2 0x11c0
+MX23_PAD_PWM3__PWM3 0x11d0
+MX23_PAD_PWM4__PWM4 0x11e0
+MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000
+MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010
+MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020
+MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030
+MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040
+MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050
+MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060
+MX23_PAD_ROTARYA__ROTARYA 0x2070
+MX23_PAD_ROTARYB__ROTARYB 0x2080
+MX23_PAD_EMI_A00__EMI_A00 0x2090
+MX23_PAD_EMI_A01__EMI_A01 0x20a0
+MX23_PAD_EMI_A02__EMI_A02 0x20b0
+MX23_PAD_EMI_A03__EMI_A03 0x20c0
+MX23_PAD_EMI_A04__EMI_A04 0x20d0
+MX23_PAD_EMI_A05__EMI_A05 0x20e0
+MX23_PAD_EMI_A06__EMI_A06 0x20f0
+MX23_PAD_EMI_A07__EMI_A07 0x2100
+MX23_PAD_EMI_A08__EMI_A08 0x2110
+MX23_PAD_EMI_A09__EMI_A09 0x2120
+MX23_PAD_EMI_A10__EMI_A10 0x2130
+MX23_PAD_EMI_A11__EMI_A11 0x2140
+MX23_PAD_EMI_A12__EMI_A12 0x2150
+MX23_PAD_EMI_BA0__EMI_BA0 0x2160
+MX23_PAD_EMI_BA1__EMI_BA1 0x2170
+MX23_PAD_EMI_CASN__EMI_CASN 0x2180
+MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190
+MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0
+MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0
+MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0
+MX23_PAD_EMI_CKE__EMI_CKE 0x21d0
+MX23_PAD_EMI_RASN__EMI_RASN 0x21e0
+MX23_PAD_EMI_WEN__EMI_WEN 0x21f0
+MX23_PAD_EMI_D00__EMI_D00 0x3000
+MX23_PAD_EMI_D01__EMI_D01 0x3010
+MX23_PAD_EMI_D02__EMI_D02 0x3020
+MX23_PAD_EMI_D03__EMI_D03 0x3030
+MX23_PAD_EMI_D04__EMI_D04 0x3040
+MX23_PAD_EMI_D05__EMI_D05 0x3050
+MX23_PAD_EMI_D06__EMI_D06 0x3060
+MX23_PAD_EMI_D07__EMI_D07 0x3070
+MX23_PAD_EMI_D08__EMI_D08 0x3080
+MX23_PAD_EMI_D09__EMI_D09 0x3090
+MX23_PAD_EMI_D10__EMI_D10 0x30a0
+MX23_PAD_EMI_D11__EMI_D11 0x30b0
+MX23_PAD_EMI_D12__EMI_D12 0x30c0
+MX23_PAD_EMI_D13__EMI_D13 0x30d0
+MX23_PAD_EMI_D14__EMI_D14 0x30e0
+MX23_PAD_EMI_D15__EMI_D15 0x30f0
+MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100
+MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110
+MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120
+MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130
+MX23_PAD_EMI_CLK__EMI_CLK 0x3140
+MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150
+MX23_PAD_GPMI_D00__LCD_D8 0x0001
+MX23_PAD_GPMI_D01__LCD_D9 0x0011
+MX23_PAD_GPMI_D02__LCD_D10 0x0021
+MX23_PAD_GPMI_D03__LCD_D11 0x0031
+MX23_PAD_GPMI_D04__LCD_D12 0x0041
+MX23_PAD_GPMI_D05__LCD_D13 0x0051
+MX23_PAD_GPMI_D06__LCD_D14 0x0061
+MX23_PAD_GPMI_D07__LCD_D15 0x0071
+MX23_PAD_GPMI_D08__LCD_D18 0x0081
+MX23_PAD_GPMI_D09__LCD_D19 0x0091
+MX23_PAD_GPMI_D10__LCD_D20 0x00a1
+MX23_PAD_GPMI_D11__LCD_D21 0x00b1
+MX23_PAD_GPMI_D12__LCD_D22 0x00c1
+MX23_PAD_GPMI_D13__LCD_D23 0x00d1
+MX23_PAD_GPMI_D14__AUART2_RX 0x00e1
+MX23_PAD_GPMI_D15__AUART2_TX 0x00f1
+MX23_PAD_GPMI_CLE__LCD_D16 0x0101
+MX23_PAD_GPMI_ALE__LCD_D17 0x0111
+MX23_PAD_GPMI_CE2N__ATA_A2 0x0121
+MX23_PAD_AUART1_RTS__IR_CLK 0x01b1
+MX23_PAD_AUART1_RX__IR_RX 0x01c1
+MX23_PAD_AUART1_TX__IR_TX 0x01d1
+MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1
+MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1
+MX23_PAD_LCD_D00__ETM_DA8 0x1001
+MX23_PAD_LCD_D01__ETM_DA9 0x1011
+MX23_PAD_LCD_D02__ETM_DA10 0x1021
+MX23_PAD_LCD_D03__ETM_DA11 0x1031
+MX23_PAD_LCD_D04__ETM_DA12 0x1041
+MX23_PAD_LCD_D05__ETM_DA13 0x1051
+MX23_PAD_LCD_D06__ETM_DA14 0x1061
+MX23_PAD_LCD_D07__ETM_DA15 0x1071
+MX23_PAD_LCD_D08__ETM_DA0 0x1081
+MX23_PAD_LCD_D09__ETM_DA1 0x1091
+MX23_PAD_LCD_D10__ETM_DA2 0x10a1
+MX23_PAD_LCD_D11__ETM_DA3 0x10b1
+MX23_PAD_LCD_D12__ETM_DA4 0x10c1
+MX23_PAD_LCD_D13__ETM_DA5 0x10d1
+MX23_PAD_LCD_D14__ETM_DA6 0x10e1
+MX23_PAD_LCD_D15__ETM_DA7 0x10f1
+MX23_PAD_LCD_RESET__ETM_TCTL 0x1121
+MX23_PAD_LCD_RS__ETM_TCLK 0x1131
+MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161
+MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171
+MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181
+MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191
+MX23_PAD_PWM0__ROTARYA 0x11a1
+MX23_PAD_PWM1__ROTARYB 0x11b1
+MX23_PAD_PWM2__GPMI_RDY3 0x11c1
+MX23_PAD_PWM3__ETM_TCTL 0x11d1
+MX23_PAD_PWM4__ETM_TCLK 0x11e1
+MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011
+MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031
+MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041
+MX23_PAD_ROTARYA__AUART2_RTS 0x2071
+MX23_PAD_ROTARYB__AUART2_CTS 0x2081
+MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002
+MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012
+MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022
+MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032
+MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042
+MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052
+MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062
+MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072
+MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082
+MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092
+MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2
+MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2
+MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2
+MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132
+MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142
+MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182
+MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2
+MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2
+MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2
+MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2
+MX23_PAD_I2C_SCL__AUART1_TX 0x01e2
+MX23_PAD_I2C_SDA__AUART1_RX 0x01f2
+MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082
+MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092
+MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2
+MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2
+MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2
+MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2
+MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2
+MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2
+MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102
+MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122
+MX23_PAD_PWM0__DUART_RX 0x11a2
+MX23_PAD_PWM1__DUART_TX 0x11b2
+MX23_PAD_PWM3__AUART1_CTS 0x11d2
+MX23_PAD_PWM4__AUART1_RTS 0x11e2
+MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002
+MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012
+MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022
+MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032
+MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042
+MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052
+MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062
+MX23_PAD_ROTARYA__SPDIF 0x2072
+MX23_PAD_ROTARYB__GPMI_CE3N 0x2082
+MX23_PAD_GPMI_D00__GPIO_0_0 0x0003
+MX23_PAD_GPMI_D01__GPIO_0_1 0x0013
+MX23_PAD_GPMI_D02__GPIO_0_2 0x0023
+MX23_PAD_GPMI_D03__GPIO_0_3 0x0033
+MX23_PAD_GPMI_D04__GPIO_0_4 0x0043
+MX23_PAD_GPMI_D05__GPIO_0_5 0x0053
+MX23_PAD_GPMI_D06__GPIO_0_6 0x0063
+MX23_PAD_GPMI_D07__GPIO_0_7 0x0073
+MX23_PAD_GPMI_D08__GPIO_0_8 0x0083
+MX23_PAD_GPMI_D09__GPIO_0_9 0x0093
+MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3
+MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3
+MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3
+MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3
+MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3
+MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3
+MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103
+MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113
+MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123
+MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133
+MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143
+MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153
+MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163
+MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173
+MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183
+MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193
+MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3
+MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3
+MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3
+MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3
+MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3
+MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3
+MX23_PAD_LCD_D00__GPIO_1_0 0x1003
+MX23_PAD_LCD_D01__GPIO_1_1 0x1013
+MX23_PAD_LCD_D02__GPIO_1_2 0x1023
+MX23_PAD_LCD_D03__GPIO_1_3 0x1033
+MX23_PAD_LCD_D04__GPIO_1_4 0x1043
+MX23_PAD_LCD_D05__GPIO_1_5 0x1053
+MX23_PAD_LCD_D06__GPIO_1_6 0x1063
+MX23_PAD_LCD_D07__GPIO_1_7 0x1073
+MX23_PAD_LCD_D08__GPIO_1_8 0x1083
+MX23_PAD_LCD_D09__GPIO_1_9 0x1093
+MX23_PAD_LCD_D10__GPIO_1_10 0x10a3
+MX23_PAD_LCD_D11__GPIO_1_11 0x10b3
+MX23_PAD_LCD_D12__GPIO_1_12 0x10c3
+MX23_PAD_LCD_D13__GPIO_1_13 0x10d3
+MX23_PAD_LCD_D14__GPIO_1_14 0x10e3
+MX23_PAD_LCD_D15__GPIO_1_15 0x10f3
+MX23_PAD_LCD_D16__GPIO_1_16 0x1103
+MX23_PAD_LCD_D17__GPIO_1_17 0x1113
+MX23_PAD_LCD_RESET__GPIO_1_18 0x1123
+MX23_PAD_LCD_RS__GPIO_1_19 0x1133
+MX23_PAD_LCD_WR__GPIO_1_20 0x1143
+MX23_PAD_LCD_CS__GPIO_1_21 0x1153
+MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163
+MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173
+MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183
+MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193
+MX23_PAD_PWM0__GPIO_1_26 0x11a3
+MX23_PAD_PWM1__GPIO_1_27 0x11b3
+MX23_PAD_PWM2__GPIO_1_28 0x11c3
+MX23_PAD_PWM3__GPIO_1_29 0x11d3
+MX23_PAD_PWM4__GPIO_1_30 0x11e3
+MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003
+MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013
+MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023
+MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033
+MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043
+MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053
+MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063
+MX23_PAD_ROTARYA__GPIO_2_7 0x2073
+MX23_PAD_ROTARYB__GPIO_2_8 0x2083
+MX23_PAD_EMI_A00__GPIO_2_9 0x2093
+MX23_PAD_EMI_A01__GPIO_2_10 0x20a3
+MX23_PAD_EMI_A02__GPIO_2_11 0x20b3
+MX23_PAD_EMI_A03__GPIO_2_12 0x20c3
+MX23_PAD_EMI_A04__GPIO_2_13 0x20d3
+MX23_PAD_EMI_A05__GPIO_2_14 0x20e3
+MX23_PAD_EMI_A06__GPIO_2_15 0x20f3
+MX23_PAD_EMI_A07__GPIO_2_16 0x2103
+MX23_PAD_EMI_A08__GPIO_2_17 0x2113
+MX23_PAD_EMI_A09__GPIO_2_18 0x2123
+MX23_PAD_EMI_A10__GPIO_2_19 0x2133
+MX23_PAD_EMI_A11__GPIO_2_20 0x2143
+MX23_PAD_EMI_A12__GPIO_2_21 0x2153
+MX23_PAD_EMI_BA0__GPIO_2_22 0x2163
+MX23_PAD_EMI_BA1__GPIO_2_23 0x2173
+MX23_PAD_EMI_CASN__GPIO_2_24 0x2183
+MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193
+MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3
+MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3
+MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3
+MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3
+MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3
+MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
new file mode 100644
index 000000000000..c8e578263ce2
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
@@ -0,0 +1,132 @@
+NVIDIA Tegra20 pinmux controller
+
+Required properties:
+- compatible: "nvidia,tegra20-pinmux"
+- reg: Should contain the register physical address and length for each of
+ the tri-state, mux, pull-up/down, and pad control register sets.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Tegra's pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, tristate, drive strength, etc.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function or tristate parameter. For this
+reason, even seemingly boolean values are actually tristates in this binding:
+unspecified, off, or on. Unspecified is represented as an absent property,
+and off/on are represented as integer values 0 and 1.
+
+Required subnode-properties:
+- nvidia,pins : An array of strings. Each string contains the name of a pin or
+ group. Valid values for these names are listed below.
+
+Optional subnode-properties:
+- nvidia,function: A string containing the name of the function to mux to the
+ pin or group. Valid values for function names are listed below. See the Tegra
+ TRM to determine which are valid for each pin or group.
+- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
+ 0: none, 1: down, 2: up.
+- nvidia,tristate: Integer.
+ 0: drive, 1: tristate.
+- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
+ 0: no, 1: yes.
+- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
+ 0: no, 1: yes.
+- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
+ most power. Controls the drive power or current. See "Low Power Mode"
+ or "LPMD1" and "LPMD0" in the Tegra TRM.
+- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
+ The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
+ Tegra TRM.
+- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
+ The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
+ Tegra TRM.
+- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
+ fastest. The range of valid values depends on the pingroup. See
+ "DRVDN_SLWR" in the Tegra TRM.
+- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
+ fastest. The range of valid values depends on the pingroup. See
+ "DRVUP_SLWF" in the Tegra TRM.
+
+Note that many of these properties are only valid for certain specific pins
+or groups. See the Tegra TRM and various pinmux spreadsheets for complete
+details regarding which groups support which functionality. The Linux pinctrl
+driver may also be a useful reference, since it consolidates, disambiguates,
+and corrects data from all those sources.
+
+Valid values for pin and group names are:
+
+ mux groups:
+
+ These all support nvidia,function, nvidia,tristate, and many support
+ nvidia,pull.
+
+ ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
+ ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
+ gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
+ ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
+ ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
+ lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
+ owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
+ spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
+ uca, ucb, uda.
+
+ tristate groups:
+
+ These only support nvidia,pull.
+
+ ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
+ ld19_18, ld21_20, ld23_22.
+
+ drive groups:
+
+ With some exceptions, these support nvidia,high-speed-mode,
+ nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
+ nvidia,pull-up-strength, nvidia,slew_rate-rising, nvidia,slew_rate-falling.
+
+ drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
+ drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
+ drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
+ drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
+ drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
+ drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
+ drive_uda.
+
+Example:
+
+ pinctrl@70000000 {
+ compatible = "nvidia,tegra20-pinmux";
+ reg = < 0x70000014 0x10 /* Tri-state registers */
+ 0x70000080 0x20 /* Mux registers */
+ 0x700000a0 0x14 /* Pull-up/down registers */
+ 0x70000868 0xa8 >; /* Pad control registers */
+ };
+
+Example board file extract:
+
+ pinctrl@70000000 {
+ sdio4_default: sdio4_default {
+ atb {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ };
+ };
+
+ sdhci@c8000600 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio4_default>;
+ };
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
new file mode 100644
index 000000000000..c275b70349c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
@@ -0,0 +1,132 @@
+NVIDIA Tegra30 pinmux controller
+
+The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
+as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
+that binding as a baseline, and only documents the differences between the
+two bindings.
+
+Required properties:
+- compatible: "nvidia,tegra30-pinmux"
+- reg: Should contain the register physical address and length for each of
+ the pad control and mux registers.
+
+Tegra30 adds the following optional properties for pin configuration subnodes:
+- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
+- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
+- nvidia,lock: Integer. Lock the pin configuration against further changes
+ until reset. 0: no, 1: yes.
+- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
+
+As with Tegra20, see the Tegra TRM for complete details regarding which groups
+support which functionality.
+
+Valid values for pin and group names are:
+
+ per-pin mux groups:
+
+ These all support nvidia,function, nvidia,tristate, nvidia,pull,
+ nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
+ nvidia,io-reset.
+
+ clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3,
+ dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0,
+ gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
+ sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1,
+ uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5,
+ lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2,
+ sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7,
+ lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5,
+ lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3,
+ lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0,
+ gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
+ gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
+ gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
+ gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4,
+ gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1,
+ gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
+ uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2,
+ gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7,
+ vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5,
+ vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
+ lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0,
+ dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5,
+ lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
+ ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
+ ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3,
+ dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0,
+ kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
+ kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
+ kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
+ kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
+ kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
+ vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
+ sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0,
+ pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7,
+ lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
+ clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1,
+ spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6,
+ spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3,
+ sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
+ sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4,
+ sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0,
+ sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
+ sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
+ cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7,
+ cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4,
+ clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7,
+ pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
+ pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
+ pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1,
+ clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr,
+ pwr_int_n.
+
+ drive groups:
+
+ These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
+ nvidia,slew_rate-rising, nvidia,slew_rate-falling. Most but not all
+ support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
+
+ ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,
+ dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg,
+ gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
+ uart3, uda, vi1.
+
+Example:
+
+ pinctrl@70000000 {
+ compatible = "nvidia,tegra30-pinmux";
+ reg = < 0x70000868 0xd0 /* Pad control registers */
+ 0x70003000 0x3e0 >; /* Mux registers */
+ };
+
+Example board file extract:
+
+ pinctrl@70000000 {
+ sdmmc4_default: pinmux {
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4",
+ "sdmmc4_rst_n_pcc3";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ sdmmc4_dat0_paa0 {
+ nvidia,pins = "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ };
+ };
+
+ sdhci@78000400 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc4_default>;
+ };
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
new file mode 100644
index 000000000000..c95ea8278f87
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@@ -0,0 +1,128 @@
+== Introduction ==
+
+Hardware modules that control pin multiplexing or configuration parameters
+such as pull-up/down, tri-state, drive-strength etc are designated as pin
+controllers. Each pin controller must be represented as a node in device tree,
+just like any other hardware module.
+
+Hardware modules whose signals are affected by pin configuration are
+designated client devices. Again, each client device must be represented as a
+node in device tree, just like any other hardware module.
+
+For a client device to operate correctly, certain pin controllers must
+set up certain specific pin configurations. Some client devices need a
+single static pin configuration, e.g. set up during initialization. Others
+need to reconfigure pins at run-time, for example to tri-state pins when the
+device is inactive. Hence, each client device can define a set of named
+states. The number and names of those states is defined by the client device's
+own binding.
+
+The common pinctrl bindings defined in this file provide an infrastructure
+for client device device tree nodes to map those state names to the pin
+configuration used by those states.
+
+Note that pin controllers themselves may also be client devices of themselves.
+For example, a pin controller may set up its own "active" state when the
+driver loads. This would allow representing a board's static pin configuration
+in a single place, rather than splitting it across multiple client device
+nodes. The decision to do this or not somewhat rests with the author of
+individual board device tree files, and any requirements imposed by the
+bindings for the individual client devices in use by that board, i.e. whether
+they require certain specific named states for dynamic pin configuration.
+
+== Pinctrl client devices ==
+
+For each client device individually, every pin state is assigned an integer
+ID. These numbers start at 0, and are contiguous. For each state ID, a unique
+property exists to define the pin configuration. Each state may also be
+assigned a name. When names are used, another property exists to map from
+those names to the integer IDs.
+
+Each client device's own binding determines the set of states the must be
+defined in its device tree node, and whether to define the set of state
+IDs that must be provided, or whether to define the set of state names that
+must be provided.
+
+Required properties:
+pinctrl-0: List of phandles, each pointing at a pin configuration
+ node. These referenced pin configuration nodes must be child
+ nodes of the pin controller that they configure. Multiple
+ entries may exist in this list so that multiple pin
+ controllers may be configured, or so that a state may be built
+ from multiple nodes for a single pin controller, each
+ contributing part of the overall configuration. See the next
+ section of this document for details of the format of these
+ pin configuration nodes.
+
+ In some cases, it may be useful to define a state, but for it
+ to be empty. This may be required when a common IP block is
+ used in an SoC either without a pin controller, or where the
+ pin controller does not affect the HW module in question. If
+ the binding for that IP block requires certain pin states to
+ exist, they must still be defined, but may be left empty.
+
+Optional properties:
+pinctrl-1: List of phandles, each pointing at a pin configuration
+ node within a pin controller.
+...
+pinctrl-n: List of phandles, each pointing at a pin configuration
+ node within a pin controller.
+pinctrl-names: The list of names to assign states. List entry 0 defines the
+ name for integer state ID 0, list entry 1 for state ID 1, and
+ so on.
+
+For example:
+
+ /* For a client device requiring named states */
+ device {
+ pinctrl-names = "active", "idle";
+ pinctrl-0 = <&state_0_node_a>;
+ pinctrl-1 = <&state_1_node_a &state_1_node_b>;
+ };
+
+ /* For the same device if using state IDs */
+ device {
+ pinctrl-0 = <&state_0_node_a>;
+ pinctrl-1 = <&state_1_node_a &state_1_node_b>;
+ };
+
+ /*
+ * For an IP block whose binding supports pin configuration,
+ * but in use on an SoC that doesn't have any pin control hardware
+ */
+ device {
+ pinctrl-names = "active", "idle";
+ pinctrl-0 = <>;
+ pinctrl-1 = <>;
+ };
+
+== Pin controller devices ==
+
+Pin controller devices should contain the pin configuration nodes that client
+devices reference.
+
+For example:
+
+ pincontroller {
+ ... /* Standard DT properties for the device itself elided */
+
+ state_0_node_a {
+ ...
+ };
+ state_1_node_a {
+ ...
+ };
+ state_1_node_b {
+ ...
+ };
+ }
+
+The contents of each of those pin configuration child nodes is defined
+entirely by the binding for the individual pin controller device. There
+exists no common standard for this content.
+
+The pin configuration nodes need not be direct children of the pin controller
+device; they may be grandchildren, for example. Whether this is legal, and
+whether there is any interaction between the child and intermediate parent
+nodes, is again defined entirely by the binding for the individual pin
+controller device.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
new file mode 100644
index 000000000000..3664d37e6799
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
@@ -0,0 +1,108 @@
+ST Microelectronics, SPEAr pinmux controller
+
+Required properties:
+- compatible : "st,spear300-pinmux"
+ : "st,spear310-pinmux"
+ : "st,spear320-pinmux"
+- reg : Address range of the pinctrl registers
+- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
+ - Its values for SPEAr300:
+ - NAND_MODE : <0>
+ - NOR_MODE : <1>
+ - PHOTO_FRAME_MODE : <2>
+ - LEND_IP_PHONE_MODE : <3>
+ - HEND_IP_PHONE_MODE : <4>
+ - LEND_WIFI_PHONE_MODE : <5>
+ - HEND_WIFI_PHONE_MODE : <6>
+ - ATA_PABX_WI2S_MODE : <7>
+ - ATA_PABX_I2S_MODE : <8>
+ - CAML_LCDW_MODE : <9>
+ - CAMU_LCD_MODE : <10>
+ - CAMU_WLCD_MODE : <11>
+ - CAML_LCD_MODE : <12>
+ - Its values for SPEAr320:
+ - AUTO_NET_SMII_MODE : <0>
+ - AUTO_NET_MII_MODE : <1>
+ - AUTO_EXP_MODE : <2>
+ - SMALL_PRINTERS_MODE : <3>
+ - EXTENDED_MODE : <4>
+
+Please refer to pinctrl-bindings.txt in this directory for details of the common
+pinctrl bindings used by client devices.
+
+SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each
+of these subnodes represents muxing for a pin, a group, or a list of pins or
+groups.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Required subnode-properties:
+- st,pins : An array of strings. Each string contains the name of a pin or
+ group.
+- st,function: A string containing the name of the function to mux to the pin or
+ group. See the SPEAr's TRM to determine which are valid for each pin or group.
+
+ Valid values for group and function names can be found from looking at the
+ group and function arrays in driver files:
+ drivers/pinctrl/spear/pinctrl-spear3*0.c
+
+Valid values for group names are:
+For All SPEAr3xx machines:
+ "firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp",
+ "gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp",
+ "gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp",
+ "timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp"
+
+For SPEAr300 machines:
+ "fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp",
+ "clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp",
+ "dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp",
+ "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
+
+For SPEAr310 machines:
+ "emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp",
+ "uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp"
+
+For SPEAr320 machines:
+ "clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp",
+ "sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp",
+ "uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp",
+ "uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp",
+ "uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp",
+ "uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp",
+ "uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp",
+ "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
+ "uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp",
+ "uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp",
+ "uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp",
+ "can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp",
+ "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp",
+ "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp",
+ "pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp",
+ "pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp",
+ "pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp",
+ "pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp",
+ "ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp",
+ "ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp",
+ "ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp",
+ "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
+ "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
+
+Valid values for function names are:
+For All SPEAr3xx machines:
+ "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
+ "uart0", "timer_0_1", "timer_2_3"
+
+For SPEAr300 machines:
+ "fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1"
+
+For SPEAr310 machines:
+ "emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0",
+ "rs485_1", "tdm"
+
+For SPEAr320 machines:
+ "clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem",
+ "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
+ "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
+ "mii0_1", "i2c1", "i2c2"
diff --git a/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt b/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
deleted file mode 100644
index 36f82dbdd14d..000000000000
--- a/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-NVIDIA Tegra 2 pinmux controller
-
-Required properties:
-- compatible : "nvidia,tegra20-pinmux"
-
diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt
index 9faac6ae3525..950856bd2e39 100644
--- a/Documentation/driver-model/devres.txt
+++ b/Documentation/driver-model/devres.txt
@@ -280,3 +280,7 @@ REGULATOR
CLOCK
devm_clk_get()
devm_clk_put()
+
+PINCTRL
+ devm_pinctrl_get()
+ devm_pinctrl_put()
diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
index d97bccf46147..e40f4b4e1977 100644
--- a/Documentation/pinctrl.txt
+++ b/Documentation/pinctrl.txt
@@ -152,11 +152,9 @@ static const struct foo_group foo_groups[] = {
};
-static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int foo_get_groups_count(struct pinctrl_dev *pctldev)
{
- if (selector >= ARRAY_SIZE(foo_groups))
- return -EINVAL;
- return 0;
+ return ARRAY_SIZE(foo_groups);
}
static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
@@ -175,7 +173,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
}
static struct pinctrl_ops foo_pctrl_ops = {
- .list_groups = foo_list_groups,
+ .get_groups_count = foo_get_groups_count,
.get_group_name = foo_get_group_name,
.get_group_pins = foo_get_group_pins,
};
@@ -186,13 +184,12 @@ static struct pinctrl_desc foo_desc = {
.pctlops = &foo_pctrl_ops,
};
-The pin control subsystem will call the .list_groups() function repeatedly
-beginning on 0 until it returns non-zero to determine legal selectors, then
-it will call the other functions to retrieve the name and pins of the group.
-Maintaining the data structure of the groups is up to the driver, this is
-just a simple example - in practice you may need more entries in your group
-structure, for example specific register ranges associated with each group
-and so on.
+The pin control subsystem will call the .get_groups_count() function to
+determine total number of legal selectors, then it will call the other functions
+to retrieve the name and pins of the group. Maintaining the data structure of
+the groups is up to the driver, this is just a simple example - in practice you
+may need more entries in your group structure, for example specific register
+ranges associated with each group and so on.
Pin configuration
@@ -606,11 +603,9 @@ static const struct foo_group foo_groups[] = {
};
-static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int foo_get_groups_count(struct pinctrl_dev *pctldev)
{
- if (selector >= ARRAY_SIZE(foo_groups))
- return -EINVAL;
- return 0;
+ return ARRAY_SIZE(foo_groups);
}
static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
@@ -629,7 +624,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
}
static struct pinctrl_ops foo_pctrl_ops = {
- .list_groups = foo_list_groups,
+ .get_groups_count = foo_get_groups_count,
.get_group_name = foo_get_group_name,
.get_group_pins = foo_get_group_pins,
};
@@ -640,7 +635,7 @@ struct foo_pmx_func {
const unsigned num_groups;
};
-static const char * const spi0_groups[] = { "spi0_1_grp" };
+static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
static const char * const i2c0_groups[] = { "i2c0_grp" };
static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
"mmc0_3_grp" };
@@ -663,11 +658,9 @@ static const struct foo_pmx_func foo_functions[] = {
},
};
-int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
+int foo_get_functions_count(struct pinctrl_dev *pctldev)
{
- if (selector >= ARRAY_SIZE(foo_functions))
- return -EINVAL;
- return 0;
+ return ARRAY_SIZE(foo_functions);
}
const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
@@ -703,7 +696,7 @@ void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
}
struct pinmux_ops foo_pmxops = {
- .list_functions = foo_list_funcs,
+ .get_functions_count = foo_get_functions_count,
.get_function_name = foo_get_fname,
.get_function_groups = foo_get_groups,
.enable = foo_enable,
@@ -786,7 +779,7 @@ and spi on the second function mapping:
#include <linux/pinctrl/machine.h>
-static const struct pinctrl_map __initdata mapping[] = {
+static const struct pinctrl_map mapping[] __initconst = {
{
.dev_name = "foo-spi.0",
.name = PINCTRL_STATE_DEFAULT,
@@ -952,13 +945,13 @@ case), we define a mapping like this:
The result of grabbing this mapping from the device with something like
this (see next paragraph):
- p = pinctrl_get(dev);
+ p = devm_pinctrl_get(dev);
s = pinctrl_lookup_state(p, "8bit");
ret = pinctrl_select_state(p, s);
or more simply:
- p = pinctrl_get_select(dev, "8bit");
+ p = devm_pinctrl_get_select(dev, "8bit");
Will be that you activate all the three bottom records in the mapping at
once. Since they share the same name, pin controller device, function and
@@ -992,7 +985,7 @@ foo_probe()
/* Allocate a state holder named "foo" etc */
struct foo_state *foo = ...;
- foo->p = pinctrl_get(&device);
+ foo->p = devm_pinctrl_get(&device);
if (IS_ERR(foo->p)) {
/* FIXME: clean up "foo" here */
return PTR_ERR(foo->p);
@@ -1000,24 +993,17 @@ foo_probe()
foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
if (IS_ERR(foo->s)) {
- pinctrl_put(foo->p);
/* FIXME: clean up "foo" here */
return PTR_ERR(s);
}
ret = pinctrl_select_state(foo->s);
if (ret < 0) {
- pinctrl_put(foo->p);
/* FIXME: clean up "foo" here */
return ret;
}
}
-foo_remove()
-{
- pinctrl_put(state->p);
-}
-
This get/lookup/select/put sequence can just as well be handled by bus drivers
if you don't want each and every driver to handle it and you know the
arrangement on your bus.
@@ -1029,6 +1015,11 @@ The semantics of the pinctrl APIs are:
kernel memory to hold the pinmux state. All mapping table parsing or similar
slow operations take place within this API.
+- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
+ to be called automatically on the retrieved pointer when the associated
+ device is removed. It is recommended to use this function over plain
+ pinctrl_get().
+
- pinctrl_lookup_state() is called in process context to obtain a handle to a
specific state for a the client device. This operation may be slow too.
@@ -1041,14 +1032,30 @@ The semantics of the pinctrl APIs are:
- pinctrl_put() frees all information associated with a pinctrl handle.
+- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
+ explicitly destroy a pinctrl object returned by devm_pinctrl_get().
+ However, use of this function will be rare, due to the automatic cleanup
+ that will occur even without calling it.
+
+ pinctrl_get() must be paired with a plain pinctrl_put().
+ pinctrl_get() may not be paired with devm_pinctrl_put().
+ devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
+ devm_pinctrl_get() may not be paired with plain pinctrl_put().
+
Usually the pin control core handled the get/put pair and call out to the
device drivers bookkeeping operations, like checking available functions and
the associated pins, whereas the enable/disable pass on to the pin controller
driver which takes care of activating and/or deactivating the mux setting by
quickly poking some registers.
-The pins are allocated for your device when you issue the pinctrl_get() call,
-after this you should be able to see this in the debugfs listing of all pins.
+The pins are allocated for your device when you issue the devm_pinctrl_get()
+call, after this you should be able to see this in the debugfs listing of all
+pins.
+
+NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
+requested pinctrl handles, for example if the pinctrl driver has not yet
+registered. Thus make sure that the error path in your driver gracefully
+cleans up and is ready to retry the probing later in the startup process.
System pin control hogging
@@ -1094,13 +1101,13 @@ it, disables and releases it, and muxes it in on the pins defined by group B:
#include <linux/pinctrl/consumer.h>
-foo_switch()
-{
- struct pinctrl *p;
- struct pinctrl_state *s1, *s2;
+struct pinctrl *p;
+struct pinctrl_state *s1, *s2;
+foo_probe()
+{
/* Setup */
- p = pinctrl_get(&device);
+ p = devm_pinctrl_get(&device);
if (IS_ERR(p))
...
@@ -1111,7 +1118,10 @@ foo_switch()
s2 = pinctrl_lookup_state(foo->p, "pos-B");
if (IS_ERR(s2))
...
+}
+foo_switch()
+{
/* Enable on position A */
ret = pinctrl_select_state(s1);
if (ret < 0)
@@ -1125,8 +1135,6 @@ foo_switch()
...
...
-
- pinctrl_put(p);
}
The above has to be done from process context.
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