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author | Murali Karicheri <m-karicheri2@ti.com> | 2013-04-03 19:39:07 +0530 |
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committer | Sekhar Nori <nsekhar@ti.com> | 2013-04-17 22:19:18 +0530 |
commit | eed48556a789d2c7fd2dacbc0060e463ed72e449 (patch) | |
tree | 90d60263b959b269fccc6c2a13833a95d3395ac8 /Documentation | |
parent | 804413f2dd0bcef6d1aef7c8b3be749be9024eee (diff) | |
download | blackbird-op-linux-eed48556a789d2c7fd2dacbc0060e463ed72e449.tar.gz blackbird-op-linux-eed48556a789d2c7fd2dacbc0060e463ed72e449.zip |
spi/davinci: add DT binding documentation
Add binding documentation for spi-davinci module.
[prakash.pm@ti.com: Follow DT naming convention for compatible property]
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/spi/spi-davinci.txt | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Documentation/devicetree/bindings/spi/spi-davinci.txt new file mode 100644 index 000000000000..6d0ac8d0ad9b --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-davinci.txt @@ -0,0 +1,51 @@ +Davinci SPI controller device bindings + +Required properties: +- #address-cells: number of cells required to define a chip select + address on the SPI bus. Should be set to 1. +- #size-cells: should be zero. +- compatible: + - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family + - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family +- reg: Offset and length of SPI controller register space +- num-cs: Number of chip selects +- ti,davinci-spi-intr-line: interrupt line used to connect the SPI + IP to the interrupt controller within the SoC. Possible values + are 0 and 1. Manual says one of the two possible interrupt + lines can be tied to the interrupt controller. Set this + based on a specifc SoC configuration. +- interrupts: interrupt number mapped to CPU. +- clocks: spi clk phandle + +Example of a NOR flash slave device (n25q032) connected to DaVinci +SPI controller device over the SPI bus. + +spi0:spi@20BF0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,dm6446-spi"; + reg = <0x20BF0000 0x1000>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <338>; + clocks = <&clkspi>; + + flash: n25q032@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <25000000>; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "test"; + reg = <0x80000 0x380000>; + }; + }; +}; |