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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2013-08-09 22:27:11 +0200
committerJason Cooper <jason@lakedaemon.net>2013-09-30 14:58:12 +0000
commit31f614edb726fcc4d5aa0f2895fbdec9b04a3ca4 (patch)
treeeedc5350cb3c435039d435fbfef39e32873ad508 /Documentation/devicetree
parent627dfcc249e2eae07982272808ad560592e730e0 (diff)
downloadblackbird-op-linux-31f614edb726fcc4d5aa0f2895fbdec9b04a3ca4.tar.gz
blackbird-op-linux-31f614edb726fcc4d5aa0f2895fbdec9b04a3ca4.zip
irqchip: armada-370-xp: implement MSI support
This commit introduces the support for the MSI interrupts in the armada-370-xp interrupt controller driver. It registers an MSI chip to the MSI chip registry, which will be used by the Marvell PCIe host controller driver. The MSI interrupts use the 16 high doorbells, and are therefore notified using IRQ1 of the main interrupt controller. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt3
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
index 61df564c0d23..d74091a8a3bf 100644
--- a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
@@ -4,6 +4,8 @@ Marvell Armada 370 and Armada XP Interrupt Controller
Required properties:
- compatible: Should be "marvell,mpic"
- interrupt-controller: Identifies the node as an interrupt controller.
+- msi-controller: Identifies the node as an PCI Message Signaled
+ Interrupt controller.
- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
The cell is the IRQ number
@@ -24,6 +26,7 @@ Example:
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
+ msi-controller;
reg = <0xd0020a00 0x1d0>,
<0xd0021070 0x58>;
};
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