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authorJianqun Xu <xjq@rock-chips.com>2014-07-05 19:10:38 +0800
committerMark Brown <broonie@linaro.org>2014-07-09 09:39:28 +0200
commitd4796e35fb67df4ec36fa5914689ced8bc51a614 (patch)
treedf64a1e3d6a0177a2dd0ef3963a94ebd2884e3e6 /Documentation/devicetree/bindings/sound/rockchip-i2s.txt
parent7171511eaec5bf23fb06078f59784a3a0626b38f (diff)
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ASoC: dt-bindings: add rockchip i2s bindings
Add devicetree bindings for i2s controller found on rk3066, rk3188 and rk3288 processors from rockchip. Signed-off-by: Jianqun Xu <xjq@rock-chips.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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+* Rockchip I2S controller
+
+The I2S bus (Inter-IC sound bus) is a serial link for digital
+audio data transfer between devices in the system.
+
+Required properties:
+
+- compatible: should be one of the followings
+ - "rockchip,rk3066-i2s": for rk3066
+ - "rockchip,rk3188-i2s", "rockchip,rk3066-i2s": for rk3188
+ - "rockchip,rk3288-i2s", "rockchip,rk3066-i2s": for rk3288
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: should contain the I2S interrupt.
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
+ Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: should include "tx" and "rx".
+- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
+- clock-names: should contain followings:
+ - "i2s_hclk": clock for I2S BUS
+ - "i2s_clk" : clock for I2S controller
+
+Example for rk3288 I2S controller:
+
+i2s@ff890000 {
+ compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
+ reg = <0xff890000 0x10000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&pdma1 0>, <&pdma1 1>;
+ dma-names = "rx", "tx";
+ clock-names = "i2s_hclk", "i2s_clk";
+ clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+};
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