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authorFenghua Yu <fenghua.yu@intel.com>2014-05-29 11:12:30 -0700
committerH. Peter Anvin <hpa@linux.intel.com>2014-05-29 14:24:28 -0700
commit6229ad278ca74acdbc8bd3a3d469322a3de91039 (patch)
treed6e72f6129630ddbf3d46b9902fecf0fb331f364 /Documentation/arm
parent446fd806f5408b623fa51f3aa084e56844563779 (diff)
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x86/xsaves: Detect xsaves/xrstors feature
Detect the xsaveopt, xsavec, xgetbv, and xsaves features in processor extended state enumberation sub-leaf (eax=0x0d, ecx=1): Bit 00: XSAVEOPT is available Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set Bit 02: Supports XGETBV with ECX = 1 if set Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set The above features are defined in the new word 10 in cpu features. The IA32_XSS MSR (index DA0H) contains a state-component bitmap that specifies the state components that software has enabled xsaves and xrstors to manage. If the bit corresponding to a state component is clear in XCR0 | IA32_XSS, xsaves and xrstors will not operate on that state component, regardless of the value of the instruction mask. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Link: http://lkml.kernel.org/r/1401387164-43416-3-git-send-email-fenghua.yu@intel.com Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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