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authorMichael Hennerich <michael.hennerich@analog.com>2012-05-29 12:41:20 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-06-04 21:19:40 -0700
commite31166f0fd48478866ee9661c36789126435ebe8 (patch)
treec5a7b345c3331935318376558429ff6e2e092aef /Documentation/ABI/testing/sysfs-bus-iio-frequency-adf4350
parentcd1678f963298a9e777f3edb72d28bc18a3a32c2 (diff)
downloadblackbird-op-linux-e31166f0fd48478866ee9661c36789126435ebe8.tar.gz
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iio: frequency: New driver for Analog Devices ADF4350/ADF4351 Wideband Synthesizers
Changes since V1: Apply Jonathan's review feedback: Introduce and use IIO_ALTVOLTAGE. Fix up comments and documentation. Remove dead code. Reorder some code fragments. Add missing iio_device_free. Convert to new API. Fix-up out of staging includes. Removed pll_locked attribute. Changes since V2: Use module_spi_driver. adf4350_remove: move gpio_free after regulator. target patch to drivers/iio Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Acked-by: Jonathan Cameron <jic23@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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+What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_frequency_resolution
+KernelVersion: 3.4.0
+Contact: linux-iio@vger.kernel.org
+Description:
+ Stores channel Y frequency resolution/channel spacing in Hz.
+ The value given directly influences the MODULUS used by
+ the fractional-N PLL. It is assumed that the algorithm
+ that is used to compute the various dividers, is able to
+ generate proper values for multiples of channel spacing.
+
+What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_refin_frequency
+KernelVersion: 3.4.0
+Contact: linux-iio@vger.kernel.org
+Description:
+ Sets channel Y REFin frequency in Hz. In some clock chained
+ applications, the reference frequency used by the PLL may
+ change during runtime. This attribute allows the user to
+ adjust the reference frequency accordingly.
+ The value written has no effect until out_altvoltageY_frequency
+ is updated. Consider to use out_altvoltageY_powerdown to power
+ down the PLL and it's RFOut buffers during REFin changes.
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