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authorVishwanath BS <vishwanath.bs@ti.com>2010-02-22 22:09:09 -0700
committerPaul Walmsley <paul@pwsan.com>2010-02-24 12:15:03 -0700
commit678bc9a2eabb7f444ef8ad1cfc5ef394e2bd8bf2 (patch)
treed9849e2d6c57dee95dd72634a86b9bf097f45c1f /CREDITS
parent358965d7bab9c70c11b64931da02667b161cb03a (diff)
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OMAP3 clock: Introduce 3630 DPLL4 HSDivider changes
Divider (M2, M3, M4, M5 and M6) field width has been increased by 1 bit in 3630. This patch has changes to accommodate this in CM dynamically based on chip version. Basically new clock nodes have been added for 3630 DPLL4 M2,M3,M4,M5 and M6 and value of these nodes are used if cpu type is 3630. Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> [paul@pwsan.com: updated to apply on 2.6.34 queue; comments added] Signed-off-by: Paul Walmsley <paul@pwsan.com>
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