diff options
| author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2013-06-17 15:03:46 -0700 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-08-13 10:01:55 -0700 |
| commit | 252957cc3a2d59179df1a2d44d219e07dc5c3f06 (patch) | |
| tree | f9e548ba17bf89320f4c40ecebe403a75ea7efae | |
| parent | d4e4ab86bcba5a72779c43dc1459f71fea3d89c8 (diff) | |
| download | blackbird-op-linux-252957cc3a2d59179df1a2d44d219e07dc5c3f06.tar.gz blackbird-op-linux-252957cc3a2d59179df1a2d44d219e07dc5c3f06.zip | |
clk/zynq/clkc: Add dedicated spinlock for the SWDT
The clk_mux for the system watchdog timer reused the register lock
dedicated to the Ethernet module - for no apparent reason.
Add a lock dedicated to the SWDT's clock register to remove this
wrong dependency.
This does not fix a specific regression but the clock driver was merged
for 3.11-rc1, so best to fix the known bugs before the release.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: added to changelog]
| -rw-r--r-- | drivers/clk/zynq/clkc.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 5c205b60a82a..515a5732d391 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -71,6 +71,7 @@ static DEFINE_SPINLOCK(armpll_lock); static DEFINE_SPINLOCK(ddrpll_lock); static DEFINE_SPINLOCK(iopll_lock); static DEFINE_SPINLOCK(armclk_lock); +static DEFINE_SPINLOCK(swdtclk_lock); static DEFINE_SPINLOCK(ddrclk_lock); static DEFINE_SPINLOCK(dciclk_lock); static DEFINE_SPINLOCK(gem0clk_lock); @@ -293,7 +294,7 @@ static void __init zynq_clk_setup(struct device_node *np) } clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT, - SLCR_SWDT_CLK_SEL, 0, 1, 0, &gem0clk_lock); + SLCR_SWDT_CLK_SEL, 0, 1, 0, &swdtclk_lock); /* DDR clocks */ clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, |
