diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2006-05-18 12:38:47 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-06-19 17:39:19 +0100 |
| commit | b0b0e13e7dd309be13ab9324e67893e62b136e44 (patch) | |
| tree | 522f2ee785c8ab5600a254cabe8b2d0326425a0c | |
| parent | c583122c26ad04bb2379933dc5acc8b9479d6c67 (diff) | |
| download | blackbird-op-linux-b0b0e13e7dd309be13ab9324e67893e62b136e44.tar.gz blackbird-op-linux-b0b0e13e7dd309be13ab9324e67893e62b136e44.zip | |
[MIPS] Remove unused instances of prom_build_cpu_map.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/mips-boards/malta/malta_smp.c | 19 | ||||
| -rw-r--r-- | arch/mips/mips-boards/sim/sim_smp.c | 21 |
2 files changed, 0 insertions, 40 deletions
diff --git a/arch/mips/mips-boards/malta/malta_smp.c b/arch/mips/mips-boards/malta/malta_smp.c index 6c6c8eeedbce..cf967170fe29 100644 --- a/arch/mips/mips-boards/malta/malta_smp.c +++ b/arch/mips/mips-boards/malta/malta_smp.c @@ -34,25 +34,6 @@ void core_send_ipi(int cpu, unsigned int action) } /* - * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map - */ - -void __init prom_build_cpu_map(void) -{ - int nextslot; - - /* - * As of November, 2004, MIPSsim only simulates one core - * at a time. However, that core may be a MIPS MT core - * with multiple virtual processors and thread contexts. - */ - - if (read_c0_config3() & (1<<2)) { - nextslot = mipsmt_build_cpu_map(1); - } -} - -/* * Platform "CPU" startup hook */ diff --git a/arch/mips/mips-boards/sim/sim_smp.c b/arch/mips/mips-boards/sim/sim_smp.c index b7084e7c4bf9..004070956cca 100644 --- a/arch/mips/mips-boards/sim/sim_smp.c +++ b/arch/mips/mips-boards/sim/sim_smp.c @@ -51,27 +51,6 @@ void core_send_ipi(int cpu, unsigned int action) } /* - * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map - */ - -void __init prom_build_cpu_map(void) -{ -#ifdef CONFIG_MIPS_MT_SMTC - int nextslot; - - /* - * As of November, 2004, MIPSsim only simulates one core - * at a time. However, that core may be a MIPS MT core - * with multiple virtual processors and thread contexts. - */ - - if (read_c0_config3() & (1<<2)) { - nextslot = mipsmt_build_cpu_map(1); - } -#endif /* CONFIG_MIPS_MT_SMTC */ -} - -/* * Platform "CPU" startup hook */ |
