diff options
| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-16 20:56:49 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-16 20:56:49 -0800 |
| commit | a1bc5cdf9f9550bd7e9e5d8400e95b164165b275 (patch) | |
| tree | 3d4e80bb369675765e39450c55c6140e1213da81 | |
| parent | 8dca6f33f026dc8a7fc2710b78a7521e899bd611 (diff) | |
| parent | 859538763155814d217054eb6e3cdff71bdb4d89 (diff) | |
| download | blackbird-op-linux-a1bc5cdf9f9550bd7e9e5d8400e95b164165b275.tar.gz blackbird-op-linux-a1bc5cdf9f9550bd7e9e5d8400e95b164165b275.zip | |
Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
31 files changed, 2082 insertions, 1756 deletions
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c index bd87cb6b7a81..2ea4b39efffa 100644 --- a/arch/ia64/kernel/perfmon.c +++ b/arch/ia64/kernel/perfmon.c @@ -628,9 +628,11 @@ static int pfm_write_ibr_dbr(int mode, pfm_context_t *ctx, void *arg, int count, #include "perfmon_itanium.h" #include "perfmon_mckinley.h" +#include "perfmon_montecito.h" #include "perfmon_generic.h" static pmu_config_t *pmu_confs[]={ + &pmu_conf_mont, &pmu_conf_mck, &pmu_conf_ita, &pmu_conf_gen, /* must be last */ diff --git a/arch/ia64/kernel/perfmon_montecito.h b/arch/ia64/kernel/perfmon_montecito.h new file mode 100644 index 000000000000..cd06ac6a686c --- /dev/null +++ b/arch/ia64/kernel/perfmon_montecito.h @@ -0,0 +1,269 @@ +/* + * This file contains the Montecito PMU register description tables + * and pmc checker used by perfmon.c. + * + * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. + * Contributed by Stephane Eranian <eranian@hpl.hp.com> + */ +static int pfm_mont_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs); + +#define RDEP_MONT_ETB (RDEP(38)|RDEP(39)|RDEP(48)|RDEP(49)|RDEP(50)|RDEP(51)|RDEP(52)|RDEP(53)|RDEP(54)|\ + RDEP(55)|RDEP(56)|RDEP(57)|RDEP(58)|RDEP(59)|RDEP(60)|RDEP(61)|RDEP(62)|RDEP(63)) +#define RDEP_MONT_DEAR (RDEP(32)|RDEP(33)|RDEP(36)) +#define RDEP_MONT_IEAR (RDEP(34)|RDEP(35)) + +static pfm_reg_desc_t pfm_mont_pmc_desc[PMU_MAX_PMCS]={ +/* pmc0 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}}, +/* pmc1 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}}, +/* pmc2 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}}, +/* pmc3 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}}, +/* pmc4 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(4),0, 0, 0}, {0,0, 0, 0}}, +/* pmc5 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(5),0, 0, 0}, {0,0, 0, 0}}, +/* pmc6 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(6),0, 0, 0}, {0,0, 0, 0}}, +/* pmc7 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(7),0, 0, 0}, {0,0, 0, 0}}, +/* pmc8 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(8),0, 0, 0}, {0,0, 0, 0}}, +/* pmc9 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(9),0, 0, 0}, {0,0, 0, 0}}, +/* pmc10 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(10),0, 0, 0}, {0,0, 0, 0}}, +/* pmc11 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(11),0, 0, 0}, {0,0, 0, 0}}, +/* pmc12 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(12),0, 0, 0}, {0,0, 0, 0}}, +/* pmc13 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(13),0, 0, 0}, {0,0, 0, 0}}, +/* pmc14 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(14),0, 0, 0}, {0,0, 0, 0}}, +/* pmc15 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(15),0, 0, 0}, {0,0, 0, 0}}, +/* pmc16 */ { PFM_REG_NOTIMPL, }, +/* pmc17 */ { PFM_REG_NOTIMPL, }, +/* pmc18 */ { PFM_REG_NOTIMPL, }, +/* pmc19 */ { PFM_REG_NOTIMPL, }, +/* pmc20 */ { PFM_REG_NOTIMPL, }, +/* pmc21 */ { PFM_REG_NOTIMPL, }, +/* pmc22 */ { PFM_REG_NOTIMPL, }, +/* pmc23 */ { PFM_REG_NOTIMPL, }, +/* pmc24 */ { PFM_REG_NOTIMPL, }, +/* pmc25 */ { PFM_REG_NOTIMPL, }, +/* pmc26 */ { PFM_REG_NOTIMPL, }, +/* pmc27 */ { PFM_REG_NOTIMPL, }, +/* pmc28 */ { PFM_REG_NOTIMPL, }, +/* pmc29 */ { PFM_REG_NOTIMPL, }, +/* pmc30 */ { PFM_REG_NOTIMPL, }, +/* pmc31 */ { PFM_REG_NOTIMPL, }, +/* pmc32 */ { PFM_REG_CONFIG, 0, 0x30f01ffffffffff, 0x30f01ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}}, +/* pmc33 */ { PFM_REG_CONFIG, 0, 0x0, 0x1ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}}, +/* pmc34 */ { PFM_REG_CONFIG, 0, 0xf01ffffffffff, 0xf01ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}}, +/* pmc35 */ { PFM_REG_CONFIG, 0, 0x0, 0x1ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}}, +/* pmc36 */ { PFM_REG_CONFIG, 0, 0xfffffff0, 0xf, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}}, +/* pmc37 */ { PFM_REG_MONITOR, 4, 0x0, 0x3fff, NULL, pfm_mont_pmc_check, {RDEP_MONT_IEAR, 0, 0, 0}, {0, 0, 0, 0}}, +/* pmc38 */ { PFM_REG_CONFIG, 0, 0xdb6, 0x2492, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}}, +/* pmc39 */ { PFM_REG_MONITOR, 6, 0x0, 0xffcf, NULL, pfm_mont_pmc_check, {RDEP_MONT_ETB,0, 0, 0}, {0,0, 0, 0}}, +/* pmc40 */ { PFM_REG_MONITOR, 6, 0x2000000, 0xf01cf, NULL, pfm_mont_pmc_check, {RDEP_MONT_DEAR,0, 0, 0}, {0,0, 0, 0}}, +/* pmc41 */ { PFM_REG_CONFIG, 0, 0x00002078fefefefe, 0x1e00018181818, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}}, +/* pmc42 */ { PFM_REG_MONITOR, 6, 0x0, 0x7ff4f, NULL, pfm_mont_pmc_check, {RDEP_MONT_ETB,0, 0, 0}, {0,0, 0, 0}}, + { PFM_REG_END , 0, 0x0, -1, NULL, NULL, {0,}, {0,}}, /* end marker */ +}; + +static pfm_reg_desc_t pfm_mont_pmd_desc[PMU_MAX_PMDS]={ +/* pmd0 */ { PFM_REG_NOTIMPL, }, +/* pmd1 */ { PFM_REG_NOTIMPL, }, +/* pmd2 */ { PFM_REG_NOTIMPL, }, +/* pmd3 */ { PFM_REG_NOTIMPL, }, +/* pmd4 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(4),0, 0, 0}}, +/* pmd5 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(5),0, 0, 0}}, +/* pmd6 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(6),0, 0, 0}}, +/* pmd7 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(7),0, 0, 0}}, +/* pmd8 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(8),0, 0, 0}}, +/* pmd9 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(9),0, 0, 0}}, +/* pmd10 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(10),0, 0, 0}}, +/* pmd11 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(11),0, 0, 0}}, +/* pmd12 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(12),0, 0, 0}}, +/* pmd13 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(13),0, 0, 0}}, +/* pmd14 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(14),0, 0, 0}}, +/* pmd15 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(15),0, 0, 0}}, +/* pmd16 */ { PFM_REG_NOTIMPL, }, +/* pmd17 */ { PFM_REG_NOTIMPL, }, +/* pmd18 */ { PFM_REG_NOTIMPL, }, +/* pmd19 */ { PFM_REG_NOTIMPL, }, +/* pmd20 */ { PFM_REG_NOTIMPL, }, +/* pmd21 */ { PFM_REG_NOTIMPL, }, +/* pmd22 */ { PFM_REG_NOTIMPL, }, +/* pmd23 */ { PFM_REG_NOTIMPL, }, +/* pmd24 */ { PFM_REG_NOTIMPL, }, +/* pmd25 */ { PFM_REG_NOTIMPL, }, +/* pmd26 */ { PFM_REG_NOTIMPL, }, +/* pmd27 */ { PFM_REG_NOTIMPL, }, +/* pmd28 */ { PFM_REG_NOTIMPL, }, +/* pmd29 */ { PFM_REG_NOTIMPL, }, +/* pmd30 */ { PFM_REG_NOTIMPL, }, +/* pmd31 */ { PFM_REG_NOTIMPL, }, +/* pmd32 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(33)|RDEP(36),0, 0, 0}, {RDEP(40),0, 0, 0}}, +/* pmd33 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(32)|RDEP(36),0, 0, 0}, {RDEP(40),0, 0, 0}}, +/* pmd34 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(35),0, 0, 0}, {RDEP(37),0, 0, 0}}, +/* pmd35 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(34),0, 0, 0}, {RDEP(37),0, 0, 0}}, +/* pmd36 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(32)|RDEP(33),0, 0, 0}, {RDEP(40),0, 0, 0}}, +/* pmd37 */ { PFM_REG_NOTIMPL, }, +/* pmd38 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd39 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd40 */ { PFM_REG_NOTIMPL, }, +/* pmd41 */ { PFM_REG_NOTIMPL, }, +/* pmd42 */ { PFM_REG_NOTIMPL, }, +/* pmd43 */ { PFM_REG_NOTIMPL, }, +/* pmd44 */ { PFM_REG_NOTIMPL, }, +/* pmd45 */ { PFM_REG_NOTIMPL, }, +/* pmd46 */ { PFM_REG_NOTIMPL, }, +/* pmd47 */ { PFM_REG_NOTIMPL, }, +/* pmd48 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd49 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd50 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd51 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd52 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd53 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd54 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd55 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd56 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd57 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd58 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd59 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd60 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd61 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd62 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, +/* pmd63 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}}, + { PFM_REG_END , 0, 0x0, -1, NULL, NULL, {0,}, {0,}}, /* end marker */ +}; + +/* + * PMC reserved fields must have their power-up values preserved + */ +static int +pfm_mont_reserved(unsigned int cnum, unsigned long *val, struct pt_regs *regs) +{ + unsigned long tmp1, tmp2, ival = *val; + + /* remove reserved areas from user value */ + tmp1 = ival & PMC_RSVD_MASK(cnum); + + /* get reserved fields values */ + tmp2 = PMC_DFL_VAL(cnum) & ~PMC_RSVD_MASK(cnum); + + *val = tmp1 | tmp2; + + DPRINT(("pmc[%d]=0x%lx, mask=0x%lx, reset=0x%lx, val=0x%lx\n", + cnum, ival, PMC_RSVD_MASK(cnum), PMC_DFL_VAL(cnum), *val)); + return 0; +} + +/* + * task can be NULL if the context is unloaded + */ +static int +pfm_mont_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs) +{ + int ret = 0; + unsigned long val32 = 0, val38 = 0, val41 = 0; + unsigned long tmpval; + int check_case1 = 0; + int is_loaded; + + /* first preserve the reserved fields */ + pfm_mont_reserved(cnum, val, regs); + + tmpval = *val; + + /* sanity check */ + if (ctx == NULL) return -EINVAL; + + is_loaded = ctx->ctx_state == PFM_CTX_LOADED || ctx->ctx_state == PFM_CTX_MASKED; + + /* + * we must clear the debug registers if pmc41 has a value which enable + * memory pipeline event constraints. In this case we need to clear the + * the debug registers if they have not yet been accessed. This is required + * to avoid picking stale state. + * PMC41 is "active" if: + * one of the pmc41.cfg_dtagXX field is different from 0x3 + * AND + * at the corresponding pmc41.en_dbrpXX is set. + * AND + * ctx_fl_using_dbreg == 0 (i.e., dbr not yet used) + */ + DPRINT(("cnum=%u val=0x%lx, using_dbreg=%d loaded=%d\n", cnum, tmpval, ctx->ctx_fl_using_dbreg, is_loaded)); + + if (cnum == 41 && is_loaded + && (tmpval & 0x1e00000000000) && (tmpval & 0x18181818UL) != 0x18181818UL && ctx->ctx_fl_using_dbreg == 0) { + + DPRINT(("pmc[%d]=0x%lx has active pmc41 settings, clearing dbr\n", cnum, tmpval)); + + /* don't mix debug with perfmon */ + if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL; + + /* + * a count of 0 will mark the debug registers if: + * AND + */ + ret = pfm_write_ibr_dbr(PFM_DATA_RR, ctx, NULL, 0, regs); + if (ret) return ret; + } + /* + * we must clear the (instruction) debug registers if: + * pmc38.ig_ibrpX is 0 (enabled) + * AND + * ctx_fl_using_dbreg == 0 (i.e., dbr not yet used) + */ + if (cnum == 38 && is_loaded && ((tmpval & 0x492UL) != 0x492UL) && ctx->ctx_fl_using_dbreg == 0) { + + DPRINT(("pmc38=0x%lx has active pmc38 settings, clearing ibr\n", tmpval)); + + /* don't mix debug with perfmon */ + if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL; + + /* + * a count of 0 will mark the debug registers as in use and also + * ensure that they are properly cleared. + */ + ret = pfm_write_ibr_dbr(PFM_CODE_RR, ctx, NULL, 0, regs); + if (ret) return ret; + + } + switch(cnum) { + case 32: val32 = *val; + val38 = ctx->ctx_pmcs[38]; + val41 = ctx->ctx_pmcs[41]; + check_case1 = 1; + break; + case 38: val38 = *val; + val32 = ctx->ctx_pmcs[32]; + val41 = ctx->ctx_pmcs[41]; + check_case1 = 1; + break; + case 41: val41 = *val; + val32 = ctx->ctx_pmcs[32]; + val38 = ctx->ctx_pmcs[38]; + check_case1 = 1; + break; + } + /* check illegal configuration which can produce inconsistencies in tagging + * i-side events in L1D and L2 caches + */ + if (check_case1) { + ret = (((val41 >> 45) & 0xf) == 0 && ((val32>>57) & 0x1) == 0) + && ((((val38>>1) & 0x3) == 0x2 || ((val38>>1) & 0x3) == 0) + || (((val38>>4) & 0x3) == 0x2 || ((val38>>4) & 0x3) == 0)); + if (ret) { + DPRINT(("invalid config pmc38=0x%lx pmc41=0x%lx pmc32=0x%lx\n", val38, val41, val32)); + return -EINVAL; + } + } + *val = tmpval; + return 0; +} + +/* + * impl_pmcs, impl_pmds are computed at runtime to minimize errors! + */ +static pmu_config_t pmu_conf_mont={ + .pmu_name = "Montecito", + .pmu_family = 0x20, + .flags = PFM_PMU_IRQ_RESEND, + .ovfl_val = (1UL << 47) - 1, + .pmd_desc = pfm_mont_pmd_desc, + .pmc_desc = pfm_mont_pmc_desc, + .num_ibrs = 8, + .num_dbrs = 8, + .use_rr_dbregs = 1 /* debug register are use for range retrictions */ +}; diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c index e3215ba64ffd..b38b6d213c15 100644 --- a/arch/ia64/mm/init.c +++ b/arch/ia64/mm/init.c @@ -635,3 +635,39 @@ mem_init (void) ia32_mem_init(); #endif } + +#ifdef CONFIG_MEMORY_HOTPLUG +void online_page(struct page *page) +{ + ClearPageReserved(page); + set_page_count(page, 1); + __free_page(page); + totalram_pages++; + num_physpages++; +} + +int add_memory(u64 start, u64 size) +{ + pg_data_t *pgdat; + struct zone *zone; + unsigned long start_pfn = start >> PAGE_SHIFT; + unsigned long nr_pages = size >> PAGE_SHIFT; + int ret; + + pgdat = NODE_DATA(0); + + zone = pgdat->node_zones + ZONE_NORMAL; + ret = __add_pages(zone, start_pfn, nr_pages); + + if (ret) + printk("%s: Problem encountered in __add_pages() as ret=%d\n", + __FUNCTION__, ret); + + return ret; +} + +int remove_memory(u64 start, u64 size) +{ + return -EINVAL; +} +#endif diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c index 30dbc98bf0b3..d27ecdcb6fca 100644 --- a/arch/ia64/pci/pci.c +++ b/arch/ia64/pci/pci.c @@ -454,14 +454,13 @@ static int __devinit is_valid_resource(struct pci_dev *dev, int idx) return 0; } -static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev) +static void __devinit +pcibios_fixup_resources(struct pci_dev *dev, int start, int limit) { struct pci_bus_region region; int i; - int limit = (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) ? \ - PCI_BRIDGE_RESOURCES : PCI_NUM_RESOURCES; - for (i = 0; i < limit; i++) { + for (i = start; i < limit; i++) { if (!dev->resource[i].flags) continue; region.start = dev->resource[i].start; @@ -472,6 +471,16 @@ static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev) } } +static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev) +{ + pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES); +} + +static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev) +{ + pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES); +} + /* * Called after each bus is probed, but before its children are examined. */ @@ -482,7 +491,7 @@ pcibios_fixup_bus (struct pci_bus *b) if (b->self) { pci_read_bridge_bases(b); - pcibios_fixup_device_resources(b->self); + pcibios_fixup_bridge_resources(b->self); } list_for_each_entry(dev, &b->devices, bus_list) pcibios_fixup_device_resources(dev); diff --git a/arch/ia64/sn/include/xtalk/hubdev.h b/arch/ia64/sn/include/xtalk/hubdev.h index 4d417c301201..7c88e9a58516 100644 --- a/arch/ia64/sn/include/xtalk/hubdev.h +++ b/arch/ia64/sn/include/xtalk/hubdev.h @@ -40,8 +40,8 @@ struct sn_flush_device_common { unsigned long sfdl_force_int_addr; unsigned long sfdl_flush_value; volatile unsigned long *sfdl_flush_addr; - uint32_t sfdl_persistent_busnum; - uint32_t sfdl_persistent_segment; + u32 sfdl_persistent_busnum; + u32 sfdl_persistent_segment; struct pcibus_info *sfdl_pcibus_info; }; @@ -56,7 +56,7 @@ struct sn_flush_device_kernel { */ struct sn_flush_nasid_entry { struct sn_flush_device_kernel **widget_p; // Used as an array of wid_num - uint64_t iio_itte[8]; + u64 iio_itte[8]; }; struct hubdev_info { @@ -70,8 +70,8 @@ struct hubdev_info { void *hdi_nodepda; void *hdi_node_vertex; - uint32_t max_segment_number; - uint32_t max_pcibus_number; + u32 max_segment_number; + u32 max_pcibus_number; }; extern void hubdev_init_node(nodepda_t *, cnodeid_t); diff --git a/arch/ia64/sn/include/xtalk/xbow.h b/arch/ia64/sn/include/xtalk/xbow.h index ec56b3432f17..90f37a4133d0 100644 --- a/arch/ia64/sn/include/xtalk/xbow.h +++ b/arch/ia64/sn/include/xtalk/xbow.h @@ -3,7 +3,8 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (C) 1992-1997,2000-2006 Silicon Graphics, Inc. All Rights + * Reserved. */ #ifndef _ASM_IA64_SN_XTALK_XBOW_H #define _ASM_IA64_SN_XTALK_XBOW_H @@ -21,94 +22,94 @@ /* Register set for each xbow link */ typedef volatile struct xb_linkregs_s { -/* +/* * we access these through synergy unswizzled space, so the address * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.) * That's why we put the register first and filler second. */ - uint32_t link_ibf; - uint32_t filler0; /* filler for proper alignment */ - uint32_t link_control; - uint32_t filler1; - uint32_t link_status; - uint32_t filler2; - uint32_t link_arb_upper; - uint32_t filler3; - uint32_t link_arb_lower; - uint32_t filler4; - uint32_t link_status_clr; - uint32_t filler5; - uint32_t link_reset; - uint32_t filler6; - uint32_t link_aux_status; - uint32_t filler7; + u32 link_ibf; + u32 filler0; /* filler for proper alignment */ + u32 link_control; + u32 filler1; + u32 link_status; + u32 filler2; + u32 link_arb_upper; + u32 filler3; + u32 link_arb_lower; + u32 filler4; + u32 link_status_clr; + u32 filler5; + u32 link_reset; + u32 filler6; + u32 link_aux_status; + u32 filler7; } xb_linkregs_t; typedef volatile struct xbow_s { - /* standard widget configuration 0x000000-0x000057 */ - struct widget_cfg xb_widget; /* 0x000000 */ - - /* helper fieldnames for accessing bridge widget */ - -#define xb_wid_id xb_widget.w_id -#define xb_wid_stat xb_widget.w_status -#define xb_wid_err_upper xb_widget.w_err_upper_addr -#define xb_wid_err_lower xb_widget.w_err_lower_addr -#define xb_wid_control xb_widget.w_control -#define xb_wid_req_timeout xb_widget.w_req_timeout -#define xb_wid_int_upper xb_widget.w_intdest_upper_addr -#define xb_wid_int_lower xb_widget.w_intdest_lower_addr -#define xb_wid_err_cmdword xb_widget.w_err_cmd_word -#define xb_wid_llp xb_widget.w_llp_cfg -#define xb_wid_stat_clr xb_widget.w_tflush - -/* + /* standard widget configuration 0x000000-0x000057 */ + struct widget_cfg xb_widget; /* 0x000000 */ + + /* helper fieldnames for accessing bridge widget */ + +#define xb_wid_id xb_widget.w_id +#define xb_wid_stat xb_widget.w_status +#define xb_wid_err_upper xb_widget.w_err_upper_addr +#define xb_wid_err_lower xb_widget.w_err_lower_addr +#define xb_wid_control xb_widget.w_control +#define xb_wid_req_timeout xb_widget.w_req_timeout +#define xb_wid_int_upper xb_widget.w_intdest_upper_addr +#define xb_wid_int_lower xb_widget.w_intdest_lower_addr +#define xb_wid_err_cmdword xb_widget.w_err_cmd_word +#define xb_wid_llp xb_widget.w_llp_cfg +#define xb_wid_stat_clr xb_widget.w_tflush + +/* * we access these through synergy unswizzled space, so the address * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.) * That's why we put the register first and filler second. */ - /* xbow-specific widget configuration 0x000058-0x0000FF */ - uint32_t xb_wid_arb_reload; /* 0x00005C */ - uint32_t _pad_000058; - uint32_t xb_perf_ctr_a; /* 0x000064 */ - uint32_t _pad_000060; - uint32_t xb_perf_ctr_b; /* 0x00006c */ - uint32_t _pad_000068; - uint32_t xb_nic; /* 0x000074 */ - uint32_t _pad_000070; - - /* Xbridge only */ - uint32_t xb_w0_rst_fnc; /* 0x00007C */ - uint32_t _pad_000078; - uint32_t xb_l8_rst_fnc; /* 0x000084 */ - uint32_t _pad_000080; - uint32_t xb_l9_rst_fnc; /* 0x00008c */ - uint32_t _pad_000088; - uint32_t xb_la_rst_fnc; /* 0x000094 */ - uint32_t _pad_000090; - uint32_t xb_lb_rst_fnc; /* 0x00009c */ - uint32_t _pad_000098; - uint32_t xb_lc_rst_fnc; /* 0x0000a4 */ - uint32_t _pad_0000a0; - uint32_t xb_ld_rst_fnc; /* 0x0000ac */ - uint32_t _pad_0000a8; - uint32_t xb_le_rst_fnc; /* 0x0000b4 */ - uint32_t _pad_0000b0; - uint32_t xb_lf_rst_fnc; /* 0x0000bc */ - uint32_t _pad_0000b8; - uint32_t xb_lock; /* 0x0000c4 */ - uint32_t _pad_0000c0; - uint32_t xb_lock_clr; /* 0x0000cc */ - uint32_t _pad_0000c8; - /* end of Xbridge only */ - uint32_t _pad_0000d0[12]; - - /* Link Specific Registers, port 8..15 0x000100-0x000300 */ - xb_linkregs_t xb_link_raw[MAX_XBOW_PORTS]; -#define xb_link(p) xb_link_raw[(p) & (MAX_XBOW_PORTS - 1)] - + /* xbow-specific widget configuration 0x000058-0x0000FF */ + u32 xb_wid_arb_reload; /* 0x00005C */ + u32 _pad_000058; + u32 xb_perf_ctr_a; /* 0x000064 */ + u32 _pad_000060; + u32 xb_perf_ctr_b; /* 0x00006c */ + u32 _pad_000068; + u32 xb_nic; /* 0x000074 */ + u32 _pad_000070; + + /* Xbridge only */ + u32 xb_w0_rst_fnc; /* 0x00007C */ + u32 _pad_000078; + u32 xb_l8_rst_fnc; /* 0x000084 */ + u32 _pad_000080; + u32 xb_l9_rst_fnc; /* 0x00008c */ + u32 _pad_000088; + u32 xb_la_rst_fnc; /* 0x000094 */ + u32 _pad_000090; + u32 xb_lb_rst_fnc; /* 0x00009c */ + u32 _pad_000098; + u32 xb_lc_rst_fnc; /* 0x0000a4 */ + u32 _pad_0000a0; + u32 xb_ld_rst_fnc; /* 0x0000ac */ + u32 _pad_0000a8; + u32 xb_le_rst_fnc; /* 0x0000b4 */ + u32 _pad_0000b0; + u32 xb_lf_rst_fnc; /* 0x0000bc */ + u32 _pad_0000b8; + u32 xb_lock; /* 0x0000c4 */ + u32 _pad_0000c0; + u32 xb_lock_clr; /* 0x0000cc */ + u32 _pad_0000c8; + /* end of Xbridge only */ + u32 _pad_0000d0[12]; + + /* Link Specific Registers, port 8..15 0x000100-0x000300 */ + xb_linkregs_t xb_link_raw[MAX_XBOW_PORTS]; } xbow_t; +#define xb_link(p) xb_link_raw[(p) & (MAX_XBOW_PORTS - 1)] + #define XB_FLAGS_EXISTS 0x1 /* device exists */ #define XB_FLAGS_MASTER 0x2 #define XB_FLAGS_SLAVE 0x0 @@ -160,7 +161,7 @@ typedef volatile struct xbow_s { /* End of Xbridge only */ /* used only in ide, but defined here within the reserved portion */ -/* of the widget0 address space (before 0xf4) */ +/* of the widget0 address space (before 0xf4) */ #define XBOW_WID_UNDEF 0xe4 /* xbow link register set base, legal value for x is 0x8..0xf */ @@ -179,29 +180,37 @@ typedef volatile struct xbow_s { /* link_control(x) */ #define XB_CTRL_LINKALIVE_IE 0x80000000 /* link comes alive */ - /* reserved: 0x40000000 */ +/* reserved: 0x40000000 */ #define XB_CTRL_PERF_CTR_MODE_MSK 0x30000000 /* perf counter mode */ -#define XB_CTRL_IBUF_LEVEL_MSK 0x0e000000 /* input packet buffer level */ -#define XB_CTRL_8BIT_MODE 0x01000000 /* force link into 8 bit mode */ -#define XB_CTRL_BAD_LLP_PKT 0x00800000 /* force bad LLP packet */ -#define XB_CTRL_WIDGET_CR_MSK 0x007c0000 /* LLP widget credit mask */ -#define XB_CTRL_WIDGET_CR_SHFT 18 /* LLP widget credit shift */ -#define XB_CTRL_ILLEGAL_DST_IE 0x00020000 /* illegal destination */ -#define XB_CTRL_OALLOC_IBUF_IE 0x00010000 /* overallocated input buffer */ - /* reserved: 0x0000fe00 */ +#define XB_CTRL_IBUF_LEVEL_MSK 0x0e000000 /* input packet buffer + level */ +#define XB_CTRL_8BIT_MODE 0x01000000 /* force link into 8 + bit mode */ +#define XB_CTRL_BAD_LLP_PKT 0x00800000 /* force bad LLP + packet */ +#define XB_CTRL_WIDGET_CR_MSK 0x007c0000 /* LLP widget credit + mask */ +#define XB_CTRL_WIDGET_CR_SHFT 18 /* LLP widget credit + shift */ +#define XB_CTRL_ILLEGAL_DST_IE 0x00020000 /* illegal destination + */ +#define XB_CTRL_OALLOC_IBUF_IE 0x00010000 /* overallocated input + buffer */ +/* reserved: 0x0000fe00 */ #define XB_CTRL_BNDWDTH_ALLOC_IE 0x00000100 /* bandwidth alloc */ #define XB_CTRL_RCV_CNT_OFLOW_IE 0x00000080 /* rcv retry overflow */ #define XB_CTRL_XMT_CNT_OFLOW_IE 0x00000040 /* xmt retry overflow */ #define XB_CTRL_XMT_MAX_RTRY_IE 0x00000020 /* max transmit retry */ #define XB_CTRL_RCV_IE 0x00000010 /* receive */ #define XB_CTRL_XMT_RTRY_IE 0x00000008 /* transmit retry */ - /* reserved: 0x00000004 */ -#define XB_CTRL_MAXREQ_TOUT_IE 0x00000002 /* maximum request timeout */ +/* reserved: 0x00000004 */ +#define XB_CTRL_MAXREQ_TOUT_IE 0x00000002 /* maximum request + timeout */ #define XB_CTRL_SRC_TOUT_IE 0x00000001 /* source timeout */ /* link_status(x) */ #define XB_STAT_LINKALIVE XB_CTRL_LINKALIVE_IE - /* reserved: 0x7ff80000 */ +/* reserved: 0x7ff80000 */ #define XB_STAT_MULTI_ERR 0x00040000 /* multi error */ #define XB_STAT_ILLEGAL_DST_ERR XB_CTRL_ILLEGAL_DST_IE #define XB_STAT_OALLOC_IBUF_ERR XB_CTRL_OALLOC_IBUF_IE @@ -211,7 +220,7 @@ typedef volatile struct xbow_s { #define XB_STAT_XMT_MAX_RTRY_ERR XB_CTRL_XMT_MAX_RTRY_IE #define XB_STAT_RCV_ERR XB_CTRL_RCV_IE #define XB_STAT_XMT_RTRY_ERR XB_CTRL_XMT_RTRY_IE - /* reserved: 0x00000004 */ +/* reserved: 0x00000004 */ #define XB_STAT_MAXREQ_TOUT_ERR XB_CTRL_MAXREQ_TOUT_IE #define XB_STAT_SRC_TOUT_ERR XB_CTRL_SRC_TOUT_IE @@ -222,7 +231,7 @@ typedef volatile struct xbow_s { #define XB_AUX_LINKFAIL_RST_BAD 0x00000040 #define XB_AUX_STAT_PRESENT 0x00000020 #define XB_AUX_STAT_PORT_WIDTH 0x00000010 - /* reserved: 0x0000000f */ +/* reserved: 0x0000000f */ /* * link_arb_upper/link_arb_lower(x), (reg) should be the link_arb_upper @@ -238,7 +247,8 @@ typedef volatile struct xbow_s { /* XBOW_WID_STAT */ #define XB_WID_STAT_LINK_INTR_SHFT (24) #define XB_WID_STAT_LINK_INTR_MASK (0xFF << XB_WID_STAT_LINK_INTR_SHFT) -#define XB_WID_STAT_LINK_INTR(x) (0x1 << (((x)&7) + XB_WID_STAT_LINK_INTR_SHFT)) +#define XB_WID_STAT_LINK_INTR(x) \ + (0x1 << (((x)&7) + XB_WID_STAT_LINK_INTR_SHFT)) #define XB_WID_STAT_WIDGET0_INTR 0x00800000 #define XB_WID_STAT_SRCID_MASK 0x000003c0 /* Xbridge only */ #define XB_WID_STAT_REG_ACC_ERR 0x00000020 @@ -264,7 +274,7 @@ typedef volatile struct xbow_s { #define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbridge */ #define XBOW_WIDGET_MFGR_NUM 0x0 #define XXBOW_WIDGET_MFGR_NUM 0x0 -#define PXBOW_WIDGET_PART_NUM 0xd100 /* PIC */ +#define PXBOW_WIDGET_PART_NUM 0xd100 /* PIC */ #define XBOW_REV_1_0 0x1 /* xbow rev 1.0 is "1" */ #define XBOW_REV_1_1 0x2 /* xbow rev 1.1 is "2" */ @@ -279,13 +289,13 @@ typedef volatile struct xbow_s { #define XBOW_WID_ARB_RELOAD_INT 0x3f /* GBR reload interval */ #define IS_XBRIDGE_XBOW(wid) \ - (XWIDGET_PART_NUM(wid) == XXBOW_WIDGET_PART_NUM && \ - XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM) + (XWIDGET_PART_NUM(wid) == XXBOW_WIDGET_PART_NUM && \ + XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM) #define IS_PIC_XBOW(wid) \ - (XWIDGET_PART_NUM(wid) == PXBOW_WIDGET_PART_NUM && \ - XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM) + (XWIDGET_PART_NUM(wid) == PXBOW_WIDGET_PART_NUM && \ + XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM) #define XBOW_WAR_ENABLED(pv, widid) ((1 << XWIDGET_REV_NUM(widid)) & pv) -#endif /* _ASM_IA64_SN_XTALK_XBOW_H */ +#endif /* _ASM_IA64_SN_XTALK_XBOW_H */ diff --git a/arch/ia64/sn/include/xtalk/xwidgetdev.h b/arch/ia64/sn/include/xtalk/xwidgetdev.h index c5f4bc5cc033..2800eda0fd68 100644 --- a/arch/ia64/sn/include/xtalk/xwidgetdev.h +++ b/arch/ia64/sn/include/xtalk/xwidgetdev.h @@ -25,28 +25,28 @@ /* widget configuration registers */ struct widget_cfg{ - uint32_t w_id; /* 0x04 */ - uint32_t w_pad_0; /* 0x00 */ - uint32_t w_status; /* 0x0c */ - uint32_t w_pad_1; /* 0x08 */ - uint32_t w_err_upper_addr; /* 0x14 */ - uint32_t w_pad_2; /* 0x10 */ - uint32_t w_err_lower_addr; /* 0x1c */ - uint32_t w_pad_3; /* 0x18 */ - uint32_t w_control; /* 0x24 */ - uint32_t w_pad_4; /* 0x20 */ - uint32_t w_req_timeout; /* 0x2c */ - uint32_t w_pad_5; /* 0x28 */ - uint32_t w_intdest_upper_addr; /* 0x34 */ - uint32_t w_pad_6; /* 0x30 */ - uint32_t w_intdest_lower_addr; /* 0x3c */ - uint32_t w_pad_7; /* 0x38 */ - uint32_t w_err_cmd_word; /* 0x44 */ - uint32_t w_pad_8; /* 0x40 */ - uint32_t w_llp_cfg; /* 0x4c */ - uint32_t w_pad_9; /* 0x48 */ - uint32_t w_tflush; /* 0x54 */ - uint32_t w_pad_10; /* 0x50 */ + u32 w_id; /* 0x04 */ + u32 w_pad_0; /* 0x00 */ + u32 w_status; /* 0x0c */ + u32 w_pad_1; /* 0x08 */ + u32 w_err_upper_addr; /* 0x14 */ + u32 w_pad_2; /* 0x10 */ + u32 w_err_lower_addr; /* 0x1c */ + u32 w_pad_3; /* 0x18 */ + u32 w_control; /* 0x24 */ + u32 w_pad_4; /* 0x20 */ + u32 w_req_timeout; /* 0x2c */ + u32 w_pad_5; /* 0x28 */ + u32 w_intdest_upper_addr; /* 0x34 */ + u32 w_pad_6; /* 0x30 */ + u32 w_intdest_lower_addr; /* 0x3c */ + u32 w_pad_7; /* 0x38 */ + u32 w_err_cmd_word; /* 0x44 */ + u32 w_pad_8; /* 0x40 */ + u32 w_llp_cfg; /* 0x4c */ + u32 w_pad_9; /* 0x48 */ + u32 w_tflush; /* 0x54 */ + u32 w_pad_10; /* 0x50 */ }; /* @@ -63,7 +63,7 @@ struct xwidget_info{ struct xwidget_hwid xwi_hwid; /* Widget Identification */ char xwi_masterxid; /* Hub's Widget Port Number */ void *xwi_hubinfo; /* Hub's provider private info */ - uint64_t *xwi_hub_provider; /* prom provider functions */ + u64 *xwi_hub_provider; /* prom provider functions */ void *xwi_vertex; }; diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c index 258d9d7aff98..233d55115d33 100644 --- a/arch/ia64/sn/kernel/io_init.c +++ b/arch/ia64/sn/kernel/io_init.c @@ -132,8 +132,8 @@ static inline u64 sal_get_pcibus_info(u64 segment, u64 busnum, u64 address) * Retrieve the pci device information given the bus and device|function number. */ static inline u64 -sal_get_pcidev_info(u64 segment, u64 bus_number, u64 devfn, u64 pci_dev, - u64 sn_irq_info) +sal_get_pcidev_info(u64 segment, u64 bus_number, u64 devfn, u64 pci_dev, + u64 sn_irq_info) { struct ia64_sal_retval ret_stuff; ret_stuff.status = 0; @@ -141,7 +141,7 @@ sal_get_pcidev_info(u64 segment, u64 bus_number, u64 devfn, u64 pci_dev, SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_GET_PCIDEV_INFO, - (u64) segment, (u64) bus_number, (u64) devfn, + (u64) segment, (u64) bus_number, (u64) devfn, (u64) pci_dev, sn_irq_info, 0, 0); return ret_stuff.v0; @@ -268,7 +268,7 @@ static void sn_fixup_ionodes(void) */ static void sn_pci_window_fixup(struct pci_dev *dev, unsigned int count, - int64_t * pci_addrs) + s64 * pci_addrs) { struct pci_controller *controller = PCI_CONTROLLER(dev->bus); unsigned int i; @@ -328,7 +328,7 @@ void sn_pci_fixup_slot(struct pci_dev *dev) struct pci_bus *host_pci_bus; struct pci_dev *host_pci_dev; struct pcidev_info *pcidev_info; - int64_t pci_addrs[PCI_ROM_RESOURCE + 1]; + s64 pci_addrs[PCI_ROM_RESOURCE + 1]; struct sn_irq_info *sn_irq_info; unsigned long size; unsigned int bus_no, devfn; diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c index 01d18b7b5bb3..ec37084bdc17 100644 --- a/arch/ia64/sn/kernel/irq.c +++ b/arch/ia64/sn/kernel/irq.c @@ -28,7 +28,7 @@ extern int sn_ioif_inited; static struct list_head **sn_irq_lh; static spinlock_t sn_irq_info_lock = SPIN_LOCK_UNLOCKED; /* non-IRQ lock */ -static inline uint64_t sn_intr_alloc(nasid_t local_nasid, int local_widget, +static inline u64 sn_intr_alloc(nasid_t local_nasid, int local_widget, u64 sn_irq_info, int req_irq, nasid_t req_nasid, int req_slice) @@ -123,7 +123,7 @@ static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask) list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe, sn_irq_lh[irq], list) { - uint64_t bridge; + u64 bridge; int local_widget, status; nasid_t local_nasid; struct sn_irq_info *new_irq_info; @@ -134,7 +134,7 @@ static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask) break; memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info)); - bridge = (uint64_t) new_irq_info->irq_bridge; + bridge = (u64) new_irq_info->irq_bridge; if (!bridge) { kfree(new_irq_info); break; /* irq is not a device interrupt */ @@ -349,10 +349,10 @@ static void force_interrupt(int irq) */ static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info) { - uint64_t regval; + u64 regval; int irr_reg_num; int irr_bit; - uint64_t irr_reg; + u64 irr_reg; struct pcidev_info *pcidev_info; struct pcibus_info *pcibus_info; diff --git a/arch/ia64/sn/kernel/tiocx.c b/arch/ia64/sn/kernel/tiocx.c index 6a7939b16a1c..d263d3e8fbb9 100644 --- a/arch/ia64/sn/kernel/tiocx.c +++ b/arch/ia64/sn/kernel/tiocx.c @@ -245,7 +245,7 @@ static int cx_device_reload(struct cx_dev *cx_dev) cx_dev->bt); } -static inline uint64_t tiocx_intr_alloc(nasid_t nasid, int widget, +static inline u64 tiocx_intr_alloc(nasid_t nasid, int widget, u64 sn_irq_info, int req_irq, nasid_t req_nasid, int req_slice) @@ -302,7 +302,7 @@ struct sn_irq_info *tiocx_irq_alloc(nasid_t nasid, int widget, int irq, void tiocx_irq_free(struct sn_irq_info *sn_irq_info) { - uint64_t bridge = (uint64_t) sn_irq_info->irq_bridge; + u64 bridge = (u64) sn_irq_info->irq_bridge; nasid_t nasid = NASID_GET(bridge); int widget; @@ -313,12 +313,12 @@ void tiocx_irq_free(struct sn_irq_info *sn_irq_info) } } -uint64_t tiocx_dma_addr(uint64_t addr) +u64 tiocx_dma_addr(u64 addr) { return PHYS_TO_TIODMA(addr); } -uint64_t tiocx_swin_base(int nasid) +u64 tiocx_swin_base(int nasid) { return TIO_SWIN_BASE(nasid, TIOCX_CORELET); } @@ -335,8 +335,8 @@ EXPORT_SYMBOL(tiocx_swin_base); static void tio_conveyor_set(nasid_t nasid, int enable_flag) { - uint64_t ice_frz; - uint64_t disable_cb = (1ull << 61); + u64 ice_frz; + u64 disable_cb = (1ull << 61); if (!(nasid & 1)) return; @@ -388,7 +388,7 @@ static int is_fpga_tio(int nasid, int *bt) static int bitstream_loaded(nasid_t nasid) { - uint64_t cx_credits; + u64 cx_credits; cx_credits = REMOTE_HUB_L(nasid, TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3); cx_credits &= TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3_CREDIT_CNT_MASK; @@ -404,14 +404,14 @@ static int tiocx_reload(struct cx_dev *cx_dev) nasid_t nasid = cx_dev->cx_id.nasid; if (bitstream_loaded(nasid)) { - uint64_t cx_id; + u64 cx_id; int rv; rv = ia64_sn_sysctl_tio_clock_reset(nasid); if (rv) { printk(KERN_ALERT "CX port JTAG reset failed.\n"); } else { - cx_id = *(volatile uint64_t *) + cx_id = *(volatile u64 *) (TIO_SWIN_BASE(nasid, TIOCX_CORELET) + WIDGET_ID); part_num = XWIDGET_PART_NUM(cx_id); diff --git a/arch/ia64/sn/pci/pcibr/pcibr_ate.c b/arch/ia64/sn/pci/pcibr/pcibr_ate.c index d1647b863e61..aa3fa5152a32 100644 --- a/arch/ia64/sn/pci/pcibr/pcibr_ate.c +++ b/arch/ia64/sn/pci/pcibr/pcibr_ate.c @@ -18,10 +18,10 @@ int pcibr_invalidate_ate = 0; /* by default don't invalidate ATE on free */ * mark_ate: Mark the ate as either free or inuse. */ static void mark_ate(struct ate_resource *ate_resource, int start, int number, - uint64_t value) + u64 value) { - uint64_t *ate = ate_resource->ate; + u64 *ate = ate_resource->ate; int index; int length = 0; @@ -38,7 +38,7 @@ static int find_free_ate(struct ate_resource *ate_resource, int start, int count) { - uint64_t *ate = ate_resource->ate; + u64 *ate = ate_resource->ate; int index; int start_free; @@ -119,7 +119,7 @@ static inline int alloc_ate_resource(struct ate_resource *ate_resource, int pcibr_ate_alloc(struct pcibus_info *pcibus_info, int count) { int status = 0; - uint64_t flag; + u64 flag; flag = pcibr_lock(pcibus_info); status = alloc_ate_resource(&pcibus_info->pbi_int_ate_resource, count); @@ -139,7 +139,7 @@ int pcibr_ate_alloc(struct pcibus_info *pcibus_info, int count) * Setup an Address Translation Entry as specified. Use either the Bridge * internal maps or the external map RAM, as appropriate. */ -static inline uint64_t *pcibr_ate_addr(struct pcibus_info *pcibus_info, +static inline u64 *pcibr_ate_addr(struct pcibus_info *pcibus_info, int ate_index) { if (ate_index < pcibus_info->pbi_int_ate_size) { @@ -153,7 +153,7 @@ static inline uint64_t *pcibr_ate_addr(struct pcibus_info *pcibus_info, */ void inline ate_write(struct pcibus_info *pcibus_info, int ate_index, int count, - volatile uint64_t ate) + volatile u64 ate) { while (count-- > 0) { if (ate_index < pcibus_info->pbi_int_ate_size) { @@ -171,9 +171,9 @@ ate_write(struct pcibus_info *pcibus_info, int ate_index, int count, void pcibr_ate_free(struct pcibus_info *pcibus_info, int index) { - volatile uint64_t ate; + volatile u64 ate; int count; - uint64_t flags; + u64 flags; if (pcibr_invalidate_ate) { /* For debugging purposes, clear the valid bit in the ATE */ diff --git a/arch/ia64/sn/pci/pcibr/pcibr_dma.c b/arch/ia64/sn/pci/pcibr/pcibr_dma.c index e68332d93171..54ce5b7ceed2 100644 --- a/arch/ia64/sn/pci/pcibr/pcibr_dma.c +++ b/arch/ia64/sn/pci/pcibr/pcibr_dma.c @@ -41,21 +41,21 @@ extern int sn_ioif_inited; static dma_addr_t pcibr_dmamap_ate32(struct pcidev_info *info, - uint64_t paddr, size_t req_size, uint64_t flags) + u64 paddr, size_t req_size, u64 flags) { struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info; struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info-> pdi_pcibus_info; - uint8_t internal_device = (PCI_SLOT(pcidev_info->pdi_host_pcidev_info-> + u8 internal_device = (PCI_SLOT(pcidev_info->pdi_host_pcidev_info-> pdi_linux_pcidev->devfn)) - 1; int ate_count; int ate_index; - uint64_t ate_flags = flags | PCI32_ATE_V; - uint64_t ate; - uint64_t pci_addr; - uint64_t xio_addr; - uint64_t offset; + u64 ate_flags = flags | PCI32_ATE_V; + u64 ate; + u64 pci_addr; + u64 xio_addr; + u64 offset; /* PIC in PCI-X mode does not supports 32bit PageMap mode */ if (IS_PIC_SOFT(pcibus_info) && IS_PCIX(pcibus_info)) { @@ -109,12 +109,12 @@ pcibr_dmamap_ate32(struct pcidev_info *info, } static dma_addr_t -pcibr_dmatrans_direct64(struct pcidev_info * info, uint64_t paddr, - uint64_t dma_attributes) +pcibr_dmatrans_direct64(struct pcidev_info * info, u64 paddr, + u64 dma_attributes) { struct pcibus_info *pcibus_info = (struct pcibus_info *) ((info->pdi_host_pcidev_info)->pdi_pcibus_info); - uint64_t pci_addr; + u64 pci_addr; /* Translate to Crosstalk View of Physical Address */ pci_addr = (IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) : @@ -127,7 +127,7 @@ pcibr_dmatrans_direct64(struct pcidev_info * info, uint64_t paddr, /* Handle Bridge Chipset differences */ if (IS_PIC_SOFT(pcibus_info)) { pci_addr |= - ((uint64_t) pcibus_info-> + ((u64) pcibus_info-> pbi_hub_xid << PIC_PCI64_ATTR_TARG_SHFT); } else pci_addr |= TIOCP_PCI64_CMDTYPE_MEM; @@ -142,17 +142,17 @@ pcibr_dmatrans_direct64(struct pcidev_info * info, uint64_t paddr, static dma_addr_t pcibr_dmatrans_direct32(struct pcidev_info * info, - uint64_t paddr, size_t req_size, uint64_t flags) + u64 paddr, size_t req_size, u64 flags) { struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info; struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info-> pdi_pcibus_info; - uint64_t xio_addr; + u64 xio_addr; - uint64_t xio_base; - uint64_t offset; - uint64_t endoff; + u64 xio_base; + u64 offset; + u64 endoff; if (IS_PCIX(pcibus_info)) { return 0; @@ -209,14 +209,14 @@ pcibr_dma_unmap(struct pci_dev *hwdev, dma_addr_t dma_handle, int direction) * unlike the PIC Device(x) Write Request Buffer Flush register. */ -void sn_dma_flush(uint64_t addr) +void sn_dma_flush(u64 addr) { nasid_t nasid; int is_tio; int wid_num; int i, j; - uint64_t flags; - uint64_t itte; + u64 flags; + u64 itte; struct hubdev_info *hubinfo; volatile struct sn_flush_device_kernel *p; volatile struct sn_flush_device_common *common; @@ -299,8 +299,8 @@ void sn_dma_flush(uint64_t addr) * If CE ever needs the sn_dma_flush mechanism, we will have * to account for that here and in tioce_bus_fixup(). */ - uint32_t tio_id = HUB_L(TIO_IOSPACE_ADDR(nasid, TIO_NODE_ID)); - uint32_t revnum = XWIDGET_PART_REV_NUM(tio_id); + u32 tio_id = HUB_L(TIO_IOSPACE_ADDR(nasid, TIO_NODE_ID)); + u32 revnum = XWIDGET_PART_REV_NUM(tio_id); /* TIOCP BRINGUP WAR (PV907516): Don't write buffer flush reg */ if ((1 << XWIDGET_PART_REV_NUM_REV(revnum)) & PV907516) { @@ -315,7 +315,7 @@ void sn_dma_flush(uint64_t addr) *common->sfdl_flush_addr = 0; /* force an interrupt. */ - *(volatile uint32_t *)(common->sfdl_force_int_addr) = 1; + *(volatile u32 *)(common->sfdl_force_int_addr) = 1; /* wait for the interrupt to come back. */ while (*(common->sfdl_flush_addr) != 0x10f) diff --git a/arch/ia64/sn/pci/pcibr/pcibr_provider.c b/arch/ia64/sn/pci/pcibr/pcibr_provider.c index e328e948175d..77a1262751d3 100644 --- a/arch/ia64/sn/pci/pcibr/pcibr_provider.c +++ b/arch/ia64/sn/pci/pcibr/pcibr_provider.c @@ -23,7 +23,7 @@ int sal_pcibr_slot_enable(struct pcibus_info *soft, int device, void *resp) { struct ia64_sal_retval ret_stuff; - uint64_t busnum; + u64 busnum; ret_stuff.status = 0; ret_stuff.v0 = 0; @@ -40,7 +40,7 @@ sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action, void *resp) { struct ia64_sal_retval ret_stuff; - uint64_t busnum; + u64 busnum; ret_stuff.status = 0; ret_stuff.v0 = 0; @@ -56,7 +56,7 @@ sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action, static int sal_pcibr_error_interrupt(struct pcibus_info *soft) { struct ia64_sal_retval ret_stuff; - uint64_t busnum; + u64 busnum; int segment; ret_stuff.status = 0; ret_stuff.v0 = 0; @@ -159,9 +159,9 @@ pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont /* Setup the PMU ATE map */ soft->pbi_int_ate_resource.lowest_free_index = 0; soft->pbi_int_ate_resource.ate = - kmalloc(soft->pbi_int_ate_size * sizeof(uint64_t), GFP_KERNEL); + kmalloc(soft->pbi_int_ate_size * sizeof(u64), GFP_KERNEL); memset(soft->pbi_int_ate_resource.ate, 0, - (soft->pbi_int_ate_size * sizeof(uint64_t))); + (soft->pbi_int_ate_size * sizeof(u64))); if (prom_bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCP) { /* TIO PCI Bridge: find nearest node with CPUs */ @@ -203,7 +203,7 @@ void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info) struct pcidev_info *pcidev_info; struct pcibus_info *pcibus_info; int bit = sn_irq_info->irq_int_bit; - uint64_t xtalk_addr = sn_irq_info->irq_xtalkaddr; + u64 xtalk_addr = sn_irq_info->irq_xtalkaddr; pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; if (pcidev_info) { diff --git a/arch/ia64/sn/pci/pcibr/pcibr_reg.c b/arch/ia64/sn/pci/pcibr/pcibr_reg.c index 79fdb91d7259..8b8bbd51d433 100644 --- a/arch/ia64/sn/pci/pcibr/pcibr_reg.c +++ b/arch/ia64/sn/pci/pcibr/pcibr_reg.c @@ -23,7 +23,7 @@ union br_ptr { /* * Control Register Access -- Read/Write 0000_0020 */ -void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) +void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, u64 bits) { union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; @@ -43,7 +43,7 @@ void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) } } -void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) +void pcireg_control_bit_set(struct pcibus_info *pcibus_info, u64 bits) { union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; @@ -66,10 +66,10 @@ void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) /* * PCI/PCIX Target Flush Register Access -- Read Only 0000_0050 */ -uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info) +u64 pcireg_tflush_get(struct pcibus_info *pcibus_info) { union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; - uint64_t ret = 0; + u64 ret = 0; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { @@ -96,10 +96,10 @@ uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info) /* * Interrupt Status Register Access -- Read Only 0000_0100 */ -uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info) +u64 pcireg_intr_status_get(struct pcibus_info * pcibus_info) { union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; - uint64_t ret = 0; + u64 ret = 0; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { @@ -121,7 +121,7 @@ uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info) /* * Interrupt Enable Register Access -- Read/Write 0000_0108 */ -void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) +void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, u64 bits) { union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; @@ -141,7 +141,7 @@ void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) } } -void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) +void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, u64 bits) { union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; @@ -165,7 +165,7 @@ void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) * Intr Host Address Register (int_addr) -- Read/Write 0000_0130 - 0000_0168 */ void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n, - uint64_t addr) + u64 addr) { union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; @@ -217,10 +217,10 @@ void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n) /* * Device(x) Write Buffer Flush Reg Access -- Read Only 0000_0240 - 0000_0258 */ -uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device) +u64 pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device) { union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; - uint64_t ret = 0; + u64 ret = 0; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { @@ -242,7 +242,7 @@ uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device) } void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index, - uint64_t val) + u64 val) { union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; @@ -262,10 +262,10 @@ void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index, } } -uint64_t __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index) +u64 __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index) { union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; - uint64_t __iomem *ret = NULL; + u64 __iomem *ret = NULL; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { diff --git a/arch/ia64/sn/pci/tioca_provider.c b/arch/ia64/sn/pci/tioca_provider.c index 27aa1842dacc..7571a4025529 100644 --- a/arch/ia64/sn/pci/tioca_provider.c +++ b/arch/ia64/sn/pci/tioca_provider.c @@ -16,7 +16,7 @@ #include <asm/sn/pcibus_provider_defs.h> #include <asm/sn/tioca_provider.h> -uint32_t tioca_gart_found; +u32 tioca_gart_found; EXPORT_SYMBOL(tioca_gart_found); /* used by agp-sgi */ LIST_HEAD(tioca_list); @@ -34,8 +34,8 @@ static int tioca_gart_init(struct tioca_kernel *); static int tioca_gart_init(struct tioca_kernel *tioca_kern) { - uint64_t ap_reg; - uint64_t offset; + u64 ap_reg; + u64 offset; struct page *tmp; struct tioca_common *tioca_common; struct tioca __iomem *ca_base; @@ -214,7 +214,7 @@ void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern) { int cap_ptr; - uint32_t reg; + u32 reg; struct tioca __iomem *tioca_base; struct pci_dev *pdev; struct tioca_common *common; @@ -276,7 +276,7 @@ EXPORT_SYMBOL(tioca_fastwrite_enable); /* used by agp-sgi */ * We will always use 0x1 * 55:55 - Swap bytes Currently unused */ -static uint64_t +static u64 tioca_dma_d64(unsigned long paddr) { dma_addr_t bus_addr; @@ -318,15 +318,15 @@ tioca_dma_d64(unsigned long paddr) * and so a given CA can only directly target nodes in the range * xxx - xxx+255. */ -static uint64_t -tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr) +static u64 +tioca_dma_d48(struct pci_dev *pdev, u64 paddr) { struct tioca_common *tioca_common; struct tioca __iomem *ca_base; - uint64_t ct_addr; + u64 ct_addr; dma_addr_t bus_addr; - uint32_t node_upper; - uint64_t agp_dma_extn; + u32 node_upper; + u64 agp_dma_extn; struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev); tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info; @@ -367,10 +367,10 @@ tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr) * dma_addr_t is guarenteed to be contiguous in CA bus space. */ static dma_addr_t -tioca_dma_mapped(struct pci_dev *pdev, uint64_t paddr, size_t req_size) +tioca_dma_mapped(struct pci_dev *pdev, u64 paddr, size_t req_size) { int i, ps, ps_shift, entry, entries, mapsize, last_entry; - uint64_t xio_addr, end_xio_addr; + u64 xio_addr, end_xio_addr; struct tioca_common *tioca_common; struct tioca_kernel *tioca_kern; dma_addr_t bus_addr = 0; @@ -514,10 +514,10 @@ tioca_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir) * The mapping mode used is based on the devices dma_mask. As a last resort * use the GART mapped mode. */ -static uint64_t -tioca_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count) +static u64 +tioca_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count) { - uint64_t mapaddr; + u64 mapaddr; /* * If card is 64 or 48 bit addresable, use a direct mapping. 32 @@ -554,8 +554,8 @@ tioca_error_intr_handler(int irq, void *arg, struct pt_regs *pt) { struct tioca_common *soft = arg; struct ia64_sal_retval ret_stuff; - uint64_t segment; - uint64_t busnum; + u64 segment; + u64 busnum; ret_stuff.status = 0; ret_stuff.v0 = 0; @@ -620,7 +620,7 @@ tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont INIT_LIST_HEAD(&tioca_kern->ca_dmamaps); tioca_kern->ca_closest_node = nasid_to_cnodeid(tioca_common->ca_closest_nasid); - tioca_common->ca_kernel_private = (uint64_t) tioca_kern; + tioca_common->ca_kernel_private = (u64) tioca_kern; bus = pci_find_bus(tioca_common->ca_common.bs_persist_segment, tioca_common->ca_common.bs_persist_busnum); diff --git a/arch/ia64/sn/pci/tioce_provider.c b/arch/ia64/sn/pci/tioce_provider.c index dda196c9e324..e52831ed93eb 100644 --- a/arch/ia64/sn/pci/tioce_provider.c +++ b/arch/ia64/sn/pci/tioce_provider.c @@ -81,10 +81,10 @@ * 61 - 0 since this is not an MSI transaction * 60:54 - reserved, MBZ */ -static uint64_t +static u64 tioce_dma_d64(unsigned long ct_addr) { - uint64_t bus_addr; + u64 bus_addr; bus_addr = ct_addr | (1UL << 63); @@ -141,9 +141,9 @@ pcidev_to_tioce(struct pci_dev *pdev, struct tioce **base, * length, and if enough resources exist, fill in the ATE's and construct a * tioce_dmamap struct to track the mapping. */ -static uint64_t +static u64 tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port, - uint64_t ct_addr, int len) + u64 ct_addr, int len) { int i; int j; @@ -152,11 +152,11 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port, int entries; int nates; int pagesize; - uint64_t *ate_shadow; - uint64_t *ate_reg; - uint64_t addr; + u64 *ate_shadow; + u64 *ate_reg; + u64 addr; struct tioce *ce_mmr; - uint64_t bus_base; + u64 bus_base; struct tioce_dmamap *map; ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base; @@ -224,7 +224,7 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port, addr = ct_addr; for (j = 0; j < nates; j++) { - uint64_t ate; + u64 ate; ate = ATE_MAKE(addr, pagesize); ate_shadow[i + j] = ate; @@ -252,15 +252,15 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port, * * Map @paddr into 32-bit bus space of the CE associated with @pcidev_info. */ -static uint64_t -tioce_dma_d32(struct pci_dev *pdev, uint64_t ct_addr) +static u64 +tioce_dma_d32(struct pci_dev *pdev, u64 ct_addr) { int dma_ok; int port; struct tioce *ce_mmr; struct tioce_kernel *ce_kern; - uint64_t ct_upper; - uint64_t ct_lower; + u64 ct_upper; + u64 ct_lower; dma_addr_t bus_addr; ct_upper = ct_addr & ~0x3fffffffUL; @@ -269,7 +269,7 @@ tioce_dma_d32(struct pci_dev *pdev, uint64_t ct_addr) pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port); if (ce_kern->ce_port[port].dirmap_refcnt == 0) { - uint64_t tmp; + u64 tmp; ce_kern->ce_port[port].dirmap_shadow = ct_upper; writeq(ct_upper, &ce_mmr->ce_ure_dir_map[port]); @@ -295,10 +295,10 @@ tioce_dma_d32(struct pci_dev *pdev, uint64_t ct_addr) * Given a TIOCE bus address, set the appropriate bit to indicate barrier * attributes. */ -static uint64_t -tioce_dma_barrier(uint64_t bus_addr, int on) +static u64 +tioce_dma_barrier(u64 bus_addr, int on) { - uint64_t barrier_bit; + u64 barrier_bit; /* barrier not supported in M40/M40S mode */ if (TIOCE_M40_ADDR(bus_addr) || TIOCE_M40S_ADDR(bus_addr)) @@ -351,7 +351,7 @@ tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir) list_for_each_entry(map, &ce_kern->ce_dmamap_list, ce_dmamap_list) { - uint64_t last; + u64 last; last = map->pci_start + map->nbytes - 1; if (bus_addr >= map->pci_start && bus_addr <= last) @@ -385,17 +385,17 @@ tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir) * This is the main wrapper for mapping host physical pages to CE PCI space. * The mapping mode used is based on the device's dma_mask. */ -static uint64_t -tioce_do_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count, +static u64 +tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count, int barrier) { unsigned long flags; - uint64_t ct_addr; - uint64_t mapaddr = 0; + u64 ct_addr; + u64 mapaddr = 0; struct tioce_kernel *ce_kern; struct tioce_dmamap *map; int port; - uint64_t dma_mask; + u64 dma_mask; dma_mask = (barrier) ? pdev->dev.coherent_dma_mask : pdev->dma_mask; @@ -425,7 +425,7 @@ tioce_do_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count, * address bits than this device can support. */ list_for_each_entry(map, &ce_kern->ce_dmamap_list, ce_dmamap_list) { - uint64_t last; + u64 last; last = map->ct_start + map->nbytes - 1; if (ct_addr >= map->ct_start && @@ -501,8 +501,8 @@ dma_map_done: * Simply call tioce_do_dma_map() to create a map with the barrier bit clear * in the address. */ -static uint64_t -tioce_dma(struct pci_dev *pdev, uint64_t paddr, size_t byte_count) +static u64 +tioce_dma(struct pci_dev *pdev, u64 paddr, size_t byte_count) { return tioce_do_dma_map(pdev, paddr, byte_count, 0); } @@ -515,8 +515,8 @@ tioce_dma(struct pci_dev *pdev, uint64_t paddr, size_t byte_count) * * Simply call tioce_do_dma_map() to create a map with the barrier bit set * in the address. - */ static uint64_t -tioce_dma_consistent(struct pci_dev *pdev, uint64_t paddr, size_t byte_count) + */ static u64 +tioce_dma_consistent(struct pci_dev *pdev, u64 paddr, size_t byte_count) { return tioce_do_dma_map(pdev, paddr, byte_count, 1); } @@ -551,7 +551,7 @@ tioce_error_intr_handler(int irq, void *arg, struct pt_regs *pt) tioce_kern_init(struct tioce_common *tioce_common) { int i; - uint32_t tmp; + u32 tmp; struct tioce *tioce_mmr; struct tioce_kernel *tioce_kern; @@ -563,7 +563,7 @@ tioce_kern_init(struct tioce_common *tioce_common) tioce_kern->ce_common = tioce_common; spin_lock_init(&tioce_kern->ce_lock); INIT_LIST_HEAD(&tioce_kern->ce_dmamap_list); - tioce_common->ce_kernel_private = (uint64_t) tioce_kern; + tioce_common->ce_kernel_private = (u64) tioce_kern; /* * Determine the secondary bus number of the port2 logical PPB. @@ -575,7 +575,7 @@ tioce_kern_init(struct tioce_common *tioce_common) raw_pci_ops->read(tioce_common->ce_pcibus.bs_persist_segment, tioce_common->ce_pcibus.bs_persist_busnum, PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1, &tmp); - tioce_kern->ce_port1_secondary = (uint8_t) tmp; + tioce_kern->ce_port1_secondary = (u8) tmp; /* * Set PMU pagesize to the largest size available, and zero out @@ -615,7 +615,7 @@ tioce_force_interrupt(struct sn_irq_info *sn_irq_info) struct pcidev_info *pcidev_info; struct tioce_common *ce_common; struct tioce *ce_mmr; - uint64_t force_int_val; + u64 force_int_val; if (!sn_irq_info->irq_bridge) return; @@ -687,7 +687,7 @@ tioce_target_interrupt(struct sn_irq_info *sn_irq_info) struct tioce_common *ce_common; struct tioce *ce_mmr; int bit; - uint64_t vector; + u64 vector; pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; if (!pcidev_info) @@ -699,7 +699,7 @@ tioce_target_interrupt(struct sn_irq_info *sn_irq_info) bit = sn_irq_info->irq_int_bit; __sn_setq_relaxed(&ce_mmr->ce_adm_int_mask, (1UL << bit)); - vector = (uint64_t)sn_irq_info->irq_irq << INTR_VECTOR_SHFT; + vector = (u64)sn_irq_info->irq_irq << INTR_VECTOR_SHFT; vector |= sn_irq_info->irq_xtalkaddr; writeq(vector, &ce_mmr->ce_adm_int_dest[bit]); __sn_clrq_relaxed(&ce_mmr->ce_adm_int_mask, (1UL << bit)); diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h index e828377ad295..7708ec669a33 100644 --- a/include/asm-ia64/pal.h +++ b/include/asm-ia64/pal.h @@ -927,7 +927,7 @@ static inline s64 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector) { struct ia64_pal_retval iprv; - PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress); + PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress); if (vector) *vector = iprv.v0; *progress = iprv.v1; diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h index 8c648bf72bbd..09b99029ac1a 100644 --- a/include/asm-ia64/processor.h +++ b/include/asm-ia64/processor.h @@ -25,8 +25,8 @@ * Limits for PMC and PMD are set to less than maximum architected values * but should be sufficient for a while */ -#define IA64_NUM_PMC_REGS 32 -#define IA64_NUM_PMD_REGS 32 +#define IA64_NUM_PMC_REGS 64 +#define IA64_NUM_PMD_REGS 64 #define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000) #define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000) diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h index e35074f526d9..a3431372c6e7 100644 --- a/include/asm-ia64/sn/intr.h +++ b/include/asm-ia64/sn/intr.h @@ -40,7 +40,7 @@ struct sn_irq_info { int irq_cpuid; /* kernel logical cpuid */ int irq_irq; /* the IRQ number */ int irq_int_bit; /* Bridge interrupt pin */ - uint64_t irq_xtalkaddr; /* xtalkaddr IRQ is sent to */ + u64 irq_xtalkaddr; /* xtalkaddr IRQ is sent to */ int irq_bridge_type;/* pciio asic type (pciio.h) */ void *irq_bridge; /* bridge generating irq */ void *irq_pciioinfo; /* associated pciio_info_t */ diff --git a/include/asm-ia64/sn/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h index 2b42d9ece26b..9334078b089a 100644 --- a/include/asm-ia64/sn/pcibr_provider.h +++ b/include/asm-ia64/sn/pcibr_provider.h @@ -44,9 +44,9 @@ #define PCI32_MAPPED_BASE 0x40000000 #define PCI32_DIRECT_BASE 0x80000000 -#define IS_PCI32_MAPPED(x) ((uint64_t)(x) < PCI32_DIRECT_BASE && \ - (uint64_t)(x) >= PCI32_MAPPED_BASE) -#define IS_PCI32_DIRECT(x) ((uint64_t)(x) >= PCI32_MAPPED_BASE) +#define IS_PCI32_MAPPED(x) ((u64)(x) < PCI32_DIRECT_BASE && \ + (u64)(x) >= PCI32_MAPPED_BASE) +#define IS_PCI32_DIRECT(x) ((u64)(x) >= PCI32_MAPPED_BASE) /* @@ -63,7 +63,7 @@ (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1)) #define MINIMAL_ATE_FLAG(addr, size) \ - (MINIMAL_ATES_REQUIRED((uint64_t)addr, size) ? 1 : 0) + (MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0) /* bit 29 of the pci address is the SWAP bit */ #define ATE_SWAPSHIFT 29 @@ -90,27 +90,27 @@ * PMU resources. */ struct ate_resource{ - uint64_t *ate; - uint64_t num_ate; - uint64_t lowest_free_index; + u64 *ate; + u64 num_ate; + u64 lowest_free_index; }; struct pcibus_info { struct pcibus_bussoft pbi_buscommon; /* common header */ - uint32_t pbi_moduleid; + u32 pbi_moduleid; short pbi_bridge_type; short pbi_bridge_mode; struct ate_resource pbi_int_ate_resource; - uint64_t pbi_int_ate_size; + u64 pbi_int_ate_size; - uint64_t pbi_dir_xbase; + u64 pbi_dir_xbase; char pbi_hub_xid; - uint64_t pbi_devreg[8]; + u64 pbi_devreg[8]; - uint32_t pbi_valid_devices; - uint32_t pbi_enabled_devices; + u32 pbi_valid_devices; + u32 pbi_enabled_devices; spinlock_t pbi_lock; }; @@ -136,22 +136,22 @@ extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int); /* * prototypes for the bridge asic register access routines in pcibr_reg.c */ -extern void pcireg_control_bit_clr(struct pcibus_info *, uint64_t); -extern void pcireg_control_bit_set(struct pcibus_info *, uint64_t); -extern uint64_t pcireg_tflush_get(struct pcibus_info *); -extern uint64_t pcireg_intr_status_get(struct pcibus_info *); -extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, uint64_t); -extern void pcireg_intr_enable_bit_set(struct pcibus_info *, uint64_t); -extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, uint64_t); +extern void pcireg_control_bit_clr(struct pcibus_info *, u64); +extern void pcireg_control_bit_set(struct pcibus_info *, u64); +extern u64 pcireg_tflush_get(struct pcibus_info *); +extern u64 pcireg_intr_status_get(struct pcibus_info *); +extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, u64); +extern void pcireg_intr_enable_bit_set(struct pcibus_info *, u64); +extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64); extern void pcireg_force_intr_set(struct pcibus_info *, int); -extern uint64_t pcireg_wrb_flush_get(struct pcibus_info *, int); -extern void pcireg_int_ate_set(struct pcibus_info *, int, uint64_t); -extern uint64_t * pcireg_int_ate_addr(struct pcibus_info *, int); +extern u64 pcireg_wrb_flush_get(struct pcibus_info *, int); +extern void pcireg_int_ate_set(struct pcibus_info *, int, u64); +extern u64 * pcireg_int_ate_addr(struct pcibus_info *, int); extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info); extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info); extern int pcibr_ate_alloc(struct pcibus_info *, int); extern void pcibr_ate_free(struct pcibus_info *, int); -extern void ate_write(struct pcibus_info *, int, int, uint64_t); +extern void ate_write(struct pcibus_info *, int, int, u64); extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device, void *resp); extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device, diff --git a/include/asm-ia64/sn/pcibus_provider_defs.h b/include/asm-ia64/sn/pcibus_provider_defs.h index ad0e8e8ae53f..ce3f6c328241 100644 --- a/include/asm-ia64/sn/pcibus_provider_defs.h +++ b/include/asm-ia64/sn/pcibus_provider_defs.h @@ -29,13 +29,13 @@ */ struct pcibus_bussoft { - uint32_t bs_asic_type; /* chipset type */ - uint32_t bs_xid; /* xwidget id */ - uint32_t bs_persist_busnum; /* Persistent Bus Number */ - uint32_t bs_persist_segment; /* Segment Number */ - uint64_t bs_legacy_io; /* legacy io pio addr */ - uint64_t bs_legacy_mem; /* legacy mem pio addr */ - uint64_t bs_base; /* widget base */ + u32 bs_asic_type; /* chipset type */ + u32 bs_xid; /* xwidget id */ + u32 bs_persist_busnum; /* Persistent Bus Number */ + u32 bs_persist_segment; /* Segment Number */ + u64 bs_legacy_io; /* legacy io pio addr */ + u64 bs_legacy_mem; /* legacy mem pio addr */ + u64 bs_base; /* widget base */ struct xwidget_info *bs_xwidget_info; }; diff --git a/include/asm-ia64/sn/pcidev.h b/include/asm-ia64/sn/pcidev.h index f65d222ca5e8..38cdffbc4c7b 100644 --- a/include/asm-ia64/sn/pcidev.h +++ b/include/asm-ia64/sn/pcidev.h @@ -55,8 +55,8 @@ struct sn_pci_controller { #define PCIIO_VENDOR_ID_NONE (-1) struct pcidev_info { - uint64_t pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */ - uint64_t pdi_slot_host_handle; /* Bus and devfn Host pci_dev */ + u64 pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */ + u64 pdi_slot_host_handle; /* Bus and devfn Host pci_dev */ struct pcibus_bussoft *pdi_pcibus_info; /* Kernel common bus soft */ struct pcidev_info *pdi_host_pcidev_info; /* Kernel Host pci_dev */ diff --git a/include/asm-ia64/sn/pic.h b/include/asm-ia64/sn/pic.h index 0de82e6b0893..5f9da5fd6e56 100644 --- a/include/asm-ia64/sn/pic.h +++ b/include/asm-ia64/sn/pic.h @@ -74,120 +74,120 @@ struct pic { /* 0x000000-0x00FFFF -- Local Registers */ /* 0x000000-0x000057 -- Standard Widget Configuration */ - uint64_t p_wid_id; /* 0x000000 */ - uint64_t p_wid_stat; /* 0x000008 */ - uint64_t p_wid_err_upper; /* 0x000010 */ - uint64_t p_wid_err_lower; /* 0x000018 */ + u64 p_wid_id; /* 0x000000 */ + u64 p_wid_stat; /* 0x000008 */ + u64 p_wid_err_upper; /* 0x000010 */ + u64 p_wid_err_lower; /* 0x000018 */ #define p_wid_err p_wid_err_lower - uint64_t p_wid_control; /* 0x000020 */ - uint64_t p_wid_req_timeout; /* 0x000028 */ - uint64_t p_wid_int_upper; /* 0x000030 */ - uint64_t p_wid_int_lower; /* 0x000038 */ + u64 p_wid_control; /* 0x000020 */ + u64 p_wid_req_timeout; /* 0x000028 */ + u64 p_wid_int_upper; /* 0x000030 */ + u64 p_wid_int_lower; /* 0x000038 */ #define p_wid_int p_wid_int_lower - uint64_t p_wid_err_cmdword; /* 0x000040 */ - uint64_t p_wid_llp; /* 0x000048 */ - uint64_t p_wid_tflush; /* 0x000050 */ + u64 p_wid_err_cmdword; /* 0x000040 */ + u64 p_wid_llp; /* 0x000048 */ + u64 p_wid_tflush; /* 0x000050 */ /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */ - uint64_t p_wid_aux_err; /* 0x000058 */ - uint64_t p_wid_resp_upper; /* 0x000060 */ - uint64_t p_wid_resp_lower; /* 0x000068 */ + u64 p_wid_aux_err; /* 0x000058 */ + u64 p_wid_resp_upper; /* 0x000060 */ + u64 p_wid_resp_lower; /* 0x000068 */ #define p_wid_resp p_wid_resp_lower - uint64_t p_wid_tst_pin_ctrl; /* 0x000070 */ - uint64_t p_wid_addr_lkerr; /* 0x000078 */ + u64 p_wid_tst_pin_ctrl; /* 0x000070 */ + u64 p_wid_addr_lkerr; /* 0x000078 */ /* 0x000080-0x00008F -- PMU & MAP */ - uint64_t p_dir_map; /* 0x000080 */ - uint64_t _pad_000088; /* 0x000088 */ + u64 p_dir_map; /* 0x000080 */ + u64 _pad_000088; /* 0x000088 */ /* 0x000090-0x00009F -- SSRAM */ - uint64_t p_map_fault; /* 0x000090 */ - uint64_t _pad_000098; /* 0x000098 */ + u64 p_map_fault; /* 0x000090 */ + u64 _pad_000098; /* 0x000098 */ /* 0x0000A0-0x0000AF -- Arbitration */ - uint64_t p_arb; /* 0x0000A0 */ - uint64_t _pad_0000A8; /* 0x0000A8 */ + u64 p_arb; /* 0x0000A0 */ + u64 _pad_0000A8; /* 0x0000A8 */ /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */ - uint64_t p_ate_parity_err; /* 0x0000B0 */ - uint64_t _pad_0000B8; /* 0x0000B8 */ + u64 p_ate_parity_err; /* 0x0000B0 */ + u64 _pad_0000B8; /* 0x0000B8 */ /* 0x0000C0-0x0000FF -- PCI/GIO */ - uint64_t p_bus_timeout; /* 0x0000C0 */ - uint64_t p_pci_cfg; /* 0x0000C8 */ - uint64_t p_pci_err_upper; /* 0x0000D0 */ - uint64_t p_pci_err_lower; /* 0x0000D8 */ + u64 p_bus_timeout; /* 0x0000C0 */ + u64 p_pci_cfg; /* 0x0000C8 */ + u64 p_pci_err_upper; /* 0x0000D0 */ + u64 p_pci_err_lower; /* 0x0000D8 */ #define p_pci_err p_pci_err_lower - uint64_t _pad_0000E0[4]; /* 0x0000{E0..F8} */ + u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */ /* 0x000100-0x0001FF -- Interrupt */ - uint64_t p_int_status; /* 0x000100 */ - uint64_t p_int_enable; /* 0x000108 */ - uint64_t p_int_rst_stat; /* 0x000110 */ - uint64_t p_int_mode; /* 0x000118 */ - uint64_t p_int_device; /* 0x000120 */ - uint64_t p_int_host_err; /* 0x000128 */ - uint64_t p_int_addr[8]; /* 0x0001{30,,,68} */ - uint64_t p_err_int_view; /* 0x000170 */ - uint64_t p_mult_int; /* 0x000178 */ - uint64_t p_force_always[8]; /* 0x0001{80,,,B8} */ - uint64_t p_force_pin[8]; /* 0x0001{C0,,,F8} */ + u64 p_int_status; /* 0x000100 */ + u64 p_int_enable; /* 0x000108 */ + u64 p_int_rst_stat; /* 0x000110 */ + u64 p_int_mode; /* 0x000118 */ + u64 p_int_device; /* 0x000120 */ + u64 p_int_host_err; /* 0x000128 */ + u64 p_int_addr[8]; /* 0x0001{30,,,68} */ + u64 p_err_int_view; /* 0x000170 */ + u64 p_mult_int; /* 0x000178 */ + u64 p_force_always[8]; /* 0x0001{80,,,B8} */ + u64 p_force_pin[8]; /* 0x0001{C0,,,F8} */ /* 0x000200-0x000298 -- Device */ - uint64_t p_device[4]; /* 0x0002{00,,,18} */ - uint64_t _pad_000220[4]; /* 0x0002{20,,,38} */ - uint64_t p_wr_req_buf[4]; /* 0x0002{40,,,58} */ - uint64_t _pad_000260[4]; /* 0x0002{60,,,78} */ - uint64_t p_rrb_map[2]; /* 0x0002{80,,,88} */ + u64 p_device[4]; /* 0x0002{00,,,18} */ + u64 _pad_000220[4]; /* 0x0002{20,,,38} */ + u64 p_wr_req_buf[4]; /* 0x0002{40,,,58} */ + u64 _pad_000260[4]; /* 0x0002{60,,,78} */ + u64 p_rrb_map[2]; /* 0x0002{80,,,88} */ #define p_even_resp p_rrb_map[0] /* 0x000280 */ #define p_odd_resp p_rrb_map[1] /* 0x000288 */ - uint64_t p_resp_status; /* 0x000290 */ - uint64_t p_resp_clear; /* 0x000298 */ + u64 p_resp_status; /* 0x000290 */ + u64 p_resp_clear; /* 0x000298 */ - uint64_t _pad_0002A0[12]; /* 0x0002{A0..F8} */ + u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */ /* 0x000300-0x0003F8 -- Buffer Address Match Registers */ struct { - uint64_t upper; /* 0x0003{00,,,F0} */ - uint64_t lower; /* 0x0003{08,,,F8} */ + u64 upper; /* 0x0003{00,,,F0} */ + u64 lower; /* 0x0003{08,,,F8} */ } p_buf_addr_match[16]; /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */ struct { - uint64_t flush_w_touch; /* 0x000{400,,,5C0} */ - uint64_t flush_wo_touch; /* 0x000{408,,,5C8} */ - uint64_t inflight; /* 0x000{410,,,5D0} */ - uint64_t prefetch; /* 0x000{418,,,5D8} */ - uint64_t total_pci_retry; /* 0x000{420,,,5E0} */ - uint64_t max_pci_retry; /* 0x000{428,,,5E8} */ - uint64_t max_latency; /* 0x000{430,,,5F0} */ - uint64_t clear_all; /* 0x000{438,,,5F8} */ + u64 flush_w_touch; /* 0x000{400,,,5C0} */ + u64 flush_wo_touch; /* 0x000{408,,,5C8} */ + u64 inflight; /* 0x000{410,,,5D0} */ + u64 prefetch; /* 0x000{418,,,5D8} */ + u64 total_pci_retry; /* 0x000{420,,,5E0} */ + u64 max_pci_retry; /* 0x000{428,,,5E8} */ + u64 max_latency; /* 0x000{430,,,5F0} */ + u64 clear_all; /* 0x000{438,,,5F8} */ } p_buf_count[8]; /* 0x000600-0x0009FF -- PCI/X registers */ - uint64_t p_pcix_bus_err_addr; /* 0x000600 */ - uint64_t p_pcix_bus_err_attr; /* 0x000608 */ - uint64_t p_pcix_bus_err_data; /* 0x000610 */ - uint64_t p_pcix_pio_split_addr; /* 0x000618 */ - uint64_t p_pcix_pio_split_attr; /* 0x000620 */ - uint64_t p_pcix_dma_req_err_attr; /* 0x000628 */ - uint64_t p_pcix_dma_req_err_addr; /* 0x000630 */ - uint64_t p_pcix_timeout; /* 0x000638 */ + u64 p_pcix_bus_err_addr; /* 0x000600 */ + u64 p_pcix_bus_err_attr; /* 0x000608 */ + u64 p_pcix_bus_err_data; /* 0x000610 */ + u64 p_pcix_pio_split_addr; /* 0x000618 */ + u64 p_pcix_pio_split_attr; /* 0x000620 */ + u64 p_pcix_dma_req_err_attr; /* 0x000628 */ + u64 p_pcix_dma_req_err_addr; /* 0x000630 */ + u64 p_pcix_timeout; /* 0x000638 */ - uint64_t _pad_000640[120]; /* 0x000{640,,,9F8} */ + u64 _pad_000640[120]; /* 0x000{640,,,9F8} */ /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */ struct { - uint64_t p_buf_addr; /* 0x000{A00,,,AF0} */ - uint64_t p_buf_attr; /* 0X000{A08,,,AF8} */ + u64 p_buf_addr; /* 0x000{A00,,,AF0} */ + u64 p_buf_attr; /* 0X000{A08,,,AF8} */ } p_pcix_read_buf_64[16]; struct { - uint64_t p_buf_addr; /* 0x000{B00,,,BE0} */ - uint64_t p_buf_attr; /* 0x000{B08,,,BE8} */ - uint64_t p_buf_valid; /* 0x000{B10,,,BF0} */ - uint64_t __pad1; /* 0x000{B18,,,BF8} */ + u64 p_buf_addr; /* 0x000{B00,,,BE0} */ + u64 p_buf_attr; /* 0x000{B08,,,BE8} */ + u64 p_buf_valid; /* 0x000{B10,,,BF0} */ + u64 __pad1; /* 0x000{B18,,,BF8} */ } p_pcix_write_buf_64[8]; /* End of Local Registers -- Start of Address Map space */ @@ -195,45 +195,45 @@ struct pic { char _pad_000c00[0x010000 - 0x000c00]; /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */ - uint64_t p_int_ate_ram[1024]; /* 0x010000-0x011fff */ + u64 p_int_ate_ram[1024]; /* 0x010000-0x011fff */ /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */ - uint64_t p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */ + u64 p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */ char _pad_014000[0x18000 - 0x014000]; /* 0x18000-0x197F8 -- PIC Write Request Ram */ - uint64_t p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */ - uint64_t p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */ - uint64_t p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */ + u64 p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */ + u64 p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */ + u64 p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */ char _pad_019800[0x20000 - 0x019800]; /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */ union { - uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ - uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ - uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ - uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ + u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ + u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ + u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ + u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ union { - uint8_t c[0x100 / 1]; - uint16_t s[0x100 / 2]; - uint32_t l[0x100 / 4]; - uint64_t d[0x100 / 8]; + u8 c[0x100 / 1]; + u16 s[0x100 / 2]; + u32 l[0x100 / 4]; + u64 d[0x100 / 8]; } f[8]; } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */ /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */ union { - uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */ - uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */ - uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */ - uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */ + u8 c[0x1000 / 1]; /* 0x028000-0x029000 */ + u16 s[0x1000 / 2]; /* 0x028000-0x029000 */ + u32 l[0x1000 / 4]; /* 0x028000-0x029000 */ + u64 d[0x1000 / 8]; /* 0x028000-0x029000 */ union { - uint8_t c[0x100 / 1]; - uint16_t s[0x100 / 2]; - uint32_t l[0x100 / 4]; - uint64_t d[0x100 / 8]; + u8 c[0x100 / 1]; + u16 s[0x100 / 2]; + u32 l[0x100 / 4]; + u64 d[0x100 / 8]; } f[8]; } p_type1_cfg; /* 0x028000-0x029000 */ @@ -241,20 +241,20 @@ struct pic { /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */ union { - uint8_t c[8 / 1]; - uint16_t s[8 / 2]; - uint32_t l[8 / 4]; - uint64_t d[8 / 8]; + u8 c[8 / 1]; + u16 s[8 / 2]; + u32 l[8 / 4]; + u64 d[8 / 8]; } p_pci_iack; /* 0x030000-0x030007 */ char _pad_030007[0x040000-0x030008]; /* 0x040000-0x030007 -- PCIX Special Cycle */ union { - uint8_t c[8 / 1]; - uint16_t s[8 / 2]; - uint32_t l[8 / 4]; - uint64_t d[8 / 8]; + u8 c[8 / 1]; + u16 s[8 / 2]; + u32 l[8 / 4]; + u64 d[8 / 8]; } p_pcix_cycle; /* 0x040000-0x040007 */ }; diff --git a/include/asm-ia64/sn/shubio.h b/include/asm-ia64/sn/shubio.h index 831b72111fdc..22a6f18a5313 100644 --- a/include/asm-ia64/sn/shubio.h +++ b/include/asm-ia64/sn/shubio.h @@ -227,13 +227,13 @@ ************************************************************************/ typedef union ii_wid_u { - uint64_t ii_wid_regval; + u64 ii_wid_regval; struct { - uint64_t w_rsvd_1:1; - uint64_t w_mfg_num:11; - uint64_t w_part_num:16; - uint64_t w_rev_num:4; - uint64_t w_rsvd:32; + u64 w_rsvd_1:1; + u64 w_mfg_num:11; + u64 w_part_num:16; + u64 w_rev_num:4; + u64 w_rsvd:32; } ii_wid_fld_s; } ii_wid_u_t; @@ -246,18 +246,18 @@ typedef union ii_wid_u { ************************************************************************/ typedef union ii_wstat_u { - uint64_t ii_wstat_regval; - struct { - uint64_t w_pending:4; - uint64_t w_xt_crd_to:1; - uint64_t w_xt_tail_to:1; - uint64_t w_rsvd_3:3; - uint64_t w_tx_mx_rty:1; - uint64_t w_rsvd_2:6; - uint64_t w_llp_tx_cnt:8; - uint64_t w_rsvd_1:8; - uint64_t w_crazy:1; - uint64_t w_rsvd:31; + u64 ii_wstat_regval; + struct { + u64 w_pending:4; + u64 w_xt_crd_to:1; + u64 w_xt_tail_to:1; + u64 w_rsvd_3:3; + u64 w_tx_mx_rty:1; + u64 w_rsvd_2:6; + u64 w_llp_tx_cnt:8; + u64 w_rsvd_1:8; + u64 w_crazy:1; + u64 w_rsvd:31; } ii_wstat_fld_s; } ii_wstat_u_t; @@ -269,16 +269,16 @@ typedef union ii_wstat_u { ************************************************************************/ typedef union ii_wcr_u { - uint64_t ii_wcr_regval; - struct { - uint64_t w_wid:4; - uint64_t w_tag:1; - uint64_t w_rsvd_1:8; - uint64_t w_dst_crd:3; - uint64_t w_f_bad_pkt:1; - uint64_t w_dir_con:1; - uint64_t w_e_thresh:5; - uint64_t w_rsvd:41; + u64 ii_wcr_regval; + struct { + u64 w_wid:4; + u64 w_tag:1; + u64 w_rsvd_1:8; + u64 w_dst_crd:3; + u64 w_f_bad_pkt:1; + u64 w_dir_con:1; + u64 w_e_thresh:5; + u64 w_rsvd:41; } ii_wcr_fld_s; } ii_wcr_u_t; @@ -310,9 +310,9 @@ typedef union ii_wcr_u { ************************************************************************/ typedef union ii_ilapr_u { - uint64_t ii_ilapr_regval; + u64 ii_ilapr_regval; struct { - uint64_t i_region:64; + u64 i_region:64; } ii_ilapr_fld_s; } ii_ilapr_u_t; @@ -330,9 +330,9 @@ typedef union ii_ilapr_u { ************************************************************************/ typedef union ii_ilapo_u { - uint64_t ii_ilapo_regval; + u64 ii_ilapo_regval; struct { - uint64_t i_io_ovrride:64; + u64 i_io_ovrride:64; } ii_ilapo_fld_s; } ii_ilapo_u_t; @@ -344,12 +344,12 @@ typedef union ii_ilapo_u { ************************************************************************/ typedef union ii_iowa_u { - uint64_t ii_iowa_regval; + u64 ii_iowa_regval; struct { - uint64_t i_w0_oac:1; - uint64_t i_rsvd_1:7; - uint64_t i_wx_oac:8; - uint64_t i_rsvd:48; + u64 i_w0_oac:1; + u64 i_rsvd_1:7; + u64 i_wx_oac:8; + u64 i_rsvd:48; } ii_iowa_fld_s; } ii_iowa_u_t; @@ -363,12 +363,12 @@ typedef union ii_iowa_u { ************************************************************************/ typedef union ii_iiwa_u { - uint64_t ii_iiwa_regval; + u64 ii_iiwa_regval; struct { - uint64_t i_w0_iac:1; - uint64_t i_rsvd_1:7; - uint64_t i_wx_iac:8; - uint64_t i_rsvd:48; + u64 i_w0_iac:1; + u64 i_rsvd_1:7; + u64 i_wx_iac:8; + u64 i_rsvd:48; } ii_iiwa_fld_s; } ii_iiwa_u_t; @@ -392,16 +392,16 @@ typedef union ii_iiwa_u { ************************************************************************/ typedef union ii_iidem_u { - uint64_t ii_iidem_regval; - struct { - uint64_t i_w8_dxs:8; - uint64_t i_w9_dxs:8; - uint64_t i_wa_dxs:8; - uint64_t i_wb_dxs:8; - uint64_t i_wc_dxs:8; - uint64_t i_wd_dxs:8; - uint64_t i_we_dxs:8; - uint64_t i_wf_dxs:8; + u64 ii_iidem_regval; + struct { + u64 i_w8_dxs:8; + u64 i_w9_dxs:8; + u64 i_wa_dxs:8; + u64 i_wb_dxs:8; + u64 i_wc_dxs:8; + u64 i_wd_dxs:8; + u64 i_we_dxs:8; + u64 i_wf_dxs:8; } ii_iidem_fld_s; } ii_iidem_u_t; @@ -413,22 +413,22 @@ typedef union ii_iidem_u { ************************************************************************/ typedef union ii_ilcsr_u { - uint64_t ii_ilcsr_regval; - struct { - uint64_t i_nullto:6; - uint64_t i_rsvd_4:2; - uint64_t i_wrmrst:1; - uint64_t i_rsvd_3:1; - uint64_t i_llp_en:1; - uint64_t i_bm8:1; - uint64_t i_llp_stat:2; - uint64_t i_remote_power:1; - uint64_t i_rsvd_2:1; - uint64_t i_maxrtry:10; - uint64_t i_d_avail_sel:2; - uint64_t i_rsvd_1:4; - uint64_t i_maxbrst:10; - uint64_t i_rsvd:22; + u64 ii_ilcsr_regval; + struct { + u64 i_nullto:6; + u64 i_rsvd_4:2; + u64 i_wrmrst:1; + u64 i_rsvd_3:1; + u64 i_llp_en:1; + u64 i_bm8:1; + u64 i_llp_stat:2; + u64 i_remote_power:1; + u64 i_rsvd_2:1; + u64 i_maxrtry:10; + u64 i_d_avail_sel:2; + u64 i_rsvd_1:4; + u64 i_maxbrst:10; + u64 i_rsvd:22; } ii_ilcsr_fld_s; } ii_ilcsr_u_t; @@ -441,11 +441,11 @@ typedef union ii_ilcsr_u { ************************************************************************/ typedef union ii_illr_u { - uint64_t ii_illr_regval; + u64 ii_illr_regval; struct { - uint64_t i_sn_cnt:16; - uint64_t i_cb_cnt:16; - uint64_t i_rsvd:32; + u64 i_sn_cnt:16; + u64 i_cb_cnt:16; + u64 i_rsvd:32; } ii_illr_fld_s; } ii_illr_u_t; @@ -464,19 +464,19 @@ typedef union ii_illr_u { ************************************************************************/ typedef union ii_iidsr_u { - uint64_t ii_iidsr_regval; - struct { - uint64_t i_level:8; - uint64_t i_pi_id:1; - uint64_t i_node:11; - uint64_t i_rsvd_3:4; - uint64_t i_enable:1; - uint64_t i_rsvd_2:3; - uint64_t i_int_sent:2; - uint64_t i_rsvd_1:2; - uint64_t i_pi0_forward_int:1; - uint64_t i_pi1_forward_int:1; - uint64_t i_rsvd:30; + u64 ii_iidsr_regval; + struct { + u64 i_level:8; + u64 i_pi_id:1; + u64 i_node:11; + u64 i_rsvd_3:4; + u64 i_enable:1; + u64 i_rsvd_2:3; + u64 i_int_sent:2; + u64 i_rsvd_1:2; + u64 i_pi0_forward_int:1; + u64 i_pi1_forward_int:1; + u64 i_rsvd:30; } ii_iidsr_fld_s; } ii_iidsr_u_t; @@ -492,13 +492,13 @@ typedef union ii_iidsr_u { ************************************************************************/ typedef union ii_igfx0_u { - uint64_t ii_igfx0_regval; + u64 ii_igfx0_regval; struct { - uint64_t i_w_num:4; - uint64_t i_pi_id:1; - uint64_t i_n_num:12; - uint64_t i_p_num:1; - uint64_t i_rsvd:46; + u64 i_w_num:4; + u64 i_pi_id:1; + u64 i_n_num:12; + u64 i_p_num:1; + u64 i_rsvd:46; } ii_igfx0_fld_s; } ii_igfx0_u_t; @@ -514,13 +514,13 @@ typedef union ii_igfx0_u { ************************************************************************/ typedef union ii_igfx1_u { - uint64_t ii_igfx1_regval; + u64 ii_igfx1_regval; struct { - uint64_t i_w_num:4; - uint64_t i_pi_id:1; - uint64_t i_n_num:12; - uint64_t i_p_num:1; - uint64_t i_rsvd:46; + u64 i_w_num:4; + u64 i_pi_id:1; + u64 i_n_num:12; + u64 i_p_num:1; + u64 i_rsvd:46; } ii_igfx1_fld_s; } ii_igfx1_u_t; @@ -532,9 +532,9 @@ typedef union ii_igfx1_u { ************************************************************************/ typedef union ii_iscr0_u { - uint64_t ii_iscr0_regval; + u64 ii_iscr0_regval; struct { - uint64_t i_scratch:64; + u64 i_scratch:64; } ii_iscr0_fld_s; } ii_iscr0_u_t; @@ -546,9 +546,9 @@ typedef union ii_iscr0_u { ************************************************************************/ typedef union ii_iscr1_u { - uint64_t ii_iscr1_regval; + u64 ii_iscr1_regval; struct { - uint64_t i_scratch:64; + u64 i_scratch:64; } ii_iscr1_fld_s; } ii_iscr1_u_t; @@ -580,13 +580,13 @@ typedef union ii_iscr1_u { ************************************************************************/ typedef union ii_itte1_u { - uint64_t ii_itte1_regval; + u64 ii_itte1_regval; struct { - uint64_t i_offset:5; - uint64_t i_rsvd_1:3; - uint64_t i_w_num:4; - uint64_t i_iosp:1; - uint64_t i_rsvd:51; + u64 i_offset:5; + u64 i_rsvd_1:3; + u64 i_w_num:4; + u64 i_iosp:1; + u64 i_rsvd:51; } ii_itte1_fld_s; } ii_itte1_u_t; @@ -618,13 +618,13 @@ typedef union ii_itte1_u { ************************************************************************/ typedef union ii_itte2_u { - uint64_t ii_itte2_regval; + u64 ii_itte2_regval; struct { - uint64_t i_offset:5; - uint64_t i_rsvd_1:3; - uint64_t i_w_num:4; - uint64_t i_iosp:1; - uint64_t i_rsvd:51; + u64 i_offset:5; + u64 i_rsvd_1:3; + u64 i_w_num:4; + u64 i_iosp:1; + u64 i_rsvd:51; } ii_itte2_fld_s; } ii_itte2_u_t; @@ -656,13 +656,13 @@ typedef union ii_itte2_u { ************************************************************************/ typedef union ii_itte3_u { - uint64_t ii_itte3_regval; + u64 ii_itte3_regval; struct { - uint64_t i_offset:5; - uint64_t i_rsvd_1:3; - uint64_t i_w_num:4; - uint64_t i_iosp:1; - uint64_t i_rsvd:51; + u64 i_offset:5; + u64 i_rsvd_1:3; + u64 i_w_num:4; + u64 i_iosp:1; + u64 i_rsvd:51; } ii_itte3_fld_s; } ii_itte3_u_t; @@ -694,13 +694,13 @@ typedef union ii_itte3_u { ************************************************************************/ typedef union ii_itte4_u { - uint64_t ii_itte4_regval; + u64 ii_itte4_regval; struct { - uint64_t i_offset:5; - uint64_t i_rsvd_1:3; - uint64_t i_w_num:4; - uint64_t i_iosp:1; - uint64_t i_rsvd:51; + u64 i_offset:5; + u64 i_rsvd_1:3; + u64 i_w_num:4; + u64 i_iosp:1; + u64 i_rsvd:51; } ii_itte4_fld_s; } ii_itte4_u_t; @@ -732,13 +732,13 @@ typedef union ii_itte4_u { ************************************************************************/ typedef union ii_itte5_u { - uint64_t ii_itte5_regval; + u64 ii_itte5_regval; struct { - uint64_t i_offset:5; - uint64_t i_rsvd_1:3; - uint64_t i_w_num:4; - uint64_t i_iosp:1; - uint64_t i_rsvd:51; + u64 i_offset:5; + u64 i_rsvd_1:3; + u64 i_w_num:4; + u64 i_iosp:1; + u64 i_rsvd:51; } ii_itte5_fld_s; } ii_itte5_u_t; @@ -770,13 +770,13 @@ typedef union ii_itte5_u { ************************************************************************/ typedef union ii_itte6_u { - uint64_t ii_itte6_regval; + u64 ii_itte6_regval; struct { - uint64_t i_offset:5; - uint64_t i_rsvd_1:3; - uint64_t i_w_num:4; - uint64_t i_iosp:1; - uint64_t i_rsvd:51; + u64 i_offset:5; + u64 i_rsvd_1:3; + u64 i_w_num:4; + u64 i_iosp:1; + u64 i_rsvd:51; } ii_itte6_fld_s; } ii_itte6_u_t; @@ -808,13 +808,13 @@ typedef union ii_itte6_u { ************************************************************************/ typedef union ii_itte7_u { - uint64_t ii_itte7_regval; + u64 ii_itte7_regval; struct { - uint64_t i_offset:5; - uint64_t i_rsvd_1:3; - uint64_t i_w_num:4; - uint64_t i_iosp:1; - uint64_t i_rsvd:51; + u64 i_offset:5; + u64 i_rsvd_1:3; + u64 i_w_num:4; + u64 i_iosp:1; + u64 i_rsvd:51; } ii_itte7_fld_s; } ii_itte7_u_t; @@ -843,22 +843,22 @@ typedef union ii_itte7_u { ************************************************************************/ typedef union ii_iprb0_u { - uint64_t ii_iprb0_regval; - struct { - uint64_t i_c:8; - uint64_t i_na:14; - uint64_t i_rsvd_2:2; - uint64_t i_nb:14; - uint64_t i_rsvd_1:2; - uint64_t i_m:2; - uint64_t i_f:1; - uint64_t i_of_cnt:5; - uint64_t i_error:1; - uint64_t i_rd_to:1; - uint64_t i_spur_wr:1; - uint64_t i_spur_rd:1; - uint64_t i_rsvd:11; - uint64_t i_mult_err:1; + u64 ii_iprb0_regval; + struct { + u64 i_c:8; + u64 i_na:14; + u64 i_rsvd_2:2; + u64 i_nb:14; + u64 i_rsvd_1:2; + u64 i_m:2; + u64 i_f:1; + u64 i_of_cnt:5; + u64 i_error:1; + u64 i_rd_to:1; + u64 i_spur_wr:1; + u64 i_spur_rd:1; + u64 i_rsvd:11; + u64 i_mult_err:1; } ii_iprb0_fld_s; } ii_iprb0_u_t; @@ -887,22 +887,22 @@ typedef union ii_iprb0_u { ************************************************************************/ typedef union ii_iprb8_u { - uint64_t ii_iprb8_regval; - struct { - uint64_t i_c:8; - uint64_t i_na:14; - uint64_t i_rsvd_2:2; - uint64_t i_nb:14; - uint64_t i_rsvd_1:2; - uint64_t i_m:2; - uint64_t i_f:1; - uint64_t i_of_cnt:5; - uint64_t i_error:1; - uint64_t i_rd_to:1; - uint64_t i_spur_wr:1; - uint64_t i_spur_rd:1; - uint64_t i_rsvd:11; - uint64_t i_mult_err:1; + u64 ii_iprb8_regval; + struct { + u64 i_c:8; + u64 i_na:14; + u64 i_rsvd_2:2; + u64 i_nb:14; + u64 i_rsvd_1:2; + u64 i_m:2; + u64 i_f:1; + u64 i_of_cnt:5; + u64 i_error:1; + u64 i_rd_to:1; + u64 i_spur_wr:1; + u64 i_spur_rd:1; + u64 i_rsvd:11; + u64 i_mult_err:1; } ii_iprb8_fld_s; } ii_iprb8_u_t; @@ -931,22 +931,22 @@ typedef union ii_iprb8_u { ************************************************************************/ typedef union ii_iprb9_u { - uint64_t ii_iprb9_regval; - struct { - uint64_t i_c:8; - uint64_t i_na:14; - uint64_t i_rsvd_2:2; - uint64_t i_nb:14; - uint64_t i_rsvd_1:2; - uint64_t i_m:2; - uint64_t i_f:1; - uint64_t i_of_cnt:5; - uint64_t i_error:1; - uint64_t i_rd_to:1; - uint64_t i_spur_wr:1; - uint64_t i_spur_rd:1; - uint64_t i_rsvd:11; - uint64_t i_mult_err:1; + u64 ii_iprb9_regval; + struct { + u64 i_c:8; + u64 i_na:14; + u64 i_rsvd_2:2; + u64 i_nb:14; + u64 i_rsvd_1:2; + u64 i_m:2; + u64 i_f:1; + u64 i_of_cnt:5; + u64 i_error:1; + u64 i_rd_to:1; + u64 i_spur_wr:1; + u64 i_spur_rd:1; + u64 i_rsvd:11; + u64 i_mult_err:1; } ii_iprb9_fld_s; } ii_iprb9_u_t; @@ -975,22 +975,22 @@ typedef union ii_iprb9_u { ************************************************************************/ typedef union ii_iprba_u { - uint64_t ii_iprba_regval; - struct { - uint64_t i_c:8; - uint64_t i_na:14; - uint64_t i_rsvd_2:2; - uint64_t i_nb:14; - uint64_t i_rsvd_1:2; - uint64_t i_m:2; - uint64_t i_f:1; - uint64_t i_of_cnt:5; - uint64_t i_error:1; - uint64_t i_rd_to:1; - uint64_t i_spur_wr:1; - uint64_t i_spur_rd:1; - uint64_t i_rsvd:11; - uint64_t i_mult_err:1; + u64 ii_iprba_regval; + struct { + u64 i_c:8; + u64 i_na:14; + u64 i_rsvd_2:2; + u64 i_nb:14; + u64 i_rsvd_1:2; + u64 i_m:2; + u64 i_f:1; + u64 i_of_cnt:5; + u64 i_error:1; + u64 i_rd_to:1; + u64 i_spur_wr:1; + u64 i_spur_rd:1; + u64 i_rsvd:11; + u64 i_mult_err:1; } ii_iprba_fld_s; } ii_iprba_u_t; @@ -1019,22 +1019,22 @@ typedef union ii_iprba_u { ************************************************************************/ typedef union ii_iprbb_u { - uint64_t ii_iprbb_regval; - struct { - uint64_t i_c:8; - uint64_t i_na:14; - uint64_t i_rsvd_2:2; - uint64_t i_nb:14; - uint64_t i_rsvd_1:2; - uint64_t i_m:2; - uint64_t i_f:1; - uint64_t i_of_cnt:5; - uint64_t i_error:1; - uint64_t i_rd_to:1; - uint64_t i_spur_wr:1; - uint64_t i_spur_rd:1; - uint64_t i_rsvd:11; - uint64_t i_mult_err:1; + u64 ii_iprbb_regval; + struct { + u64 i_c:8; + u64 i_na:14; + u64 i_rsvd_2:2; + u64 i_nb:14; + u64 i_rsvd_1:2; + u64 i_m:2; + u64 i_f:1; + u64 i_of_cnt:5; + u64 i_error:1; + u64 i_rd_to:1; + u64 i_spur_wr:1; + u64 i_spur_rd:1; + u64 i_rsvd:11; + u64 i_mult_err:1; } ii_iprbb_fld_s; } ii_iprbb_u_t; @@ -1063,22 +1063,22 @@ typedef union ii_iprbb_u { ************************************************************************/ typedef union ii_iprbc_u { - uint64_t ii_iprbc_regval; - struct { - uint64_t i_c:8; - uint64_t i_na:14; - uint64_t i_rsvd_2:2; - uint64_t i_nb:14; - uint64_t i_rsvd_1:2; - uint64_t i_m:2; - uint64_t i_f:1; - uint64_t i_of_cnt:5; - uint64_t i_error:1; - uint64_t i_rd_to:1; - uint64_t i_spur_wr:1; - uint64_t i_spur_rd:1; - uint64_t i_rsvd:11; - uint64_t i_mult_err:1; + u64 ii_iprbc_regval; + struct { + u64 i_c:8; + u64 i_na:14; + u64 i_rsvd_2:2; + u64 i_nb:14; + u64 i_rsvd_1:2; + u64 i_m:2; + u64 i_f:1; + u64 i_of_cnt:5; + u64 i_error:1; + u64 i_rd_to:1; + u64 i_spur_wr:1; + u64 i_spur_rd:1; + u64 i_rsvd:11; + u64 i_mult_err:1; } ii_iprbc_fld_s; } ii_iprbc_u_t; @@ -1107,22 +1107,22 @@ typedef union ii_iprbc_u { ************************************************************************/ typedef union ii_iprbd_u { - uint64_t ii_iprbd_regval; - struct { - uint64_t i_c:8; - uint64_t i_na:14; - uint64_t i_rsvd_2:2; - uint64_t i_nb:14; - uint64_t i_rsvd_1:2; - uint64_t i_m:2; - uint64_t i_f:1; - uint64_t i_of_cnt:5; - uint64_t i_error:1; - uint64_t i_rd_to:1; - uint64_t i_spur_wr:1; - uint64_t i_spur_rd:1; - uint64_t i_rsvd:11; - uint64_t i_mult_err:1; + u64 ii_iprbd_regval; + struct { + u64 i_c:8; + u64 i_na:14; + u64 i_rsvd_2:2; + u64 i_nb:14; + u64 i_rsvd_1:2; + u64 i_m:2; + u64 i_f:1; + u64 i_of_cnt:5; + u64 i_error:1; + u64 i_rd_to:1; + u64 i_spur_wr:1; + u64 i_spur_rd:1; + u64 i_rsvd:11; + u64 i_mult_err:1; } ii_iprbd_fld_s; } ii_iprbd_u_t; @@ -1151,22 +1151,22 @@ typedef union ii_iprbd_u { ************************************************************************/ typedef union ii_iprbe_u { - uint64_t ii_iprbe_regval; - struct { - uint64_t i_c:8; - uint64_t i_na:14; - uint64_t i_rsvd_2:2; - uint64_t i_nb:14; - uint64_t i_rsvd_1:2; - uint64_t i_m:2; - uint64_t i_f:1; - uint64_t i_of_cnt:5; - uint64_t i_error:1; - uint64_t i_rd_to:1; - uint64_t i_spur_wr:1; - uint64_t i_spur_rd:1; - uint64_t i_rsvd:11; - uint64_t i_mult_err:1; + u64 ii_iprbe_regval; + struct { + u64 i_c:8; + u64 i_na:14; + u64 i_rsvd_2:2; + u64 i_nb:14; + u64 i_rsvd_1:2; + u64 i_m:2; + u64 i_f:1; + u64 i_of_cnt:5; + u64 i_error:1; + u64 i_rd_to:1; + u64 i_spur_wr:1; + u64 i_spur_rd:1; + u64 i_rsvd:11; + u64 i_mult_err:1; } ii_iprbe_fld_s; } ii_iprbe_u_t; @@ -1195,22 +1195,22 @@ typedef union ii_iprbe_u { ************************************************************************/ typedef union ii_iprbf_u { - uint64_t ii_iprbf_regval; - struct { - uint64_t i_c:8; - uint64_t i_na:14; - uint64_t i_rsvd_2:2; - uint64_t i_nb:14; - uint64_t i_rsvd_1:2; - uint64_t i_m:2; - uint64_t i_f:1; - uint64_t i_of_cnt:5; - uint64_t i_error:1; - uint64_t i_rd_to:1; - uint64_t i_spur_wr:1; - uint64_t i_spur_rd:1; - uint64_t i_rsvd:11; - uint64_t i_mult_err:1; + u64 ii_iprbf_regval; + struct { + u64 i_c:8; + u64 i_na:14; + u64 i_rsvd_2:2; + u64 i_nb:14; + u64 i_rsvd_1:2; + u64 i_m:2; + u64 i_f:1; + u64 i_of_cnt:5; + u64 i_error:1; + u64 i_rd_to:1; + u64 i_spur_wr:1; + u64 i_spur_rd:1; + u64 i_rsvd:11; + u64 i_mult_err:1; } ii_iprbe_fld_s; } ii_iprbf_u_t; @@ -1232,10 +1232,10 @@ typedef union ii_iprbf_u { ************************************************************************/ typedef union ii_ixcc_u { - uint64_t ii_ixcc_regval; + u64 ii_ixcc_regval; struct { - uint64_t i_time_out:26; - uint64_t i_rsvd:38; + u64 i_time_out:26; + u64 i_rsvd:38; } ii_ixcc_fld_s; } ii_ixcc_u_t; @@ -1256,16 +1256,16 @@ typedef union ii_ixcc_u { ************************************************************************/ typedef union ii_imem_u { - uint64_t ii_imem_regval; - struct { - uint64_t i_w0_esd:1; - uint64_t i_rsvd_3:3; - uint64_t i_b0_esd:1; - uint64_t i_rsvd_2:3; - uint64_t i_b1_esd:1; - uint64_t i_rsvd_1:3; - uint64_t i_clr_precise:1; - uint64_t i_rsvd:51; + u64 ii_imem_regval; + struct { + u64 i_w0_esd:1; + u64 i_rsvd_3:3; + u64 i_b0_esd:1; + u64 i_rsvd_2:3; + u64 i_b1_esd:1; + u64 i_rsvd_1:3; + u64 i_clr_precise:1; + u64 i_rsvd:51; } ii_imem_fld_s; } ii_imem_u_t; @@ -1294,13 +1294,13 @@ typedef union ii_imem_u { ************************************************************************/ typedef union ii_ixtt_u { - uint64_t ii_ixtt_regval; + u64 ii_ixtt_regval; struct { - uint64_t i_tail_to:26; - uint64_t i_rsvd_1:6; - uint64_t i_rrsp_ps:23; - uint64_t i_rrsp_to:5; - uint64_t i_rsvd:4; + u64 i_tail_to:26; + u64 i_rsvd_1:6; + u64 i_rrsp_ps:23; + u64 i_rrsp_to:5; + u64 i_rsvd:4; } ii_ixtt_fld_s; } ii_ixtt_u_t; @@ -1316,37 +1316,37 @@ typedef union ii_ixtt_u { ************************************************************************/ typedef union ii_ieclr_u { - uint64_t ii_ieclr_regval; - struct { - uint64_t i_e_prb_0:1; - uint64_t i_rsvd:7; - uint64_t i_e_prb_8:1; - uint64_t i_e_prb_9:1; - uint64_t i_e_prb_a:1; - uint64_t i_e_prb_b:1; - uint64_t i_e_prb_c:1; - uint64_t i_e_prb_d:1; - uint64_t i_e_prb_e:1; - uint64_t i_e_prb_f:1; - uint64_t i_e_crazy:1; - uint64_t i_e_bte_0:1; - uint64_t i_e_bte_1:1; - uint64_t i_reserved_1:10; - uint64_t i_spur_rd_hdr:1; - uint64_t i_cam_intr_to:1; - uint64_t i_cam_overflow:1; - uint64_t i_cam_read_miss:1; - uint64_t i_ioq_rep_underflow:1; - uint64_t i_ioq_req_underflow:1; - uint64_t i_ioq_rep_overflow:1; - uint64_t i_ioq_req_overflow:1; - uint64_t i_iiq_rep_overflow:1; - uint64_t i_iiq_req_overflow:1; - uint64_t i_ii_xn_rep_cred_overflow:1; - uint64_t i_ii_xn_req_cred_overflow:1; - uint64_t i_ii_xn_invalid_cmd:1; - uint64_t i_xn_ii_invalid_cmd:1; - uint64_t i_reserved_2:21; + u64 ii_ieclr_regval; + struct { + u64 i_e_prb_0:1; + u64 i_rsvd:7; + u64 i_e_prb_8:1; + u64 i_e_prb_9:1; + u64 i_e_prb_a:1; + u64 i_e_prb_b:1; + u64 i_e_prb_c:1; + u64 i_e_prb_d:1; + u64 i_e_prb_e:1; + u64 i_e_prb_f:1; + u64 i_e_crazy:1; + u64 i_e_bte_0:1; + u64 i_e_bte_1:1; + u64 i_reserved_1:10; + u64 i_spur_rd_hdr:1; + u64 i_cam_intr_to:1; + u64 i_cam_overflow:1; + u64 i_cam_read_miss:1; + u64 i_ioq_rep_underflow:1; + u64 i_ioq_req_underflow:1; + u64 i_ioq_rep_overflow:1; + u64 i_ioq_req_overflow:1; + u64 i_iiq_rep_overflow:1; + u64 i_iiq_req_overflow:1; + u64 i_ii_xn_rep_cred_overflow:1; + u64 i_ii_xn_req_cred_overflow:1; + u64 i_ii_xn_invalid_cmd:1; + u64 i_xn_ii_invalid_cmd:1; + u64 i_reserved_2:21; } ii_ieclr_fld_s; } ii_ieclr_u_t; @@ -1360,12 +1360,12 @@ typedef union ii_ieclr_u { ************************************************************************/ typedef union ii_ibcr_u { - uint64_t ii_ibcr_regval; + u64 ii_ibcr_regval; struct { - uint64_t i_count:4; - uint64_t i_rsvd_1:4; - uint64_t i_soft_reset:1; - uint64_t i_rsvd:55; + u64 i_count:4; + u64 i_rsvd_1:4; + u64 i_soft_reset:1; + u64 i_rsvd:55; } ii_ibcr_fld_s; } ii_ibcr_u_t; @@ -1399,22 +1399,22 @@ typedef union ii_ibcr_u { ************************************************************************/ typedef union ii_ixsm_u { - uint64_t ii_ixsm_regval; - struct { - uint64_t i_byte_en:32; - uint64_t i_reserved:1; - uint64_t i_tag:3; - uint64_t i_alt_pactyp:4; - uint64_t i_bo:1; - uint64_t i_error:1; - uint64_t i_vbpm:1; - uint64_t i_gbr:1; - uint64_t i_ds:2; - uint64_t i_ct:1; - uint64_t i_tnum:5; - uint64_t i_pactyp:4; - uint64_t i_sidn:4; - uint64_t i_didn:4; + u64 ii_ixsm_regval; + struct { + u64 i_byte_en:32; + u64 i_reserved:1; + u64 i_tag:3; + u64 i_alt_pactyp:4; + u64 i_bo:1; + u64 i_error:1; + u64 i_vbpm:1; + u64 i_gbr:1; + u64 i_ds:2; + u64 i_ct:1; + u64 i_tnum:5; + u64 i_pactyp:4; + u64 i_sidn:4; + u64 i_didn:4; } ii_ixsm_fld_s; } ii_ixsm_u_t; @@ -1426,11 +1426,11 @@ typedef union ii_ixsm_u { ************************************************************************/ typedef union ii_ixss_u { - uint64_t ii_ixss_regval; + u64 ii_ixss_regval; struct { - uint64_t i_sideband:8; - uint64_t i_rsvd:55; - uint64_t i_valid:1; + u64 i_sideband:8; + u64 i_rsvd:55; + u64 i_valid:1; } ii_ixss_fld_s; } ii_ixss_u_t; @@ -1447,17 +1447,17 @@ typedef union ii_ixss_u { ************************************************************************/ typedef union ii_ilct_u { - uint64_t ii_ilct_regval; - struct { - uint64_t i_test_seed:20; - uint64_t i_test_mask:8; - uint64_t i_test_data:20; - uint64_t i_test_valid:1; - uint64_t i_test_cberr:1; - uint64_t i_test_flit:3; - uint64_t i_test_clear:1; - uint64_t i_test_err_capture:1; - uint64_t i_rsvd:9; + u64 ii_ilct_regval; + struct { + u64 i_test_seed:20; + u64 i_test_mask:8; + u64 i_test_data:20; + u64 i_test_valid:1; + u64 i_test_cberr:1; + u64 i_test_flit:3; + u64 i_test_clear:1; + u64 i_test_err_capture:1; + u64 i_rsvd:9; } ii_ilct_fld_s; } ii_ilct_u_t; @@ -1482,20 +1482,20 @@ typedef union ii_ilct_u { ************************************************************************/ typedef union ii_iieph1_u { - uint64_t ii_iieph1_regval; - struct { - uint64_t i_command:7; - uint64_t i_rsvd_5:1; - uint64_t i_suppl:14; - uint64_t i_rsvd_4:1; - uint64_t i_source:14; - uint64_t i_rsvd_3:1; - uint64_t i_err_type:4; - uint64_t i_rsvd_2:4; - uint64_t i_overrun:1; - uint64_t i_rsvd_1:3; - uint64_t i_valid:1; - uint64_t i_rsvd:13; + u64 ii_iieph1_regval; + struct { + u64 i_command:7; + u64 i_rsvd_5:1; + u64 i_suppl:14; + u64 i_rsvd_4:1; + u64 i_source:14; + u64 i_rsvd_3:1; + u64 i_err_type:4; + u64 i_rsvd_2:4; + u64 i_overrun:1; + u64 i_rsvd_1:3; + u64 i_valid:1; + u64 i_rsvd:13; } ii_iieph1_fld_s; } ii_iieph1_u_t; @@ -1511,13 +1511,13 @@ typedef union ii_iieph1_u { ************************************************************************/ typedef union ii_iieph2_u { - uint64_t ii_iieph2_regval; + u64 ii_iieph2_regval; struct { - uint64_t i_rsvd_0:3; - uint64_t i_address:47; - uint64_t i_rsvd_1:10; - uint64_t i_tail:1; - uint64_t i_rsvd:3; + u64 i_rsvd_0:3; + u64 i_address:47; + u64 i_rsvd_1:10; + u64 i_tail:1; + u64 i_rsvd:3; } ii_iieph2_fld_s; } ii_iieph2_u_t; @@ -1532,9 +1532,9 @@ typedef union ii_iieph2_u { ************************************************************************/ typedef union ii_islapr_u { - uint64_t ii_islapr_regval; + u64 ii_islapr_regval; struct { - uint64_t i_region:64; + u64 i_region:64; } ii_islapr_fld_s; } ii_islapr_u_t; @@ -1547,10 +1547,10 @@ typedef union ii_islapr_u { ************************************************************************/ typedef union ii_islapo_u { - uint64_t ii_islapo_regval; + u64 ii_islapo_regval; struct { - uint64_t i_io_sbx_ovrride:56; - uint64_t i_rsvd:8; + u64 i_io_sbx_ovrride:56; + u64 i_rsvd:8; } ii_islapo_fld_s; } ii_islapo_u_t; @@ -1563,14 +1563,14 @@ typedef union ii_islapo_u { ************************************************************************/ typedef union ii_iwi_u { - uint64_t ii_iwi_regval; - struct { - uint64_t i_prescale:24; - uint64_t i_rsvd:8; - uint64_t i_timeout:8; - uint64_t i_rsvd1:8; - uint64_t i_intrpt_retry_period:8; - uint64_t i_rsvd2:8; + u64 ii_iwi_regval; + struct { + u64 i_prescale:24; + u64 i_rsvd:8; + u64 i_timeout:8; + u64 i_rsvd1:8; + u64 i_intrpt_retry_period:8; + u64 i_rsvd2:8; } ii_iwi_fld_s; } ii_iwi_u_t; @@ -1582,26 +1582,26 @@ typedef union ii_iwi_u { ************************************************************************/ typedef union ii_iwel_u { - uint64_t ii_iwel_regval; - struct { - uint64_t i_intr_timed_out:1; - uint64_t i_rsvd:7; - uint64_t i_cam_overflow:1; - uint64_t i_cam_read_miss:1; - uint64_t i_rsvd1:2; - uint64_t i_ioq_rep_underflow:1; - uint64_t i_ioq_req_underflow:1; - uint64_t i_ioq_rep_overflow:1; - uint64_t i_ioq_req_overflow:1; - uint64_t i_iiq_rep_overflow:1; - uint64_t i_iiq_req_overflow:1; - uint64_t i_rsvd2:6; - uint64_t i_ii_xn_rep_cred_over_under:1; - uint64_t i_ii_xn_req_cred_over_under:1; - uint64_t i_rsvd3:6; - uint64_t i_ii_xn_invalid_cmd:1; - uint64_t i_xn_ii_invalid_cmd:1; - uint64_t i_rsvd4:30; + u64 ii_iwel_regval; + struct { + u64 i_intr_timed_out:1; + u64 i_rsvd:7; + u64 i_cam_overflow:1; + u64 i_cam_read_miss:1; + u64 i_rsvd1:2; + u64 i_ioq_rep_underflow:1; + u64 i_ioq_req_underflow:1; + u64 i_ioq_rep_overflow:1; + u64 i_ioq_req_overflow:1; + u64 i_iiq_rep_overflow:1; + u64 i_iiq_req_overflow:1; + u64 i_rsvd2:6; + u64 i_ii_xn_rep_cred_over_under:1; + u64 i_ii_xn_req_cred_over_under:1; + u64 i_rsvd3:6; + u64 i_ii_xn_invalid_cmd:1; + u64 i_xn_ii_invalid_cmd:1; + u64 i_rsvd4:30; } ii_iwel_fld_s; } ii_iwel_u_t; @@ -1612,22 +1612,22 @@ typedef union ii_iwel_u { ************************************************************************/ typedef union ii_iwc_u { - uint64_t ii_iwc_regval; - struct { - uint64_t i_dma_byte_swap:1; - uint64_t i_rsvd:3; - uint64_t i_cam_read_lines_reset:1; - uint64_t i_rsvd1:3; - uint64_t i_ii_xn_cred_over_under_log:1; - uint64_t i_rsvd2:19; - uint64_t i_xn_rep_iq_depth:5; - uint64_t i_rsvd3:3; - uint64_t i_xn_req_iq_depth:5; - uint64_t i_rsvd4:3; - uint64_t i_iiq_depth:6; - uint64_t i_rsvd5:12; - uint64_t i_force_rep_cred:1; - uint64_t i_force_req_cred:1; + u64 ii_iwc_regval; + struct { + u64 i_dma_byte_swap:1; + u64 i_rsvd:3; + u64 i_cam_read_lines_reset:1; + u64 i_rsvd1:3; + u64 i_ii_xn_cred_over_under_log:1; + u64 i_rsvd2:19; + u64 i_xn_rep_iq_depth:5; + u64 i_rsvd3:3; + u64 i_xn_req_iq_depth:5; + u64 i_rsvd4:3; + u64 i_iiq_depth:6; + u64 i_rsvd5:12; + u64 i_force_rep_cred:1; + u64 i_force_req_cred:1; } ii_iwc_fld_s; } ii_iwc_u_t; @@ -1638,12 +1638,12 @@ typedef union ii_iwc_u { ************************************************************************/ typedef union ii_iws_u { - uint64_t ii_iws_regval; + u64 ii_iws_regval; struct { - uint64_t i_xn_rep_iq_credits:5; - uint64_t i_rsvd:3; - uint64_t i_xn_req_iq_credits:5; - uint64_t i_rsvd1:51; + u64 i_xn_rep_iq_credits:5; + u64 i_rsvd:3; + u64 i_xn_req_iq_credits:5; + u64 i_rsvd1:51; } ii_iws_fld_s; } ii_iws_u_t; @@ -1654,26 +1654,26 @@ typedef union ii_iws_u { ************************************************************************/ typedef union ii_iweim_u { - uint64_t ii_iweim_regval; - struct { - uint64_t i_intr_timed_out:1; - uint64_t i_rsvd:7; - uint64_t i_cam_overflow:1; - uint64_t i_cam_read_miss:1; - uint64_t i_rsvd1:2; - uint64_t i_ioq_rep_underflow:1; - uint64_t i_ioq_req_underflow:1; - uint64_t i_ioq_rep_overflow:1; - uint64_t i_ioq_req_overflow:1; - uint64_t i_iiq_rep_overflow:1; - uint64_t i_iiq_req_overflow:1; - uint64_t i_rsvd2:6; - uint64_t i_ii_xn_rep_cred_overflow:1; - uint64_t i_ii_xn_req_cred_overflow:1; - uint64_t i_rsvd3:6; - uint64_t i_ii_xn_invalid_cmd:1; - uint64_t i_xn_ii_invalid_cmd:1; - uint64_t i_rsvd4:30; + u64 ii_iweim_regval; + struct { + u64 i_intr_timed_out:1; + u64 i_rsvd:7; + u64 i_cam_overflow:1; + u64 i_cam_read_miss:1; + u64 i_rsvd1:2; + u64 i_ioq_rep_underflow:1; + u64 i_ioq_req_underflow:1; + u64 i_ioq_rep_overflow:1; + u64 i_ioq_req_overflow:1; + u64 i_iiq_rep_overflow:1; + u64 i_iiq_req_overflow:1; + u64 i_rsvd2:6; + u64 i_ii_xn_rep_cred_overflow:1; + u64 i_ii_xn_req_cred_overflow:1; + u64 i_rsvd3:6; + u64 i_ii_xn_invalid_cmd:1; + u64 i_xn_ii_invalid_cmd:1; + u64 i_rsvd4:30; } ii_iweim_fld_s; } ii_iweim_u_t; @@ -1688,13 +1688,13 @@ typedef union ii_iweim_u { ************************************************************************/ typedef union ii_ipca_u { - uint64_t ii_ipca_regval; + u64 ii_ipca_regval; struct { - uint64_t i_wid:4; - uint64_t i_adjust:1; - uint64_t i_rsvd_1:3; - uint64_t i_field:2; - uint64_t i_rsvd:54; + u64 i_wid:4; + u64 i_adjust:1; + u64 i_rsvd_1:3; + u64 i_field:2; + u64 i_rsvd:54; } ii_ipca_fld_s; } ii_ipca_u_t; @@ -1709,12 +1709,12 @@ typedef union ii_ipca_u { ************************************************************************/ typedef union ii_iprte0a_u { - uint64_t ii_iprte0a_regval; + u64 ii_iprte0a_regval; struct { - uint64_t i_rsvd_1:54; - uint64_t i_widget:4; - uint64_t i_to_cnt:5; - uint64_t i_vld:1; + u64 i_rsvd_1:54; + u64 i_widget:4; + u64 i_to_cnt:5; + u64 i_vld:1; } ii_iprte0a_fld_s; } ii_iprte0a_u_t; @@ -1729,12 +1729,12 @@ typedef union ii_iprte0a_u { ************************************************************************/ typedef union ii_iprte1a_u { - uint64_t ii_iprte1a_regval; + u64 ii_iprte1a_regval; struct { - uint64_t i_rsvd_1:54; - uint64_t i_widget:4; - uint64_t i_to_cnt:5; - uint64_t i_vld:1; + u64 i_rsvd_1:54; + u64 i_widget:4; + u64 i_to_cnt:5; + u64 i_vld:1; } ii_iprte1a_fld_s; } ii_iprte1a_u_t; @@ -1749,12 +1749,12 @@ typedef union ii_iprte1a_u { ************************************************************************/ typedef union ii_iprte2a_u { - uint64_t ii_iprte2a_regval; + u64 ii_iprte2a_regval; struct { - uint64_t i_rsvd_1:54; - uint64_t i_widget:4; - uint64_t i_to_cnt:5; - uint64_t i_vld:1; + u64 i_rsvd_1:54; + u64 i_widget:4; + u64 i_to_cnt:5; + u64 i_vld:1; } ii_iprte2a_fld_s; } ii_iprte2a_u_t; @@ -1769,12 +1769,12 @@ typedef union ii_iprte2a_u { ************************************************************************/ typedef union ii_iprte3a_u { - uint64_t ii_iprte3a_regval; + u64 ii_iprte3a_regval; struct { - uint64_t i_rsvd_1:54; - uint64_t i_widget:4; - uint64_t i_to_cnt:5; - uint64_t i_vld:1; + u64 i_rsvd_1:54; + u64 i_widget:4; + u64 i_to_cnt:5; + u64 i_vld:1; } ii_iprte3a_fld_s; } ii_iprte3a_u_t; @@ -1789,12 +1789,12 @@ typedef union ii_iprte3a_u { ************************************************************************/ typedef union ii_iprte4a_u { - uint64_t ii_iprte4a_regval; + u64 ii_iprte4a_regval; struct { - uint64_t i_rsvd_1:54; - uint64_t i_widget:4; - uint64_t i_to_cnt:5; - uint64_t i_vld:1; + u64 i_rsvd_1:54; + u64 i_widget:4; + u64 i_to_cnt:5; + u64 i_vld:1; } ii_iprte4a_fld_s; } ii_iprte4a_u_t; @@ -1809,12 +1809,12 @@ typedef union ii_iprte4a_u { ************************************************************************/ typedef union ii_iprte5a_u { - uint64_t ii_iprte5a_regval; + u64 ii_iprte5a_regval; struct { - uint64_t i_rsvd_1:54; - uint64_t i_widget:4; - uint64_t i_to_cnt:5; - uint64_t i_vld:1; + u64 i_rsvd_1:54; + u64 i_widget:4; + u64 i_to_cnt:5; + u64 i_vld:1; } ii_iprte5a_fld_s; } ii_iprte5a_u_t; @@ -1829,12 +1829,12 @@ typedef union ii_iprte5a_u { ************************************************************************/ typedef union ii_iprte6a_u { - uint64_t ii_iprte6a_regval; + u64 ii_iprte6a_regval; struct { - uint64_t i_rsvd_1:54; - uint64_t i_widget:4; - uint64_t i_to_cnt:5; - uint64_t i_vld:1; + u64 i_rsvd_1:54; + u64 i_widget:4; + u64 i_to_cnt:5; + u64 i_vld:1; } ii_iprte6a_fld_s; } ii_iprte6a_u_t; @@ -1849,12 +1849,12 @@ typedef union ii_iprte6a_u { ************************************************************************/ typedef union ii_iprte7a_u { - uint64_t ii_iprte7a_regval; + u64 ii_iprte7a_regval; struct { - uint64_t i_rsvd_1:54; - uint64_t i_widget:4; - uint64_t i_to_cnt:5; - uint64_t i_vld:1; + u64 i_rsvd_1:54; + u64 i_widget:4; + u64 i_to_cnt:5; + u64 i_vld:1; } ii_iprtea7_fld_s; } ii_iprte7a_u_t; @@ -1869,12 +1869,12 @@ typedef union ii_iprte7a_u { ************************************************************************/ typedef union ii_iprte0b_u { - uint64_t ii_iprte0b_regval; + u64 ii_iprte0b_regval; struct { - uint64_t i_rsvd_1:3; - uint64_t i_address:47; - uint64_t i_init:3; - uint64_t i_source:11; + u64 i_rsvd_1:3; + u64 i_address:47; + u64 i_init:3; + u64 i_source:11; } ii_iprte0b_fld_s; } ii_iprte0b_u_t; @@ -1889,12 +1889,12 @@ typedef union ii_iprte0b_u { ************************************************************************/ typedef union ii_iprte1b_u { - uint64_t ii_iprte1b_regval; + u64 ii_iprte1b_regval; struct { - uint64_t i_rsvd_1:3; - uint64_t i_address:47; - uint64_t i_init:3; - uint64_t i_source:11; + u64 i_rsvd_1:3; + u64 i_address:47; + u64 i_init:3; + u64 i_source:11; } ii_iprte1b_fld_s; } ii_iprte1b_u_t; @@ -1909,12 +1909,12 @@ typedef union ii_iprte1b_u { ************************************************************************/ typedef union ii_iprte2b_u { - uint64_t ii_iprte2b_regval; + u64 ii_iprte2b_regval; struct { - uint64_t i_rsvd_1:3; - uint64_t i_address:47; - uint64_t i_init:3; - uint64_t i_source:11; + u64 i_rsvd_1:3; + u64 i_address:47; + u64 i_init:3; + u64 i_source:11; } ii_iprte2b_fld_s; } ii_iprte2b_u_t; @@ -1929,12 +1929,12 @@ typedef union ii_iprte2b_u { ************************************************************************/ typedef union ii_iprte3b_u { - uint64_t ii_iprte3b_regval; + u64 ii_iprte3b_regval; struct { - uint64_t i_rsvd_1:3; - uint64_t i_address:47; - uint64_t i_init:3; - uint64_t i_source:11; + u64 i_rsvd_1:3; + u64 i_address:47; + u64 i_init:3; + u64 i_source:11; } ii_iprte3b_fld_s; } ii_iprte3b_u_t; @@ -1949,12 +1949,12 @@ typedef union ii_iprte3b_u { ************************************************************************/ typedef union ii_iprte4b_u { - uint64_t ii_iprte4b_regval; + u64 ii_iprte4b_regval; struct { - uint64_t i_rsvd_1:3; - uint64_t i_address:47; - uint64_t i_init:3; - uint64_t i_source:11; + u64 i_rsvd_1:3; + u64 i_address:47; + u64 i_init:3; + u64 i_source:11; } ii_iprte4b_fld_s; } ii_iprte4b_u_t; @@ -1969,12 +1969,12 @@ typedef union ii_iprte4b_u { ************************************************************************/ typedef union ii_iprte5b_u { - uint64_t ii_iprte5b_regval; + u64 ii_iprte5b_regval; struct { - uint64_t i_rsvd_1:3; - uint64_t i_address:47; - uint64_t i_init:3; - uint64_t i_source:11; + u64 i_rsvd_1:3; + u64 i_address:47; + u64 i_init:3; + u64 i_source:11; } ii_iprte5b_fld_s; } ii_iprte5b_u_t; @@ -1989,12 +1989,12 @@ typedef union ii_iprte5b_u { ************************************************************************/ typedef union ii_iprte6b_u { - uint64_t ii_iprte6b_regval; + u64 ii_iprte6b_regval; struct { - uint64_t i_rsvd_1:3; - uint64_t i_address:47; - uint64_t i_init:3; - uint64_t i_source:11; + u64 i_rsvd_1:3; + u64 i_address:47; + u64 i_init:3; + u64 i_source:11; } ii_iprte6b_fld_s; } ii_iprte6b_u_t; @@ -2010,12 +2010,12 @@ typedef union ii_iprte6b_u { ************************************************************************/ typedef union ii_iprte7b_u { - uint64_t ii_iprte7b_regval; + u64 ii_iprte7b_regval; struct { - uint64_t i_rsvd_1:3; - uint64_t i_address:47; - uint64_t i_init:3; - uint64_t i_source:11; + u64 i_rsvd_1:3; + u64 i_address:47; + u64 i_init:3; + u64 i_source:11; } ii_iprte7b_fld_s; } ii_iprte7b_u_t; @@ -2038,13 +2038,13 @@ typedef union ii_iprte7b_u { ************************************************************************/ typedef union ii_ipdr_u { - uint64_t ii_ipdr_regval; + u64 ii_ipdr_regval; struct { - uint64_t i_te:3; - uint64_t i_rsvd_1:1; - uint64_t i_pnd:1; - uint64_t i_init_rpcnt:1; - uint64_t i_rsvd:58; + u64 i_te:3; + u64 i_rsvd_1:1; + u64 i_pnd:1; + u64 i_init_rpcnt:1; + u64 i_rsvd:58; } ii_ipdr_fld_s; } ii_ipdr_u_t; @@ -2066,11 +2066,11 @@ typedef union ii_ipdr_u { ************************************************************************/ typedef union ii_icdr_u { - uint64_t ii_icdr_regval; + u64 ii_icdr_regval; struct { - uint64_t i_crb_num:4; - uint64_t i_pnd:1; - uint64_t i_rsvd:59; + u64 i_crb_num:4; + u64 i_pnd:1; + u64 i_rsvd:59; } ii_icdr_fld_s; } ii_icdr_u_t; @@ -2092,13 +2092,13 @@ typedef union ii_icdr_u { ************************************************************************/ typedef union ii_ifdr_u { - uint64_t ii_ifdr_regval; + u64 ii_ifdr_regval; struct { - uint64_t i_ioq_max_rq:7; - uint64_t i_set_ioq_rq:1; - uint64_t i_ioq_max_rp:7; - uint64_t i_set_ioq_rp:1; - uint64_t i_rsvd:48; + u64 i_ioq_max_rq:7; + u64 i_set_ioq_rq:1; + u64 i_ioq_max_rp:7; + u64 i_set_ioq_rp:1; + u64 i_rsvd:48; } ii_ifdr_fld_s; } ii_ifdr_u_t; @@ -2114,12 +2114,12 @@ typedef union ii_ifdr_u { ************************************************************************/ typedef union ii_iiap_u { - uint64_t ii_iiap_regval; + u64 ii_iiap_regval; struct { - uint64_t i_rq_mls:6; - uint64_t i_rsvd_1:2; - uint64_t i_rp_mls:6; - uint64_t i_rsvd:50; + u64 i_rq_mls:6; + u64 i_rsvd_1:2; + u64 i_rp_mls:6; + u64 i_rsvd:50; } ii_iiap_fld_s; } ii_iiap_u_t; @@ -2133,22 +2133,22 @@ typedef union ii_iiap_u { ************************************************************************/ typedef union ii_icmr_u { - uint64_t ii_icmr_regval; - struct { - uint64_t i_sp_msg:1; - uint64_t i_rd_hdr:1; - uint64_t i_rsvd_4:2; - uint64_t i_c_cnt:4; - uint64_t i_rsvd_3:4; - uint64_t i_clr_rqpd:1; - uint64_t i_clr_rppd:1; - uint64_t i_rsvd_2:2; - uint64_t i_fc_cnt:4; - uint64_t i_crb_vld:15; - uint64_t i_crb_mark:15; - uint64_t i_rsvd_1:2; - uint64_t i_precise:1; - uint64_t i_rsvd:11; + u64 ii_icmr_regval; + struct { + u64 i_sp_msg:1; + u64 i_rd_hdr:1; + u64 i_rsvd_4:2; + u64 i_c_cnt:4; + u64 i_rsvd_3:4; + u64 i_clr_rqpd:1; + u64 i_clr_rppd:1; + u64 i_rsvd_2:2; + u64 i_fc_cnt:4; + u64 i_crb_vld:15; + u64 i_crb_mark:15; + u64 i_rsvd_1:2; + u64 i_precise:1; + u64 i_rsvd:11; } ii_icmr_fld_s; } ii_icmr_u_t; @@ -2161,13 +2161,13 @@ typedef union ii_icmr_u { ************************************************************************/ typedef union ii_iccr_u { - uint64_t ii_iccr_regval; + u64 ii_iccr_regval; struct { - uint64_t i_crb_num:4; - uint64_t i_rsvd_1:4; - uint64_t i_cmd:8; - uint64_t i_pending:1; - uint64_t i_rsvd:47; + u64 i_crb_num:4; + u64 i_rsvd_1:4; + u64 i_cmd:8; + u64 i_pending:1; + u64 i_rsvd:47; } ii_iccr_fld_s; } ii_iccr_u_t; @@ -2178,10 +2178,10 @@ typedef union ii_iccr_u { ************************************************************************/ typedef union ii_icto_u { - uint64_t ii_icto_regval; + u64 ii_icto_regval; struct { - uint64_t i_timeout:8; - uint64_t i_rsvd:56; + u64 i_timeout:8; + u64 i_rsvd:56; } ii_icto_fld_s; } ii_icto_u_t; @@ -2197,10 +2197,10 @@ typedef union ii_icto_u { ************************************************************************/ typedef union ii_ictp_u { - uint64_t ii_ictp_regval; + u64 ii_ictp_regval; struct { - uint64_t i_prescale:24; - uint64_t i_rsvd:40; + u64 i_prescale:24; + u64 i_rsvd:40; } ii_ictp_fld_s; } ii_ictp_u_t; @@ -2228,14 +2228,14 @@ typedef union ii_ictp_u { ************************************************************************/ typedef union ii_icrb0_a_u { - uint64_t ii_icrb0_a_regval; - struct { - uint64_t ia_iow:1; - uint64_t ia_vld:1; - uint64_t ia_addr:47; - uint64_t ia_tnum:5; - uint64_t ia_sidn:4; - uint64_t ia_rsvd:6; + u64 ii_icrb0_a_regval; + struct { + u64 ia_iow:1; + u64 ia_vld:1; + u64 ia_addr:47; + u64 ia_tnum:5; + u64 ia_sidn:4; + u64 ia_rsvd:6; } ii_icrb0_a_fld_s; } ii_icrb0_a_u_t; @@ -2249,30 +2249,30 @@ typedef union ii_icrb0_a_u { ************************************************************************/ typedef union ii_icrb0_b_u { - uint64_t ii_icrb0_b_regval; - struct { - uint64_t ib_xt_err:1; - uint64_t ib_mark:1; - uint64_t ib_ln_uce:1; - uint64_t ib_errcode:3; - uint64_t ib_error:1; - uint64_t ib_stall__bte_1:1; - uint64_t ib_stall__bte_0:1; - uint64_t ib_stall__intr:1; - uint64_t ib_stall_ib:1; - uint64_t ib_intvn:1; - uint64_t ib_wb:1; - uint64_t ib_hold:1; - uint64_t ib_ack:1; - uint64_t ib_resp:1; - uint64_t ib_ack_cnt:11; - uint64_t ib_rsvd:7; - uint64_t ib_exc:5; - uint64_t ib_init:3; - uint64_t ib_imsg:8; - uint64_t ib_imsgtype:2; - uint64_t ib_use_old:1; - uint64_t ib_rsvd_1:11; + u64 ii_icrb0_b_regval; + struct { + u64 ib_xt_err:1; + u64 ib_mark:1; + u64 ib_ln_uce:1; + u64 ib_errcode:3; + u64 ib_error:1; + u64 ib_stall__bte_1:1; + u64 ib_stall__bte_0:1; + u64 ib_stall__intr:1; + u64 ib_stall_ib:1; + u64 ib_intvn:1; + u64 ib_wb:1; + u64 ib_hold:1; + u64 ib_ack:1; + u64 ib_resp:1; + u64 ib_ack_cnt:11; + u64 ib_rsvd:7; + u64 ib_exc:5; + u64 ib_init:3; + u64 ib_imsg:8; + u64 ib_imsgtype:2; + u64 ib_use_old:1; + u64 ib_rsvd_1:11; } ii_icrb0_b_fld_s; } ii_icrb0_b_u_t; @@ -2286,17 +2286,17 @@ typedef union ii_icrb0_b_u { ************************************************************************/ typedef union ii_icrb0_c_u { - uint64_t ii_icrb0_c_regval; - struct { - uint64_t ic_source:15; - uint64_t ic_size:2; - uint64_t ic_ct:1; - uint64_t ic_bte_num:1; - uint64_t ic_gbr:1; - uint64_t ic_resprqd:1; - uint64_t ic_bo:1; - uint64_t ic_suppl:15; - uint64_t ic_rsvd:27; + u64 ii_icrb0_c_regval; + struct { + u64 ic_source:15; + u64 ic_size:2; + u64 ic_ct:1; + u64 ic_bte_num:1; + u64 ic_gbr:1; + u64 ic_resprqd:1; + u64 ic_bo:1; + u64 ic_suppl:15; + u64 ic_rsvd:27; } ii_icrb0_c_fld_s; } ii_icrb0_c_u_t; @@ -2310,14 +2310,14 @@ typedef union ii_icrb0_c_u { ************************************************************************/ typedef union ii_icrb0_d_u { - uint64_t ii_icrb0_d_regval; - struct { - uint64_t id_pa_be:43; - uint64_t id_bte_op:1; - uint64_t id_pr_psc:4; - uint64_t id_pr_cnt:4; - uint64_t id_sleep:1; - uint64_t id_rsvd:11; + u64 ii_icrb0_d_regval; + struct { + u64 id_pa_be:43; + u64 id_bte_op:1; + u64 id_pr_psc:4; + u64 id_pr_cnt:4; + u64 id_sleep:1; + u64 id_rsvd:11; } ii_icrb0_d_fld_s; } ii_icrb0_d_u_t; @@ -2331,14 +2331,14 @@ typedef union ii_icrb0_d_u { ************************************************************************/ typedef union ii_icrb0_e_u { - uint64_t ii_icrb0_e_regval; - struct { - uint64_t ie_timeout:8; - uint64_t ie_context:15; - uint64_t ie_rsvd:1; - uint64_t ie_tvld:1; - uint64_t ie_cvld:1; - uint64_t ie_rsvd_0:38; + u64 ii_icrb0_e_regval; + struct { + u64 ie_timeout:8; + u64 ie_context:15; + u64 ie_rsvd:1; + u64 ie_tvld:1; + u64 ie_cvld:1; + u64 ie_rsvd_0:38; } ii_icrb0_e_fld_s; } ii_icrb0_e_u_t; @@ -2351,12 +2351,12 @@ typedef union ii_icrb0_e_u { ************************************************************************/ typedef union ii_icsml_u { - uint64_t ii_icsml_regval; + u64 ii_icsml_regval; struct { - uint64_t i_tt_addr:47; - uint64_t i_newsuppl_ex:14; - uint64_t i_reserved:2; - uint64_t i_overflow:1; + u64 i_tt_addr:47; + u64 i_newsuppl_ex:14; + u64 i_reserved:2; + u64 i_overflow:1; } ii_icsml_fld_s; } ii_icsml_u_t; @@ -2369,10 +2369,10 @@ typedef union ii_icsml_u { ************************************************************************/ typedef union ii_icsmm_u { - uint64_t ii_icsmm_regval; + u64 ii_icsmm_regval; struct { - uint64_t i_tt_ack_cnt:11; - uint64_t i_reserved:53; + u64 i_tt_ack_cnt:11; + u64 i_reserved:53; } ii_icsmm_fld_s; } ii_icsmm_u_t; @@ -2385,48 +2385,48 @@ typedef union ii_icsmm_u { ************************************************************************/ typedef union ii_icsmh_u { - uint64_t ii_icsmh_regval; - struct { - uint64_t i_tt_vld:1; - uint64_t i_xerr:1; - uint64_t i_ft_cwact_o:1; - uint64_t i_ft_wact_o:1; - uint64_t i_ft_active_o:1; - uint64_t i_sync:1; - uint64_t i_mnusg:1; - uint64_t i_mnusz:1; - uint64_t i_plusz:1; - uint64_t i_plusg:1; - uint64_t i_tt_exc:5; - uint64_t i_tt_wb:1; - uint64_t i_tt_hold:1; - uint64_t i_tt_ack:1; - uint64_t i_tt_resp:1; - uint64_t i_tt_intvn:1; - uint64_t i_g_stall_bte1:1; - uint64_t i_g_stall_bte0:1; - uint64_t i_g_stall_il:1; - uint64_t i_g_stall_ib:1; - uint64_t i_tt_imsg:8; - uint64_t i_tt_imsgtype:2; - uint64_t i_tt_use_old:1; - uint64_t i_tt_respreqd:1; - uint64_t i_tt_bte_num:1; - uint64_t i_cbn:1; - uint64_t i_match:1; - uint64_t i_rpcnt_lt_34:1; - uint64_t i_rpcnt_ge_34:1; - uint64_t i_rpcnt_lt_18:1; - uint64_t i_rpcnt_ge_18:1; - uint64_t i_rpcnt_lt_2:1; - uint64_t i_rpcnt_ge_2:1; - uint64_t i_rqcnt_lt_18:1; - uint64_t i_rqcnt_ge_18:1; - uint64_t i_rqcnt_lt_2:1; - uint64_t i_rqcnt_ge_2:1; - uint64_t i_tt_device:7; - uint64_t i_tt_init:3; - uint64_t i_reserved:5; + u64 ii_icsmh_regval; + struct { + u64 i_tt_vld:1; + u64 i_xerr:1; + u64 i_ft_cwact_o:1; + u64 i_ft_wact_o:1; + u64 i_ft_active_o:1; + u64 i_sync:1; + u64 i_mnusg:1; + u64 i_mnusz:1; + u64 i_plusz:1; + u64 i_plusg:1; + u64 i_tt_exc:5; + u64 i_tt_wb:1; + u64 i_tt_hold:1; + u64 i_tt_ack:1; + u64 i_tt_resp:1; + u64 i_tt_intvn:1; + u64 i_g_stall_bte1:1; + u64 i_g_stall_bte0:1; + u64 i_g_stall_il:1; + u64 i_g_stall_ib:1; + u64 i_tt_imsg:8; + u64 i_tt_imsgtype:2; + u64 i_tt_use_old:1; + u64 i_tt_respreqd:1; + u64 i_tt_bte_num:1; + u64 i_cbn:1; + u64 i_match:1; + u64 i_rpcnt_lt_34:1; + u64 i_rpcnt_ge_34:1; + u64 i_rpcnt_lt_18:1; + u64 i_rpcnt_ge_18:1; + u64 i_rpcnt_lt_2:1; + u64 i_rpcnt_ge_2:1; + u64 i_rqcnt_lt_18:1; + u64 i_rqcnt_ge_18:1; + u64 i_rqcnt_lt_2:1; + u64 i_rqcnt_ge_2:1; + u64 i_tt_device:7; + u64 i_tt_init:3; + u64 i_reserved:5; } ii_icsmh_fld_s; } ii_icsmh_u_t; @@ -2439,14 +2439,14 @@ typedef union ii_icsmh_u { ************************************************************************/ typedef union ii_idbss_u { - uint64_t ii_idbss_regval; - struct { - uint64_t i_iioclk_core_submenu:3; - uint64_t i_rsvd:5; - uint64_t i_fsbclk_wrapper_submenu:3; - uint64_t i_rsvd_1:5; - uint64_t i_iioclk_menu:5; - uint64_t i_rsvd_2:43; + u64 ii_idbss_regval; + struct { + u64 i_iioclk_core_submenu:3; + u64 i_rsvd:5; + u64 i_fsbclk_wrapper_submenu:3; + u64 i_rsvd_1:5; + u64 i_iioclk_menu:5; + u64 i_rsvd_2:43; } ii_idbss_fld_s; } ii_idbss_u_t; @@ -2466,13 +2466,13 @@ typedef union ii_idbss_u { ************************************************************************/ typedef union ii_ibls0_u { - uint64_t ii_ibls0_regval; + u64 ii_ibls0_regval; struct { - uint64_t i_length:16; - uint64_t i_error:1; - uint64_t i_rsvd_1:3; - uint64_t i_busy:1; - uint64_t i_rsvd:43; + u64 i_length:16; + u64 i_error:1; + u64 i_rsvd_1:3; + u64 i_busy:1; + u64 i_rsvd:43; } ii_ibls0_fld_s; } ii_ibls0_u_t; @@ -2487,11 +2487,11 @@ typedef union ii_ibls0_u { ************************************************************************/ typedef union ii_ibsa0_u { - uint64_t ii_ibsa0_regval; + u64 ii_ibsa0_regval; struct { - uint64_t i_rsvd_1:7; - uint64_t i_addr:42; - uint64_t i_rsvd:15; + u64 i_rsvd_1:7; + u64 i_addr:42; + u64 i_rsvd:15; } ii_ibsa0_fld_s; } ii_ibsa0_u_t; @@ -2506,11 +2506,11 @@ typedef union ii_ibsa0_u { ************************************************************************/ typedef union ii_ibda0_u { - uint64_t ii_ibda0_regval; + u64 ii_ibda0_regval; struct { - uint64_t i_rsvd_1:7; - uint64_t i_addr:42; - uint64_t i_rsvd:15; + u64 i_rsvd_1:7; + u64 i_addr:42; + u64 i_rsvd:15; } ii_ibda0_fld_s; } ii_ibda0_u_t; @@ -2527,14 +2527,14 @@ typedef union ii_ibda0_u { ************************************************************************/ typedef union ii_ibct0_u { - uint64_t ii_ibct0_regval; - struct { - uint64_t i_zerofill:1; - uint64_t i_rsvd_2:3; - uint64_t i_notify:1; - uint64_t i_rsvd_1:3; - uint64_t i_poison:1; - uint64_t i_rsvd:55; + u64 ii_ibct0_regval; + struct { + u64 i_zerofill:1; + u64 i_rsvd_2:3; + u64 i_notify:1; + u64 i_rsvd_1:3; + u64 i_poison:1; + u64 i_rsvd:55; } ii_ibct0_fld_s; } ii_ibct0_u_t; @@ -2546,11 +2546,11 @@ typedef union ii_ibct0_u { ************************************************************************/ typedef union ii_ibna0_u { - uint64_t ii_ibna0_regval; + u64 ii_ibna0_regval; struct { - uint64_t i_rsvd_1:7; - uint64_t i_addr:42; - uint64_t i_rsvd:15; + u64 i_rsvd_1:7; + u64 i_addr:42; + u64 i_rsvd:15; } ii_ibna0_fld_s; } ii_ibna0_u_t; @@ -2563,13 +2563,13 @@ typedef union ii_ibna0_u { ************************************************************************/ typedef union ii_ibia0_u { - uint64_t ii_ibia0_regval; + u64 ii_ibia0_regval; struct { - uint64_t i_rsvd_2:1; - uint64_t i_node_id:11; - uint64_t i_rsvd_1:4; - uint64_t i_level:7; - uint64_t i_rsvd:41; + u64 i_rsvd_2:1; + u64 i_node_id:11; + u64 i_rsvd_1:4; + u64 i_level:7; + u64 i_rsvd:41; } ii_ibia0_fld_s; } ii_ibia0_u_t; @@ -2589,13 +2589,13 @@ typedef union ii_ibia0_u { ************************************************************************/ typedef union ii_ibls1_u { - uint64_t ii_ibls1_regval; + u64 ii_ibls1_regval; struct { - uint64_t i_length:16; - uint64_t i_error:1; - uint64_t i_rsvd_1:3; - uint64_t i_busy:1; - uint64_t i_rsvd:43; + u64 i_length:16; + u64 i_error:1; + u64 i_rsvd_1:3; + u64 i_busy:1; + u64 i_rsvd:43; } ii_ibls1_fld_s; } ii_ibls1_u_t; @@ -2610,11 +2610,11 @@ typedef union ii_ibls1_u { ************************************************************************/ typedef union ii_ibsa1_u { - uint64_t ii_ibsa1_regval; + u64 ii_ibsa1_regval; struct { - uint64_t i_rsvd_1:7; - uint64_t i_addr:33; - uint64_t i_rsvd:24; + u64 i_rsvd_1:7; + u64 i_addr:33; + u64 i_rsvd:24; } ii_ibsa1_fld_s; } ii_ibsa1_u_t; @@ -2629,11 +2629,11 @@ typedef union ii_ibsa1_u { ************************************************************************/ typedef union ii_ibda1_u { - uint64_t ii_ibda1_regval; + u64 ii_ibda1_regval; struct { - uint64_t i_rsvd_1:7; - uint64_t i_addr:33; - uint64_t i_rsvd:24; + u64 i_rsvd_1:7; + u64 i_addr:33; + u64 i_rsvd:24; } ii_ibda1_fld_s; } ii_ibda1_u_t; @@ -2650,14 +2650,14 @@ typedef union ii_ibda1_u { ************************************************************************/ typedef union ii_ibct1_u { - uint64_t ii_ibct1_regval; - struct { - uint64_t i_zerofill:1; - uint64_t i_rsvd_2:3; - uint64_t i_notify:1; - uint64_t i_rsvd_1:3; - uint64_t i_poison:1; - uint64_t i_rsvd:55; + u64 ii_ibct1_regval; + struct { + u64 i_zerofill:1; + u64 i_rsvd_2:3; + u64 i_notify:1; + u64 i_rsvd_1:3; + u64 i_poison:1; + u64 i_rsvd:55; } ii_ibct1_fld_s; } ii_ibct1_u_t; @@ -2669,11 +2669,11 @@ typedef union ii_ibct1_u { ************************************************************************/ typedef union ii_ibna1_u { - uint64_t ii_ibna1_regval; + u64 ii_ibna1_regval; struct { - uint64_t i_rsvd_1:7; - uint64_t i_addr:33; - uint64_t i_rsvd:24; + u64 i_rsvd_1:7; + u64 i_addr:33; + u64 i_rsvd:24; } ii_ibna1_fld_s; } ii_ibna1_u_t; @@ -2686,13 +2686,13 @@ typedef union ii_ibna1_u { ************************************************************************/ typedef union ii_ibia1_u { - uint64_t ii_ibia1_regval; + u64 ii_ibia1_regval; struct { - uint64_t i_pi_id:1; - uint64_t i_node_id:8; - uint64_t i_rsvd_1:7; - uint64_t i_level:7; - uint64_t i_rsvd:41; + u64 i_pi_id:1; + u64 i_node_id:8; + u64 i_rsvd_1:7; + u64 i_level:7; + u64 i_rsvd:41; } ii_ibia1_fld_s; } ii_ibia1_u_t; @@ -2712,12 +2712,12 @@ typedef union ii_ibia1_u { ************************************************************************/ typedef union ii_ipcr_u { - uint64_t ii_ipcr_regval; + u64 ii_ipcr_regval; struct { - uint64_t i_ippr0_c:4; - uint64_t i_ippr1_c:4; - uint64_t i_icct:8; - uint64_t i_rsvd:48; + u64 i_ippr0_c:4; + u64 i_ippr1_c:4; + u64 i_icct:8; + u64 i_rsvd:48; } ii_ipcr_fld_s; } ii_ipcr_u_t; @@ -2728,10 +2728,10 @@ typedef union ii_ipcr_u { ************************************************************************/ typedef union ii_ippr_u { - uint64_t ii_ippr_regval; + u64 ii_ippr_regval; struct { - uint64_t i_ippr0:32; - uint64_t i_ippr1:32; + u64 i_ippr0:32; + u64 i_ippr1:32; } ii_ippr_fld_s; } ii_ippr_u_t; @@ -3267,15 +3267,15 @@ typedef ii_icrb0_e_u_t icrbe_t; #define IO_PERF_SETS 32 /* Bit for the widget in inbound access register */ -#define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) +#define IIO_IIWA_WIDGET(_w) ((u64)(1ULL << _w)) /* Bit for the widget in outbound access register */ -#define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) +#define IIO_IOWA_WIDGET(_w) ((u64)(1ULL << _w)) /* NOTE: The following define assumes that we are going to get * widget numbers from 8 thru F and the device numbers within * widget from 0 thru 7. */ -#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d)))) +#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((u64)(1ULL << (8 * ((w) - 8) + (d)))) /* IO Interrupt Destination Register */ #define IIO_IIDSR_SENT_SHIFT 28 @@ -3302,9 +3302,9 @@ typedef ii_icrb0_e_u_t icrbe_t; */ typedef union hubii_wcr_u { - uint64_t wcr_reg_value; + u64 wcr_reg_value; struct { - uint64_t wcr_widget_id:4, /* LLP crossbar credit */ + u64 wcr_widget_id:4, /* LLP crossbar credit */ wcr_tag_mode:1, /* Tag mode */ wcr_rsvd1:8, /* Reserved */ wcr_xbar_crd:3, /* LLP crossbar credit */ @@ -3324,9 +3324,9 @@ performance registers */ performed */ typedef union io_perf_sel { - uint64_t perf_sel_reg; + u64 perf_sel_reg; struct { - uint64_t perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48; + u64 perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48; } perf_sel_bits; } io_perf_sel_t; @@ -3334,24 +3334,24 @@ typedef union io_perf_sel { hardware problems there is only one counter, not two. */ typedef union io_perf_cnt { - uint64_t perf_cnt; + u64 perf_cnt; struct { - uint64_t perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32; + u64 perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32; } perf_cnt_bits; } io_perf_cnt_t; typedef union iprte_a { - uint64_t entry; - struct { - uint64_t i_rsvd_1:3; - uint64_t i_addr:38; - uint64_t i_init:3; - uint64_t i_source:8; - uint64_t i_rsvd:2; - uint64_t i_widget:4; - uint64_t i_to_cnt:5; - uint64_t i_vld:1; + u64 entry; + struct { + u64 i_rsvd_1:3; + u64 i_addr:38; + u64 i_init:3; + u64 i_source:8; + u64 i_rsvd:2; + u64 i_widget:4; + u64 i_to_cnt:5; + u64 i_vld:1; } iprte_fields; } iprte_a_t; diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h index 8b9e10e7cdba..e77f0c9b7d3d 100644 --- a/include/asm-ia64/sn/sn_sal.h +++ b/include/asm-ia64/sn/sn_sal.h @@ -273,7 +273,7 @@ ia64_sn_console_putc(char ch) ret_stuff.v0 = 0; ret_stuff.v1 = 0; ret_stuff.v2 = 0; - SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (uint64_t)ch, 0, 0, 0, 0, 0, 0); + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (u64)ch, 0, 0, 0, 0, 0, 0); return ret_stuff.status; } @@ -290,7 +290,7 @@ ia64_sn_console_putb(const char *buf, int len) ret_stuff.v0 = 0; ret_stuff.v1 = 0; ret_stuff.v2 = 0; - SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (uint64_t)buf, (uint64_t)len, 0, 0, 0, 0, 0); + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (u64)buf, (u64)len, 0, 0, 0, 0, 0); if ( ret_stuff.status == 0 ) { return ret_stuff.v0; @@ -310,7 +310,7 @@ ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec) ret_stuff.v0 = 0; ret_stuff.v1 = 0; ret_stuff.v2 = 0; - SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (uint64_t)hook, (uint64_t)rec, 0, 0, 0, 0, 0); + SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (u64)hook, (u64)rec, 0, 0, 0, 0, 0); return ret_stuff.status; } @@ -398,7 +398,7 @@ ia64_sn_console_intr_status(void) * Enable an interrupt on the SAL console device. */ static inline void -ia64_sn_console_intr_enable(uint64_t intr) +ia64_sn_console_intr_enable(u64 intr) { struct ia64_sal_retval ret_stuff; @@ -415,7 +415,7 @@ ia64_sn_console_intr_enable(uint64_t intr) * Disable an interrupt on the SAL console device. */ static inline void -ia64_sn_console_intr_disable(uint64_t intr) +ia64_sn_console_intr_disable(u64 intr) { struct ia64_sal_retval ret_stuff; @@ -441,7 +441,7 @@ ia64_sn_console_xmit_chars(char *buf, int len) ret_stuff.v1 = 0; ret_stuff.v2 = 0; SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_XMIT_CHARS, - (uint64_t)buf, (uint64_t)len, + (u64)buf, (u64)len, 0, 0, 0, 0, 0); if (ret_stuff.status == 0) { diff --git a/include/asm-ia64/sn/tioca.h b/include/asm-ia64/sn/tioca.h index bc1aacfb9483..666222d7f0f6 100644 --- a/include/asm-ia64/sn/tioca.h +++ b/include/asm-ia64/sn/tioca.h @@ -19,47 +19,47 @@ */ struct tioca { - uint64_t ca_id; /* 0x000000 */ - uint64_t ca_control1; /* 0x000008 */ - uint64_t ca_control2; /* 0x000010 */ - uint64_t ca_status1; /* 0x000018 */ - uint64_t ca_status2; /* 0x000020 */ - uint64_t ca_gart_aperature; /* 0x000028 */ - uint64_t ca_gfx_detach; /* 0x000030 */ - uint64_t ca_inta_dest_addr; /* 0x000038 */ - uint64_t ca_intb_dest_addr; /* 0x000040 */ - uint64_t ca_err_int_dest_addr; /* 0x000048 */ - uint64_t ca_int_status; /* 0x000050 */ - uint64_t ca_int_status_alias; /* 0x000058 */ - uint64_t ca_mult_error; /* 0x000060 */ - uint64_t ca_mult_error_alias; /* 0x000068 */ - uint64_t ca_first_error; /* 0x000070 */ - uint64_t ca_int_mask; /* 0x000078 */ - uint64_t ca_crm_pkterr_type; /* 0x000080 */ - uint64_t ca_crm_pkterr_type_alias; /* 0x000088 */ - uint64_t ca_crm_ct_error_detail_1; /* 0x000090 */ - uint64_t ca_crm_ct_error_detail_2; /* 0x000098 */ - uint64_t ca_crm_tnumto; /* 0x0000A0 */ - uint64_t ca_gart_err; /* 0x0000A8 */ - uint64_t ca_pcierr_type; /* 0x0000B0 */ - uint64_t ca_pcierr_addr; /* 0x0000B8 */ - - uint64_t ca_pad_0000C0[3]; /* 0x0000{C0..D0} */ - - uint64_t ca_pci_rd_buf_flush; /* 0x0000D8 */ - uint64_t ca_pci_dma_addr_extn; /* 0x0000E0 */ - uint64_t ca_agp_dma_addr_extn; /* 0x0000E8 */ - uint64_t ca_force_inta; /* 0x0000F0 */ - uint64_t ca_force_intb; /* 0x0000F8 */ - uint64_t ca_debug_vector_sel; /* 0x000100 */ - uint64_t ca_debug_mux_core_sel; /* 0x000108 */ - uint64_t ca_debug_mux_pci_sel; /* 0x000110 */ - uint64_t ca_debug_domain_sel; /* 0x000118 */ - - uint64_t ca_pad_000120[28]; /* 0x0001{20..F8} */ - - uint64_t ca_gart_ptr_table; /* 0x200 */ - uint64_t ca_gart_tlb_addr[8]; /* 0x2{08..40} */ + u64 ca_id; /* 0x000000 */ + u64 ca_control1; /* 0x000008 */ + u64 ca_control2; /* 0x000010 */ + u64 ca_status1; /* 0x000018 */ + u64 ca_status2; /* 0x000020 */ + u64 ca_gart_aperature; /* 0x000028 */ + u64 ca_gfx_detach; /* 0x000030 */ + u64 ca_inta_dest_addr; /* 0x000038 */ + u64 ca_intb_dest_addr; /* 0x000040 */ + u64 ca_err_int_dest_addr; /* 0x000048 */ + u64 ca_int_status; /* 0x000050 */ + u64 ca_int_status_alias; /* 0x000058 */ + u64 ca_mult_error; /* 0x000060 */ + u64 ca_mult_error_alias; /* 0x000068 */ + u64 ca_first_error; /* 0x000070 */ + u64 ca_int_mask; /* 0x000078 */ + u64 ca_crm_pkterr_type; /* 0x000080 */ + u64 ca_crm_pkterr_type_alias; /* 0x000088 */ + u64 ca_crm_ct_error_detail_1; /* 0x000090 */ + u64 ca_crm_ct_error_detail_2; /* 0x000098 */ + u64 ca_crm_tnumto; /* 0x0000A0 */ + u64 ca_gart_err; /* 0x0000A8 */ + u64 ca_pcierr_type; /* 0x0000B0 */ + u64 ca_pcierr_addr; /* 0x0000B8 */ + + u64 ca_pad_0000C0[3]; /* 0x0000{C0..D0} */ + + u64 ca_pci_rd_buf_flush; /* 0x0000D8 */ + u64 ca_pci_dma_addr_extn; /* 0x0000E0 */ + u64 ca_agp_dma_addr_extn; /* 0x0000E8 */ + u64 ca_force_inta; /* 0x0000F0 */ + u64 ca_force_intb; /* 0x0000F8 */ + u64 ca_debug_vector_sel; /* 0x000100 */ + u64 ca_debug_mux_core_sel; /* 0x000108 */ + u64 ca_debug_mux_pci_sel; /* 0x000110 */ + u64 ca_debug_domain_sel; /* 0x000118 */ + + u64 ca_pad_000120[28]; /* 0x0001{20..F8} */ + + u64 ca_gart_ptr_table; /* 0x200 */ + u64 ca_gart_tlb_addr[8]; /* 0x2{08..40} */ }; /* diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h index b532ef6148ed..ab7fe2463468 100644 --- a/include/asm-ia64/sn/tioca_provider.h +++ b/include/asm-ia64/sn/tioca_provider.h @@ -56,31 +56,31 @@ struct tioca_kernel { /* * General GART stuff */ - uint64_t ca_ap_size; /* size of aperature in bytes */ - uint32_t ca_gart_entries; /* # uint64_t entries in gart */ - uint32_t ca_ap_pagesize; /* aperature page size in bytes */ - uint64_t ca_ap_bus_base; /* bus address of CA aperature */ - uint64_t ca_gart_size; /* gart size in bytes */ - uint64_t *ca_gart; /* gart table vaddr */ - uint64_t ca_gart_coretalk_addr; /* gart coretalk addr */ - uint8_t ca_gart_iscoherent; /* used in tioca_tlbflush */ + u64 ca_ap_size; /* size of aperature in bytes */ + u32 ca_gart_entries; /* # u64 entries in gart */ + u32 ca_ap_pagesize; /* aperature page size in bytes */ + u64 ca_ap_bus_base; /* bus address of CA aperature */ + u64 ca_gart_size; /* gart size in bytes */ + u64 *ca_gart; /* gart table vaddr */ + u64 ca_gart_coretalk_addr; /* gart coretalk addr */ + u8 ca_gart_iscoherent; /* used in tioca_tlbflush */ /* PCI GART convenience values */ - uint64_t ca_pciap_base; /* pci aperature bus base address */ - uint64_t ca_pciap_size; /* pci aperature size (bytes) */ - uint64_t ca_pcigart_base; /* gfx GART bus base address */ - uint64_t *ca_pcigart; /* gfx GART vm address */ - uint32_t ca_pcigart_entries; - uint32_t ca_pcigart_start; /* PCI start index in ca_gart */ + u64 ca_pciap_base; /* pci aperature bus base address */ + u64 ca_pciap_size; /* pci aperature size (bytes) */ + u64 ca_pcigart_base; /* gfx GART bus base address */ + u64 *ca_pcigart; /* gfx GART vm address */ + u32 ca_pcigart_entries; + u32 ca_pcigart_start; /* PCI start index in ca_gart */ void *ca_pcigart_pagemap; /* AGP GART convenience values */ - uint64_t ca_gfxap_base; /* gfx aperature bus base address */ - uint64_t ca_gfxap_size; /* gfx aperature size (bytes) */ - uint64_t ca_gfxgart_base; /* gfx GART bus base address */ - uint64_t *ca_gfxgart; /* gfx GART vm address */ - uint32_t ca_gfxgart_entries; - uint32_t ca_gfxgart_start; /* agpgart start index in ca_gart */ + u64 ca_gfxap_base; /* gfx aperature bus base address */ + u64 ca_gfxap_size; /* gfx aperature size (bytes) */ + u64 ca_gfxgart_base; /* gfx GART bus base address */ + u64 *ca_gfxgart; /* gfx GART vm address */ + u32 ca_gfxgart_entries; + u32 ca_gfxgart_start; /* agpgart start index in ca_gart */ }; /* @@ -93,11 +93,11 @@ struct tioca_kernel { struct tioca_common { struct pcibus_bussoft ca_common; /* common pciio header */ - uint32_t ca_rev; - uint32_t ca_closest_nasid; + u32 ca_rev; + u32 ca_closest_nasid; - uint64_t ca_prom_private; - uint64_t ca_kernel_private; + u64 ca_prom_private; + u64 ca_kernel_private; }; /** @@ -139,9 +139,9 @@ tioca_paddr_to_gart(unsigned long paddr) */ static inline unsigned long -tioca_physpage_to_gart(uint64_t page_addr) +tioca_physpage_to_gart(u64 page_addr) { - uint64_t coretalk_addr; + u64 coretalk_addr; coretalk_addr = PHYS_TO_TIODMA(page_addr); if (!coretalk_addr) { @@ -161,7 +161,7 @@ tioca_physpage_to_gart(uint64_t page_addr) static inline void tioca_tlbflush(struct tioca_kernel *tioca_kernel) { - volatile uint64_t tmp; + volatile u64 tmp; volatile struct tioca *ca_base; struct tioca_common *tioca_common; @@ -200,7 +200,7 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel) tmp = __sn_readq_relaxed(&ca_base->ca_control2); } -extern uint32_t tioca_gart_found; +extern u32 tioca_gart_found; extern struct list_head tioca_list; extern int tioca_init_provider(void); extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern); diff --git a/include/asm-ia64/sn/tioce.h b/include/asm-ia64/sn/tioce.h index ecaddf960086..d4c990712eac 100644 --- a/include/asm-ia64/sn/tioce.h +++ b/include/asm-ia64/sn/tioce.h @@ -35,72 +35,72 @@ typedef volatile struct tioce { /* * ADMIN : Administration Registers */ - uint64_t ce_adm_id; /* 0x000000 */ - uint64_t ce_pad_000008; /* 0x000008 */ - uint64_t ce_adm_dyn_credit_status; /* 0x000010 */ - uint64_t ce_adm_last_credit_status; /* 0x000018 */ - uint64_t ce_adm_credit_limit; /* 0x000020 */ - uint64_t ce_adm_force_credit; /* 0x000028 */ - uint64_t ce_adm_control; /* 0x000030 */ - uint64_t ce_adm_mmr_chn_timeout; /* 0x000038 */ - uint64_t ce_adm_ssp_ure_timeout; /* 0x000040 */ - uint64_t ce_adm_ssp_dre_timeout; /* 0x000048 */ - uint64_t ce_adm_ssp_debug_sel; /* 0x000050 */ - uint64_t ce_adm_int_status; /* 0x000058 */ - uint64_t ce_adm_int_status_alias; /* 0x000060 */ - uint64_t ce_adm_int_mask; /* 0x000068 */ - uint64_t ce_adm_int_pending; /* 0x000070 */ - uint64_t ce_adm_force_int; /* 0x000078 */ - uint64_t ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */ - uint64_t ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */ - uint64_t ce_adm_error_summary; /* 0x000100 */ - uint64_t ce_adm_error_summary_alias; /* 0x000108 */ - uint64_t ce_adm_error_mask; /* 0x000110 */ - uint64_t ce_adm_first_error; /* 0x000118 */ - uint64_t ce_adm_error_overflow; /* 0x000120 */ - uint64_t ce_adm_error_overflow_alias; /* 0x000128 */ - uint64_t ce_pad_000130[2]; /* 0x000130 -- 0x000138 */ - uint64_t ce_adm_tnum_error; /* 0x000140 */ - uint64_t ce_adm_mmr_err_detail; /* 0x000148 */ - uint64_t ce_adm_msg_sram_perr_detail; /* 0x000150 */ - uint64_t ce_adm_bap_sram_perr_detail; /* 0x000158 */ - uint64_t ce_adm_ce_sram_perr_detail; /* 0x000160 */ - uint64_t ce_adm_ce_credit_oflow_detail; /* 0x000168 */ - uint64_t ce_adm_tx_link_idle_max_timer; /* 0x000170 */ - uint64_t ce_adm_pcie_debug_sel; /* 0x000178 */ - uint64_t ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */ - - uint64_t ce_adm_pcie_debug_sel_top; /* 0x000200 */ - uint64_t ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */ - uint64_t ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */ - uint64_t ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */ - uint64_t ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */ - uint64_t ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */ - uint64_t ce_adm_pcie_trig_compare_top; /* 0x000230 */ - uint64_t ce_adm_pcie_trig_compare_en_top; /* 0x000238 */ - uint64_t ce_adm_ssp_debug_sel_top; /* 0x000240 */ - uint64_t ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */ - uint64_t ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */ - uint64_t ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */ - uint64_t ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */ - uint64_t ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */ - uint64_t ce_adm_ssp_trig_compare_top; /* 0x000270 */ - uint64_t ce_adm_ssp_trig_compare_en_top; /* 0x000278 */ - uint64_t ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */ - - uint64_t ce_adm_bap_ctrl; /* 0x000400 */ - uint64_t ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */ - - uint64_t ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */ - uint64_t ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */ - - uint64_t ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */ - uint64_t ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */ - - uint64_t ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */ - uint64_t ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */ - - uint64_t ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */ + u64 ce_adm_id; /* 0x000000 */ + u64 ce_pad_000008; /* 0x000008 */ + u64 ce_adm_dyn_credit_status; /* 0x000010 */ + u64 ce_adm_last_credit_status; /* 0x000018 */ + u64 ce_adm_credit_limit; /* 0x000020 */ + u64 ce_adm_force_credit; /* 0x000028 */ + u64 ce_adm_control; /* 0x000030 */ + u64 ce_adm_mmr_chn_timeout; /* 0x000038 */ + u64 ce_adm_ssp_ure_timeout; /* 0x000040 */ + u64 ce_adm_ssp_dre_timeout; /* 0x000048 */ + u64 ce_adm_ssp_debug_sel; /* 0x000050 */ + u64 ce_adm_int_status; /* 0x000058 */ + u64 ce_adm_int_status_alias; /* 0x000060 */ + u64 ce_adm_int_mask; /* 0x000068 */ + u64 ce_adm_int_pending; /* 0x000070 */ + u64 ce_adm_force_int; /* 0x000078 */ + u64 ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */ + u64 ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */ + u64 ce_adm_error_summary; /* 0x000100 */ + u64 ce_adm_error_summary_alias; /* 0x000108 */ + u64 ce_adm_error_mask; /* 0x000110 */ + u64 ce_adm_first_error; /* 0x000118 */ + u64 ce_adm_error_overflow; /* 0x000120 */ + u64 ce_adm_error_overflow_alias; /* 0x000128 */ + u64 ce_pad_000130[2]; /* 0x000130 -- 0x000138 */ + u64 ce_adm_tnum_error; /* 0x000140 */ + u64 ce_adm_mmr_err_detail; /* 0x000148 */ + u64 ce_adm_msg_sram_perr_detail; /* 0x000150 */ + u64 ce_adm_bap_sram_perr_detail; /* 0x000158 */ + u64 ce_adm_ce_sram_perr_detail; /* 0x000160 */ + u64 ce_adm_ce_credit_oflow_detail; /* 0x000168 */ + u64 ce_adm_tx_link_idle_max_timer; /* 0x000170 */ + u64 ce_adm_pcie_debug_sel; /* 0x000178 */ + u64 ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */ + + u64 ce_adm_pcie_debug_sel_top; /* 0x000200 */ + u64 ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */ + u64 ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */ + u64 ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */ + u64 ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */ + u64 ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */ + u64 ce_adm_pcie_trig_compare_top; /* 0x000230 */ + u64 ce_adm_pcie_trig_compare_en_top; /* 0x000238 */ + u64 ce_adm_ssp_debug_sel_top; /* 0x000240 */ + u64 ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */ + u64 ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */ + u64 ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */ + u64 ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */ + u64 ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */ + u64 ce_adm_ssp_trig_compare_top; /* 0x000270 */ + u64 ce_adm_ssp_trig_compare_en_top; /* 0x000278 */ + u64 ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */ + + u64 ce_adm_bap_ctrl; /* 0x000400 */ + u64 ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */ + + u64 ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */ + u64 ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */ + + u64 ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */ + u64 ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */ + + u64 ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */ + u64 ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */ + + u64 ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */ /* * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2) @@ -109,141 +109,141 @@ typedef volatile struct tioce { */ #define ce_lsi(link_num) ce_lsi[link_num-1] struct ce_lsi_reg { - uint64_t ce_lsi_lpu_id; /* 0x00z000 */ - uint64_t ce_lsi_rst; /* 0x00z008 */ - uint64_t ce_lsi_dbg_stat; /* 0x00z010 */ - uint64_t ce_lsi_dbg_cfg; /* 0x00z018 */ - uint64_t ce_lsi_ltssm_ctrl; /* 0x00z020 */ - uint64_t ce_lsi_lk_stat; /* 0x00z028 */ - uint64_t ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */ - uint64_t ce_lsi_int_and_stat; /* 0x00z040 */ - uint64_t ce_lsi_int_mask; /* 0x00z048 */ - uint64_t ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */ - uint64_t ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */ - uint64_t ce_pad_00z108; /* 0x00z108 */ - uint64_t ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */ - uint64_t ce_pad_00z118; /* 0x00z118 */ - uint64_t ce_lsi_lk_perf_cnt1; /* 0x00z120 */ - uint64_t ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */ - uint64_t ce_lsi_lk_perf_cnt2; /* 0x00z130 */ - uint64_t ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */ - uint64_t ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */ - uint64_t ce_lsi_lk_lyr_cfg; /* 0x00z200 */ - uint64_t ce_lsi_lk_lyr_status; /* 0x00z208 */ - uint64_t ce_lsi_lk_lyr_int_stat; /* 0x00z210 */ - uint64_t ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */ - uint64_t ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */ - uint64_t ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */ - uint64_t ce_lsi_fc_upd_ctl; /* 0x00z240 */ - uint64_t ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */ - uint64_t ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */ - uint64_t ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */ - uint64_t ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */ - uint64_t ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */ - uint64_t ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */ - uint64_t ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */ - uint64_t ce_lsi_rply_tmr_thr; /* 0x00z410 */ - uint64_t ce_lsi_rply_tmr; /* 0x00z418 */ - uint64_t ce_lsi_rply_num_stat; /* 0x00z420 */ - uint64_t ce_lsi_rty_buf_max_addr; /* 0x00z428 */ - uint64_t ce_lsi_rty_fifo_ptr; /* 0x00z430 */ - uint64_t ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */ - uint64_t ce_lsi_rty_fifo_cred; /* 0x00z440 */ - uint64_t ce_lsi_seq_cnt; /* 0x00z448 */ - uint64_t ce_lsi_ack_sent_seq_num; /* 0x00z450 */ - uint64_t ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */ - uint64_t ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */ - uint64_t ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */ - uint64_t ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */ - uint64_t ce_pad_00z478; /* 0x00z478 */ - uint64_t ce_lsi_mem_addr_ctl; /* 0x00z480 */ - uint64_t ce_lsi_mem_d_ld0; /* 0x00z488 */ - uint64_t ce_lsi_mem_d_ld1; /* 0x00z490 */ - uint64_t ce_lsi_mem_d_ld2; /* 0x00z498 */ - uint64_t ce_lsi_mem_d_ld3; /* 0x00z4A0 */ - uint64_t ce_lsi_mem_d_ld4; /* 0x00z4A8 */ - uint64_t ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */ - uint64_t ce_lsi_rty_d_cnt; /* 0x00z4C0 */ - uint64_t ce_lsi_seq_buf_cnt; /* 0x00z4C8 */ - uint64_t ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */ - uint64_t ce_pad_00z4D8; /* 0x00z4D8 */ - uint64_t ce_lsi_ack_lat_thr; /* 0x00z4E0 */ - uint64_t ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */ - uint64_t ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */ - uint64_t ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */ - uint64_t ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */ - uint64_t ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */ - uint64_t ce_lsi_phy_lyr_cfg; /* 0x00z600 */ - uint64_t ce_pad_00z608; /* 0x00z608 */ - uint64_t ce_lsi_phy_lyr_int_stat; /* 0x00z610 */ - uint64_t ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */ - uint64_t ce_lsi_phy_lyr_int_mask; /* 0x00z620 */ - uint64_t ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */ - uint64_t ce_lsi_rcv_phy_cfg; /* 0x00z680 */ - uint64_t ce_lsi_rcv_phy_stat1; /* 0x00z688 */ - uint64_t ce_lsi_rcv_phy_stat2; /* 0x00z690 */ - uint64_t ce_lsi_rcv_phy_stat3; /* 0x00z698 */ - uint64_t ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */ - uint64_t ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */ - uint64_t ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */ - uint64_t ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */ - uint64_t ce_lsi_tx_phy_cfg; /* 0x00z700 */ - uint64_t ce_lsi_tx_phy_stat; /* 0x00z708 */ - uint64_t ce_lsi_tx_phy_int_stat; /* 0x00z710 */ - uint64_t ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */ - uint64_t ce_lsi_tx_phy_int_mask; /* 0x00z720 */ - uint64_t ce_lsi_tx_phy_stat2; /* 0x00z728 */ - uint64_t ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */ - uint64_t ce_lsi_ltssm_cfg1; /* 0x00z780 */ - uint64_t ce_lsi_ltssm_cfg2; /* 0x00z788 */ - uint64_t ce_lsi_ltssm_cfg3; /* 0x00z790 */ - uint64_t ce_lsi_ltssm_cfg4; /* 0x00z798 */ - uint64_t ce_lsi_ltssm_cfg5; /* 0x00z7A0 */ - uint64_t ce_lsi_ltssm_stat1; /* 0x00z7A8 */ - uint64_t ce_lsi_ltssm_stat2; /* 0x00z7B0 */ - uint64_t ce_lsi_ltssm_int_stat; /* 0x00z7B8 */ - uint64_t ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */ - uint64_t ce_lsi_ltssm_int_mask; /* 0x00z7C8 */ - uint64_t ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */ - uint64_t ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */ - uint64_t ce_lsi_gb_cfg1; /* 0x00z800 */ - uint64_t ce_lsi_gb_cfg2; /* 0x00z808 */ - uint64_t ce_lsi_gb_cfg3; /* 0x00z810 */ - uint64_t ce_lsi_gb_cfg4; /* 0x00z818 */ - uint64_t ce_lsi_gb_stat; /* 0x00z820 */ - uint64_t ce_lsi_gb_int_stat; /* 0x00z828 */ - uint64_t ce_lsi_gb_int_stat_test; /* 0x00z830 */ - uint64_t ce_lsi_gb_int_mask; /* 0x00z838 */ - uint64_t ce_lsi_gb_pwr_dn1; /* 0x00z840 */ - uint64_t ce_lsi_gb_pwr_dn2; /* 0x00z848 */ - uint64_t ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */ + u64 ce_lsi_lpu_id; /* 0x00z000 */ + u64 ce_lsi_rst; /* 0x00z008 */ + u64 ce_lsi_dbg_stat; /* 0x00z010 */ + u64 ce_lsi_dbg_cfg; /* 0x00z018 */ + u64 ce_lsi_ltssm_ctrl; /* 0x00z020 */ + u64 ce_lsi_lk_stat; /* 0x00z028 */ + u64 ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */ + u64 ce_lsi_int_and_stat; /* 0x00z040 */ + u64 ce_lsi_int_mask; /* 0x00z048 */ + u64 ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */ + u64 ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */ + u64 ce_pad_00z108; /* 0x00z108 */ + u64 ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */ + u64 ce_pad_00z118; /* 0x00z118 */ + u64 ce_lsi_lk_perf_cnt1; /* 0x00z120 */ + u64 ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */ + u64 ce_lsi_lk_perf_cnt2; /* 0x00z130 */ + u64 ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */ + u64 ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */ + u64 ce_lsi_lk_lyr_cfg; /* 0x00z200 */ + u64 ce_lsi_lk_lyr_status; /* 0x00z208 */ + u64 ce_lsi_lk_lyr_int_stat; /* 0x00z210 */ + u64 ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */ + u64 ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */ + u64 ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */ + u64 ce_lsi_fc_upd_ctl; /* 0x00z240 */ + u64 ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */ + u64 ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */ + u64 ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */ + u64 ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */ + u64 ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */ + u64 ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */ + u64 ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */ + u64 ce_lsi_rply_tmr_thr; /* 0x00z410 */ + u64 ce_lsi_rply_tmr; /* 0x00z418 */ + u64 ce_lsi_rply_num_stat; /* 0x00z420 */ + u64 ce_lsi_rty_buf_max_addr; /* 0x00z428 */ + u64 ce_lsi_rty_fifo_ptr; /* 0x00z430 */ + u64 ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */ + u64 ce_lsi_rty_fifo_cred; /* 0x00z440 */ + u64 ce_lsi_seq_cnt; /* 0x00z448 */ + u64 ce_lsi_ack_sent_seq_num; /* 0x00z450 */ + u64 ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */ + u64 ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */ + u64 ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */ + u64 ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */ + u64 ce_pad_00z478; /* 0x00z478 */ + u64 ce_lsi_mem_addr_ctl; /* 0x00z480 */ + u64 ce_lsi_mem_d_ld0; /* 0x00z488 */ + u64 ce_lsi_mem_d_ld1; /* 0x00z490 */ + u64 ce_lsi_mem_d_ld2; /* 0x00z498 */ + u64 ce_lsi_mem_d_ld3; /* 0x00z4A0 */ + u64 ce_lsi_mem_d_ld4; /* 0x00z4A8 */ + u64 ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */ + u64 ce_lsi_rty_d_cnt; /* 0x00z4C0 */ + u64 ce_lsi_seq_buf_cnt; /* 0x00z4C8 */ + u64 ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */ + u64 ce_pad_00z4D8; /* 0x00z4D8 */ + u64 ce_lsi_ack_lat_thr; /* 0x00z4E0 */ + u64 ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */ + u64 ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */ + u64 ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */ + u64 ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */ + u64 ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */ + u64 ce_lsi_phy_lyr_cfg; /* 0x00z600 */ + u64 ce_pad_00z608; /* 0x00z608 */ + u64 ce_lsi_phy_lyr_int_stat; /* 0x00z610 */ + u64 ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */ + u64 ce_lsi_phy_lyr_int_mask; /* 0x00z620 */ + u64 ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */ + u64 ce_lsi_rcv_phy_cfg; /* 0x00z680 */ + u64 ce_lsi_rcv_phy_stat1; /* 0x00z688 */ + u64 ce_lsi_rcv_phy_stat2; /* 0x00z690 */ + u64 ce_lsi_rcv_phy_stat3; /* 0x00z698 */ + u64 ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */ + u64 ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */ + u64 ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */ + u64 ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */ + u64 ce_lsi_tx_phy_cfg; /* 0x00z700 */ + u64 ce_lsi_tx_phy_stat; /* 0x00z708 */ + u64 ce_lsi_tx_phy_int_stat; /* 0x00z710 */ + u64 ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */ + u64 ce_lsi_tx_phy_int_mask; /* 0x00z720 */ + u64 ce_lsi_tx_phy_stat2; /* 0x00z728 */ + u64 ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */ + u64 ce_lsi_ltssm_cfg1; /* 0x00z780 */ + u64 ce_lsi_ltssm_cfg2; /* 0x00z788 */ + u64 ce_lsi_ltssm_cfg3; /* 0x00z790 */ + u64 ce_lsi_ltssm_cfg4; /* 0x00z798 */ + u64 ce_lsi_ltssm_cfg5; /* 0x00z7A0 */ + u64 ce_lsi_ltssm_stat1; /* 0x00z7A8 */ + u64 ce_lsi_ltssm_stat2; /* 0x00z7B0 */ + u64 ce_lsi_ltssm_int_stat; /* 0x00z7B8 */ + u64 ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */ + u64 ce_lsi_ltssm_int_mask; /* 0x00z7C8 */ + u64 ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */ + u64 ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */ + u64 ce_lsi_gb_cfg1; /* 0x00z800 */ + u64 ce_lsi_gb_cfg2; /* 0x00z808 */ + u64 ce_lsi_gb_cfg3; /* 0x00z810 */ + u64 ce_lsi_gb_cfg4; /* 0x00z818 */ + u64 ce_lsi_gb_stat; /* 0x00z820 */ + u64 ce_lsi_gb_int_stat; /* 0x00z828 */ + u64 ce_lsi_gb_int_stat_test; /* 0x00z830 */ + u64 ce_lsi_gb_int_mask; /* 0x00z838 */ + u64 ce_lsi_gb_pwr_dn1; /* 0x00z840 */ + u64 ce_lsi_gb_pwr_dn2; /* 0x00z848 */ + u64 ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */ } ce_lsi[2]; - uint64_t ce_pad_004000[10]; /* 0x004000 -- 0x004048 */ + u64 ce_pad_004000[10]; /* 0x004000 -- 0x004048 */ /* * CRM: Coretalk Receive Module Registers */ - uint64_t ce_crm_debug_mux; /* 0x004050 */ - uint64_t ce_pad_004058; /* 0x004058 */ - uint64_t ce_crm_ssp_err_cmd_wrd; /* 0x004060 */ - uint64_t ce_crm_ssp_err_addr; /* 0x004068 */ - uint64_t ce_crm_ssp_err_syn; /* 0x004070 */ + u64 ce_crm_debug_mux; /* 0x004050 */ + u64 ce_pad_004058; /* 0x004058 */ + u64 ce_crm_ssp_err_cmd_wrd; /* 0x004060 */ + u64 ce_crm_ssp_err_addr; /* 0x004068 */ + u64 ce_crm_ssp_err_syn; /* 0x004070 */ - uint64_t ce_pad_004078[499]; /* 0x004078 -- 0x005008 */ + u64 ce_pad_004078[499]; /* 0x004078 -- 0x005008 */ /* * CXM: Coretalk Xmit Module Registers */ - uint64_t ce_cxm_dyn_credit_status; /* 0x005010 */ - uint64_t ce_cxm_last_credit_status; /* 0x005018 */ - uint64_t ce_cxm_credit_limit; /* 0x005020 */ - uint64_t ce_cxm_force_credit; /* 0x005028 */ - uint64_t ce_cxm_disable_bypass; /* 0x005030 */ - uint64_t ce_pad_005038[3]; /* 0x005038 -- 0x005048 */ - uint64_t ce_cxm_debug_mux; /* 0x005050 */ + u64 ce_cxm_dyn_credit_status; /* 0x005010 */ + u64 ce_cxm_last_credit_status; /* 0x005018 */ + u64 ce_cxm_credit_limit; /* 0x005020 */ + u64 ce_cxm_force_credit; /* 0x005028 */ + u64 ce_cxm_disable_bypass; /* 0x005030 */ + u64 ce_pad_005038[3]; /* 0x005038 -- 0x005048 */ + u64 ce_cxm_debug_mux; /* 0x005050 */ - uint64_t ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */ + u64 ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */ /* * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2) @@ -258,209 +258,209 @@ typedef volatile struct tioce { #define ce_utl(link_num) ce_dtl_utl[link_num-1] struct ce_dtl_utl_reg { /* DTL */ - uint64_t ce_dtl_dtdr_credit_limit; /* 0x00y000 */ - uint64_t ce_dtl_dtdr_credit_force; /* 0x00y008 */ - uint64_t ce_dtl_dyn_credit_status; /* 0x00y010 */ - uint64_t ce_dtl_dtl_last_credit_stat; /* 0x00y018 */ - uint64_t ce_dtl_dtl_ctrl; /* 0x00y020 */ - uint64_t ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */ - uint64_t ce_dtl_debug_sel; /* 0x00y050 */ - uint64_t ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */ + u64 ce_dtl_dtdr_credit_limit; /* 0x00y000 */ + u64 ce_dtl_dtdr_credit_force; /* 0x00y008 */ + u64 ce_dtl_dyn_credit_status; /* 0x00y010 */ + u64 ce_dtl_dtl_last_credit_stat; /* 0x00y018 */ + u64 ce_dtl_dtl_ctrl; /* 0x00y020 */ + u64 ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */ + u64 ce_dtl_debug_sel; /* 0x00y050 */ + u64 ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */ /* UTL */ - uint64_t ce_utl_utl_ctrl; /* 0x00z000 */ - uint64_t ce_utl_debug_sel; /* 0x00z008 */ - uint64_t ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */ + u64 ce_utl_utl_ctrl; /* 0x00z000 */ + u64 ce_utl_debug_sel; /* 0x00z008 */ + u64 ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */ } ce_dtl_utl[2]; - uint64_t ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */ + u64 ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */ /* * URE: Upstream Request Engine */ - uint64_t ce_ure_dyn_credit_status; /* 0x00B010 */ - uint64_t ce_ure_last_credit_status; /* 0x00B018 */ - uint64_t ce_ure_credit_limit; /* 0x00B020 */ - uint64_t ce_pad_00B028; /* 0x00B028 */ - uint64_t ce_ure_control; /* 0x00B030 */ - uint64_t ce_ure_status; /* 0x00B038 */ - uint64_t ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */ - uint64_t ce_ure_debug_sel; /* 0x00B050 */ - uint64_t ce_ure_pcie_debug_sel; /* 0x00B058 */ - uint64_t ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */ - uint64_t ce_ure_ssp_err_addr; /* 0x00B068 */ - uint64_t ce_ure_page_map; /* 0x00B070 */ - uint64_t ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */ - uint64_t ce_ure_pipe_sel1; /* 0x00B088 */ - uint64_t ce_ure_pipe_mask1; /* 0x00B090 */ - uint64_t ce_ure_pipe_sel2; /* 0x00B098 */ - uint64_t ce_ure_pipe_mask2; /* 0x00B0A0 */ - uint64_t ce_ure_pcie1_credits_sent; /* 0x00B0A8 */ - uint64_t ce_ure_pcie1_credits_used; /* 0x00B0B0 */ - uint64_t ce_ure_pcie1_credit_limit; /* 0x00B0B8 */ - uint64_t ce_ure_pcie2_credits_sent; /* 0x00B0C0 */ - uint64_t ce_ure_pcie2_credits_used; /* 0x00B0C8 */ - uint64_t ce_ure_pcie2_credit_limit; /* 0x00B0D0 */ - uint64_t ce_ure_pcie_force_credit; /* 0x00B0D8 */ - uint64_t ce_ure_rd_tnum_val; /* 0x00B0E0 */ - uint64_t ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */ - uint64_t ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */ - uint64_t ce_ure_rd_tnum_error; /* 0x00B0F8 */ - uint64_t ce_ure_rd_tnum_first_cl; /* 0x00B100 */ - uint64_t ce_ure_rd_tnum_link_buf; /* 0x00B108 */ - uint64_t ce_ure_wr_tnum_val; /* 0x00B110 */ - uint64_t ce_ure_sram_err_addr0; /* 0x00B118 */ - uint64_t ce_ure_sram_err_addr1; /* 0x00B120 */ - uint64_t ce_ure_sram_err_addr2; /* 0x00B128 */ - uint64_t ce_ure_sram_rd_addr0; /* 0x00B130 */ - uint64_t ce_ure_sram_rd_addr1; /* 0x00B138 */ - uint64_t ce_ure_sram_rd_addr2; /* 0x00B140 */ - uint64_t ce_ure_sram_wr_addr0; /* 0x00B148 */ - uint64_t ce_ure_sram_wr_addr1; /* 0x00B150 */ - uint64_t ce_ure_sram_wr_addr2; /* 0x00B158 */ - uint64_t ce_ure_buf_flush10; /* 0x00B160 */ - uint64_t ce_ure_buf_flush11; /* 0x00B168 */ - uint64_t ce_ure_buf_flush12; /* 0x00B170 */ - uint64_t ce_ure_buf_flush13; /* 0x00B178 */ - uint64_t ce_ure_buf_flush20; /* 0x00B180 */ - uint64_t ce_ure_buf_flush21; /* 0x00B188 */ - uint64_t ce_ure_buf_flush22; /* 0x00B190 */ - uint64_t ce_ure_buf_flush23; /* 0x00B198 */ - uint64_t ce_ure_pcie_control1; /* 0x00B1A0 */ - uint64_t ce_ure_pcie_control2; /* 0x00B1A8 */ - - uint64_t ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */ + u64 ce_ure_dyn_credit_status; /* 0x00B010 */ + u64 ce_ure_last_credit_status; /* 0x00B018 */ + u64 ce_ure_credit_limit; /* 0x00B020 */ + u64 ce_pad_00B028; /* 0x00B028 */ + u64 ce_ure_control; /* 0x00B030 */ + u64 ce_ure_status; /* 0x00B038 */ + u64 ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */ + u64 ce_ure_debug_sel; /* 0x00B050 */ + u64 ce_ure_pcie_debug_sel; /* 0x00B058 */ + u64 ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */ + u64 ce_ure_ssp_err_addr; /* 0x00B068 */ + u64 ce_ure_page_map; /* 0x00B070 */ + u64 ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */ + u64 ce_ure_pipe_sel1; /* 0x00B088 */ + u64 ce_ure_pipe_mask1; /* 0x00B090 */ + u64 ce_ure_pipe_sel2; /* 0x00B098 */ + u64 ce_ure_pipe_mask2; /* 0x00B0A0 */ + u64 ce_ure_pcie1_credits_sent; /* 0x00B0A8 */ + u64 ce_ure_pcie1_credits_used; /* 0x00B0B0 */ + u64 ce_ure_pcie1_credit_limit; /* 0x00B0B8 */ + u64 ce_ure_pcie2_credits_sent; /* 0x00B0C0 */ + u64 ce_ure_pcie2_credits_used; /* 0x00B0C8 */ + u64 ce_ure_pcie2_credit_limit; /* 0x00B0D0 */ + u64 ce_ure_pcie_force_credit; /* 0x00B0D8 */ + u64 ce_ure_rd_tnum_val; /* 0x00B0E0 */ + u64 ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */ + u64 ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */ + u64 ce_ure_rd_tnum_error; /* 0x00B0F8 */ + u64 ce_ure_rd_tnum_first_cl; /* 0x00B100 */ + u64 ce_ure_rd_tnum_link_buf; /* 0x00B108 */ + u64 ce_ure_wr_tnum_val; /* 0x00B110 */ + u64 ce_ure_sram_err_addr0; /* 0x00B118 */ + u64 ce_ure_sram_err_addr1; /* 0x00B120 */ + u64 ce_ure_sram_err_addr2; /* 0x00B128 */ + u64 ce_ure_sram_rd_addr0; /* 0x00B130 */ + u64 ce_ure_sram_rd_addr1; /* 0x00B138 */ + u64 ce_ure_sram_rd_addr2; /* 0x00B140 */ + u64 ce_ure_sram_wr_addr0; /* 0x00B148 */ + u64 ce_ure_sram_wr_addr1; /* 0x00B150 */ + u64 ce_ure_sram_wr_addr2; /* 0x00B158 */ + u64 ce_ure_buf_flush10; /* 0x00B160 */ + u64 ce_ure_buf_flush11; /* 0x00B168 */ + u64 ce_ure_buf_flush12; /* 0x00B170 */ + u64 ce_ure_buf_flush13; /* 0x00B178 */ + u64 ce_ure_buf_flush20; /* 0x00B180 */ + u64 ce_ure_buf_flush21; /* 0x00B188 */ + u64 ce_ure_buf_flush22; /* 0x00B190 */ + u64 ce_ure_buf_flush23; /* 0x00B198 */ + u64 ce_ure_pcie_control1; /* 0x00B1A0 */ + u64 ce_ure_pcie_control2; /* 0x00B1A8 */ + + u64 ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */ /* Upstream Data Buffer, Port1 */ struct ce_ure_maint_ups_dat1_data { - uint64_t data63_0[512]; /* 0x00C000 -- 0x00CFF8 */ - uint64_t data127_64[512]; /* 0x00D000 -- 0x00DFF8 */ - uint64_t parity[512]; /* 0x00E000 -- 0x00EFF8 */ + u64 data63_0[512]; /* 0x00C000 -- 0x00CFF8 */ + u64 data127_64[512]; /* 0x00D000 -- 0x00DFF8 */ + u64 parity[512]; /* 0x00E000 -- 0x00EFF8 */ } ce_ure_maint_ups_dat1; /* Upstream Header Buffer, Port1 */ struct ce_ure_maint_ups_hdr1_data { - uint64_t data63_0[512]; /* 0x00F000 -- 0x00FFF8 */ - uint64_t data127_64[512]; /* 0x010000 -- 0x010FF8 */ - uint64_t parity[512]; /* 0x011000 -- 0x011FF8 */ + u64 data63_0[512]; /* 0x00F000 -- 0x00FFF8 */ + u64 data127_64[512]; /* 0x010000 -- 0x010FF8 */ + u64 parity[512]; /* 0x011000 -- 0x011FF8 */ } ce_ure_maint_ups_hdr1; /* Upstream Data Buffer, Port2 */ struct ce_ure_maint_ups_dat2_data { - uint64_t data63_0[512]; /* 0x012000 -- 0x012FF8 */ - uint64_t data127_64[512]; /* 0x013000 -- 0x013FF8 */ - uint64_t parity[512]; /* 0x014000 -- 0x014FF8 */ + u64 data63_0[512]; /* 0x012000 -- 0x012FF8 */ + u64 data127_64[512]; /* 0x013000 -- 0x013FF8 */ + u64 parity[512]; /* 0x014000 -- 0x014FF8 */ } ce_ure_maint_ups_dat2; /* Upstream Header Buffer, Port2 */ struct ce_ure_maint_ups_hdr2_data { - uint64_t data63_0[512]; /* 0x015000 -- 0x015FF8 */ - uint64_t data127_64[512]; /* 0x016000 -- 0x016FF8 */ - uint64_t parity[512]; /* 0x017000 -- 0x017FF8 */ + u64 data63_0[512]; /* 0x015000 -- 0x015FF8 */ + u64 data127_64[512]; /* 0x016000 -- 0x016FF8 */ + u64 parity[512]; /* 0x017000 -- 0x017FF8 */ } ce_ure_maint_ups_hdr2; /* Downstream Data Buffer */ struct ce_ure_maint_dns_dat_data { - uint64_t data63_0[512]; /* 0x018000 -- 0x018FF8 */ - uint64_t data127_64[512]; /* 0x019000 -- 0x019FF8 */ - uint64_t parity[512]; /* 0x01A000 -- 0x01AFF8 */ + u64 data63_0[512]; /* 0x018000 -- 0x018FF8 */ + u64 data127_64[512]; /* 0x019000 -- 0x019FF8 */ + u64 parity[512]; /* 0x01A000 -- 0x01AFF8 */ } ce_ure_maint_dns_dat; /* Downstream Header Buffer */ struct ce_ure_maint_dns_hdr_data { - uint64_t data31_0[64]; /* 0x01B000 -- 0x01B1F8 */ - uint64_t data95_32[64]; /* 0x01B200 -- 0x01B3F8 */ - uint64_t parity[64]; /* 0x01B400 -- 0x01B5F8 */ + u64 data31_0[64]; /* 0x01B000 -- 0x01B1F8 */ + u64 data95_32[64]; /* 0x01B200 -- 0x01B3F8 */ + u64 parity[64]; /* 0x01B400 -- 0x01B5F8 */ } ce_ure_maint_dns_hdr; /* RCI Buffer Data */ struct ce_ure_maint_rci_data { - uint64_t data41_0[64]; /* 0x01B600 -- 0x01B7F8 */ - uint64_t data69_42[64]; /* 0x01B800 -- 0x01B9F8 */ + u64 data41_0[64]; /* 0x01B600 -- 0x01B7F8 */ + u64 data69_42[64]; /* 0x01B800 -- 0x01B9F8 */ } ce_ure_maint_rci; /* Response Queue */ - uint64_t ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */ + u64 ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */ - uint64_t ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */ + u64 ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */ /* Admin Build-a-Packet Buffer */ struct ce_adm_maint_bap_buf_data { - uint64_t data63_0[258]; /* 0x024000 -- 0x024808 */ - uint64_t data127_64[258]; /* 0x024810 -- 0x025018 */ - uint64_t parity[258]; /* 0x025020 -- 0x025828 */ + u64 data63_0[258]; /* 0x024000 -- 0x024808 */ + u64 data127_64[258]; /* 0x024810 -- 0x025018 */ + u64 parity[258]; /* 0x025020 -- 0x025828 */ } ce_adm_maint_bap_buf; - uint64_t ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */ + u64 ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */ /* URE: 40bit PMU ATE Buffer */ /* 0x030000 -- 0x037FF8 */ - uint64_t ce_ure_ate40[TIOCE_NUM_M40_ATES]; + u64 ce_ure_ate40[TIOCE_NUM_M40_ATES]; /* URE: 32/40bit PMU ATE Buffer */ /* 0x038000 -- 0x03BFF8 */ - uint64_t ce_ure_ate3240[TIOCE_NUM_M3240_ATES]; + u64 ce_ure_ate3240[TIOCE_NUM_M3240_ATES]; - uint64_t ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */ + u64 ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */ /* * DRE: Down Stream Request Engine */ - uint64_t ce_dre_dyn_credit_status1; /* 0x040010 */ - uint64_t ce_dre_dyn_credit_status2; /* 0x040018 */ - uint64_t ce_dre_last_credit_status1; /* 0x040020 */ - uint64_t ce_dre_last_credit_status2; /* 0x040028 */ - uint64_t ce_dre_credit_limit1; /* 0x040030 */ - uint64_t ce_dre_credit_limit2; /* 0x040038 */ - uint64_t ce_dre_force_credit1; /* 0x040040 */ - uint64_t ce_dre_force_credit2; /* 0x040048 */ - uint64_t ce_dre_debug_mux1; /* 0x040050 */ - uint64_t ce_dre_debug_mux2; /* 0x040058 */ - uint64_t ce_dre_ssp_err_cmd_wrd; /* 0x040060 */ - uint64_t ce_dre_ssp_err_addr; /* 0x040068 */ - uint64_t ce_dre_comp_err_cmd_wrd; /* 0x040070 */ - uint64_t ce_dre_comp_err_addr; /* 0x040078 */ - uint64_t ce_dre_req_status; /* 0x040080 */ - uint64_t ce_dre_config1; /* 0x040088 */ - uint64_t ce_dre_config2; /* 0x040090 */ - uint64_t ce_dre_config_req_status; /* 0x040098 */ - uint64_t ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */ - uint64_t ce_dre_dyn_fifo; /* 0x040100 */ - uint64_t ce_pad_040108[3]; /* 0x040108 -- 0x040118 */ - uint64_t ce_dre_last_fifo; /* 0x040120 */ - - uint64_t ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */ + u64 ce_dre_dyn_credit_status1; /* 0x040010 */ + u64 ce_dre_dyn_credit_status2; /* 0x040018 */ + u64 ce_dre_last_credit_status1; /* 0x040020 */ + u64 ce_dre_last_credit_status2; /* 0x040028 */ + u64 ce_dre_credit_limit1; /* 0x040030 */ + u64 ce_dre_credit_limit2; /* 0x040038 */ + u64 ce_dre_force_credit1; /* 0x040040 */ + u64 ce_dre_force_credit2; /* 0x040048 */ + u64 ce_dre_debug_mux1; /* 0x040050 */ + u64 ce_dre_debug_mux2; /* 0x040058 */ + u64 ce_dre_ssp_err_cmd_wrd; /* 0x040060 */ + u64 ce_dre_ssp_err_addr; /* 0x040068 */ + u64 ce_dre_comp_err_cmd_wrd; /* 0x040070 */ + u64 ce_dre_comp_err_addr; /* 0x040078 */ + u64 ce_dre_req_status; /* 0x040080 */ + u64 ce_dre_config1; /* 0x040088 */ + u64 ce_dre_config2; /* 0x040090 */ + u64 ce_dre_config_req_status; /* 0x040098 */ + u64 ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */ + u64 ce_dre_dyn_fifo; /* 0x040100 */ + u64 ce_pad_040108[3]; /* 0x040108 -- 0x040118 */ + u64 ce_dre_last_fifo; /* 0x040120 */ + + u64 ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */ /* DRE Downstream Head Queue */ struct ce_dre_maint_ds_head_queue { - uint64_t data63_0[32]; /* 0x040200 -- 0x0402F8 */ - uint64_t data127_64[32]; /* 0x040300 -- 0x0403F8 */ - uint64_t parity[32]; /* 0x040400 -- 0x0404F8 */ + u64 data63_0[32]; /* 0x040200 -- 0x0402F8 */ + u64 data127_64[32]; /* 0x040300 -- 0x0403F8 */ + u64 parity[32]; /* 0x040400 -- 0x0404F8 */ } ce_dre_maint_ds_head_q; - uint64_t ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */ + u64 ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */ /* DRE Downstream Data Queue */ struct ce_dre_maint_ds_data_queue { - uint64_t data63_0[256]; /* 0x041000 -- 0x0417F8 */ - uint64_t ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */ - uint64_t data127_64[256]; /* 0x042000 -- 0x0427F8 */ - uint64_t ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */ - uint64_t parity[256]; /* 0x043000 -- 0x0437F8 */ - uint64_t ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */ + u64 data63_0[256]; /* 0x041000 -- 0x0417F8 */ + u64 ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */ + u64 data127_64[256]; /* 0x042000 -- 0x0427F8 */ + u64 ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */ + u64 parity[256]; /* 0x043000 -- 0x0437F8 */ + u64 ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */ } ce_dre_maint_ds_data_q; /* DRE URE Upstream Response Queue */ struct ce_dre_maint_ure_us_rsp_queue { - uint64_t data63_0[8]; /* 0x044000 -- 0x044038 */ - uint64_t ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */ - uint64_t data127_64[8]; /* 0x044100 -- 0x044138 */ - uint64_t ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */ - uint64_t parity[8]; /* 0x044200 -- 0x044238 */ - uint64_t ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */ + u64 data63_0[8]; /* 0x044000 -- 0x044038 */ + u64 ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */ + u64 data127_64[8]; /* 0x044100 -- 0x044138 */ + u64 ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */ + u64 parity[8]; /* 0x044200 -- 0x044238 */ + u64 ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */ } ce_dre_maint_ure_us_rsp_q; - uint64_t ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */ + u64 ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */ - uint64_t ce_end_of_struct; /* 0x044400 */ + u64 ce_end_of_struct; /* 0x044400 */ } tioce_t; @@ -625,11 +625,11 @@ typedef volatile struct tioce { #define CE_URE_BUS_MASK (0xFFULL << BUS_SRC_ID_SHFT) #define CE_URE_DEV_MASK (0x1FULL << DEV_SRC_ID_SHFT) #define CE_URE_FNC_MASK (0x07ULL << FNC_SRC_ID_SHFT) -#define CE_URE_PIPE_BUS(b) (((uint64_t)(b) << BUS_SRC_ID_SHFT) & \ +#define CE_URE_PIPE_BUS(b) (((u64)(b) << BUS_SRC_ID_SHFT) & \ CE_URE_BUS_MASK) -#define CE_URE_PIPE_DEV(d) (((uint64_t)(d) << DEV_SRC_ID_SHFT) & \ +#define CE_URE_PIPE_DEV(d) (((u64)(d) << DEV_SRC_ID_SHFT) & \ CE_URE_DEV_MASK) -#define CE_URE_PIPE_FNC(f) (((uint64_t)(f) << FNC_SRC_ID_SHFT) & \ +#define CE_URE_PIPE_FNC(f) (((u64)(f) << FNC_SRC_ID_SHFT) & \ CE_URE_FNC_MASK) #define CE_URE_SEL1_SHFT 0 @@ -660,9 +660,9 @@ typedef volatile struct tioce { #define CE_URE_PN1_MASK (0xFFULL << CE_URE_PN1_SHFT) #define CE_URE_PN2_SHFT 24 #define CE_URE_PN2_MASK (0xFFULL << CE_URE_PN2_SHFT) -#define CE_URE_PN1_SET(n) (((uint64_t)(n) << CE_URE_PN1_SHFT) & \ +#define CE_URE_PN1_SET(n) (((u64)(n) << CE_URE_PN1_SHFT) & \ CE_URE_PN1_MASK) -#define CE_URE_PN2_SET(n) (((uint64_t)(n) << CE_URE_PN2_SHFT) & \ +#define CE_URE_PN2_SET(n) (((u64)(n) << CE_URE_PN2_SHFT) & \ CE_URE_PN2_MASK) /* ce_ure_pcie_control2 register bit masks & shifts */ @@ -681,9 +681,9 @@ typedef volatile struct tioce { #define CE_URE_PSN1_MASK (0x1FFFULL << CE_URE_PSN1_SHFT) #define CE_URE_PSN2_SHFT 32 #define CE_URE_PSN2_MASK (0x1FFFULL << CE_URE_PSN2_SHFT) -#define CE_URE_PSN1_SET(n) (((uint64_t)(n) << CE_URE_PSN1_SHFT) & \ +#define CE_URE_PSN1_SET(n) (((u64)(n) << CE_URE_PSN1_SHFT) & \ CE_URE_PSN1_MASK) -#define CE_URE_PSN2_SET(n) (((uint64_t)(n) << CE_URE_PSN2_SHFT) & \ +#define CE_URE_PSN2_SET(n) (((u64)(n) << CE_URE_PSN2_SHFT) & \ CE_URE_PSN2_MASK) /* diff --git a/include/asm-ia64/sn/tioce_provider.h b/include/asm-ia64/sn/tioce_provider.h index cb414908671d..6d62b13f7ae7 100644 --- a/include/asm-ia64/sn/tioce_provider.h +++ b/include/asm-ia64/sn/tioce_provider.h @@ -21,9 +21,9 @@ struct tioce_common { struct pcibus_bussoft ce_pcibus; /* common pciio header */ - uint32_t ce_rev; - uint64_t ce_kernel_private; - uint64_t ce_prom_private; + u32 ce_rev; + u64 ce_kernel_private; + u64 ce_prom_private; }; struct tioce_kernel { @@ -31,31 +31,31 @@ struct tioce_kernel { spinlock_t ce_lock; struct list_head ce_dmamap_list; - uint64_t ce_ate40_shadow[TIOCE_NUM_M40_ATES]; - uint64_t ce_ate3240_shadow[TIOCE_NUM_M3240_ATES]; - uint32_t ce_ate3240_pagesize; + u64 ce_ate40_shadow[TIOCE_NUM_M40_ATES]; + u64 ce_ate3240_shadow[TIOCE_NUM_M3240_ATES]; + u32 ce_ate3240_pagesize; - uint8_t ce_port1_secondary; + u8 ce_port1_secondary; /* per-port resources */ struct { int dirmap_refcnt; - uint64_t dirmap_shadow; + u64 dirmap_shadow; } ce_port[TIOCE_NUM_PORTS]; }; struct tioce_dmamap { struct list_head ce_dmamap_list; /* headed by tioce_kernel */ - uint32_t refcnt; + u32 refcnt; - uint64_t nbytes; /* # bytes mapped */ + u64 nbytes; /* # bytes mapped */ - uint64_t ct_start; /* coretalk start address */ - uint64_t pci_start; /* bus start address */ + u64 ct_start; /* coretalk start address */ + u64 pci_start; /* bus start address */ - uint64_t *ate_hw; /* hw ptr of first ate in map */ - uint64_t *ate_shadow; /* shadow ptr of firat ate */ - uint16_t ate_count; /* # ate's in the map */ + u64 *ate_hw; /* hw ptr of first ate in map */ + u64 *ate_shadow; /* shadow ptr of firat ate */ + u16 ate_count; /* # ate's in the map */ }; extern int tioce_init_provider(void); diff --git a/include/asm-ia64/sn/tiocp.h b/include/asm-ia64/sn/tiocp.h index 5f2489c9d2dd..f47c08ab483c 100644 --- a/include/asm-ia64/sn/tiocp.h +++ b/include/asm-ia64/sn/tiocp.h @@ -21,189 +21,189 @@ struct tiocp{ /* 0x000000-0x00FFFF -- Local Registers */ /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */ - uint64_t cp_id; /* 0x000000 */ - uint64_t cp_stat; /* 0x000008 */ - uint64_t cp_err_upper; /* 0x000010 */ - uint64_t cp_err_lower; /* 0x000018 */ + u64 cp_id; /* 0x000000 */ + u64 cp_stat; /* 0x000008 */ + u64 cp_err_upper; /* 0x000010 */ + u64 cp_err_lower; /* 0x000018 */ #define cp_err cp_err_lower - uint64_t cp_control; /* 0x000020 */ - uint64_t cp_req_timeout; /* 0x000028 */ - uint64_t cp_intr_upper; /* 0x000030 */ - uint64_t cp_intr_lower; /* 0x000038 */ + u64 cp_control; /* 0x000020 */ + u64 cp_req_timeout; /* 0x000028 */ + u64 cp_intr_upper; /* 0x000030 */ + u64 cp_intr_lower; /* 0x000038 */ #define cp_intr cp_intr_lower - uint64_t cp_err_cmdword; /* 0x000040 */ - uint64_t _pad_000048; /* 0x000048 */ - uint64_t cp_tflush; /* 0x000050 */ + u64 cp_err_cmdword; /* 0x000040 */ + u64 _pad_000048; /* 0x000048 */ + u64 cp_tflush; /* 0x000050 */ /* 0x000058-0x00007F -- Bridge-specific Configuration */ - uint64_t cp_aux_err; /* 0x000058 */ - uint64_t cp_resp_upper; /* 0x000060 */ - uint64_t cp_resp_lower; /* 0x000068 */ + u64 cp_aux_err; /* 0x000058 */ + u64 cp_resp_upper; /* 0x000060 */ + u64 cp_resp_lower; /* 0x000068 */ #define cp_resp cp_resp_lower - uint64_t cp_tst_pin_ctrl; /* 0x000070 */ - uint64_t cp_addr_lkerr; /* 0x000078 */ + u64 cp_tst_pin_ctrl; /* 0x000070 */ + u64 cp_addr_lkerr; /* 0x000078 */ /* 0x000080-0x00008F -- PMU & MAP */ - uint64_t cp_dir_map; /* 0x000080 */ - uint64_t _pad_000088; /* 0x000088 */ + u64 cp_dir_map; /* 0x000080 */ + u64 _pad_000088; /* 0x000088 */ /* 0x000090-0x00009F -- SSRAM */ - uint64_t cp_map_fault; /* 0x000090 */ - uint64_t _pad_000098; /* 0x000098 */ + u64 cp_map_fault; /* 0x000090 */ + u64 _pad_000098; /* 0x000098 */ /* 0x0000A0-0x0000AF -- Arbitration */ - uint64_t cp_arb; /* 0x0000A0 */ - uint64_t _pad_0000A8; /* 0x0000A8 */ + u64 cp_arb; /* 0x0000A0 */ + u64 _pad_0000A8; /* 0x0000A8 */ /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */ - uint64_t cp_ate_parity_err; /* 0x0000B0 */ - uint64_t _pad_0000B8; /* 0x0000B8 */ + u64 cp_ate_parity_err; /* 0x0000B0 */ + u64 _pad_0000B8; /* 0x0000B8 */ /* 0x0000C0-0x0000FF -- PCI/GIO */ - uint64_t cp_bus_timeout; /* 0x0000C0 */ - uint64_t cp_pci_cfg; /* 0x0000C8 */ - uint64_t cp_pci_err_upper; /* 0x0000D0 */ - uint64_t cp_pci_err_lower; /* 0x0000D8 */ + u64 cp_bus_timeout; /* 0x0000C0 */ + u64 cp_pci_cfg; /* 0x0000C8 */ + u64 cp_pci_err_upper; /* 0x0000D0 */ + u64 cp_pci_err_lower; /* 0x0000D8 */ #define cp_pci_err cp_pci_err_lower - uint64_t _pad_0000E0[4]; /* 0x0000{E0..F8} */ + u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */ /* 0x000100-0x0001FF -- Interrupt */ - uint64_t cp_int_status; /* 0x000100 */ - uint64_t cp_int_enable; /* 0x000108 */ - uint64_t cp_int_rst_stat; /* 0x000110 */ - uint64_t cp_int_mode; /* 0x000118 */ - uint64_t cp_int_device; /* 0x000120 */ - uint64_t cp_int_host_err; /* 0x000128 */ - uint64_t cp_int_addr[8]; /* 0x0001{30,,,68} */ - uint64_t cp_err_int_view; /* 0x000170 */ - uint64_t cp_mult_int; /* 0x000178 */ - uint64_t cp_force_always[8]; /* 0x0001{80,,,B8} */ - uint64_t cp_force_pin[8]; /* 0x0001{C0,,,F8} */ + u64 cp_int_status; /* 0x000100 */ + u64 cp_int_enable; /* 0x000108 */ + u64 cp_int_rst_stat; /* 0x000110 */ + u64 cp_int_mode; /* 0x000118 */ + u64 cp_int_device; /* 0x000120 */ + u64 cp_int_host_err; /* 0x000128 */ + u64 cp_int_addr[8]; /* 0x0001{30,,,68} */ + u64 cp_err_int_view; /* 0x000170 */ + u64 cp_mult_int; /* 0x000178 */ + u64 cp_force_always[8]; /* 0x0001{80,,,B8} */ + u64 cp_force_pin[8]; /* 0x0001{C0,,,F8} */ /* 0x000200-0x000298 -- Device */ - uint64_t cp_device[4]; /* 0x0002{00,,,18} */ - uint64_t _pad_000220[4]; /* 0x0002{20,,,38} */ - uint64_t cp_wr_req_buf[4]; /* 0x0002{40,,,58} */ - uint64_t _pad_000260[4]; /* 0x0002{60,,,78} */ - uint64_t cp_rrb_map[2]; /* 0x0002{80,,,88} */ + u64 cp_device[4]; /* 0x0002{00,,,18} */ + u64 _pad_000220[4]; /* 0x0002{20,,,38} */ + u64 cp_wr_req_buf[4]; /* 0x0002{40,,,58} */ + u64 _pad_000260[4]; /* 0x0002{60,,,78} */ + u64 cp_rrb_map[2]; /* 0x0002{80,,,88} */ #define cp_even_resp cp_rrb_map[0] /* 0x000280 */ #define cp_odd_resp cp_rrb_map[1] /* 0x000288 */ - uint64_t cp_resp_status; /* 0x000290 */ - uint64_t cp_resp_clear; /* 0x000298 */ + u64 cp_resp_status; /* 0x000290 */ + u64 cp_resp_clear; /* 0x000298 */ - uint64_t _pad_0002A0[12]; /* 0x0002{A0..F8} */ + u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */ /* 0x000300-0x0003F8 -- Buffer Address Match Registers */ struct { - uint64_t upper; /* 0x0003{00,,,F0} */ - uint64_t lower; /* 0x0003{08,,,F8} */ + u64 upper; /* 0x0003{00,,,F0} */ + u64 lower; /* 0x0003{08,,,F8} */ } cp_buf_addr_match[16]; /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */ struct { - uint64_t flush_w_touch; /* 0x000{400,,,5C0} */ - uint64_t flush_wo_touch; /* 0x000{408,,,5C8} */ - uint64_t inflight; /* 0x000{410,,,5D0} */ - uint64_t prefetch; /* 0x000{418,,,5D8} */ - uint64_t total_pci_retry; /* 0x000{420,,,5E0} */ - uint64_t max_pci_retry; /* 0x000{428,,,5E8} */ - uint64_t max_latency; /* 0x000{430,,,5F0} */ - uint64_t clear_all; /* 0x000{438,,,5F8} */ + u64 flush_w_touch; /* 0x000{400,,,5C0} */ + u64 flush_wo_touch; /* 0x000{408,,,5C8} */ + u64 inflight; /* 0x000{410,,,5D0} */ + u64 prefetch; /* 0x000{418,,,5D8} */ + u64 total_pci_retry; /* 0x000{420,,,5E0} */ + u64 max_pci_retry; /* 0x000{428,,,5E8} */ + u64 max_latency; /* 0x000{430,,,5F0} */ + u64 clear_all; /* 0x000{438,,,5F8} */ } cp_buf_count[8]; /* 0x000600-0x0009FF -- PCI/X registers */ - uint64_t cp_pcix_bus_err_addr; /* 0x000600 */ - uint64_t cp_pcix_bus_err_attr; /* 0x000608 */ - uint64_t cp_pcix_bus_err_data; /* 0x000610 */ - uint64_t cp_pcix_pio_split_addr; /* 0x000618 */ - uint64_t cp_pcix_pio_split_attr; /* 0x000620 */ - uint64_t cp_pcix_dma_req_err_attr; /* 0x000628 */ - uint64_t cp_pcix_dma_req_err_addr; /* 0x000630 */ - uint64_t cp_pcix_timeout; /* 0x000638 */ + u64 cp_pcix_bus_err_addr; /* 0x000600 */ + u64 cp_pcix_bus_err_attr; /* 0x000608 */ + u64 cp_pcix_bus_err_data; /* 0x000610 */ + u64 cp_pcix_pio_split_addr; /* 0x000618 */ + u64 cp_pcix_pio_split_attr; /* 0x000620 */ + u64 cp_pcix_dma_req_err_attr; /* 0x000628 */ + u64 cp_pcix_dma_req_err_addr; /* 0x000630 */ + u64 cp_pcix_timeout; /* 0x000638 */ - uint64_t _pad_000640[24]; /* 0x000{640,,,6F8} */ + u64 _pad_000640[24]; /* 0x000{640,,,6F8} */ /* 0x000700-0x000737 -- Debug Registers */ - uint64_t cp_ct_debug_ctl; /* 0x000700 */ - uint64_t cp_br_debug_ctl; /* 0x000708 */ - uint64_t cp_mux3_debug_ctl; /* 0x000710 */ - uint64_t cp_mux4_debug_ctl; /* 0x000718 */ - uint64_t cp_mux5_debug_ctl; /* 0x000720 */ - uint64_t cp_mux6_debug_ctl; /* 0x000728 */ - uint64_t cp_mux7_debug_ctl; /* 0x000730 */ + u64 cp_ct_debug_ctl; /* 0x000700 */ + u64 cp_br_debug_ctl; /* 0x000708 */ + u64 cp_mux3_debug_ctl; /* 0x000710 */ + u64 cp_mux4_debug_ctl; /* 0x000718 */ + u64 cp_mux5_debug_ctl; /* 0x000720 */ + u64 cp_mux6_debug_ctl; /* 0x000728 */ + u64 cp_mux7_debug_ctl; /* 0x000730 */ - uint64_t _pad_000738[89]; /* 0x000{738,,,9F8} */ + u64 _pad_000738[89]; /* 0x000{738,,,9F8} */ /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */ struct { - uint64_t cp_buf_addr; /* 0x000{A00,,,AF0} */ - uint64_t cp_buf_attr; /* 0X000{A08,,,AF8} */ + u64 cp_buf_addr; /* 0x000{A00,,,AF0} */ + u64 cp_buf_attr; /* 0X000{A08,,,AF8} */ } cp_pcix_read_buf_64[16]; struct { - uint64_t cp_buf_addr; /* 0x000{B00,,,BE0} */ - uint64_t cp_buf_attr; /* 0x000{B08,,,BE8} */ - uint64_t cp_buf_valid; /* 0x000{B10,,,BF0} */ - uint64_t __pad1; /* 0x000{B18,,,BF8} */ + u64 cp_buf_addr; /* 0x000{B00,,,BE0} */ + u64 cp_buf_attr; /* 0x000{B08,,,BE8} */ + u64 cp_buf_valid; /* 0x000{B10,,,BF0} */ + u64 __pad1; /* 0x000{B18,,,BF8} */ } cp_pcix_write_buf_64[8]; /* End of Local Registers -- Start of Address Map space */ - char _pad_000c00[0x010000 - 0x000c00]; + char _pad_000c00[0x010000 - 0x000c00]; /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */ - uint64_t cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */ + u64 cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */ - char _pad_012000[0x14000 - 0x012000]; + char _pad_012000[0x14000 - 0x012000]; /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */ - uint64_t cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */ + u64 cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */ - char _pad_016000[0x18000 - 0x016000]; + char _pad_016000[0x18000 - 0x016000]; /* 0x18000-0x197F8 -- TIOCP Write Request Ram */ - uint64_t cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */ - uint64_t cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */ - uint64_t cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */ + u64 cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */ + u64 cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */ + u64 cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */ - char _pad_019800[0x1C000 - 0x019800]; + char _pad_019800[0x1C000 - 0x019800]; /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */ - uint64_t cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */ - uint64_t cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */ - uint64_t cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */ + u64 cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */ + u64 cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */ + u64 cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */ - char _pad_01F000[0x20000 - 0x01F000]; + char _pad_01F000[0x20000 - 0x01F000]; /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */ - char _pad_020000[0x021000 - 0x20000]; + char _pad_020000[0x021000 - 0x20000]; /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */ union { - uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ - uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ - uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ - uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ + u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ + u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ + u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ + u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ union { - uint8_t c[0x100 / 1]; - uint16_t s[0x100 / 2]; - uint32_t l[0x100 / 4]; - uint64_t d[0x100 / 8]; + u8 c[0x100 / 1]; + u16 s[0x100 / 2]; + u32 l[0x100 / 4]; + u64 d[0x100 / 8]; } f[8]; } cp_type0_cfg_dev[7]; /* 0x02{1000,,,7FFF} */ /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */ union { - uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */ - uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */ - uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */ - uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */ + u8 c[0x1000 / 1]; /* 0x028000-0x029000 */ + u16 s[0x1000 / 2]; /* 0x028000-0x029000 */ + u32 l[0x1000 / 4]; /* 0x028000-0x029000 */ + u64 d[0x1000 / 8]; /* 0x028000-0x029000 */ union { - uint8_t c[0x100 / 1]; - uint16_t s[0x100 / 2]; - uint32_t l[0x100 / 4]; - uint64_t d[0x100 / 8]; + u8 c[0x100 / 1]; + u16 s[0x100 / 2]; + u32 l[0x100 / 4]; + u64 d[0x100 / 8]; } f[8]; } cp_type1_cfg; /* 0x028000-0x029000 */ @@ -211,30 +211,30 @@ struct tiocp{ /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */ union { - uint8_t c[8 / 1]; - uint16_t s[8 / 2]; - uint32_t l[8 / 4]; - uint64_t d[8 / 8]; + u8 c[8 / 1]; + u16 s[8 / 2]; + u32 l[8 / 4]; + u64 d[8 / 8]; } cp_pci_iack; /* 0x030000-0x030007 */ char _pad_030007[0x040000-0x030008]; /* 0x040000-0x040007 -- PCIX Special Cycle */ union { - uint8_t c[8 / 1]; - uint16_t s[8 / 2]; - uint32_t l[8 / 4]; - uint64_t d[8 / 8]; + u8 c[8 / 1]; + u16 s[8 / 2]; + u32 l[8 / 4]; + u64 d[8 / 8]; } cp_pcix_cycle; /* 0x040000-0x040007 */ char _pad_040007[0x200000-0x040008]; /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */ union { - uint8_t c[0x100000 / 1]; - uint16_t s[0x100000 / 2]; - uint32_t l[0x100000 / 4]; - uint64_t d[0x100000 / 8]; + u8 c[0x100000 / 1]; + u16 s[0x100000 / 2]; + u32 l[0x100000 / 4]; + u64 d[0x100000 / 8]; } cp_devio_raw[6]; /* 0x200000-0x7FFFFF */ #define cp_devio(n) cp_devio_raw[((n)<2)?(n*2):(n+2)] @@ -243,10 +243,10 @@ struct tiocp{ /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush */ union { - uint8_t c[0x100000 / 1]; - uint16_t s[0x100000 / 2]; - uint32_t l[0x100000 / 4]; - uint64_t d[0x100000 / 8]; + u8 c[0x100000 / 1]; + u16 s[0x100000 / 2]; + u32 l[0x100000 / 4]; + u64 d[0x100000 / 8]; } cp_devio_raw_flush[6]; /* 0xA00000-0xBFFFFF */ #define cp_devio_flush(n) cp_devio_raw_flush[((n)<2)?(n*2):(n+2)] diff --git a/include/asm-ia64/sn/tiocx.h b/include/asm-ia64/sn/tiocx.h index 5699e75e5024..d29728492f36 100644 --- a/include/asm-ia64/sn/tiocx.h +++ b/include/asm-ia64/sn/tiocx.h @@ -40,10 +40,10 @@ struct cx_drv { }; /* create DMA address by stripping AS bits */ -#define TIOCX_DMA_ADDR(a) (uint64_t)((uint64_t)(a) & 0xffffcfffffffffUL) +#define TIOCX_DMA_ADDR(a) (u64)((u64)(a) & 0xffffcfffffffffUL) -#define TIOCX_TO_TIOCX_DMA_ADDR(a) (uint64_t)(((uint64_t)(a) & 0xfffffffff) | \ - ((((uint64_t)(a)) & 0xffffc000000000UL) <<2)) +#define TIOCX_TO_TIOCX_DMA_ADDR(a) (u64)(((u64)(a) & 0xfffffffff) | \ + ((((u64)(a)) & 0xffffc000000000UL) <<2)) #define TIO_CE_ASIC_PARTNUM 0xce00 #define TIOCX_CORELET 3 @@ -63,10 +63,10 @@ extern int cx_device_unregister(struct cx_dev *); extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int); extern int cx_driver_unregister(struct cx_drv *); extern int cx_driver_register(struct cx_drv *); -extern uint64_t tiocx_dma_addr(uint64_t addr); -extern uint64_t tiocx_swin_base(int nasid); -extern void tiocx_mmr_store(int nasid, uint64_t offset, uint64_t value); -extern uint64_t tiocx_mmr_load(int nasid, uint64_t offset); +extern u64 tiocx_dma_addr(u64 addr); +extern u64 tiocx_swin_base(int nasid); +extern void tiocx_mmr_store(int nasid, u64 offset, u64 value); +extern u64 tiocx_mmr_load(int nasid, u64 offset); #endif // __KERNEL__ #endif // _ASM_IA64_SN_TIO_TIOCX__ |
