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| author | Kyle Moffett <Kyle.D.Moffett@boeing.com> | 2011-12-22 10:19:11 +0000 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2012-02-23 10:49:59 +1100 |
| commit | 9ca163c8602681ad098910f48f89b97f0cb87c4f (patch) | |
| tree | e2aa87c28be3b1253273b1a1e609b5d0e9d6feb7 | |
| parent | 98cca250aecaf3f1b2fec003e1c0ce0bfaa4be36 (diff) | |
| download | blackbird-op-linux-9ca163c8602681ad098910f48f89b97f0cb87c4f.tar.gz blackbird-op-linux-9ca163c8602681ad098910f48f89b97f0cb87c4f.zip | |
fsl/mpic: Create and document the "single-cpu-affinity" device-tree flag
The Freescale MPIC (and perhaps others in the future) is incapable of
routing non-IPI interrupts to more than once CPU at a time. Currently
all of the Freescale boards msut pass the MPIC_SINGLE_DEST_CPU flag to
mpic_alloc(), but that information should really be present in the
device-tree.
Older board code can't rely on the device-tree having the property set,
but newer platforms won't need it manually specified in the code.
[BenH: Remove unrelated changes, folded in a different patch]
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| -rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/mpic.txt | 6 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi | 1 | ||||
| -rw-r--r-- | arch/powerpc/sysdev/mpic.c | 2 |
3 files changed, 9 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt index ebafba29fc5f..b393ccf1e9f3 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt @@ -64,6 +64,12 @@ PROPERTIES device-trees omit this property on MPIC nodes even when the MPIC is in fact big-endian, so certain boards override this property. + - single-cpu-affinity + Usage: optional + Value type: <empty> + If present the MPIC will be assumed to only be able to route + non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC). + INTERRUPT SPECIFIER DEFINITION Interrupt specifiers consists of 4 cells encoded as diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi index 47f2b676bc7d..658bd81982cb 100644 --- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi +++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi @@ -40,6 +40,7 @@ mpic: pic@40000 { compatible = "fsl,mpic"; device_type = "open-pic"; big-endian; + single-cpu-affinity; }; timer@41100 { diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 9deec44ede83..c297a524f761 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -1187,6 +1187,8 @@ struct mpic * __init mpic_alloc(struct device_node *node, flags |= MPIC_BIG_ENDIAN; if (of_get_property(node, "pic-no-reset", NULL)) flags |= MPIC_NO_RESET; + if (of_get_property(node, "single-cpu-affinity", NULL)) + flags |= MPIC_SINGLE_DEST_CPU; if (of_device_is_compatible(node, "fsl,mpic")) flags |= MPIC_FSL; |
