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| author | Linus Torvalds <torvalds@g5.osdl.org> | 2005-10-29 12:19:15 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-10-29 12:19:15 -0700 |
| commit | e9d52234e35b27ea4ea5f2ab64ca47b1a0c740ab (patch) | |
| tree | 318d37a7d55c79e6f7d86163fb28e0eccbb0fe83 | |
| parent | 955c5038823748e529a49f0e33ab635d92843500 (diff) | |
| parent | 09af7b443c257460d45cb6c1896d29f173fef35b (diff) | |
| download | blackbird-op-linux-e9d52234e35b27ea4ea5f2ab64ca47b1a0c740ab.tar.gz blackbird-op-linux-e9d52234e35b27ea4ea5f2ab64ca47b1a0c740ab.zip | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
522 files changed, 49209 insertions, 13775 deletions
diff --git a/Documentation/mips/AU1xxx_IDE.README b/Documentation/mips/AU1xxx_IDE.README new file mode 100644 index 000000000000..a7e4c4ea3560 --- /dev/null +++ b/Documentation/mips/AU1xxx_IDE.README @@ -0,0 +1,168 @@ +README for MIPS AU1XXX IDE driver - Released 2005-07-15 + +ABOUT +----- +This file describes the 'drivers/ide/mips/au1xxx-ide.c', related files and the +services they provide. + +If you are short in patience and just want to know how to add your hard disc to +the white or black list, go to the 'ADD NEW HARD DISC TO WHITE OR BLACK LIST' +section. + + +LICENSE +------- + +Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions + +This program is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free Software +Foundation; either version 2 of the License, or (at your option) any later +version. + +THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND +FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR +BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +You should have received a copy of the GNU General Public License along with +this program; if not, write to the Free Software Foundation, Inc., +675 Mass Ave, Cambridge, MA 02139, USA. + +Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE + Interface and Linux Device Driver" Application Note. + + +FILES, CONFIGS AND COMPATABILITY +-------------------------------- + +Two files are introduced: + + a) 'include/asm-mips/mach-au1x00/au1xxx_ide.h' + containes : struct _auide_hwif + struct drive_list_entry dma_white_list + struct drive_list_entry dma_black_list + timing parameters for PIO mode 0/1/2/3/4 + timing parameters for MWDMA 0/1/2 + + b) 'drivers/ide/mips/au1xxx-ide.c' + contains the functionality of the AU1XXX IDE driver + +Four configs variables are introduced: + + CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA - enable the PIO+DBDMA mode + CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA - enable the MWDMA mode + CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON - set Burstable FIFO in DBDMA + controler + CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ - maximum transfer size + per descriptor + +If MWDMA is enabled and the connected hard disc is not on the white list, the +kernel switches to a "safe mwdma mode" at boot time. In this mode the IDE +performance is substantial slower then in full speed mwdma. In this case +please add your hard disc to the white list (follow instruction from 'ADD NEW +HARD DISC TO WHITE OR BLACK LIST' section). + + +SUPPORTED IDE MODES +------------------- + +The AU1XXX IDE driver supported all PIO modes - PIO mode 0/1/2/3/4 - and all +MWDMA modes - MWDMA 0/1/2 -. There is no support for SWDMA and UDMA mode. + +To change the PIO mode use the program hdparm with option -p, e.g. +'hdparm -p0 [device]' for PIO mode 0. To enable the MWDMA mode use the option +-X, e.g. 'hdparm -X32 [device]' for MWDMA mode 0. + + +PERFORMANCE CONFIGURATIONS +-------------------------- + +If the used system doesn't need USB support enable the following kernel configs: + +CONFIG_IDE=y +CONFIG_BLK_DEV_IDE=y +CONFIG_IDE_GENERIC=y +CONFIG_BLK_DEV_IDEPCI=y +CONFIG_BLK_DEV_GENERIC=y +CONFIG_BLK_DEV_IDEDMA_PCI=y +CONFIG_IDEDMA_PCI_AUTO=y +CONFIG_BLK_DEV_IDE_AU1XXX=y +CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y +CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON=y +CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128 +CONFIG_BLK_DEV_IDEDMA=y +CONFIG_IDEDMA_AUTO=y + +If the used system need the USB support enable the following kernel configs for +high IDE to USB throughput. + +CONFIG_BLK_DEV_IDEDISK=y +CONFIG_IDE_GENERIC=y +CONFIG_BLK_DEV_IDEPCI=y +CONFIG_BLK_DEV_GENERIC=y +CONFIG_BLK_DEV_IDEDMA_PCI=y +CONFIG_IDEDMA_PCI_AUTO=y +CONFIG_BLK_DEV_IDE_AU1XXX=y +CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y +CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128 +CONFIG_BLK_DEV_IDEDMA=y +CONFIG_IDEDMA_AUTO=y + + +ADD NEW HARD DISC TO WHITE OR BLACK LIST +---------------------------------------- + +Step 1 : detect the model name of your hard disc + + a) connect your hard disc to the AU1XXX + + b) boot your kernel and get the hard disc model. + + Example boot log: + + --snipped-- + Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 + ide: Assuming 50MHz system bus speed for PIO modes; override with idebus=xx + Au1xxx IDE(builtin) configured for MWDMA2 + Probing IDE interface ide0... + hda: Maxtor 6E040L0, ATA DISK drive + ide0 at 0xac800000-0xac800007,0xac8001c0 on irq 64 + hda: max request size: 64KiB + hda: 80293248 sectors (41110 MB) w/2048KiB Cache, CHS=65535/16/63, (U)DMA + --snipped-- + + In this example 'Maxtor 6E040L0'. + +Step 2 : edit 'include/asm-mips/mach-au1x00/au1xxx_ide.h' + + Add your hard disc to the dma_white_list or dma_black_list structur. + +Step 3 : Recompile the kernel + + Enable MWDMA support in the kernel configuration. Recompile the kernel and + reboot. + +Step 4 : Tests + + If you have add a hard disc to the white list, please run some stress tests + for verification. + + +ACKNOWLEDGMENTS +--------------- + +These drivers wouldn't have been done without the base of kernel 2.4.x AU1XXX +IDE driver from AMD. + +Additional input also from: +Matthias Lenk <matthias.lenk@amd.com> + +Happy hacking! +Enrico Walther <enrico.walther@amd.com> diff --git a/MAINTAINERS b/MAINTAINERS index 251a28e2d4cc..e88d193d42f8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1643,7 +1643,7 @@ S: Maintained MIPS P: Ralf Baechle M: ralf@linux-mips.org -W: http://oss.sgi.com/mips/mips-howto.html +W: http://www.linux-mips.org/ L: linux-mips@linux-mips.org S: Maintained diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 4cd724c05700..0097a0d53b3b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -4,216 +4,147 @@ config MIPS # Horrible source of confusion. Die, die, die ... select EMBEDDED -# shouldn't it be per-subarchitecture? -config ARCH_MAY_HAVE_PC_FDC - bool - default y - mainmenu "Linux/MIPS Kernel Configuration" source "init/Kconfig" -config SYS_SUPPORTS_32BIT_KERNEL - bool -config SYS_SUPPORTS_64BIT_KERNEL - bool -config CPU_SUPPORTS_32BIT_KERNEL - bool -config CPU_SUPPORTS_64BIT_KERNEL - bool - -menu "Kernel type" - -choice - - prompt "Kernel code model" - help - You should only select this option if you have a workload that - actually benefits from 64-bit processing or if your machine has - large memory. You will only be presented a single option in this - menu if your system does not support both 32-bit and 64-bit kernels. - -config 32BIT - bool "32-bit kernel" - depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL - select TRAD_SIGNALS - help - Select this option if you want to build a 32-bit kernel. - -config 64BIT - bool "64-bit kernel" - depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL - help - Select this option if you want to build a 64-bit kernel. - -endchoice - -endmenu - menu "Machine selection" -config MACH_JAZZ - bool "Support for the Jazz family of machines" - select ARC - select ARC32 - select GENERIC_ISA_DMA - select I8259 - select ISA - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - help - This a family of machines based on the MIPS R4030 chipset which was - used by several vendors to build RISC/os and Windows NT workstations. - Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and - Olivetti M700-10 workstations. +choice + prompt "System type" + default SGI_IP22 -config ACER_PICA_61 - bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)" - depends on MACH_JAZZ && EXPERIMENTAL +config MIPS_MTX1 + bool "Support for 4G Systems MTX-1 board" select DMA_NONCOHERENT - help - This is a machine with a R4400 133/150 MHz CPU. To compile a Linux - kernel that runs on these, say Y here. For details about Linux on - the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at - <http://www.linux-mips.org/>. + select HW_HAS_PCI + select SOC_AU1500 + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_LITTLE_ENDIAN -config MIPS_MAGNUM_4000 - bool "Support for MIPS Magnum 4000" - depends on MACH_JAZZ +config MIPS_BOSPORUS + bool "AMD Alchemy Bosporus board" + select SOC_AU1500 select DMA_NONCOHERENT - help - This is a machine with a R4000 100 MHz CPU. To compile a Linux - kernel that runs on these, say Y here. For details about Linux on - the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at - <http://www.linux-mips.org/>. + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_LITTLE_ENDIAN -config OLIVETTI_M700 - bool "Support for Olivetti M700-10" - depends on MACH_JAZZ +config MIPS_PB1000 + bool "AMD Alchemy PB1000 board" + select SOC_AU1000 select DMA_NONCOHERENT - help - This is a machine with a R4000 100 MHz CPU. To compile a Linux - kernel that runs on these, say Y here. For details about Linux on - the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at - <http://www.linux-mips.org/>. - -config MACH_VR41XX - bool "Support for NEC VR4100 series based machines" - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select HW_HAS_PCI + select SWAP_IO_SPACE + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_LITTLE_ENDIAN -config NEC_CMBVR4133 - bool "Support for NEC CMB-VR4133" - depends on MACH_VR41XX - select CPU_VR41XX +config MIPS_PB1100 + bool "AMD Alchemy PB1100 board" + select SOC_AU1100 select DMA_NONCOHERENT - select IRQ_CPU select HW_HAS_PCI + select SWAP_IO_SPACE + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_LITTLE_ENDIAN -config ROCKHOPPER - bool "Support for Rockhopper baseboard" - depends on NEC_CMBVR4133 - select I8259 - select HAVE_STD_PC_SERIAL_PORT +config MIPS_PB1500 + bool "AMD Alchemy PB1500 board" + select SOC_AU1500 + select DMA_NONCOHERENT + select HW_HAS_PCI + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_LITTLE_ENDIAN -config CASIO_E55 - bool "Support for CASIO CASSIOPEIA E-10/15/55/65" - depends on MACH_VR41XX - select CPU_LITTLE_ENDIAN +config MIPS_PB1550 + bool "AMD Alchemy PB1550 board" + select SOC_AU1550 select DMA_NONCOHERENT - select IRQ_CPU - select ISA + select HW_HAS_PCI + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_LITTLE_ENDIAN -config IBM_WORKPAD - bool "Support for IBM WorkPad z50" - depends on MACH_VR41XX - select CPU_LITTLE_ENDIAN +config MIPS_PB1200 + bool "AMD Alchemy PB1200 board" + select SOC_AU1200 select DMA_NONCOHERENT - select IRQ_CPU - select ISA + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_LITTLE_ENDIAN -config TANBAC_TB022X - bool "Support for TANBAC VR4131 multichip module and TANBAC VR4131DIMM" - depends on MACH_VR41XX - select CPU_LITTLE_ENDIAN +config MIPS_DB1000 + bool "AMD Alchemy DB1000 board" + select SOC_AU1000 select DMA_NONCOHERENT - select IRQ_CPU select HW_HAS_PCI - help - The TANBAC VR4131 multichip module(TB0225) and - the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms - manufactured by TANBAC. - Please refer to <http://www.tanbac.co.jp/> - about VR4131 multichip module and VR4131DIMM. + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_LITTLE_ENDIAN -config TANBAC_TB0226 - bool "Support for TANBAC Mbase(TB0226)" - depends on TANBAC_TB022X - select GPIO_VR41XX - help - The TANBAC Mbase(TB0226) is a MIPS-based platform manufactured by TANBAC. - Please refer to <http://www.tanbac.co.jp/> about Mbase. - -config TANBAC_TB0287 - bool "Support for TANBAC Mini-ITX DIMM base(TB0287)" - depends on TANBAC_TB022X - help - The TANBAC Mini-ITX DIMM base(TB0287) is a MIPS-based platform manufactured by TANBAC. - Please refer to <http://www.tanbac.co.jp/> about Mini-ITX DIMM base. - -config VICTOR_MPC30X - bool "Support for Victor MP-C303/304" - depends on MACH_VR41XX - select CPU_LITTLE_ENDIAN +config MIPS_DB1100 + bool "AMD Alchemy DB1100 board" + select SOC_AU1100 select DMA_NONCOHERENT - select IRQ_CPU - select HW_HAS_PCI + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_LITTLE_ENDIAN -config ZAO_CAPCELLA - bool "Support for ZAO Networks Capcella" - depends on MACH_VR41XX - select CPU_LITTLE_ENDIAN +config MIPS_DB1500 + bool "AMD Alchemy DB1500 board" + select SOC_AU1500 select DMA_NONCOHERENT - select IRQ_CPU select HW_HAS_PCI + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN -config PCI_VR41XX - bool "Add PCI control unit support of NEC VR4100 series" - depends on MACH_VR41XX && HW_HAS_PCI - default y - select PCI +config MIPS_DB1550 + bool "AMD Alchemy DB1550 board" + select SOC_AU1550 + select HW_HAS_PCI + select DMA_NONCOHERENT + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_LITTLE_ENDIAN -config VRC4173 - tristate "Add NEC VRC4173 companion chip support" - depends on MACH_VR41XX && PCI_VR41XX - ---help--- - The NEC VRC4173 is a companion chip for NEC VR4122/VR4131. +config MIPS_DB1200 + bool "AMD Alchemy DB1200 board" + select SOC_AU1200 + select DMA_COHERENT + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_LITTLE_ENDIAN -config TOSHIBA_JMR3927 - bool "Support for Toshiba JMR-TX3927 board" +config MIPS_MIRAGE + bool "AMD Alchemy Mirage board" select DMA_NONCOHERENT - select HW_HAS_PCI - select SWAP_IO_SPACE - select SYS_SUPPORTS_32BIT_KERNEL + select SOC_AU1500 + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_LITTLE_ENDIAN config MIPS_COBALT bool "Support for Cobalt Server" - depends on EXPERIMENTAL select DMA_NONCOHERENT select HW_HAS_PCI select I8259 select IRQ_CPU + select MIPS_GT64111 + select SYS_HAS_CPU_NEVADA select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN config MACH_DECSTATION bool "Support for DECstations" select BOOT_ELF32 select DMA_NONCOHERENT + select EARLY_PRINTK select IRQ_CPU + select SYS_HAS_CPU_R3000 + select SYS_HAS_CPU_R4X00 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - ---help--- + select SYS_SUPPORTS_LITTLE_ENDIAN + help This enables support for DEC's MIPS based workstations. For details see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the DECstation porting pages on <http://decstation.unix-ag.org/>. @@ -234,8 +165,10 @@ config MIPS_EV64120 select DMA_NONCOHERENT select HW_HAS_PCI select MIPS_GT64120 + select SYS_HAS_CPU_R5000 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN help This is an evaluation board based on the Galileo GT-64120 single-chip system controller that contains a MIPS R5000 compatible @@ -243,10 +176,6 @@ config MIPS_EV64120 <http://www.marvell.com/>. Say Y here if you wish to build a kernel for this platform. -config EVB_PCI1 - bool "Enable Second PCI (PCI1)" - depends on MIPS_EV64120 - config MIPS_EV96100 bool "Support for Galileo EV96100 Evaluation board (EXPERIMENTAL)" depends on EXPERIMENTAL @@ -256,8 +185,11 @@ config MIPS_EV96100 select MIPS_GT96100 select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_HAS_CPU_R5000 + select SYS_HAS_CPU_RM7000 select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_BIG_ENDIAN help This is an evaluation board based on the Galileo GT-96100 LAN/WAN communications controllers containing a MIPS R5000 compatible core @@ -268,8 +200,11 @@ config MIPS_IVR bool "Support for Globespan IVR board" select DMA_NONCOHERENT select HW_HAS_PCI + select ITE_BOARD_GEN + select SYS_HAS_CPU_NEVADA select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN help This is an evaluation board built by Globespan to showcase thir iVR (Internet Video Recorder) design. It utilizes a QED RM5231 @@ -277,37 +212,16 @@ config MIPS_IVR located at <http://www.globespan.net/>. Say Y here if you wish to build a kernel for this platform. -config LASAT - bool "Support for LASAT Networks platforms" - select DMA_NONCOHERENT - select HW_HAS_PCI - select MIPS_GT64120 - select R5000_CPU_SCACHE - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - -config PICVUE - tristate "PICVUE LCD display driver" - depends on LASAT - -config PICVUE_PROC - tristate "PICVUE LCD display driver /proc interface" - depends on PICVUE - -config DS1603 - bool "DS1603 RTC driver" - depends on LASAT - -config LASAT_SYSCTL - bool "LASAT sysctl interface" - depends on LASAT - config MIPS_ITE8172 bool "Support for ITE 8172G board" select DMA_NONCOHERENT select HW_HAS_PCI + select ITE_BOARD_GEN + select SYS_HAS_CPU_R5432 + select SYS_HAS_CPU_NEVADA select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN help Ths is an evaluation board made by ITE <http://www.ite.com.tw/> with ATX form factor that utilizes a MIPS R5000 to work with its @@ -315,42 +229,86 @@ config MIPS_ITE8172 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build a kernel for this platform. -config IT8172_REVC - bool "Support for older IT8172 (Rev C)" - depends on MIPS_ITE8172 +config MACH_JAZZ + bool "Support for the Jazz family of machines" + select ARC + select ARC32 + select ARCH_MAY_HAVE_PC_FDC + select GENERIC_ISA_DMA + select I8259 + select ISA + select SYS_HAS_CPU_R4X00 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL help - Say Y here to support the older, Revision C version of the Integrated - Technology Express, Inc. ITE8172 SBC. Vendor page at - <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the - board at <http://www.mvista.com/partners/semiconductor/ite.html>. + This a family of machines based on the MIPS R4030 chipset which was + used by several vendors to build RISC/os and Windows NT workstations. + Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and + Olivetti M700-10 workstations. + +config LASAT + bool "Support for LASAT Networks platforms" + select DMA_NONCOHERENT + select HW_HAS_PCI + select MIPS_GT64120 + select MIPS_NILE4 + select R5000_CPU_SCACHE + select SYS_HAS_CPU_R5000 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN config MIPS_ATLAS bool "Support for MIPS Atlas board" select BOOT_ELF32 select DMA_NONCOHERENT + select IRQ_CPU select HW_HAS_PCI + select MIPS_BOARDS_GEN + select MIPS_BONITO64 select MIPS_GT64120 + select MIPS_MSC + select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_CPU_MIPS64_R1 + select SYS_HAS_CPU_NEVADA + select SYS_HAS_CPU_RM7000 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN help - This enables support for the QED R5231-based MIPS Atlas evaluation + This enables support for the MIPS Technologies Atlas evaluation board. config MIPS_MALTA bool "Support for MIPS Malta board" + select ARCH_MAY_HAVE_PC_FDC select BOOT_ELF32 select HAVE_STD_PC_SERIAL_PORT select DMA_NONCOHERENT + select IRQ_CPU select GENERIC_ISA_DMA select HW_HAS_PCI select I8259 + select MIPS_BOARDS_GEN + select MIPS_BONITO64 select MIPS_GT64120 + select MIPS_MSC select SWAP_IO_SPACE + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_CPU_MIPS64_R1 + select SYS_HAS_CPU_NEVADA + select SYS_HAS_CPU_RM7000 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN help - This enables support for the VR5000-based MIPS Malta evaluation + This enables support for the MIPS Technologies Malta evaluation board. config MIPS_SEAD @@ -358,50 +316,64 @@ config MIPS_SEAD depends on EXPERIMENTAL select IRQ_CPU select DMA_NONCOHERENT + select MIPS_BOARDS_GEN + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_CPU_MIPS64_R1 select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN + help + This enables support for the MIPS Technologies SEAD evaluation + board. -config MOMENCO_OCELOT - bool "Support for Momentum Ocelot board" +config MIPS_SIM + bool 'Support for MIPS simulator (MIPSsim)' select DMA_NONCOHERENT - select HW_HAS_PCI select IRQ_CPU - select IRQ_CPU_RM7K - select MIPS_GT64120 - select RM7000_CPU_SCACHE - select SWAP_IO_SPACE + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN help - The Ocelot is a MIPS-based Single Board Computer (SBC) made by - Momentum Computer <http://www.momenco.com/>. + This option enables support for MIPS Technologies MIPSsim software + emulator. -config MOMENCO_OCELOT_G - bool "Support for Momentum Ocelot-G board" +config MOMENCO_JAGUAR_ATX + bool "Support for Momentum Jaguar board" + select BOOT_ELF32 select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU select IRQ_CPU_RM7K + select IRQ_MV64340 + select LIMITED_DMA select PCI_MARVELL select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_HAS_CPU_RM9000 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN help - The Ocelot is a MIPS-based Single Board Computer (SBC) made by + The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by Momentum Computer <http://www.momenco.com/>. -config MOMENCO_OCELOT_C - bool "Support for Momentum Ocelot-C board" +config MOMENCO_OCELOT + bool "Support for Momentum Ocelot board" select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU - select IRQ_MV64340 - select PCI_MARVELL + select IRQ_CPU_RM7K + select MIPS_GT64120 select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_HAS_CPU_RM7000 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN help The Ocelot is a MIPS-based Single Board Computer (SBC) made by Momentum Computer <http://www.momenco.com/>. @@ -417,80 +389,95 @@ config MOMENCO_OCELOT_3 select PCI_MARVELL select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_HAS_CPU_RM9000 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN help The Ocelot-3 is based off Discovery III System Controller and PMC-Sierra Rm79000 core. -config MOMENCO_JAGUAR_ATX - bool "Support for Momentum Jaguar board" - select BOOT_ELF32 +config MOMENCO_OCELOT_C + bool "Support for Momentum Ocelot-C board" select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU - select IRQ_CPU_RM7K select IRQ_MV64340 - select LIMITED_DMA select PCI_MARVELL select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_HAS_CPU_RM7000 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN help - The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by + The Ocelot is a MIPS-based Single Board Computer (SBC) made by Momentum Computer <http://www.momenco.com/>. -config JAGUAR_DMALOW - bool "Low DMA Mode" - depends on MOMENCO_JAGUAR_ATX - help - Select to Y if jump JP5 is set on your board, N otherwise. Normally - the jumper is set, so if you feel unsafe, just say Y. - -config PMC_YOSEMITE - bool "Support for PMC-Sierra Yosemite eval board" - select DMA_COHERENT +config MOMENCO_OCELOT_G + bool "Support for Momentum Ocelot-G board" + select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU select IRQ_CPU_RM7K - select IRQ_CPU_RM9K + select PCI_MARVELL + select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_HAS_CPU_RM7000 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN help - Yosemite is an evaluation board for the RM9000x2 processor - manufactured by PMC-Sierra + The Ocelot is a MIPS-based Single Board Computer (SBC) made by + Momentum Computer <http://www.momenco.com/>. -config HYPERTRANSPORT - bool "Hypertransport Support for PMC-Sierra Yosemite" - depends on PMC_YOSEMITE +config MIPS_XXS1500 + bool "Support for MyCable XXS1500 board" + select DMA_NONCOHERENT + select SOC_AU1500 + select SYS_SUPPORTS_LITTLE_ENDIAN + +config PNX8550_V2PCI + bool "Support for Philips PNX8550 based Viper2-PCI board" + select PNX8550 + select SYS_SUPPORTS_LITTLE_ENDIAN + +config PNX8550_JBS + bool "Support for Philips PNX8550 based JBS board" + select PNX8550 + select SYS_SUPPORTS_LITTLE_ENDIAN config DDB5074 bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)" depends on EXPERIMENTAL + select DDB5XXX_COMMON select DMA_NONCOHERENT select HAVE_STD_PC_SERIAL_PORT select HW_HAS_PCI select IRQ_CPU select I8259 select ISA + select SYS_HAS_CPU_R5000 select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN help This enables support for the VR5000-based NEC DDB Vrc-5074 evaluation board. config DDB5476 bool "Support for NEC DDB Vrc-5476" + select DDB5XXX_COMMON select DMA_NONCOHERENT select HAVE_STD_PC_SERIAL_PORT select HW_HAS_PCI select IRQ_CPU select I8259 select ISA + select SYS_HAS_CPU_R5432 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN help This enables support for the R5432-based NEC DDB Vrc-5476 evaluation board. @@ -501,12 +488,15 @@ config DDB5476 config DDB5477 bool "Support for NEC DDB Vrc-5477" + select DDB5XXX_COMMON select DMA_NONCOHERENT select HW_HAS_PCI select I8259 select IRQ_CPU + select SYS_HAS_CPU_R5432 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN help This enables support for the R5432-based NEC DDB Vrc-5477, or Rockhopper/SolutionGear boards with R5432/R5500 CPUs. @@ -514,10 +504,28 @@ config DDB5477 Features : kernel debugging, serial terminal, NFS root fs, on-board ether port USB, AC97, PCI, etc. -config DDB5477_BUS_FREQUENCY - int "bus frequency (in kHZ, 0 for auto-detect)" - depends on DDB5477 - default 0 +config MACH_VR41XX + bool "Support for NEC VR4100 series based machines" + select SYS_HAS_CPU_VR41XX + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + +config PMC_YOSEMITE + bool "Support for PMC-Sierra Yosemite eval board" + select DMA_COHERENT + select HW_HAS_PCI + select IRQ_CPU + select IRQ_CPU_RM7K + select IRQ_CPU_RM9K + select SWAP_IO_SPACE + select SYS_HAS_CPU_RM9000 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM + help + Yosemite is an evaluation board for the RM9000x2 processor + manufactured by PMC-Sierra. config QEMU bool "Support for Qemu" @@ -527,15 +535,16 @@ config QEMU select I8259 select ISA select SWAP_IO_SPACE + select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN help - Qemu is a software emulator which among other architectures also - can simulate a MIPS32 4Kc system. This patch adds support for the - system architecture that currently is being simulated by Qemu. It - will eventually be removed again when Qemu has the capability to - simulate actual MIPS hardware platforms. More information on Qemu - can be found at http://www.linux-mips.org/wiki/Qemu. + Qemu is a software emulator which among other architectures also + can simulate a MIPS32 4Kc system. This patch adds support for the + system architecture that currently is being simulated by Qemu. It + will eventually be removed again when Qemu has the capability to + simulate actual MIPS hardware platforms. More information on Qemu + can be found at http://www.linux-mips.org/wiki/Qemu. config SGI_IP22 bool "Support for SGI IP22 (Indy/Indigo2)" @@ -543,11 +552,15 @@ config SGI_IP22 select ARC32 select BOOT_ELF32 select DMA_NONCOHERENT + select HW_HAS_EISA select IP22_CPU_SCACHE select IRQ_CPU select SWAP_IO_SPACE + select SYS_HAS_CPU_R4X00 + select SYS_HAS_CPU_R5000 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN help This are the SGI Indy, Challenge S and Indigo2, as well as certain OEM variants like the Tandem CMN B006S. To compile a Linux kernel @@ -557,70 +570,18 @@ config SGI_IP27 bool "Support for SGI IP27 (Origin200/2000)" select ARC select ARC64 + select BOOT_ELF64 select DMA_IP27 select HW_HAS_PCI select PCI_DOMAINS + select SYS_HAS_CPU_R10000 select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN help This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics workstations. To compile a Linux kernel that runs on these, say Y here. -#config SGI_SN0_XXL -# bool "IP27 XXL" -# depends on SGI_IP27 -# This options adds support for userspace processes upto 16TB size. -# Normally the limit is just .5TB. - -config SGI_SN0_N_MODE - bool "IP27 N-Mode" - depends on SGI_IP27 - help - The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be - configured in either N-Modes which allows for more nodes or M-Mode - which allows for more memory. Your system is most probably - running in M-Mode, so you should say N here. - -config ARCH_DISCONTIGMEM_ENABLE - bool - default y if SGI_IP27 - help - Say Y to upport efficient handling of discontiguous physical memory, - for architectures which are either NUMA (Non-Uniform Memory Access) - or have huge holes in the physical address space for other reasons. - See <file:Documentation/vm/numa> for more. - -config NUMA - bool "NUMA Support" - depends on SGI_IP27 - help - Say Y to compile the kernel to support NUMA (Non-Uniform Memory - Access). This option is for configuring high-end multiprocessor - server machines. If in doubt, say N. - -config MAPPED_KERNEL - bool "Mapped kernel support" - depends on SGI_IP27 - help - Change the way a Linux kernel is loaded into memory on a MIPS64 - machine. This is required in order to support text replication and - NUMA. If you need to understand it, read the source code. - -config REPLICATE_KTEXT - bool "Kernel text replication support" - depends on SGI_IP27 - help - Say Y here to enable replicating the kernel text across multiple - nodes in a NUMA cluster. This trades memory for speed. - -config REPLICATE_EXHANDLERS - bool "Exception handler replication support" - depends on SGI_IP27 - help - Say Y here to enable replicating the kernel exception handlers - across multiple nodes in a NUMA cluster. This trades memory for - speed. - config SGI_IP32 bool "Support for SGI IP32 (O2) (EXPERIMENTAL)" depends on EXPERIMENTAL @@ -633,353 +594,152 @@ config SGI_IP32 select HW_HAS_PCI select R5000_CPU_SCACHE select RM7000_CPU_SCACHE + select SYS_HAS_CPU_R5000 + select SYS_HAS_CPU_R10000 if BROKEN + select SYS_HAS_CPU_RM7000 select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN help If you want this kernel to run on SGI O2 workstation, say Y here. -config SOC_AU1X00 - bool "Support for AMD/Alchemy Au1X00 SOCs" - select SYS_SUPPORTS_32BIT_KERNEL - -choice - prompt "Au1X00 SOC Type" - depends on SOC_AU1X00 - help - Say Y here to enable support for one of three AMD/Alchemy - SOCs. For additional documentation see www.amd.com. - -config SOC_AU1000 - bool "SOC_AU1000" -config SOC_AU1100 - bool "SOC_AU1100" -config SOC_AU1500 - bool "SOC_AU1500" -config SOC_AU1550 - bool "SOC_AU1550" - -endchoice - -choice - prompt "AMD/Alchemy Au1x00 board support" - depends on SOC_AU1X00 - help - These are evaluation boards built by AMD/Alchemy to - showcase their Au1X00 Internet Edge Processors. The SOC design - is based on the MIPS32 architecture running at 266/400/500MHz - with many integrated peripherals. Further information can be - found at their website, <http://www.amd.com/>. Say Y here if you - wish to build a kernel for this platform. - -config MIPS_PB1000 - bool "PB1000 board" - depends on SOC_AU1000 - select DMA_NONCOHERENT - select HW_HAS_PCI - select SWAP_IO_SPACE - -config MIPS_PB1100 - bool "PB1100 board" - depends on SOC_AU1100 - select DMA_NONCOHERENT - select HW_HAS_PCI - select SWAP_IO_SPACE - -config MIPS_PB1500 - bool "PB1500 board" - depends on SOC_AU1500 - select DMA_COHERENT - select HW_HAS_PCI - -config MIPS_PB1550 - bool "PB1550 board" - depends on SOC_AU1550 - select DMA_COHERENT - select HW_HAS_PCI - select MIPS_DISABLE_OBSOLETE_IDE - -config MIPS_DB1000 - bool "DB1000 board" - depends on SOC_AU1000 - select DMA_NONCOHERENT - select HW_HAS_PCI - -config MIPS_DB1100 - bool "DB1100 board" - depends on SOC_AU1100 - select DMA_NONCOHERENT - -config MIPS_DB1500 - bool "DB1500 board" - depends on SOC_AU1500 - select DMA_COHERENT - select HW_HAS_PCI - select MIPS_DISABLE_OBSOLETE_IDE - -config MIPS_DB1550 - bool "DB1550 board" - depends on SOC_AU1550 - select HW_HAS_PCI - select DMA_COHERENT - select MIPS_DISABLE_OBSOLETE_IDE - -config MIPS_BOSPORUS - bool "Bosporus board" - depends on SOC_AU1500 - select DMA_NONCOHERENT - -config MIPS_MIRAGE - bool "Mirage board" - depends on SOC_AU1500 - select DMA_NONCOHERENT - -config MIPS_XXS1500 - bool "MyCable XXS1500 board" - depends on SOC_AU1500 - select DMA_NONCOHERENT - -config MIPS_MTX1 - bool "4G Systems MTX-1 board" - depends on SOC_AU1500 - select HW_HAS_PCI - select DMA_NONCOHERENT - -endchoice - -config SIBYTE_SB1xxx_SOC - bool "Support for Broadcom BCM1xxx SOCs (EXPERIMENTAL)" - depends on EXPERIMENTAL +config SIBYTE_BIGSUR + bool "Support for Sibyte BigSur" select BOOT_ELF32 select DMA_COHERENT + select PCI_DOMAINS + select SIBYTE_BCM1x80 select SWAP_IO_SPACE - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - -choice - prompt "BCM1xxx SOC-based board" - depends on SIBYTE_SB1xxx_SOC - default SIBYTE_SWARM - help - Enable support for boards based on the SiByte line of SOCs - from Broadcom. There are configurations for the known - evaluation boards, or you can choose "Other" and add your - own board support code. + select SYS_HAS_CPU_SB1 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN config SIBYTE_SWARM - bool "BCM91250A-SWARM" + bool "Support for Sibyte BCM91250A-SWARM" + select BOOT_ELF32 + select DMA_COHERENT select SIBYTE_SB1250 + select SWAP_IO_SPACE + select SYS_HAS_CPU_SB1 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_LITTLE_ENDIAN config SIBYTE_SENTOSA - bool "BCM91250E-Sentosa" + bool "Support for Sibyte BCM91250E-Sentosa" + depends on EXPERIMENTAL + select BOOT_ELF32 + select DMA_COHERENT select SIBYTE_SB1250 + select SWAP_IO_SPACE + select SYS_HAS_CPU_SB1 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN config SIBYTE_RHONE - bool "BCM91125E-Rhone" + bool "Support for Sibyte BCM91125E-Rhone" + depends on EXPERIMENTAL + select BOOT_ELF32 + select DMA_COHERENT select SIBYTE_BCM1125H + select SWAP_IO_SPACE + select SYS_HAS_CPU_SB1 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN config SIBYTE_CARMEL - bool "BCM91120x-Carmel" + bool "Support for Sibyte BCM91120x-Carmel" + depends on EXPERIMENTAL + select BOOT_ELF32 + select DMA_COHERENT select SIBYTE_BCM1120 + select SWAP_IO_SPACE + select SYS_HAS_CPU_SB1 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN config SIBYTE_PTSWARM - bool "BCM91250PT-PTSWARM" + bool "Support for Sibyte BCM91250PT-PTSWARM" + depends on EXPERIMENTAL + select BOOT_ELF32 + select DMA_COHERENT select SIBYTE_SB1250 + select SWAP_IO_SPACE + select SYS_HAS_CPU_SB1 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_LITTLE_ENDIAN config SIBYTE_LITTLESUR - bool "BCM91250C2-LittleSur" + bool "Support for Sibyte BCM91250C2-LittleSur" + depends on EXPERIMENTAL + select BOOT_ELF32 + select DMA_COHERENT select SIBYTE_SB1250 + select SWAP_IO_SPACE + select SYS_HAS_CPU_SB1 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_LITTLE_ENDIAN config SIBYTE_CRHINE - bool "BCM91120C-CRhine" + bool "Support for Sibyte BCM91120C-CRhine" + depends on EXPERIMENTAL + select BOOT_ELF32 + select DMA_COHERENT select SIBYTE_BCM1120 + select SWAP_IO_SPACE + select SYS_HAS_CPU_SB1 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN config SIBYTE_CRHONE - bool "BCM91125C-CRhone" - select SIBYTE_BCM1125 - -config SIBYTE_UNKNOWN - bool "Other" - -endchoice - -config SIBYTE_BOARD - bool - depends on SIBYTE_SB1xxx_SOC && !SIBYTE_UNKNOWN - default y - -choice - prompt "BCM1xxx SOC Type" - depends on SIBYTE_UNKNOWN - default SIBYTE_UNK_BCM1250 - help - Since you haven't chosen a known evaluation board from - Broadcom, you must explicitly pick the SOC this kernel is - targetted for. - -config SIBYTE_UNK_BCM1250 - bool "BCM1250" - select SIBYTE_SB1250 - -config SIBYTE_UNK_BCM1120 - bool "BCM1120" - select SIBYTE_BCM1120 - -config SIBYTE_UNK_BCM1125 - bool "BCM1125" + bool "Support for Sibyte BCM91125C-CRhone" + depends on EXPERIMENTAL + select BOOT_ELF32 + select DMA_COHERENT select SIBYTE_BCM1125 - -config SIBYTE_UNK_BCM1125H - bool "BCM1125H" - select SIBYTE_BCM1125H - -endchoice - -config SIBYTE_SB1250 - bool - select HW_HAS_PCI - -config SIBYTE_BCM1120 - bool - select SIBYTE_BCM112X - -config SIBYTE_BCM1125 - bool - select HW_HAS_PCI - select SIBYTE_BCM112X - -config SIBYTE_BCM1125H - bool - select HW_HAS_PCI - select SIBYTE_BCM112X - -config SIBYTE_BCM112X - bool - -choice - prompt "SiByte SOC Stepping" - depends on SIBYTE_SB1xxx_SOC - -config CPU_SB1_PASS_1 - bool "1250 Pass1" - depends on SIBYTE_SB1250 - select CPU_HAS_PREFETCH - -config CPU_SB1_PASS_2_1250 - bool "1250 An" - depends on SIBYTE_SB1250 - select CPU_SB1_PASS_2 - help - Also called BCM1250 Pass 2 - -config CPU_SB1_PASS_2_2 - bool "1250 Bn" - depends on SIBYTE_SB1250 - select CPU_HAS_PREFETCH - help - Also called BCM1250 Pass 2.2 - -config CPU_SB1_PASS_4 - bool "1250 Cn" - depends on SIBYTE_SB1250 - select CPU_HAS_PREFETCH - help - Also called BCM1250 Pass 3 - -config CPU_SB1_PASS_2_112x - bool "112x Hybrid" - depends on SIBYTE_BCM112X - select CPU_SB1_PASS_2 - -config CPU_SB1_PASS_3 - bool "112x An" - depends on SIBYTE_BCM112X - select CPU_HAS_PREFETCH - -endchoice - -config CPU_SB1_PASS_2 - bool - -config SIBYTE_HAS_LDT - bool - depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H) - default y - -config SIMULATION - bool "Running under simulation" - depends on SIBYTE_SB1xxx_SOC - help - Build a kernel suitable for running under the GDB simulator. - Primarily adjusts the kernel's notion of time. - -config SIBYTE_CFE - bool "Booting from CFE" - depends on SIBYTE_SB1xxx_SOC - help - Make use of the CFE API for enumerating available memory, - controlling secondary CPUs, and possibly console output. - -config SIBYTE_CFE_CONSOLE - bool "Use firmware console" - depends on SIBYTE_CFE - help - Use the CFE API's console write routines during boot. Other console - options (VT console, sb1250 duart console, etc.) should not be - configured. - -config SIBYTE_STANDALONE - bool - depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE - default y - -config SIBYTE_STANDALONE_RAM_SIZE - int "Memory size (in megabytes)" - depends on SIBYTE_STANDALONE - default "32" - -config SIBYTE_BUS_WATCHER - bool "Support for Bus Watcher statistics" - depends on SIBYTE_SB1xxx_SOC - help - Handle and keep statistics on the bus error interrupts (COR_ECC, - BAD_ECC, IO_BUS). - -config SIBYTE_BW_TRACE - bool "Capture bus trace before bus error" - depends on SIBYTE_BUS_WATCHER - help - Run a continuous bus trace, dumping the raw data as soon as - a ZBbus error is detected. Cannot work if ZBbus profiling - is turned on, and also will interfere with JTAG-based trace - buffer activity. Raw buffer data is dumped to console, and - must be processed off-line. - -config SIBYTE_SB1250_PROF - bool "Support for SB1/SOC profiling - SB1/SCD perf counters" - depends on SIBYTE_SB1xxx_SOC - -config SIBYTE_TBPROF - bool "Support for ZBbus profiling" - depends on SIBYTE_SB1xxx_SOC + select SWAP_IO_SPACE + select SYS_HAS_CPU_SB1 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_LITTLE_ENDIAN config SNI_RM200_PCI bool "Support for SNI RM200 PCI" select ARC select ARC32 + select ARCH_MAY_HAVE_PC_FDC select BOOT_ELF32 select DMA_NONCOHERENT select GENERIC_ISA_DMA select HAVE_STD_PC_SERIAL_PORT + select HW_HAS_EISA select HW_HAS_PCI select I8259 select ISA + select SYS_HAS_CPU_R4X00 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_BIG_ENDIAN if EXPERIMENTAL + select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_LITTLE_ENDIAN help The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid Technology and now in turn merged with Fujitsu. Say Y here to support this machine type. +config TOSHIBA_JMR3927 + bool "Support for Toshiba JMR-TX3927 board" + select DMA_NONCOHERENT + select HW_HAS_PCI + select MIPS_TX3927 + select SWAP_IO_SPACE + select SYS_HAS_CPU_TX39XX + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select TOSHIBA_BOARDS + config TOSHIBA_RBTX4927 bool "Support for Toshiba TBTX49[23]7 board" select DMA_NONCOHERENT @@ -988,15 +748,51 @@ config TOSHIBA_RBTX4927 select I8259 select ISA select SWAP_IO_SPACE + select SYS_HAS_CPU_TX49XX select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select TOSHIBA_BOARDS help This Toshiba board is based on the TX4927 processor. Say Y here to support this machine type -config TOSHIBA_FPCIB0 - bool "FPCIB0 Backplane Support" - depends on TOSHIBA_RBTX4927 +config TOSHIBA_RBTX4938 + bool "Support for Toshiba RBTX4938 board" + select HAVE_STD_PC_SERIAL_PORT + select DMA_NONCOHERENT + select GENERIC_ISA_DMA + select HAS_TXX9_SERIAL + select HW_HAS_PCI + select I8259 + select ISA + select SWAP_IO_SPACE + select SYS_HAS_CPU_TX49XX + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select TOSHIBA_BOARDS + help + This Toshiba board is based on the TX4938 processor. Say Y here to + support this machine type + +endchoice + +source "arch/mips/ddb5xxx/Kconfig" +source "arch/mips/gt64120/ev64120/Kconfig" +source "arch/mips/jazz/Kconfig" +source "arch/mips/ite-boards/Kconfig" +source "arch/mips/lasat/Kconfig" +source "arch/mips/momentum/Kconfig" +source "arch/mips/pmc-sierra/Kconfig" +source "arch/mips/sgi-ip27/Kconfig" +source "arch/mips/sibyte/Kconfig" +source "arch/mips/tx4927/Kconfig" +source "arch/mips/tx4938/Kconfig" +source "arch/mips/vr41xx/Kconfig" +source "arch/mips/philips/pnx8550/common/Kconfig" + +endmenu config RWSEM_GENERIC_SPINLOCK bool @@ -1014,8 +810,9 @@ config GENERIC_CALIBRATE_DELAY # config ARC bool - depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP27 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 - default y + +config ARCH_MAY_HAVE_PC_FDC + bool config DMA_COHERENT bool @@ -1034,51 +831,65 @@ config DMA_NONCOHERENT config DMA_NEED_PCI_MAP_STATE bool +config OWN_DMA + bool + config EARLY_PRINTK bool - depends on MACH_DECSTATION - default y config GENERIC_ISA_DMA bool - depends on SNI_RM200_PCI || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 || MIPS_MALTA - default y config I8259 bool - depends on SNI_RM200_PCI || DDB5477 || DDB5476 || DDB5074 || MACH_JAZZ || MIPS_MALTA || MIPS_COBALT - default y config LIMITED_DMA bool select HIGHMEM + select SYS_SUPPORTS_HIGHMEM config MIPS_BONITO64 bool - depends on MIPS_ATLAS || MIPS_MALTA - default y config MIPS_MSC bool - depends on MIPS_ATLAS || MIPS_MALTA - default y config MIPS_NILE4 bool - depends on LASAT - default y config MIPS_DISABLE_OBSOLETE_IDE bool -config CPU_LITTLE_ENDIAN - bool "Generate little endian code" - default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA - default n if MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927 +# +# Endianess selection. Suffiently obscure so many users don't know what to +# answer,so we try hard to limit the available choices. Also the use of a +# choice statement should be more obvious to the user. +# +choice + prompt "Endianess selection" help Some MIPS machines can be configured for either little or big endian - byte order. These modes require different kernels. Say Y if your - machine is little endian, N if it's a big endian machine. + byte order. These modes require different kernels and a different + Linux distribution. In general there is one prefered byteorder for a + particular system but some systems are just as commonly used in the + one or the other endianess. + +config CPU_BIG_ENDIAN + bool "Big endian" + depends on SYS_SUPPORTS_BIG_ENDIAN + +config CPU_LITTLE_ENDIAN + bool "Little endian" + depends on SYS_SUPPORTS_LITTLE_ENDIAN + help + +endchoice + +config SYS_SUPPORTS_BIG_ENDIAN + bool + +config SYS_SUPPORTS_LITTLE_ENDIAN + bool config IRQ_CPU bool @@ -1086,42 +897,69 @@ config IRQ_CPU config IRQ_CPU_RM7K bool +config IRQ_CPU_RM9K + bool + config IRQ_MV64340 bool config DDB5XXX_COMMON bool - depends on DDB5074 || DDB5476 || DDB5477 - default y config MIPS_BOARDS_GEN bool - depends on MIPS_ATLAS || MIPS_MALTA || MIPS_SEAD - default y config MIPS_GT64111 bool - depends on MIPS_COBALT - default y config MIPS_GT64120 bool - depends on MIPS_EV64120 || MIPS_EV96100 || LASAT || MIPS_ATLAS || MIPS_MALTA || MOMENCO_OCELOT - default y config MIPS_TX3927 bool - depends on TOSHIBA_JMR3927 select HAS_TXX9_SERIAL - default y config PCI_MARVELL bool config ITE_BOARD_GEN bool - depends on MIPS_IVR || MIPS_ITE8172 - default y + +config SOC_AU1000 + bool + select SOC_AU1X00 + +config SOC_AU1100 + bool + select SOC_AU1X00 + +config SOC_AU1500 + bool + select SOC_AU1X00 + +config SOC_AU1550 + bool + select SOC_AU1X00 + +config SOC_AU1200 + bool + select SOC_AU1X00 + +config SOC_AU1X00 + bool + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_32BIT_KERNEL + +config PNX8550 + bool + select SOC_PNX8550 + +config SOC_PNX8550 + bool + select DMA_NONCOHERENT + select HW_HAS_PCI + select SYS_HAS_CPU_R4X00 + select SYS_SUPPORTS_32BIT_KERNEL config SWAP_IO_SPACE bool @@ -1148,6 +986,9 @@ config SYSCLK_100 endchoice +config ARC32 + bool + config AU1X00_USB_DEVICE bool depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000 @@ -1155,11 +996,7 @@ config AU1X00_USB_DEVICE config MIPS_GT96100 bool - depends on MIPS_EV96100 - default y - help - Say Y here to support the Galileo Technology GT96100 communications - controller card. There is a web page at <http://www.galileot.com/>. + select MIPS_GT64120 config IT8172_CIR bool @@ -1173,8 +1010,6 @@ config IT8712 config BOOT_ELF32 bool - depends on MACH_DECSTATION || MIPS_ATLAS || MIPS_MALTA || MOMENCO_JAGUAR_ATX || MOMENCO_OCELOT_3 || SIBYTE_SB1xxx_SOC || SGI_IP32 || SGI_IP22 || SNI_RM200_PCI - default y config MIPS_L1_CACHE_SHIFT int @@ -1182,11 +1017,6 @@ config MIPS_L1_CACHE_SHIFT default "7" if SGI_IP27 default "5" -config ARC32 - bool - depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32 - default y - config HAVE_STD_PC_SERIAL_PORT bool @@ -1206,30 +1036,12 @@ config ARC_PROMLIB config ARC64 bool - depends on SGI_IP27 - default y config BOOT_ELF64 bool - depends on SGI_IP27 - default y - -#config MAPPED_PCI_IO y -# bool -# depends on SGI_IP27 -# default y - -config QL_ISP_A64 - bool - depends on SGI_IP27 - default y config TOSHIBA_BOARDS bool - depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 - default y - -endmenu menu "CPU selection" @@ -1237,18 +1049,69 @@ choice prompt "CPU type" default CPU_R4X00 -config CPU_MIPS32 - bool "MIPS32" +config CPU_MIPS32_R1 + bool "MIPS32 Release 1" + depends on SYS_HAS_CPU_MIPS32_R1 + select CPU_HAS_PREFETCH select CPU_SUPPORTS_32BIT_KERNEL + help + Choose this option to build a kernel for release 1 or later of the + MIPS32 architecture. Most modern embedded systems with a 32-bit + MIPS processor are based on a MIPS32 processor. If you know the + specific type of processor in your system, choose those that one + otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system. + Release 2 of the MIPS32 architecture is available since several + years so chances are you even have a MIPS32 Release 2 processor + in which case you should choose CPU_MIPS32_R2 instead for better + performance. + +config CPU_MIPS32_R2 + bool "MIPS32 Release 2" + depends on SYS_HAS_CPU_MIPS32_R2 + select CPU_HAS_PREFETCH + select CPU_SUPPORTS_32BIT_KERNEL + help + Choose this option to build a kernel for release 2 or later of the + MIPS32 architecture. Most modern embedded systems with a 32-bit + MIPS processor are based on a MIPS32 processor. If you know the + specific type of processor in your system, choose those that one + otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system. -config CPU_MIPS64 - bool "MIPS64" +config CPU_MIPS64_R1 + bool "MIPS64 Release 1" + depends on SYS_HAS_CPU_MIPS64_R1 + select CPU_HAS_PREFETCH select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL + help + Choose this option to build a kernel for release 1 or later of the + MIPS64 architecture. Many modern embedded systems with a 64-bit + MIPS processor are based on a MIPS64 processor. If you know the + specific type of processor in your system, choose those that one + otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system. + Release 2 of the MIPS64 architecture is available since several + years so chances are you even have a MIPS64 Release 2 processor + in which case you should choose CPU_MIPS64_R2 instead for better + performance. + +config CPU_MIPS64_R2 + bool "MIPS64 Release 2" + depends on SYS_HAS_CPU_MIPS64_R2 + select CPU_HAS_PREFETCH + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + help + Choose this option to build a kernel for release 2 or later of the + MIPS64 architecture. Many modern embedded systems with a 64-bit + MIPS processor are based on a MIPS64 processor. If you know the + specific type of processor in your system, choose those that one + otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system. config CPU_R3000 bool "R3000" + depends on SYS_HAS_CPU_R3000 select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM help Please make sure to pick the right CPU type. Linux/MIPS is not designed to be generic, i.e. Kernels compiled for R3000 CPUs will @@ -1259,20 +1122,23 @@ config CPU_R3000 config CPU_TX39XX bool "R39XX" + depends on SYS_HAS_CPU_TX39XX select CPU_SUPPORTS_32BIT_KERNEL config CPU_VR41XX bool "R41xx" + depends on SYS_HAS_CPU_VR41XX select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL help - The options selects support for the NEC VR41xx series of processors. + The options selects support for the NEC VR4100 series of processors. Only choose this option if you have one of these processors as a kernel built with this option will not run on any other type of processor or vice versa. config CPU_R4300 bool "R4300" + depends on SYS_HAS_CPU_R4300 select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL help @@ -1280,6 +1146,7 @@ config CPU_R4300 config CPU_R4X00 bool "R4x00" + depends on SYS_HAS_CPU_R4X00 select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL help @@ -1288,11 +1155,13 @@ config CPU_R4X00 config CPU_TX49XX bool "R49XX" + depends on SYS_HAS_CPU_TX49XX select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL config CPU_R5000 bool "R5000" + depends on SYS_HAS_CPU_R5000 select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL help @@ -1300,10 +1169,14 @@ config CPU_R5000 config CPU_R5432 bool "R5432" + depends on SYS_HAS_CPU_R5432 + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL config CPU_R6000 bool "R6000" depends on EXPERIMENTAL + depends on SYS_HAS_CPU_R6000 select CPU_SUPPORTS_32BIT_KERNEL help MIPS Technologies R6000 and R6000A series processors. Note these @@ -1311,6 +1184,7 @@ config CPU_R6000 config CPU_NEVADA bool "RM52xx" + depends on SYS_HAS_CPU_NEVADA select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL help @@ -1319,6 +1193,8 @@ config CPU_NEVADA config CPU_R8000 bool "R8000" depends on EXPERIMENTAL + depends on SYS_HAS_CPU_R8000 + select CPU_HAS_PREFETCH select CPU_SUPPORTS_64BIT_KERNEL help MIPS Technologies R8000 processors. Note these processors are @@ -1326,25 +1202,151 @@ config CPU_R8000 config CPU_R10000 bool "R10000" + depends on SYS_HAS_CPU_R10000 + select CPU_HAS_PREFETCH select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM help MIPS Technologies R10000-series processors. config CPU_RM7000 bool "RM7000" + depends on SYS_HAS_CPU_RM7000 + select CPU_HAS_PREFETCH select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM config CPU_RM9000 bool "RM9000" + depends on SYS_HAS_CPU_RM9000 + select CPU_HAS_PREFETCH select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM config CPU_SB1 bool "SB1" + depends on SYS_HAS_CPU_SB1 select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + +endchoice + +config SYS_HAS_CPU_MIPS32_R1 + bool + +config SYS_HAS_CPU_MIPS32_R2 + bool + +config SYS_HAS_CPU_MIPS64_R1 + bool + +config SYS_HAS_CPU_MIPS64_R2 + bool + +config SYS_HAS_CPU_R3000 + bool + +config SYS_HAS_CPU_TX39XX + bool + +config SYS_HAS_CPU_VR41XX + bool + +config SYS_HAS_CPU_R4300 + bool + +config SYS_HAS_CPU_R4X00 + bool + +config SYS_HAS_CPU_TX49XX + bool + +config SYS_HAS_CPU_R5000 + bool + +config SYS_HAS_CPU_R5432 + bool + +config SYS_HAS_CPU_R6000 + bool + +config SYS_HAS_CPU_NEVADA + bool + +config SYS_HAS_CPU_R8000 + bool + +config SYS_HAS_CPU_R10000 + bool + +config SYS_HAS_CPU_RM7000 + bool + +config SYS_HAS_CPU_RM9000 + bool + +config SYS_HAS_CPU_SB1 + bool + +endmenu + +# +# These two indicate any levelof the MIPS32 and MIPS64 architecture +# +config CPU_MIPS32 + bool + default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 + +config CPU_MIPS64 + bool + default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 + +# +# These two indicate the revision of the architecture, either 32 bot 64 bit. +# +config CPU_MIPSR1 + bool + default y if CPU_MIPS32_R1 || CPU_MIPS64_R1 + +config CPU_MIPSR2 + bool + default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 + +config SYS_SUPPORTS_32BIT_KERNEL + bool +config SYS_SUPPORTS_64BIT_KERNEL + bool +config CPU_SUPPORTS_32BIT_KERNEL + bool +config CPU_SUPPORTS_64BIT_KERNEL + bool + +menu "Kernel type" + +choice + + prompt "Kernel code model" + help + You should only select this option if you have a workload that + actually benefits from 64-bit processing or if your machine has + large memory. You will only be presented a single option in this + menu if your system does not support both 32-bit and 64-bit kernels. + +config 32BIT + bool "32-bit kernel" + depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL + select TRAD_SIGNALS + help + Select this option if you want to build a 32-bit kernel. +config 64BIT + bool "64-bit kernel" + depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL + help + Select this option if you want to build a 64-bit kernel. endchoice @@ -1416,12 +1418,43 @@ config SIBYTE_DMA_PAGEOPS SiByte Linux port. Seems to give a small performance benefit. config CPU_HAS_PREFETCH - bool "Enable prefetches" if CPU_SB1 && !CPU_SB1_PASS_2 - default y if CPU_MIPS32 || CPU_MIPS64 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 + bool + +config MIPS_MT + bool "Enable MIPS MT" + +choice + prompt "MIPS MT options" + depends on MIPS_MT -config VTAG_ICACHE - bool "Support for Virtual Tagged I-cache" if CPU_MIPS64 || CPU_MIPS32 - default y if CPU_SB1 +config MIPS_MT_SMP + bool "Use 1 TC on each available VPE for SMP" + select SMP + +config MIPS_VPE_LOADER + bool "VPE loader support." + depends on MIPS_MT + help + Includes a loader for loading an elf relocatable object + onto another VPE and running it. + +endchoice + +config MIPS_VPE_LOADER_TOM + bool "Load VPE program into memory hidden from linux" + depends on MIPS_VPE_LOADER + default y + help + The loader can use memory that is present but has been hidden from + Linux using the kernel command line option "mem=xxMB". It's up to + you to ensure the amount you put in the option and the space your + program requires is less or equal to the amount physically present. + +# this should possibly be in drivers/char, but it is rather cpu related. Hmmm +config MIPS_VPE_APSP_API + bool "Enable support for AP/SP API (RTLX)" + depends on MIPS_VPE_LOADER + help config SB1_PASS_1_WORKAROUNDS bool @@ -1440,7 +1473,7 @@ config SB1_PASS_2_1_WORKAROUNDS config 64BIT_PHYS_ADDR bool "Support for 64-bit physical address space" - depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT + depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32_R1 || CPU_MIPS64_R1) && 32BIT config CPU_ADVANCED bool "Override CPU Options" @@ -1463,7 +1496,7 @@ config CPU_HAS_LLSC config CPU_HAS_LLDSCD bool "lld/scd Instructions available" if CPU_ADVANCED - default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32 + default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32_R1 help Say Y here if your CPU has the lld and scd instructions, the 64-bit equivalents of ll and sc. Say Y here for better performance, N if @@ -1477,12 +1510,52 @@ config CPU_HAS_WB machines which require flushing of write buffers in software. Saying Y is the safe option; N may result in kernel malfunction and crashes. +menu "MIPSR2 Interrupt handling" + depends on CPU_MIPSR2 && CPU_ADVANCED + +config CPU_MIPSR2_IRQ_VI + bool "Vectored interrupt mode" + help + Vectored interrupt mode allowing faster dispatching of interrupts. + The board support code needs to be written to take advantage of this + mode. Compatibility code is included to allow the kernel to run on + a CPU that does not support vectored interrupts. It's safe to + say Y here. + +config CPU_MIPSR2_IRQ_EI + bool "External interrupt controller mode" + help + Extended interrupt mode takes advantage of an external interrupt + controller to allow fast dispatching from many possible interrupt + sources. Say N unless you know that external interrupt support is + required. + +config CPU_MIPSR2_SRS + bool "Make shadow set registers available for interrupt handlers" + depends on CPU_MIPSR2_IRQ_VI || CPU_MIPSR2_IRQ_EI + help + Allow the kernel to use shadow register sets for fast interrupts. + Interrupt handlers must be specially written to use shadow sets. + Say N unless you know that shadow register set upport is needed. +endmenu + config CPU_HAS_SYNC bool depends on !CPU_R3000 default y # +# Use the generic interrupt handling code in kernel/irq/: +# +config GENERIC_HARDIRQS + bool + default y + +config GENERIC_IRQ_PROBE + bool + default y + +# # - Highmem only makes sense for the 32-bit kernel. # - The current highmem code will only work properly on physically indexed # caches such as R3000, SB1, R7000 or those that look like they're virtually @@ -1491,14 +1564,19 @@ config CPU_HAS_SYNC # where it's known to be safe. This will not offer highmem on a few systems # such as MIPS32 and MIPS64 CPUs which may have virtual and physically # indexed CPUs but we're playing safe. -# - We should not offer highmem for system of which we already know that they -# don't have memory configurations that could gain from highmem support in -# the kernel because they don't support configurations with RAM at physical -# addresses > 0x20000000. +# - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we +# know they might have memory configurations that could make use of highmem +# support. # config HIGHMEM bool "High Memory Support" - depends on 32BIT && (CPU_R3000 || CPU_SB1 || CPU_R7000 || CPU_RM9000 || CPU_R10000) && !(MACH_DECSTATION || MOMENCO_JAGUAR_ATX) + depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM + +config CPU_SUPPORTS_HIGHMEM + bool + +config SYS_SUPPORTS_HIGHMEM + bool config ARCH_FLATMEM_ENABLE def_bool y @@ -1508,7 +1586,7 @@ source "mm/Kconfig" config SMP bool "Multi-Processing support" - depends on CPU_RM9000 || (SIBYTE_SB1250 && !SIBYTE_STANDALONE) || SGI_IP27 + depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP ---help--- This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If @@ -1543,14 +1621,7 @@ config NR_CPUS This is purely to save memory - each supported CPU adds approximately eight kilobytes to the kernel image. -config PREEMPT - bool "Preemptible Kernel" - help - This option reduces the latency of the kernel when reacting to - real-time or interactive events by allowing a low priority process to - be preempted even if it is in kernel mode executing a system call. - This allows applications to run more reliably even when the system is - under load. +source "kernel/Kconfig.preempt" config RTC_DS1742 bool "DS1742 BRAM/RTC support" @@ -1566,14 +1637,16 @@ config MIPS_INSANE_LARGE This will result in additional memory usage, so it is not recommended for normal users. +endmenu + config RWSEM_GENERIC_SPINLOCK bool default y -endmenu - menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)" +config HW_HAS_EISA + bool config HW_HAS_PCI bool @@ -1607,7 +1680,7 @@ config ISA config EISA bool "EISA support" - depends on SGI_IP22 || SNI_RM200_PCI + depends on HW_HAS_EISA select ISA ---help--- The Extended Industry Standard Architecture (EISA) bus was @@ -1641,12 +1714,6 @@ config MMU bool default y -config MCA - bool - -config SBUS - bool - source "drivers/pcmcia/Kconfig" source "drivers/pci/hotplug/Kconfig" @@ -1659,7 +1726,6 @@ source "fs/Kconfig.binfmt" config TRAD_SIGNALS bool - default y if 32BIT config BUILD_ELF64 bool "Use 64-bit ELF format for building" @@ -1678,7 +1744,7 @@ config BUILD_ELF64 config BINFMT_IRIX bool "Include IRIX binary compatibility" - depends on !CPU_LITTLE_ENDIAN && 32BIT && BROKEN + depends on CPU_BIG_ENDIAN && 32BIT && BROKEN config MIPS32_COMPAT bool "Kernel support for Linux/MIPS 32-bit binary compatibility" @@ -1718,9 +1784,26 @@ config BINFMT_ELF32 bool default y if MIPS32_O32 || MIPS32_N32 +config SECCOMP + bool "Enable seccomp to safely compute untrusted bytecode" + depends on PROC_FS && BROKEN + default y + help + This kernel feature is useful for number crunching applications + that may need to compute untrusted bytecode during their + execution. By using pipes or other transports made available to + the process as file descriptors supporting the read/write + syscalls, it's possible to isolate those applications in + their own address space using seccomp. Once seccomp is + enabled via /proc/<pid>/seccomp, it cannot be disabled + and the task is only allowed to execute a few safe syscalls + defined by each seccomp mode. + + If unsure, say Y. Only embedded should say N here. + config PM bool "Power Management support (EXPERIMENTAL)" - depends on EXPERIMENTAL && MACH_AU1X00 + depends on EXPERIMENTAL && SOC_AU1X00 endmenu @@ -1730,6 +1813,8 @@ source "drivers/Kconfig" source "fs/Kconfig" +source "arch/mips/oprofile/Kconfig" + source "arch/mips/Kconfig.debug" source "security/Kconfig" @@ -1737,18 +1822,3 @@ source "security/Kconfig" source "crypto/Kconfig" source "lib/Kconfig" - -# -# Use the generic interrupt handling code in kernel/irq/: -# -config GENERIC_HARDIRQS - bool - default y - -config GENERIC_IRQ_PROBE - bool - default y - -config ISA_DMA_API - bool - default y diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 346e803f153b..02692027730a 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -52,6 +52,21 @@ ifdef CONFIG_CROSSCOMPILE CROSS_COMPILE := $(tool-prefix) endif +CHECKFLAGS-y += -D__linux__ -D__mips__ \ + -D_ABIO32=1 \ + -D_ABIN32=2 \ + -D_ABI64=3 +CHECKFLAGS-$(CONFIG_32BIT) += -D_MIPS_SIM=_ABIO32 \ + -D_MIPS_SZLONG=32 \ + -D__PTRDIFF_TYPE__=int +CHECKFLAGS-$(CONFIG_64BIT) += -m64 -D_MIPS_SIM=_ABI64 \ + -D_MIPS_SZLONG=64 \ + -D__PTRDIFF_TYPE__="long int" +CHECKFLAGS-$(CONFIG_CPU_BIG_ENDIAN) += -D__MIPSEB__ +CHECKFLAGS-$(CONFIG_CPU_LITTLE_ENDIAN) += -D__MIPSEL__ + +CHECKFLAGS = $(CHECKFLAGS-y) + ifdef CONFIG_BUILD_ELF64 gas-abi = 64 ld-emul = $(64bit-emul) @@ -79,9 +94,18 @@ endif cflags-y += -I $(TOPDIR)/include/asm/gcc cflags-y += -G 0 -mno-abicalls -fno-pic -pipe cflags-y += $(call cc-option, -finline-limit=100000) -LDFLAGS_vmlinux += -G 0 -static -n +LDFLAGS_vmlinux += -G 0 -static -n -nostdlib MODFLAGS += -mlong-calls +# +# We explicitly add the endianness specifier if needed, this allows +# to compile kernels with a toolchain for the other endianness. We +# carefully avoid to add it redundantly because gcc 3.3/3.4 complains +# when fed the toolchain default! +# +cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB) +cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL) + cflags-$(CONFIG_SB1XXX_CORELIS) += -mno-sched-prolog -fno-omit-frame-pointer # @@ -167,14 +191,22 @@ cflags-$(CONFIG_CPU_TX49XX) += \ $(call set_gccflags,r4600,mips3,r4600,mips3,mips2) \ -Wa,--trap -cflags-$(CONFIG_CPU_MIPS32) += \ +cflags-$(CONFIG_CPU_MIPS32_R1) += \ $(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \ -Wa,--trap -cflags-$(CONFIG_CPU_MIPS64) += \ +cflags-$(CONFIG_CPU_MIPS32_R2) += \ + $(call set_gccflags,mips32r2,mips32r2,r4600,mips3,mips2) \ + -Wa,--trap + +cflags-$(CONFIG_CPU_MIPS64_R1) += \ $(call set_gccflags,mips64,mips64,r4600,mips3,mips2) \ -Wa,--trap +cflags-$(CONFIG_CPU_MIPS64_R2) += \ + $(call set_gccflags,mips64r2,mips64r2,r4600,mips3,mips2) \ + -Wa,--trap + cflags-$(CONFIG_CPU_R5000) += \ $(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \ -Wa,--trap @@ -196,6 +228,7 @@ cflags-$(CONFIG_CPU_RM9000) += \ $(call set_gccflags,rm9000,mips4,r5000,mips4,mips2) \ -Wa,--trap + cflags-$(CONFIG_CPU_SB1) += \ $(call set_gccflags,sb1,mips64,r5000,mips4,mips2) \ -Wa,--trap @@ -266,6 +299,13 @@ cflags-$(CONFIG_MIPS_PB1550) += -Iinclude/asm-mips/mach-pb1x00 load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 # +# AMD Alchemy Pb1200 eval board +# +libs-$(CONFIG_MIPS_PB1200) += arch/mips/au1000/pb1200/ +cflags-$(CONFIG_MIPS_PB1200) += -Iinclude/asm-mips/mach-pb1x00 +load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000 + +# # AMD Alchemy Db1000 eval board # libs-$(CONFIG_MIPS_DB1000) += arch/mips/au1000/db1x00/ @@ -294,6 +334,13 @@ cflags-$(CONFIG_MIPS_DB1550) += -Iinclude/asm-mips/mach-db1x00 load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 # +# AMD Alchemy Db1200 eval board +# +libs-$(CONFIG_MIPS_DB1200) += arch/mips/au1000/pb1200/ +cflags-$(CONFIG_MIPS_DB1200) += -Iinclude/asm-mips/mach-db1x00 +load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 + +# # AMD Alchemy Bosporus eval board # libs-$(CONFIG_MIPS_BOSPORUS) += arch/mips/au1000/db1x00/ @@ -323,6 +370,7 @@ load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 # Cobalt Server # core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/ +cflags-$(CONFIG_MIPS_COBALT) += -Iinclude/asm-mips/cobalt load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000 # @@ -389,6 +437,13 @@ core-$(CONFIG_MIPS_SEAD) += arch/mips/mips-boards/sead/ load-$(CONFIG_MIPS_SEAD) += 0xffffffff80100000 # +# MIPS SIM +# +core-$(CONFIG_MIPS_SIM) += arch/mips/mips-boards/sim/ +cflags-$(CONFIG_MIPS_SIM) += -Iinclude/asm-mips/mach-sim +load-$(CONFIG_MIPS_SIM) += 0x80100000 + +# # Momentum Ocelot board # # The Ocelot setup.o must be linked early - it does the ioremap() for the @@ -514,6 +569,19 @@ load-$(CONFIG_CASIO_E55) += 0xffffffff80004000 load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000 # +# Common Philips PNX8550 +# +core-$(CONFIG_SOC_PNX8550) += arch/mips/philips/pnx8550/common/ +cflags-$(CONFIG_SOC_PNX8550) += -Iinclude/asm-mips/mach-pnx8550 + +# +# Philips PNX8550 JBS board +# +libs-$(CONFIG_PNX8550_JBS) += arch/mips/philips/pnx8550/jbs/ +#cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550 +load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000 + +# # SGI IP22 (Indy/Indigo2) # # Set the load address to >= 0xffffffff88069000 if you want to leave space for @@ -582,10 +650,20 @@ load-$(CONFIG_SGI_IP32) += 0xffffffff80004000 # removed (as happens, even if they have __initcall/module_init) # core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/sb1250/ -cflags-$(CONFIG_SIBYTE_BCM112X) += -Iinclude/asm-mips/mach-sibyte +cflags-$(CONFIG_SIBYTE_BCM112X) += -Iinclude/asm-mips/mach-sibyte \ + -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/sb1250/ -cflags-$(CONFIG_SIBYTE_SB1250) += -Iinclude/asm-mips/mach-sibyte +cflags-$(CONFIG_SIBYTE_SB1250) += -Iinclude/asm-mips/mach-sibyte \ + -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL + +core-$(CONFIG_SIBYTE_BCM1x55) += arch/mips/sibyte/bcm1480/ +cflags-$(CONFIG_SIBYTE_BCM1x55) += -Iinclude/asm-mips/mach-sibyte \ + -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL + +core-$(CONFIG_SIBYTE_BCM1x80) += arch/mips/sibyte/bcm1480/ +cflags-$(CONFIG_SIBYTE_BCM1x80) += -Iinclude/asm-mips/mach-sibyte \ + -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL # # Sibyte BCM91120x (Carmel) board @@ -593,6 +671,7 @@ cflags-$(CONFIG_SIBYTE_SB1250) += -Iinclude/asm-mips/mach-sibyte # Sibyte BCM91125C (CRhone) board # Sibyte BCM91125E (Rhone) board # Sibyte SWARM board +# Sibyte BCM91x80 (BigSur) board # libs-$(CONFIG_SIBYTE_CARMEL) += arch/mips/sibyte/swarm/ load-$(CONFIG_SIBYTE_CARMEL) := 0xffffffff80100000 @@ -606,6 +685,8 @@ libs-$(CONFIG_SIBYTE_SENTOSA) += arch/mips/sibyte/swarm/ load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000 libs-$(CONFIG_SIBYTE_SWARM) += arch/mips/sibyte/swarm/ load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000 +libs-$(CONFIG_SIBYTE_BIGSUR) += arch/mips/sibyte/swarm/ +load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 # # SNI RM200 PCI @@ -629,6 +710,13 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/toshiba_rbtx4927/ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/ load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000 +# +# Toshiba RBTX4938 board +# +core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/toshiba_rbtx4938/ +core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/common/ +load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000 + cflags-y += -Iinclude/asm-mips/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ @@ -701,10 +789,29 @@ ifdef CONFIG_BOOT_ELF64 all: $(vmlinux-64) endif +ifdef CONFIG_MIPS_ATLAS +all: vmlinux.srec +endif + +ifdef CONFIG_MIPS_MALTA +all: vmlinux.srec +endif + +ifdef CONFIG_MIPS_SEAD +all: vmlinux.srec +endif + +ifdef CONFIG_QEMU +all: vmlinux.bin +endif + ifdef CONFIG_SNI_RM200_PCI all: vmlinux.ecoff endif +vmlinux.bin: $(vmlinux-32) + +@$(call makeboot,$@) + vmlinux.ecoff vmlinux.rm200: $(vmlinux-32) +@$(call makeboot,$@) @@ -720,7 +827,6 @@ archclean: @$(MAKE) $(clean)=arch/mips/boot @$(MAKE) $(clean)=arch/mips/lasat - CLEAN_FILES += vmlinux.32 \ vmlinux.64 \ vmlinux.ecoff diff --git a/arch/mips/arc/Makefile b/arch/mips/arc/Makefile index e8424932e1a3..4f349ec1ea2d 100644 --- a/arch/mips/arc/Makefile +++ b/arch/mips/arc/Makefile @@ -3,7 +3,7 @@ # lib-y += cmdline.o env.o file.o identify.o init.o \ - misc.o time.o tree.o + misc.o salone.o time.o tree.o lib-$(CONFIG_ARC_MEMORY) += memory.o lib-$(CONFIG_ARC_CONSOLE) += arc_con.o diff --git a/arch/mips/arc/identify.c b/arch/mips/arc/identify.c index 0dd7a345eb79..1bd6199e174a 100644 --- a/arch/mips/arc/identify.c +++ b/arch/mips/arc/identify.c @@ -44,6 +44,11 @@ static struct smatch mach_table[] = { MACH_GROUP_SGI, MACH_SGI_IP28, PROM_FLAG_ARCS + }, { "SGI-IP30", + "SGI Octane", + MACH_GROUP_SGI, + MACH_SGI_IP30, + PROM_FLAG_ARCS }, { "SGI-IP32", "SGI O2", MACH_GROUP_SGI, diff --git a/arch/mips/au1000/common/Makefile b/arch/mips/au1000/common/Makefile index 594b75e5e080..a1edfd1f643c 100644 --- a/arch/mips/au1000/common/Makefile +++ b/arch/mips/au1000/common/Makefile @@ -8,7 +8,7 @@ obj-y += prom.o int-handler.o irq.o puts.o time.o reset.o \ au1xxx_irqmap.o clocks.o platform.o power.o setup.o \ - sleeper.o cputable.o dma.o dbdma.o + sleeper.o cputable.o dma.o dbdma.o gpio.o obj-$(CONFIG_AU1X00_USB_DEVICE) += usbdev.o obj-$(CONFIG_KGDB) += dbg_io.o diff --git a/arch/mips/au1000/common/au1xxx_irqmap.c b/arch/mips/au1000/common/au1xxx_irqmap.c index 8a0f39f67c59..0b2c03c52319 100644 --- a/arch/mips/au1000/common/au1xxx_irqmap.c +++ b/arch/mips/au1000/common/au1xxx_irqmap.c @@ -173,14 +173,14 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = { { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0}, { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0}, - { AU1550_TOY_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1550_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1550_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1550_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, - { AU1550_RTC_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1550_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1550_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1550_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, + { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0}, { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, @@ -201,14 +201,14 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = { { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0}, { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0}, - { AU1200_TOY_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1200_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1200_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1200_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, - { AU1200_RTC_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1200_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1200_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1200_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, + { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0}, { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 }, { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0}, diff --git a/arch/mips/au1000/common/cputable.c b/arch/mips/au1000/common/cputable.c index f5521dfccfd6..4dbde82c8215 100644 --- a/arch/mips/au1000/common/cputable.c +++ b/arch/mips/au1000/common/cputable.c @@ -37,7 +37,8 @@ struct cpu_spec cpu_specs[] = { { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 }, { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 }, { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 }, - { 0xffffffff, 0x04030200, "Au1200 AA", 0, 1 }, + { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 }, + { 0xffffffff, 0x04030201, "Au1200 AC", 0, 1 }, { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 }, }; diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c index adfc3172aace..d00e8247d6c2 100644 --- a/arch/mips/au1000/common/dbdma.c +++ b/arch/mips/au1000/common/dbdma.c @@ -29,6 +29,7 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. * */ + #include <linux/config.h> #include <linux/kernel.h> #include <linux/errno.h> @@ -38,10 +39,12 @@ #include <linux/string.h> #include <linux/delay.h> #include <linux/interrupt.h> +#include <linux/module.h> #include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1xxx_dbdma.h> #include <asm/system.h> + #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) /* @@ -61,37 +64,10 @@ static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock); */ #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1)) -static volatile dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; -static int dbdma_initialized; +static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; +static int dbdma_initialized=0; static void au1xxx_dbdma_init(void); -typedef struct dbdma_device_table { - u32 dev_id; - u32 dev_flags; - u32 dev_tsize; - u32 dev_devwidth; - u32 dev_physaddr; /* If FIFO */ - u32 dev_intlevel; - u32 dev_intpolarity; -} dbdev_tab_t; - -typedef struct dbdma_chan_config { - u32 chan_flags; - u32 chan_index; - dbdev_tab_t *chan_src; - dbdev_tab_t *chan_dest; - au1x_dma_chan_t *chan_ptr; - au1x_ddma_desc_t *chan_desc_base; - au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr; - void *chan_callparam; - void (*chan_callback)(int, void *, struct pt_regs *); -} chan_tab_t; - -#define DEV_FLAGS_INUSE (1 << 0) -#define DEV_FLAGS_ANYUSE (1 << 1) -#define DEV_FLAGS_OUT (1 << 2) -#define DEV_FLAGS_IN (1 << 3) - static dbdev_tab_t dbdev_tab[] = { #ifdef CONFIG_SOC_AU1550 /* UARTS */ @@ -157,25 +133,25 @@ static dbdev_tab_t dbdev_tab[] = { { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, + { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, + { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 }, + { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 }, - { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_AES_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, + { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, - { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, - { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, + { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 }, + { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 }, { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 }, - { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, + { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 }, + { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 }, { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 }, + { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 }, + { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 }, { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, @@ -184,6 +160,24 @@ static dbdev_tab_t dbdev_tab[] = { { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + + /* Provide 16 user definable device types */ + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, }; #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t)) @@ -203,6 +197,36 @@ find_dbdev_id (u32 id) return NULL; } +void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp) +{ + return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); +} +EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt); + +u32 +au1xxx_ddma_add_device(dbdev_tab_t *dev) +{ + u32 ret = 0; + dbdev_tab_t *p=NULL; + static u16 new_id=0x1000; + + p = find_dbdev_id(0); + if ( NULL != p ) + { + memcpy(p, dev, sizeof(dbdev_tab_t)); + p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id); + ret = p->dev_id; + new_id++; +#if 0 + printk("add_device: id:%x flags:%x padd:%x\n", + p->dev_id, p->dev_flags, p->dev_physaddr ); +#endif + } + + return ret; +} +EXPORT_SYMBOL(au1xxx_ddma_add_device); + /* Allocate a channel and return a non-zero descriptor if successful. */ u32 @@ -215,7 +239,7 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, int i; dbdev_tab_t *stp, *dtp; chan_tab_t *ctp; - volatile au1x_dma_chan_t *cp; + au1x_dma_chan_t *cp; /* We do the intialization on the first channel allocation. * We have to wait because of the interrupt handler initialization @@ -225,9 +249,6 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, au1xxx_dbdma_init(); dbdma_initialized = 1; - if ((srcid > DSCR_NDEV_IDS) || (destid > DSCR_NDEV_IDS)) - return 0; - if ((stp = find_dbdev_id(srcid)) == NULL) return 0; if ((dtp = find_dbdev_id(destid)) == NULL) return 0; @@ -271,7 +292,6 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, */ ctp = kmalloc(sizeof(chan_tab_t), GFP_KERNEL); chan_tab_ptr[i] = ctp; - ctp->chan_index = chan = i; break; } } @@ -279,10 +299,11 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, if (ctp != NULL) { memset(ctp, 0, sizeof(chan_tab_t)); + ctp->chan_index = chan = i; dcp = DDMA_CHANNEL_BASE; dcp += (0x0100 * chan); ctp->chan_ptr = (au1x_dma_chan_t *)dcp; - cp = (volatile au1x_dma_chan_t *)dcp; + cp = (au1x_dma_chan_t *)dcp; ctp->chan_src = stp; ctp->chan_dest = dtp; ctp->chan_callback = callback; @@ -299,6 +320,9 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, i |= DDMA_CFG_DED; if (dtp->dev_intpolarity) i |= DDMA_CFG_DP; + if ((stp->dev_flags & DEV_FLAGS_SYNC) || + (dtp->dev_flags & DEV_FLAGS_SYNC)) + i |= DDMA_CFG_SYNC; cp->ddma_cfg = i; au_sync(); @@ -309,14 +333,14 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, rv = (u32)(&chan_tab_ptr[chan]); } else { - /* Release devices. - */ + /* Release devices */ stp->dev_flags &= ~DEV_FLAGS_INUSE; dtp->dev_flags &= ~DEV_FLAGS_INUSE; } } return rv; } +EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc); /* Set the device width if source or destination is a FIFO. * Should be 8, 16, or 32 bits. @@ -344,6 +368,7 @@ au1xxx_dbdma_set_devwidth(u32 chanid, int bits) return rv; } +EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth); /* Allocate a descriptor ring, initializing as much as possible. */ @@ -370,7 +395,8 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries) * and if we try that first we are likely to not waste larger * slabs of memory. */ - desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), GFP_KERNEL); + desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), + GFP_KERNEL|GFP_DMA); if (desc_base == 0) return 0; @@ -381,7 +407,7 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries) kfree((const void *)desc_base); i = entries * sizeof(au1x_ddma_desc_t); i += (sizeof(au1x_ddma_desc_t) - 1); - if ((desc_base = (u32)kmalloc(i, GFP_KERNEL)) == 0) + if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0) return 0; desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t)); @@ -403,7 +429,13 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries) cmd0 |= DSCR_CMD0_SID(srcid); cmd0 |= DSCR_CMD0_DID(destid); cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV; - cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_CURRENT); + cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE); + + /* is it mem to mem transfer? */ + if(((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) && + ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS))) { + cmd0 |= DSCR_CMD0_MEM; + } switch (stp->dev_devwidth) { case 8: @@ -461,9 +493,14 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries) /* If source input is fifo, set static address. */ if (stp->dev_flags & DEV_FLAGS_IN) { - src0 = stp->dev_physaddr; + if ( stp->dev_flags & DEV_FLAGS_BURSTABLE ) + src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST); + else src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC); + } + if (stp->dev_physaddr) + src0 = stp->dev_physaddr; /* Set up dest1. For now, assume no stride and increment. * A channel attribute update can change this later. @@ -487,10 +524,18 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries) /* If destination output is fifo, set static address. */ if (dtp->dev_flags & DEV_FLAGS_OUT) { - dest0 = dtp->dev_physaddr; + if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE ) + dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST); + else dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC); } + if (dtp->dev_physaddr) + dest0 = dtp->dev_physaddr; +#if 0 + printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", + dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 ); +#endif for (i=0; i<entries; i++) { dp->dscr_cmd0 = cmd0; dp->dscr_cmd1 = cmd1; @@ -499,6 +544,8 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries) dp->dscr_dest0 = dest0; dp->dscr_dest1 = dest1; dp->dscr_stat = 0; + dp->sw_context = 0; + dp->sw_status = 0; dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1)); dp++; } @@ -511,13 +558,14 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries) return (u32)(ctp->chan_desc_base); } +EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc); /* Put a source buffer into the DMA ring. * This updates the source pointer and byte count. Normally used * for memory to fifo transfers. */ u32 -au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes) +_au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags) { chan_tab_t *ctp; au1x_ddma_desc_t *dp; @@ -544,8 +592,24 @@ au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes) */ dp->dscr_source0 = virt_to_phys(buf); dp->dscr_cmd1 = nbytes; - dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ - ctp->chan_ptr->ddma_dbell = 0xffffffff; /* Make it go */ + /* Check flags */ + if (flags & DDMA_FLAGS_IE) + dp->dscr_cmd0 |= DSCR_CMD0_IE; + if (flags & DDMA_FLAGS_NOIE) + dp->dscr_cmd0 &= ~DSCR_CMD0_IE; + + /* + * There is an errata on the Au1200/Au1550 parts that could result + * in "stale" data being DMA'd. It has to do with the snoop logic on + * the dache eviction buffer. NONCOHERENT_IO is on by default for + * these parts. If it is fixedin the future, these dma_cache_inv will + * just be nothing more than empty macros. See io.h. + * */ + dma_cache_wback_inv((unsigned long)buf, nbytes); + dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ + au_sync(); + dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); + ctp->chan_ptr->ddma_dbell = 0; /* Get next descriptor pointer. */ @@ -555,13 +619,14 @@ au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes) */ return nbytes; } +EXPORT_SYMBOL(_au1xxx_dbdma_put_source); /* Put a destination buffer into the DMA ring. * This updates the destination pointer and byte count. Normally used * to place an empty buffer into the ring for fifo to memory transfers. */ u32 -au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes) +_au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags) { chan_tab_t *ctp; au1x_ddma_desc_t *dp; @@ -583,11 +648,33 @@ au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes) if (dp->dscr_cmd0 & DSCR_CMD0_V) return 0; - /* Load up buffer address and byte count. - */ + /* Load up buffer address and byte count */ + + /* Check flags */ + if (flags & DDMA_FLAGS_IE) + dp->dscr_cmd0 |= DSCR_CMD0_IE; + if (flags & DDMA_FLAGS_NOIE) + dp->dscr_cmd0 &= ~DSCR_CMD0_IE; + dp->dscr_dest0 = virt_to_phys(buf); dp->dscr_cmd1 = nbytes; +#if 0 + printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", + dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0, + dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 ); +#endif + /* + * There is an errata on the Au1200/Au1550 parts that could result in + * "stale" data being DMA'd. It has to do with the snoop logic on the + * dache eviction buffer. NONCOHERENT_IO is on by default for these + * parts. If it is fixedin the future, these dma_cache_inv will just + * be nothing more than empty macros. See io.h. + * */ + dma_cache_inv((unsigned long)buf,nbytes); dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ + au_sync(); + dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); + ctp->chan_ptr->ddma_dbell = 0; /* Get next descriptor pointer. */ @@ -597,6 +684,7 @@ au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes) */ return nbytes; } +EXPORT_SYMBOL(_au1xxx_dbdma_put_dest); /* Get a destination buffer into the DMA ring. * Normally used to get a full buffer from the ring during fifo @@ -646,7 +734,7 @@ void au1xxx_dbdma_stop(u32 chanid) { chan_tab_t *ctp; - volatile au1x_dma_chan_t *cp; + au1x_dma_chan_t *cp; int halt_timeout = 0; ctp = *((chan_tab_t **)chanid); @@ -666,6 +754,7 @@ au1xxx_dbdma_stop(u32 chanid) cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V); au_sync(); } +EXPORT_SYMBOL(au1xxx_dbdma_stop); /* Start using the current descriptor pointer. If the dbdma encounters * a not valid descriptor, it will stop. In this case, we can just @@ -675,17 +764,17 @@ void au1xxx_dbdma_start(u32 chanid) { chan_tab_t *ctp; - volatile au1x_dma_chan_t *cp; + au1x_dma_chan_t *cp; ctp = *((chan_tab_t **)chanid); - cp = ctp->chan_ptr; cp->ddma_desptr = virt_to_phys(ctp->cur_ptr); cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */ au_sync(); - cp->ddma_dbell = 0xffffffff; /* Make it go */ + cp->ddma_dbell = 0; au_sync(); } +EXPORT_SYMBOL(au1xxx_dbdma_start); void au1xxx_dbdma_reset(u32 chanid) @@ -704,15 +793,21 @@ au1xxx_dbdma_reset(u32 chanid) do { dp->dscr_cmd0 &= ~DSCR_CMD0_V; + /* reset our SW status -- this is used to determine + * if a descriptor is in use by upper level SW. Since + * posting can reset 'V' bit. + */ + dp->sw_status = 0; dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); } while (dp != ctp->chan_desc_base); } +EXPORT_SYMBOL(au1xxx_dbdma_reset); u32 au1xxx_get_dma_residue(u32 chanid) { chan_tab_t *ctp; - volatile au1x_dma_chan_t *cp; + au1x_dma_chan_t *cp; u32 rv; ctp = *((chan_tab_t **)chanid); @@ -738,8 +833,7 @@ au1xxx_dbdma_chan_free(u32 chanid) au1xxx_dbdma_stop(chanid); - if (ctp->chan_desc_base != NULL) - kfree(ctp->chan_desc_base); + kfree((void *)ctp->chan_desc_base); stp->dev_flags &= ~DEV_FLAGS_INUSE; dtp->dev_flags &= ~DEV_FLAGS_INUSE; @@ -747,15 +841,16 @@ au1xxx_dbdma_chan_free(u32 chanid) kfree(ctp); } +EXPORT_SYMBOL(au1xxx_dbdma_chan_free); static irqreturn_t dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs) { - u32 intstat; - u32 chan_index; + u32 intstat; + u32 chan_index; chan_tab_t *ctp; au1x_ddma_desc_t *dp; - volatile au1x_dma_chan_t *cp; + au1x_dma_chan_t *cp; intstat = dbdma_gptr->ddma_intstat; au_sync(); @@ -774,19 +869,27 @@ dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs) (ctp->chan_callback)(irq, ctp->chan_callparam, regs); ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); - - return IRQ_HANDLED; + return IRQ_RETVAL(1); } -static void -au1xxx_dbdma_init(void) +static void au1xxx_dbdma_init(void) { + int irq_nr; + dbdma_gptr->ddma_config = 0; dbdma_gptr->ddma_throttle = 0; dbdma_gptr->ddma_inten = 0xffff; au_sync(); - if (request_irq(AU1550_DDMA_INT, dbdma_interrupt, SA_INTERRUPT, +#if defined(CONFIG_SOC_AU1550) + irq_nr = AU1550_DDMA_INT; +#elif defined(CONFIG_SOC_AU1200) + irq_nr = AU1200_DDMA_INT; +#else + #error Unknown Au1x00 SOC +#endif + + if (request_irq(irq_nr, dbdma_interrupt, SA_INTERRUPT, "Au1xxx dbdma", (void *)dbdma_gptr)) printk("Can't get 1550 dbdma irq"); } @@ -797,7 +900,8 @@ au1xxx_dbdma_dump(u32 chanid) chan_tab_t *ctp; au1x_ddma_desc_t *dp; dbdev_tab_t *stp, *dtp; - volatile au1x_dma_chan_t *cp; + au1x_dma_chan_t *cp; + u32 i = 0; ctp = *((chan_tab_t **)chanid); stp = ctp->chan_src; @@ -822,15 +926,64 @@ au1xxx_dbdma_dump(u32 chanid) dp = ctp->chan_desc_base; do { - printk("dp %08x, cmd0 %08x, cmd1 %08x\n", - (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1); - printk("src0 %08x, src1 %08x, dest0 %08x\n", - dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0); - printk("dest1 %08x, stat %08x, nxtptr %08x\n", - dp->dscr_dest1, dp->dscr_stat, dp->dscr_nxtptr); + printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n", + i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1); + printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n", + dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1); + printk("stat %08x, nxtptr %08x\n", + dp->dscr_stat, dp->dscr_nxtptr); dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); } while (dp != ctp->chan_desc_base); } +/* Put a descriptor into the DMA ring. + * This updates the source/destination pointers and byte count. + */ +u32 +au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr ) +{ + chan_tab_t *ctp; + au1x_ddma_desc_t *dp; + u32 nbytes=0; + + /* I guess we could check this to be within the + * range of the table...... + */ + ctp = *((chan_tab_t **)chanid); + + /* We should have multiple callers for a particular channel, + * an interrupt doesn't affect this pointer nor the descriptor, + * so no locking should be needed. + */ + dp = ctp->put_ptr; + + /* If the descriptor is valid, we are way ahead of the DMA + * engine, so just return an error condition. + */ + if (dp->dscr_cmd0 & DSCR_CMD0_V) + return 0; + + /* Load up buffer addresses and byte count. + */ + dp->dscr_dest0 = dscr->dscr_dest0; + dp->dscr_source0 = dscr->dscr_source0; + dp->dscr_dest1 = dscr->dscr_dest1; + dp->dscr_source1 = dscr->dscr_source1; + dp->dscr_cmd1 = dscr->dscr_cmd1; + nbytes = dscr->dscr_cmd1; + /* Allow the caller to specifiy if an interrupt is generated */ + dp->dscr_cmd0 &= ~DSCR_CMD0_IE; + dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V; + ctp->chan_ptr->ddma_dbell = 0; + + /* Get next descriptor pointer. + */ + ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); + + /* return something not zero. + */ + return nbytes; +} + #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ diff --git a/arch/mips/au1000/common/dma.c b/arch/mips/au1000/common/dma.c index 372c33f1353d..1905c6b104f2 100644 --- a/arch/mips/au1000/common/dma.c +++ b/arch/mips/au1000/common/dma.c @@ -39,7 +39,6 @@ #include <linux/string.h> #include <linux/delay.h> #include <linux/interrupt.h> -#include <linux/module.h> #include <asm/system.h> #include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1000_dma.h> diff --git a/arch/mips/au1000/common/gpio.c b/arch/mips/au1000/common/gpio.c new file mode 100644 index 000000000000..5f5915b83142 --- /dev/null +++ b/arch/mips/au1000/common/gpio.c @@ -0,0 +1,119 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include <linux/config.h> +#include <linux/module.h> +#include <au1000.h> +#include <au1xxx_gpio.h> + +#define gpio1 sys +#if !defined(CONFIG_SOC_AU1000) +static AU1X00_GPIO2 * const gpio2 = (AU1X00_GPIO2 *)GPIO2_BASE; + +#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000 + +int au1xxx_gpio2_read(int signal) +{ + signal -= 200; +/* gpio2->dir &= ~(0x01 << signal); //Set GPIO to input */ + return ((gpio2->pinstate >> signal) & 0x01); +} + +void au1xxx_gpio2_write(int signal, int value) +{ + signal -= 200; + + gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << signal) | + (value << signal); +} + +void au1xxx_gpio2_tristate(int signal) +{ + signal -= 200; + gpio2->dir &= ~(0x01 << signal); /* Set GPIO to input */ +} +#endif + +int au1xxx_gpio1_read(int signal) +{ +/* gpio1->trioutclr |= (0x01 << signal); */ + return ((gpio1->pinstaterd >> signal) & 0x01); +} + +void au1xxx_gpio1_write(int signal, int value) +{ + if(value) + gpio1->outputset = (0x01 << signal); + else + gpio1->outputclr = (0x01 << signal); /* Output a Zero */ +} + +void au1xxx_gpio1_tristate(int signal) +{ + gpio1->trioutclr = (0x01 << signal); /* Tristate signal */ +} + + +int au1xxx_gpio_read(int signal) +{ + if(signal >= 200) +#if defined(CONFIG_SOC_AU1000) + return 0; +#else + return au1xxx_gpio2_read(signal); +#endif + else + return au1xxx_gpio1_read(signal); +} + +void au1xxx_gpio_write(int signal, int value) +{ + if(signal >= 200) +#if defined(CONFIG_SOC_AU1000) + ; +#else + au1xxx_gpio2_write(signal, value); +#endif + else + au1xxx_gpio1_write(signal, value); +} + +void au1xxx_gpio_tristate(int signal) +{ + if(signal >= 200) +#if defined(CONFIG_SOC_AU1000) + ; +#else + au1xxx_gpio2_tristate(signal); +#endif + else + au1xxx_gpio1_tristate(signal); +} + +void au1xxx_gpio1_set_inputs(void) +{ + gpio1->pininputen = 0; +} + +EXPORT_SYMBOL(au1xxx_gpio1_set_inputs); +EXPORT_SYMBOL(au1xxx_gpio_tristate); +EXPORT_SYMBOL(au1xxx_gpio_write); +EXPORT_SYMBOL(au1xxx_gpio_read); diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index d1eb5a4a9a19..1339a0979f66 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c @@ -83,7 +83,7 @@ inline void local_disable_irq(unsigned int irq_nr); void (*board_init_irq)(void); #ifdef CONFIG_PM -extern void counter0_irq(int irq, void *dev_id, struct pt_regs *regs); +extern irqreturn_t counter0_irq(int irq, void *dev_id, struct pt_regs *regs); #endif static DEFINE_SPINLOCK(irq_lock); @@ -253,52 +253,72 @@ void restore_local_and_enable(int controller, unsigned long mask) static struct hw_interrupt_type rise_edge_irq_type = { - "Au1000 Rise Edge", - startup_irq, - shutdown_irq, - local_enable_irq, - local_disable_irq, - mask_and_ack_rise_edge_irq, - end_irq, - NULL + .typename = "Au1000 Rise Edge", + .startup = startup_irq, + .shutdown = shutdown_irq, + .enable = local_enable_irq, + .disable = local_disable_irq, + .ack = mask_and_ack_rise_edge_irq, + .end = end_irq, }; static struct hw_interrupt_type fall_edge_irq_type = { - "Au1000 Fall Edge", - startup_irq, - shutdown_irq, - local_enable_irq, - local_disable_irq, - mask_and_ack_fall_edge_irq, - end_irq, - NULL + .typename = "Au1000 Fall Edge", + .startup = startup_irq, + .shutdown = shutdown_irq, + .enable = local_enable_irq, + .disable = local_disable_irq, + .ack = mask_and_ack_fall_edge_irq, + .end = end_irq, }; static struct hw_interrupt_type either_edge_irq_type = { - "Au1000 Rise or Fall Edge", - startup_irq, - shutdown_irq, - local_enable_irq, - local_disable_irq, - mask_and_ack_either_edge_irq, - end_irq, - NULL + .typename = "Au1000 Rise or Fall Edge", + .startup = startup_irq, + .shutdown = shutdown_irq, + .enable = local_enable_irq, + .disable = local_disable_irq, + .ack = mask_and_ack_either_edge_irq, + .end = end_irq, }; static struct hw_interrupt_type level_irq_type = { - "Au1000 Level", - startup_irq, - shutdown_irq, - local_enable_irq, - local_disable_irq, - mask_and_ack_level_irq, - end_irq, - NULL + .typename = "Au1000 Level", + .startup = startup_irq, + .shutdown = shutdown_irq, + .enable = local_enable_irq, + .disable = local_disable_irq, + .ack = mask_and_ack_level_irq, + .end = end_irq, }; #ifdef CONFIG_PM -void startup_match20_interrupt(void) +void startup_match20_interrupt(irqreturn_t (*handler)(int, void *, struct pt_regs *)) { + struct irq_desc *desc = &irq_desc[AU1000_TOY_MATCH2_INT]; + + static struct irqaction action; + memset(&action, 0, sizeof(struct irqaction)); + + /* This is a big problem.... since we didn't use request_irq + * when kernel/irq.c calls probe_irq_xxx this interrupt will + * be probed for usage. This will end up disabling the device :( + * Give it a bogus "action" pointer -- this will keep it from + * getting auto-probed! + * + * By setting the status to match that of request_irq() we + * can avoid it. --cgray + */ + action.dev_id = handler; + action.flags = SA_INTERRUPT; + cpus_clear(action.mask); + action.name = "Au1xxx TOY"; + action.handler = handler; + action.next = NULL; + + desc->action = &action; + desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS); + local_enable_irq(AU1000_TOY_MATCH2_INT); } #endif @@ -426,7 +446,6 @@ void __init arch_init_irq(void) extern int au1xxx_ic0_nr_irqs; cp0_status = read_c0_status(); - memset(irq_desc, 0, sizeof(irq_desc)); set_except_vector(0, au1000_IRQ); /* Initialize interrupt controllers to a safe state. @@ -492,7 +511,7 @@ void intc0_req0_irqdispatch(struct pt_regs *regs) intc0_req0 |= au_readl(IC0_REQ0INT); if (!intc0_req0) return; - +#ifdef AU1000_USB_DEV_REQ_INT /* * Because of the tight timing of SETUP token to reply * transactions, the USB devices-side packet complete @@ -503,7 +522,7 @@ void intc0_req0_irqdispatch(struct pt_regs *regs) do_IRQ(AU1000_USB_DEV_REQ_INT, regs); return; } - +#endif irq = au_ffs(intc0_req0) - 1; intc0_req0 &= ~(1<<irq); do_IRQ(irq, regs); @@ -521,17 +540,7 @@ void intc0_req1_irqdispatch(struct pt_regs *regs) irq = au_ffs(intc0_req1) - 1; intc0_req1 &= ~(1<<irq); -#ifdef CONFIG_PM - if (irq == AU1000_TOY_MATCH2_INT) { - mask_and_ack_rise_edge_irq(irq); - counter0_irq(irq, NULL, regs); - local_enable_irq(irq); - } - else -#endif - { - do_IRQ(irq, regs); - } + do_IRQ(irq, regs); } diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c index 0776b2db5641..1f7b465c8038 100644 --- a/arch/mips/au1000/common/platform.c +++ b/arch/mips/au1000/common/platform.c @@ -7,13 +7,15 @@ * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ +#include <linux/config.h> #include <linux/device.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/resource.h> -#include <asm/mach-au1x00/au1000.h> +#include <asm/mach-au1x00/au1xxx.h> +/* OHCI (USB full speed host controller) */ static struct resource au1xxx_usb_ohci_resources[] = { [0] = { .start = USB_OHCI_BASE, @@ -41,8 +43,252 @@ static struct platform_device au1xxx_usb_ohci_device = { .resource = au1xxx_usb_ohci_resources, }; +/*** AU1100 LCD controller ***/ + +#ifdef CONFIG_FB_AU1100 +static struct resource au1100_lcd_resources[] = { + [0] = { + .start = LCD_PHYS_ADDR, + .end = LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1100_LCD_INT, + .end = AU1100_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1100_lcd_dmamask = ~(u32)0; + +static struct platform_device au1100_lcd_device = { + .name = "au1100-lcd", + .id = 0, + .dev = { + .dma_mask = &au1100_lcd_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(au1100_lcd_resources), + .resource = au1100_lcd_resources, +}; +#endif + +#ifdef CONFIG_SOC_AU1200 +/* EHCI (USB high speed host controller) */ +static struct resource au1xxx_usb_ehci_resources[] = { + [0] = { + .start = USB_EHCI_BASE, + .end = USB_EHCI_BASE + USB_EHCI_LEN - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1000_USB_HOST_INT, + .end = AU1000_USB_HOST_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ehci_dmamask = ~(u32)0; + +static struct platform_device au1xxx_usb_ehci_device = { + .name = "au1xxx-ehci", + .id = 0, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources), + .resource = au1xxx_usb_ehci_resources, +}; + +/* Au1200 UDC (USB gadget controller) */ +static struct resource au1xxx_usb_gdt_resources[] = { + [0] = { + .start = USB_UDC_BASE, + .end = USB_UDC_BASE + USB_UDC_LEN - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_USB_INT, + .end = AU1200_USB_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource au1xxx_mmc_resources[] = { + [0] = { + .start = SD0_PHYS_ADDR, + .end = SD0_PHYS_ADDR + 0x40, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = SD1_PHYS_ADDR, + .end = SD1_PHYS_ADDR + 0x40, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 udc_dmamask = ~(u32)0; + +static struct platform_device au1xxx_usb_gdt_device = { + .name = "au1xxx-udc", + .id = 0, + .dev = { + .dma_mask = &udc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources), + .resource = au1xxx_usb_gdt_resources, +}; + +/* Au1200 UOC (USB OTG controller) */ +static struct resource au1xxx_usb_otg_resources[] = { + [0] = { + .start = USB_UOC_BASE, + .end = USB_UOC_BASE + USB_UOC_LEN - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_USB_INT, + .end = AU1200_USB_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 uoc_dmamask = ~(u32)0; + +static struct platform_device au1xxx_usb_otg_device = { + .name = "au1xxx-uoc", + .id = 0, + .dev = { + .dma_mask = &uoc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources), + .resource = au1xxx_usb_otg_resources, +}; + +static struct resource au1200_lcd_resources[] = { + [0] = { + .start = LCD_PHYS_ADDR, + .end = LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_LCD_INT, + .end = AU1200_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource au1200_ide0_resources[] = { + [0] = { + .start = AU1XXX_ATA_PHYS_ADDR, + .end = AU1XXX_ATA_PHYS_ADDR + AU1XXX_ATA_PHYS_LEN, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1XXX_ATA_INT, + .end = AU1XXX_ATA_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1200_lcd_dmamask = ~(u32)0; + +static struct platform_device au1200_lcd_device = { + .name = "au1200-lcd", + .id = 0, + .dev = { + .dma_mask = &au1200_lcd_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(au1200_lcd_resources), + .resource = au1200_lcd_resources, +}; + + +static u64 ide0_dmamask = ~(u32)0; + +static struct platform_device au1200_ide0_device = { + .name = "au1200-ide", + .id = 0, + .dev = { + .dma_mask = &ide0_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(au1200_ide0_resources), + .resource = au1200_ide0_resources, +}; + +static u64 au1xxx_mmc_dmamask = ~(u32)0; + +static struct platform_device au1xxx_mmc_device = { + .name = "au1xxx-mmc", + .id = 0, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(au1xxx_mmc_resources), + .resource = au1xxx_mmc_resources, +}; +#endif /* #ifdef CONFIG_SOC_AU1200 */ + +static struct platform_device au1x00_pcmcia_device = { + .name = "au1x00-pcmcia", + .id = 0, +}; + +#ifdef CONFIG_MIPS_DB1200 + +static struct resource smc91x_resources[] = { + [0] = { + .name = "smc91x-regs", + .start = AU1XXX_SMC91111_PHYS_ADDR, + .end = AU1XXX_SMC91111_PHYS_ADDR + 0xfffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1XXX_SMC91111_IRQ, + .end = AU1XXX_SMC91111_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +#endif + static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xxx_usb_ohci_device, + &au1x00_pcmcia_device, +#ifdef CONFIG_FB_AU1100 + &au1100_lcd_device, +#endif +#ifdef CONFIG_SOC_AU1200 +#if 0 /* fixme */ + &au1xxx_usb_ehci_device, +#endif + &au1xxx_usb_gdt_device, + &au1xxx_usb_otg_device, + &au1200_lcd_device, + &au1200_ide0_device, + &au1xxx_mmc_device, +#endif +#ifdef CONFIG_MIPS_DB1200 + &smc91x_device, +#endif }; int au1xxx_platform_init(void) diff --git a/arch/mips/au1000/common/power.c b/arch/mips/au1000/common/power.c index c40daccbb5b1..f85093b8d54d 100644 --- a/arch/mips/au1000/common/power.c +++ b/arch/mips/au1000/common/power.c @@ -34,11 +34,13 @@ #include <linux/pm.h> #include <linux/slab.h> #include <linux/sysctl.h> +#include <linux/jiffies.h> #include <asm/string.h> #include <asm/uaccess.h> #include <asm/io.h> #include <asm/system.h> +#include <asm/cacheflush.h> #include <asm/mach-au1x00/au1000.h> #ifdef CONFIG_PM @@ -50,7 +52,7 @@ # define DPRINTK(fmt, args...) #endif -static void calibrate_delay(void); +static void au1000_calibrate_delay(void); extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); @@ -260,7 +262,7 @@ int au_sleep(void) } static int pm_do_sleep(ctl_table * ctl, int write, struct file *file, - void *buffer, size_t * len) + void __user *buffer, size_t * len, loff_t *ppos) { int retval = 0; #ifdef SLEEP_TEST_TIMEOUT @@ -294,10 +296,9 @@ static int pm_do_sleep(ctl_table * ctl, int write, struct file *file, } static int pm_do_suspend(ctl_table * ctl, int write, struct file *file, - void *buffer, size_t * len) + void __user *buffer, size_t * len, loff_t *ppos) { int retval = 0; - void au1k_wait(void); if (!write) { *len = 0; @@ -306,7 +307,7 @@ static int pm_do_suspend(ctl_table * ctl, int write, struct file *file, if (retval) return retval; suspend_mode = 1; - au1k_wait(); + retval = pm_send_all(PM_RESUME, (void *) 0); } return retval; @@ -314,7 +315,7 @@ static int pm_do_suspend(ctl_table * ctl, int write, struct file *file, static int pm_do_freq(ctl_table * ctl, int write, struct file *file, - void *buffer, size_t * len) + void __user *buffer, size_t * len, loff_t *ppos) { int retval = 0, i; unsigned long val, pll; @@ -409,14 +410,14 @@ static int pm_do_freq(ctl_table * ctl, int write, struct file *file, /* We don't want _any_ interrupts other than - * match20. Otherwise our calibrate_delay() + * match20. Otherwise our au1000_calibrate_delay() * calculation will be off, potentially a lot. */ intc0_mask = save_local_and_disable(0); intc1_mask = save_local_and_disable(1); local_enable_irq(AU1000_TOY_MATCH2_INT); spin_unlock_irqrestore(&pm_lock, flags); - calibrate_delay(); + au1000_calibrate_delay(); restore_local_and_enable(0, intc0_mask); restore_local_and_enable(1, intc1_mask); return retval; @@ -456,7 +457,7 @@ __initcall(pm_init); better than 1% */ #define LPS_PREC 8 -static void calibrate_delay(void) +static void au1000_calibrate_delay(void) { unsigned long ticks, loopbit; int lps_precision = LPS_PREC; diff --git a/arch/mips/au1000/common/prom.c b/arch/mips/au1000/common/prom.c index 22e5a85af4d5..9c171afd9a53 100644 --- a/arch/mips/au1000/common/prom.c +++ b/arch/mips/au1000/common/prom.c @@ -75,7 +75,8 @@ void prom_init_cmdline(void) } if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ --cp; - *cp = '\0'; + if (prom_argc > 1) + *cp = '\0'; } diff --git a/arch/mips/au1000/common/puts.c b/arch/mips/au1000/common/puts.c index c2ae4624b77b..2705829cd466 100644 --- a/arch/mips/au1000/common/puts.c +++ b/arch/mips/au1000/common/puts.c @@ -39,7 +39,6 @@ #define TIMEOUT 0xffffff #define SLOW_DOWN -static const char digits[16] = "0123456789abcdef"; static volatile unsigned long * const com1 = (unsigned long *)SERIAL_BASE; @@ -54,7 +53,7 @@ static inline void slow_down(void) #endif void -putch(const unsigned char c) +prom_putchar(const unsigned char c) { unsigned char ch; int i = 0; @@ -69,77 +68,3 @@ putch(const unsigned char c) } while (0 == (ch & TX_BUSY)); com1[SER_DATA] = c; } - -void -puts(unsigned char *cp) -{ - unsigned char ch; - int i = 0; - - while (*cp) { - do { - ch = com1[SER_CMD]; - slow_down(); - i++; - if (i>TIMEOUT) { - break; - } - } while (0 == (ch & TX_BUSY)); - com1[SER_DATA] = *cp++; - } - putch('\r'); - putch('\n'); -} - -void -fputs(const char *cp) -{ - unsigned char ch; - int i = 0; - - while (*cp) { - - do { - ch = com1[SER_CMD]; - slow_down(); - i++; - if (i>TIMEOUT) { - break; - } - } while (0 == (ch & TX_BUSY)); - com1[SER_DATA] = *cp++; - } -} - - -void -put64(uint64_t ul) -{ - int cnt; - unsigned ch; - - cnt = 16; /* 16 nibbles in a 64 bit long */ - putch('0'); - putch('x'); - do { - cnt--; - ch = (unsigned char)(ul >> cnt * 4) & 0x0F; - putch(digits[ch]); - } while (cnt > 0); -} - -void -put32(unsigned u) -{ - int cnt; - unsigned ch; - - cnt = 8; /* 8 nibbles in a 32 bit long */ - putch('0'); - putch('x'); - do { - cnt--; - ch = (unsigned char)(u >> cnt * 4) & 0x0F; - putch(digits[ch]); - } while (cnt > 0); -} diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c index eff89e109ce6..1ef15d5ef943 100644 --- a/arch/mips/au1000/common/setup.c +++ b/arch/mips/au1000/common/setup.c @@ -32,6 +32,7 @@ #include <linux/mm.h> #include <linux/delay.h> #include <linux/interrupt.h> +#include <linux/module.h> #include <asm/cpu.h> #include <asm/bootinfo.h> @@ -57,7 +58,7 @@ extern void au1xxx_time_init(void); extern void au1xxx_timer_setup(struct irqaction *irq); extern void set_cpuspec(void); -static int __init au1x00_setup(void) +void __init plat_setup(void) { struct cpu_spec *sp; char *argptr; @@ -106,8 +107,6 @@ static int __init au1x00_setup(void) /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/ #ifdef CONFIG_MIPS_HYDROGEN3 strcat(argptr, " video=au1100fb:panel:Hydrogen_3_NEC_panel_320x240,nohwcursor"); -#else - strcat(argptr, " video=au1100fb:panel:s10,nohwcursor"); #endif } #endif @@ -153,15 +152,11 @@ static int __init au1x00_setup(void) au_sync(); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); au_writel(0, SYS_TOYTRIM); - - return 0; } -early_initcall(au1x00_setup); - #if defined(CONFIG_64BIT_PHYS_ADDR) /* This routine should be valid for all Au1x based boards */ -phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) +phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) { u32 start, end; @@ -192,4 +187,5 @@ phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) /* default nop */ return phys_addr; } +EXPORT_SYMBOL(__fixup_bigphys_addr); #endif diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index 57675b41480e..883d3f3d8c53 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -50,7 +50,6 @@ #include <linux/mc146818rtc.h> #include <linux/timex.h> -extern void startup_match20_interrupt(void); extern void do_softirq(void); extern volatile unsigned long wall_jiffies; unsigned long missed_heart_beats = 0; @@ -58,14 +57,17 @@ unsigned long missed_heart_beats = 0; static unsigned long r4k_offset; /* Amount to increment compare reg each time */ static unsigned long r4k_cur; /* What counter should be at next timer irq */ int no_au1xxx_32khz; -void (*au1k_wait_ptr)(void); +extern int allow_au1k_wait; /* default off for CP0 Counter */ /* Cycle counter value at the previous timer interrupt.. */ static unsigned int timerhi = 0, timerlo = 0; #ifdef CONFIG_PM -#define MATCH20_INC 328 -extern void startup_match20_interrupt(void); +#if HZ < 100 || HZ > 1000 +#error "unsupported HZ value! Must be in [100,1000]" +#endif +#define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */ +extern void startup_match20_interrupt(irqreturn_t (*handler)(int, void *, struct pt_regs *)); static unsigned long last_pc0, last_match20; #endif @@ -117,17 +119,16 @@ null: } #ifdef CONFIG_PM -void counter0_irq(int irq, void *dev_id, struct pt_regs *regs) +irqreturn_t counter0_irq(int irq, void *dev_id, struct pt_regs *regs) { unsigned long pc0; int time_elapsed; static int jiffie_drift = 0; - kstat.irqs[0][irq]++; if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) { /* should never happen! */ - printk(KERN_WARNING "counter 0 w status eror\n"); - return; + printk(KERN_WARNING "counter 0 w status error\n"); + return IRQ_NONE; } pc0 = au_readl(SYS_TOYREAD); @@ -164,6 +165,8 @@ void counter0_irq(int irq, void *dev_id, struct pt_regs *regs) update_process_times(user_mode(regs)); #endif } + + return IRQ_HANDLED; } /* When we wakeup from sleep, we have to "catch up" on all of the @@ -388,7 +391,6 @@ void au1xxx_timer_setup(struct irqaction *irq) { unsigned int est_freq; extern unsigned long (*do_gettimeoffset)(void); - extern void au1k_wait(void); printk("calculating r4koff... "); r4k_offset = cal_r4koff(); @@ -441,18 +443,18 @@ void au1xxx_timer_setup(struct irqaction *irq) au_sync(); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); - /* setup match20 to interrupt once every 10ms */ + /* setup match20 to interrupt once every HZ */ last_pc0 = last_match20 = au_readl(SYS_TOYREAD); au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); au_sync(); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); - startup_match20_interrupt(); + startup_match20_interrupt(counter0_irq); do_gettimeoffset = do_fast_pm_gettimeoffset; /* We can use the real 'wait' instruction. */ - au1k_wait_ptr = au1k_wait; + allow_au1k_wait = 1; } #else diff --git a/arch/mips/au1000/common/usbdev.c b/arch/mips/au1000/common/usbdev.c index 447a9a4612a8..0b21bed7ee55 100644 --- a/arch/mips/au1000/common/usbdev.c +++ b/arch/mips/au1000/common/usbdev.c @@ -1005,11 +1005,11 @@ process_ep0_receive (struct usb_dev* dev) #endif dev->ep0_stage = SETUP_STAGE; break; - } + } spin_unlock(&ep0->lock); - // we're done processing the packet, free it - kfree(pkt); + // we're done processing the packet, free it + kfree(pkt); } @@ -1072,8 +1072,7 @@ dma_done_ep0_intr(int irq, void *dev_id, struct pt_regs *regs) clear_dma_done1(ep0->indma); pkt = send_packet_complete(ep0); - if (pkt) - kfree(pkt); + kfree(pkt); } /* @@ -1302,8 +1301,7 @@ usbdev_exit(void) endpoint_flush(ep); } - if (usbdev.full_conf_desc) - kfree(usbdev.full_conf_desc); + kfree(usbdev.full_conf_desc); } int diff --git a/arch/mips/au1000/csb250/init.c b/arch/mips/au1000/csb250/init.c index bd99733abc0b..a4898b1bc66a 100644 --- a/arch/mips/au1000/csb250/init.c +++ b/arch/mips/au1000/csb250/init.c @@ -35,7 +35,6 @@ #include <asm/bootinfo.h> #include <linux/string.h> #include <linux/kernel.h> -#include <linux/sched.h> int prom_argc; char **prom_argv, **prom_envp; diff --git a/arch/mips/au1000/db1x00/irqmap.c b/arch/mips/au1000/db1x00/irqmap.c index 8f6ef0dbe1f8..f63024a9893a 100644 --- a/arch/mips/au1000/db1x00/irqmap.c +++ b/arch/mips/au1000/db1x00/irqmap.c @@ -48,6 +48,38 @@ #include <asm/system.h> #include <asm/mach-au1x00/au1000.h> +#ifdef CONFIG_MIPS_DB1500 +char irq_tab_alchemy[][5] __initdata = { + [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT371 */ + [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */ +}; +#endif + +#ifdef CONFIG_MIPS_BOSPORUS +char irq_tab_alchemy[][5] __initdata = { + [11] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 11 - miniPCI */ + [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - SN1741 */ + [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */ +}; +#endif + +#ifdef CONFIG_MIPS_MIRAGE +char irq_tab_alchemy[][5] __initdata = { + [11] = { -1, INTD, INTX, INTX, INTX}, /* IDSEL 11 - SMI VGX */ + [12] = { -1, INTX, INTX, INTC, INTX}, /* IDSEL 12 - PNX1300 */ + [13] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 13 - miniPCI */ +}; +#endif + +#ifdef CONFIG_MIPS_DB1550 +char irq_tab_alchemy[][5] __initdata = { + [11] = { -1, INTC, INTX, INTX, INTX}, /* IDSEL 11 - on-board HPT371 */ + [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */ + [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */ +}; +#endif + + au1xxx_irq_map_t au1xxx_irq_map[] = { #ifndef CONFIG_MIPS_MIRAGE diff --git a/arch/mips/au1000/db1x00/mirage_ts.c b/arch/mips/au1000/db1x00/mirage_ts.c index ade35e432004..c29852c24b4f 100644 --- a/arch/mips/au1000/db1x00/mirage_ts.c +++ b/arch/mips/au1000/db1x00/mirage_ts.c @@ -102,15 +102,15 @@ static struct { } mirage_ts_cal = { #if 0 - xscale: 84, - xtrans: -157, - yscale: 66, - ytrans: -150, + .xscale = 84, + .xtrans = -157, + .yscale = 66, + .ytrans = -150, #else - xscale: 84, - xtrans: -150, - yscale: 66, - ytrans: -146, + .xscale = 84, + .xtrans = -150, + .yscale = 66, + .ytrans = -146, #endif }; diff --git a/arch/mips/au1000/hydrogen3/init.c b/arch/mips/au1000/hydrogen3/init.c index 8cc9879dd582..01ab28483959 100644 --- a/arch/mips/au1000/hydrogen3/init.c +++ b/arch/mips/au1000/hydrogen3/init.c @@ -37,7 +37,6 @@ #include <linux/config.h> #include <linux/string.h> #include <linux/kernel.h> -#include <linux/sched.h> int prom_argc; char **prom_argv, **prom_envp; diff --git a/arch/mips/au1000/mtx-1/init.c b/arch/mips/au1000/mtx-1/init.c index 02e7dbcff727..88f2b6d97281 100644 --- a/arch/mips/au1000/mtx-1/init.c +++ b/arch/mips/au1000/mtx-1/init.c @@ -33,7 +33,6 @@ #include <linux/sched.h> #include <linux/init.h> #include <linux/mm.h> -#include <linux/sched.h> #include <linux/bootmem.h> #include <asm/addrspace.h> #include <asm/bootinfo.h> diff --git a/arch/mips/au1000/mtx-1/irqmap.c b/arch/mips/au1000/mtx-1/irqmap.c index ddcb9d089dc1..f9a0a8b9def2 100644 --- a/arch/mips/au1000/mtx-1/irqmap.c +++ b/arch/mips/au1000/mtx-1/irqmap.c @@ -47,6 +47,17 @@ #include <asm/system.h> #include <asm/mach-au1x00/au1000.h> +char irq_tab_alchemy[][5] __initdata = { + [0] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 00 - AdapterA-Slot0 (top) */ + [1] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 01 - AdapterA-Slot1 (bottom) */ + [2] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 02 - AdapterB-Slot0 (top) */ + [3] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 03 - AdapterB-Slot1 (bottom) */ + [4] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 04 - AdapterC-Slot0 (top) */ + [5] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 05 - AdapterC-Slot1 (bottom) */ + [6] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 06 - AdapterD-Slot0 (top) */ + [7] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 07 - AdapterD-Slot1 (bottom) */ +}; + au1xxx_irq_map_t au1xxx_irq_map[] = { { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0}, { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, diff --git a/arch/mips/au1000/pb1000/init.c b/arch/mips/au1000/pb1000/init.c index 34713c5df0d7..e9fa1bab81f3 100644 --- a/arch/mips/au1000/pb1000/init.c +++ b/arch/mips/au1000/pb1000/init.c @@ -65,5 +65,4 @@ void __init prom_init(void) memsize = simple_strtol(memsize_str, NULL, 0); } add_memory_region(0, memsize, BOOT_MEM_RAM); - return 0; } diff --git a/arch/mips/au1000/pb1200/Makefile b/arch/mips/au1000/pb1200/Makefile new file mode 100644 index 000000000000..22b673cf55af --- /dev/null +++ b/arch/mips/au1000/pb1200/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the Alchemy Semiconductor PB1200 board. +# + +lib-y := init.o board_setup.o irqmap.o diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c new file mode 100644 index 000000000000..a45b17538ac9 --- /dev/null +++ b/arch/mips/au1000/pb1200/board_setup.c @@ -0,0 +1,193 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Alchemy Pb1200/Db1200 board setup. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include <linux/config.h> +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/ioport.h> +#include <linux/mm.h> +#include <linux/console.h> +#include <linux/mc146818rtc.h> +#include <linux/delay.h> + +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX) +#include <linux/ide.h> +#endif + +#include <asm/cpu.h> +#include <asm/bootinfo.h> +#include <asm/irq.h> +#include <asm/mipsregs.h> +#include <asm/reboot.h> +#include <asm/pgtable.h> +#include <asm/mach-au1x00/au1000.h> +#include <asm/mach-au1x00/au1xxx_dbdma.h> + +#ifdef CONFIG_MIPS_PB1200 +#include <asm/mach-pb1x00/pb1200.h> +#endif + +#ifdef CONFIG_MIPS_DB1200 +#include <asm/mach-db1x00/db1200.h> +#define PB1200_ETH_INT DB1200_ETH_INT +#define PB1200_IDE_INT DB1200_IDE_INT +#endif + +extern void _board_init_irq(void); +extern void (*board_init_irq)(void); + +void board_reset (void) +{ + bcsr->resets = 0; + bcsr->system = 0; +} + +void __init board_setup(void) +{ + char *argptr = NULL; + u32 pin_func; + +#if 0 + /* Enable PSC1 SYNC for AC97. Normaly done in audio driver, + * but it is board specific code, so put it here. + */ + pin_func = au_readl(SYS_PINFUNC); + au_sync(); + pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; + au_writel(pin_func, SYS_PINFUNC); + + au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */ + au_sync(); +#endif + +#if defined(CONFIG_I2C_AU1550) + { + u32 freq0, clksrc; + + /* Select SMBUS in CPLD */ + bcsr->resets &= ~(BCSR_RESETS_PCS0MUX); + + pin_func = au_readl(SYS_PINFUNC); + au_sync(); + pin_func &= ~(3<<17 | 1<<4); + /* Set GPIOs correctly */ + pin_func |= 2<<17; + au_writel(pin_func, SYS_PINFUNC); + au_sync(); + + /* The i2c driver depends on 50Mhz clock */ + freq0 = au_readl(SYS_FREQCTRL0); + au_sync(); + freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1); + freq0 |= (3<<SYS_FC_FRDIV1_BIT); + /* 396Mhz / (3+1)*2 == 49.5Mhz */ + au_writel(freq0, SYS_FREQCTRL0); + au_sync(); + freq0 |= SYS_FC_FE1; + au_writel(freq0, SYS_FREQCTRL0); + au_sync(); + + clksrc = au_readl(SYS_CLKSRC); + au_sync(); + clksrc &= ~0x01f00000; + /* bit 22 is EXTCLK0 for PSC0 */ + clksrc |= (0x3 << 22); + au_writel(clksrc, SYS_CLKSRC); + au_sync(); + } +#endif + +#ifdef CONFIG_FB_AU1200 + argptr = prom_getcmdline(); +#ifdef CONFIG_MIPS_PB1200 + strcat(argptr, " video=au1200fb:panel:bs"); +#endif +#ifdef CONFIG_MIPS_DB1200 + strcat(argptr, " video=au1200fb:panel:bs"); +#endif +#endif + + /* The Pb1200 development board uses external MUX for PSC0 to + support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI + */ +#if defined(CONFIG_AU1XXX_PSC_SPI) && defined(CONFIG_I2C_AU1550) + #error I2C and SPI are mutually exclusive. Both are physically connected to PSC0.\ + Refer to Pb1200/Db1200 documentation. +#elif defined( CONFIG_AU1XXX_PSC_SPI ) + bcsr->resets |= BCSR_RESETS_PCS0MUX; + /*Hard Coding Value to enable Temp Sensors [bit 14] Value for SOC Au1200. Pls refer documentation*/ + bcsr->resets =0x900f; +#elif defined( CONFIG_I2C_AU1550 ) + bcsr->resets &= (~BCSR_RESETS_PCS0MUX); +#endif + au_sync(); + +#ifdef CONFIG_MIPS_PB1200 + printk("AMD Alchemy Pb1200 Board\n"); +#endif +#ifdef CONFIG_MIPS_DB1200 + printk("AMD Alchemy Db1200 Board\n"); +#endif + + /* Setup Pb1200 External Interrupt Controller */ + { + extern void (*board_init_irq)(void); + extern void _board_init_irq(void); + board_init_irq = _board_init_irq; + } +} + +int +board_au1200fb_panel (void) +{ + BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; + int p; + + p = bcsr->switches; + p >>= 8; + p &= 0x0F; + return p; +} + +int +board_au1200fb_panel_init (void) +{ + /* Apply power */ + BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; + bcsr->board |= (BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL); + /*printk("board_au1200fb_panel_init()\n"); */ + return 0; +} + +int +board_au1200fb_panel_shutdown (void) +{ + /* Remove power */ + BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; + bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL); + /*printk("board_au1200fb_panel_shutdown()\n"); */ + return 0; +} + diff --git a/arch/mips/au1000/pb1200/init.c b/arch/mips/au1000/pb1200/init.c new file mode 100644 index 000000000000..27f09e374e15 --- /dev/null +++ b/arch/mips/au1000/pb1200/init.c @@ -0,0 +1,69 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * PB1200 board setup + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/bootmem.h> +#include <asm/addrspace.h> +#include <asm/bootinfo.h> +#include <linux/string.h> +#include <linux/kernel.h> + +int prom_argc; +char **prom_argv, **prom_envp; +extern void __init prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "Alchemy Pb1200"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = (int) fw_arg0; + prom_argv = (char **) fw_arg1; + prom_envp = (char **) fw_arg2; + + mips_machgroup = MACH_GROUP_ALCHEMY; + mips_machtype = MACH_PB1200; + + prom_init_cmdline(); + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + memsize = 0x08000000; + } else { + memsize = simple_strtol(memsize_str, NULL, 0); + } + add_memory_region(0, memsize, BOOT_MEM_RAM); +} diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c new file mode 100644 index 000000000000..59e70e5cf325 --- /dev/null +++ b/arch/mips/au1000/pb1200/irqmap.c @@ -0,0 +1,182 @@ +/* + * BRIEF MODULE DESCRIPTION + * Au1xxx irq map table + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include <linux/config.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/kernel_stat.h> +#include <linux/module.h> +#include <linux/signal.h> +#include <linux/sched.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/timex.h> +#include <linux/slab.h> +#include <linux/random.h> +#include <linux/delay.h> + +#include <asm/bitops.h> +#include <asm/bootinfo.h> +#include <asm/io.h> +#include <asm/mipsregs.h> +#include <asm/system.h> +#include <asm/mach-au1x00/au1000.h> + +#ifdef CONFIG_MIPS_PB1200 +#include <asm/mach-pb1x00/pb1200.h> +#endif + +#ifdef CONFIG_MIPS_DB1200 +#include <asm/mach-db1x00/db1200.h> +#define PB1200_INT_BEGIN DB1200_INT_BEGIN +#define PB1200_INT_END DB1200_INT_END +#endif + +au1xxx_irq_map_t au1xxx_irq_map[] = { + { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade +}; + +int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); + +/* + * Support for External interrupts on the PbAu1200 Development platform. + */ +static volatile int pb1200_cascade_en=0; + +irqreturn_t pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs) +{ + unsigned short bisr = bcsr->int_status; + int extirq_nr = 0; + + /* Clear all the edge interrupts. This has no effect on level */ + bcsr->int_status = bisr; + for( ; bisr; bisr &= (bisr-1) ) + { + extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr); + /* Ack and dispatch IRQ */ + do_IRQ(extirq_nr,regs); + } + return IRQ_RETVAL(1); +} + +inline void pb1200_enable_irq(unsigned int irq_nr) +{ + bcsr->intset_mask = 1<<(irq_nr - PB1200_INT_BEGIN); + bcsr->intset = 1<<(irq_nr - PB1200_INT_BEGIN); +} + +inline void pb1200_disable_irq(unsigned int irq_nr) +{ + bcsr->intclr_mask = 1<<(irq_nr - PB1200_INT_BEGIN); + bcsr->intclr = 1<<(irq_nr - PB1200_INT_BEGIN); +} + +static unsigned int pb1200_startup_irq( unsigned int irq_nr ) +{ + if (++pb1200_cascade_en == 1) + { + request_irq(AU1000_GPIO_7, &pb1200_cascade_handler, + 0, "Pb1200 Cascade", (void *)&pb1200_cascade_handler ); +#ifdef CONFIG_MIPS_PB1200 + /* We have a problem with CPLD rev3. Enable a workaround */ + if( ((bcsr->whoami & BCSR_WHOAMI_CPLD)>>4) <= 3) + { + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("Pb1200 must be at CPLD rev4. Please have Pb1200\n"); + printk("updated to latest revision. This software will not\n"); + printk("work on anything less than CPLD rev4\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + while(1); + } +#endif + } + pb1200_enable_irq(irq_nr); + return 0; +} + +static void pb1200_shutdown_irq( unsigned int irq_nr ) +{ + pb1200_disable_irq(irq_nr); + if (--pb1200_cascade_en == 0) + { + free_irq(AU1000_GPIO_7,&pb1200_cascade_handler ); + } + return; +} + +static inline void pb1200_mask_and_ack_irq(unsigned int irq_nr) +{ + pb1200_disable_irq( irq_nr ); +} + +static void pb1200_end_irq(unsigned int irq_nr) +{ + if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { + pb1200_enable_irq(irq_nr); + } +} + +static struct hw_interrupt_type external_irq_type = +{ +#ifdef CONFIG_MIPS_PB1200 + "Pb1200 Ext", +#endif +#ifdef CONFIG_MIPS_DB1200 + "Db1200 Ext", +#endif + pb1200_startup_irq, + pb1200_shutdown_irq, + pb1200_enable_irq, + pb1200_disable_irq, + pb1200_mask_and_ack_irq, + pb1200_end_irq, + NULL +}; + +void _board_init_irq(void) +{ + int irq_nr; + + for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++) + { + irq_desc[irq_nr].handler = &external_irq_type; + pb1200_disable_irq(irq_nr); + } + + /* GPIO_7 can not be hooked here, so it is hooked upon first + request of any source attached to the cascade */ +} + diff --git a/arch/mips/au1000/pb1500/irqmap.c b/arch/mips/au1000/pb1500/irqmap.c index 476e25001681..8cb76c2edb5e 100644 --- a/arch/mips/au1000/pb1500/irqmap.c +++ b/arch/mips/au1000/pb1500/irqmap.c @@ -47,6 +47,11 @@ #include <asm/system.h> #include <asm/mach-au1x00/au1000.h> +char irq_tab_alchemy[][5] __initdata = { + [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT370 */ + [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */ +}; + au1xxx_irq_map_t au1xxx_irq_map[] = { { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0}, { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, diff --git a/arch/mips/au1000/pb1550/irqmap.c b/arch/mips/au1000/pb1550/irqmap.c index 889d4949ee76..47c7a1c19f4b 100644 --- a/arch/mips/au1000/pb1550/irqmap.c +++ b/arch/mips/au1000/pb1550/irqmap.c @@ -47,6 +47,11 @@ #include <asm/system.h> #include <asm/mach-au1x00/au1000.h> +char irq_tab_alchemy[][5] __initdata = { + [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */ + [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */ +}; + au1xxx_irq_map_t au1xxx_irq_map[] = { { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile index efbeac326815..0dc84417bf49 100644 --- a/arch/mips/boot/Makefile +++ b/arch/mips/boot/Makefile @@ -33,6 +33,9 @@ vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX) $(obj)/elf2ecoff: $(obj)/elf2ecoff.c $(HOSTCC) -o $@ $^ +vmlinux.bin: $(VMLINUX) + $(OBJCOPY) -O binary $(strip-flags) $(VMLINUX) $(obj)/vmlinux.bin + vmlinux.srec: $(VMLINUX) $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec @@ -45,5 +48,6 @@ archhelp: clean-files += addinitrd \ elf2ecoff \ + vmlinux.bin \ vmlinux.ecoff \ vmlinux.srec diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile index a5e6554b2326..3b6b7579d1de 100644 --- a/arch/mips/cobalt/Makefile +++ b/arch/mips/cobalt/Makefile @@ -2,6 +2,6 @@ # Makefile for the Cobalt micro systems family specific parts of the kernel # -obj-y := irq.o int-handler.o reset.o setup.o promcon.o +obj-y := irq.o int-handler.o reset.o setup.o EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/cobalt/int-handler.S b/arch/mips/cobalt/int-handler.S index 1a21dec1b3ca..f92608e8d84f 100644 --- a/arch/mips/cobalt/int-handler.S +++ b/arch/mips/cobalt/int-handler.S @@ -18,8 +18,8 @@ SAVE_ALL CLI - la ra, ret_from_irq - move a1, sp + PTR_LA ra, ret_from_irq + move a0, sp j cobalt_irq END(cobalt_handle_int) diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c index 6d2a81581397..0d90851f925e 100644 --- a/arch/mips/cobalt/irq.c +++ b/arch/mips/cobalt/irq.c @@ -10,6 +10,8 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/pci.h> #include <asm/i8259.h> #include <asm/irq_cpu.h> @@ -25,8 +27,8 @@ extern void cobalt_handle_int(void); * the CPU interrupt lines, and ones that come in on the via chip. The CPU * mappings are: * - * 16, - Software interrupt 0 (unused) IE_SW0 - * 17 - Software interrupt 1 (unused) IE_SW0 + * 16 - Software interrupt 0 (unused) IE_SW0 + * 17 - Software interrupt 1 (unused) IE_SW1 * 18 - Galileo chip (timer) IE_IRQ0 * 19 - Tulip 0 + NCR SCSI IE_IRQ1 * 20 - Tulip 1 IE_IRQ2 @@ -42,61 +44,94 @@ extern void cobalt_handle_int(void); * 15 - IDE1 */ -asmlinkage void cobalt_irq(struct pt_regs *regs) +static inline void galileo_irq(struct pt_regs *regs) { - unsigned int pending = read_c0_status() & read_c0_cause(); - - if (pending & CAUSEF_IP2) { /* int 18 */ - unsigned long irq_src = GALILEO_INL(GT_INTRCAUSE_OFS); - - /* Check for timer irq ... */ - if (irq_src & GALILEO_T0EXP) { - /* Clear the int line */ - GALILEO_OUTL(0, GT_INTRCAUSE_OFS); - do_IRQ(COBALT_TIMER_IRQ, regs); - } - return; - } + unsigned int mask, pending, devfn; - if (pending & CAUSEF_IP6) { /* int 22 */ - int irq = i8259_irq(); + mask = GALILEO_INL(GT_INTRMASK_OFS); + pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask; - if (irq >= 0) - do_IRQ(irq, regs); - return; - } + if (pending & GALILEO_INTR_T0EXP) { - if (pending & CAUSEF_IP3) { /* int 19 */ - do_IRQ(COBALT_ETH0_IRQ, regs); - return; - } + GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS); + do_IRQ(COBALT_GALILEO_IRQ, regs); - if (pending & CAUSEF_IP4) { /* int 20 */ - do_IRQ(COBALT_ETH1_IRQ, regs); - return; - } + } else if (pending & GALILEO_INTR_RETRY_CTR) { - if (pending & CAUSEF_IP5) { /* int 21 */ - do_IRQ(COBALT_SERIAL_IRQ, regs); - return; - } + devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8; + GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS); + printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n", + PCI_SLOT(devfn), PCI_FUNC(devfn)); + + } else { - if (pending & CAUSEF_IP7) { /* int 23 */ - do_IRQ(COBALT_QUBE_SLOT_IRQ, regs); - return; + GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS); + printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending); } } +static inline void via_pic_irq(struct pt_regs *regs) +{ + int irq; + + irq = i8259_irq(); + if (irq >= 0) + do_IRQ(irq, regs); +} + +asmlinkage void cobalt_irq(struct pt_regs *regs) +{ + unsigned pending; + + pending = read_c0_status() & read_c0_cause(); + + if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */ + + galileo_irq(regs); + + else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */ + + via_pic_irq(regs); + + else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */ + + do_IRQ(COBALT_CPU_IRQ + 3, regs); + + else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */ + + do_IRQ(COBALT_CPU_IRQ + 4, regs); + + else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */ + + do_IRQ(COBALT_CPU_IRQ + 5, regs); + + else if (pending & CAUSEF_IP7) /* IRQ 23 */ + + do_IRQ(COBALT_CPU_IRQ + 7, regs); +} + +static struct irqaction irq_via = { + no_action, 0, { { 0, } }, "cascade", NULL, NULL +}; + void __init arch_init_irq(void) { + /* + * Mask all Galileo interrupts. The Galileo + * handler is set in cobalt_timer_setup() + */ + GALILEO_OUTL(0, GT_INTRMASK_OFS); + set_except_vector(0, cobalt_handle_int); init_i8259_irqs(); /* 0 ... 15 */ - mips_cpu_irq_init(16); /* 16 ... 23 */ + mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */ /* * Mask all cpu interrupts * (except IE4, we already masked those at VIA level) */ change_c0_status(ST0_IM, IE_IRQ4); + + setup_irq(COBALT_VIA_IRQ, &irq_via); } diff --git a/arch/mips/cobalt/promcon.c b/arch/mips/cobalt/promcon.c deleted file mode 100644 index f03df761e9f1..000000000000 --- a/arch/mips/cobalt/promcon.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * PROM console for Cobalt Raq2 - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 1997 by Ralf Baechle - * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv) - * - */ - -#include <linux/init.h> -#include <linux/console.h> -#include <linux/kdev_t.h> -#include <linux/serial_reg.h> - -#include <asm/delay.h> -#include <asm/serial.h> -#include <asm/io.h> - -static unsigned long port = 0xc800000; - -static __inline__ void ns16550_cons_put_char(char ch, unsigned long ioaddr) -{ - char lsr; - - do { - lsr = inb(ioaddr + UART_LSR); - } while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE)); - outb(ch, ioaddr + UART_TX); -} - -static __inline__ char ns16550_cons_get_char(unsigned long ioaddr) -{ - while ((inb(ioaddr + UART_LSR) & UART_LSR_DR) == 0) - udelay(1); - return inb(ioaddr + UART_RX); -} - -void ns16550_console_write(struct console *co, const char *s, unsigned count) -{ - char lsr, ier; - unsigned i; - - ier = inb(port + UART_IER); - outb(0x00, port + UART_IER); - for (i=0; i < count; i++, s++) { - - if(*s == '\n') - ns16550_cons_put_char('\r', port); - ns16550_cons_put_char(*s, port); - } - - do { - lsr = inb(port + UART_LSR); - } while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE)); - - outb(ier, port + UART_IER); -} - -char getDebugChar(void) -{ - return ns16550_cons_get_char(port); -} - -void putDebugChar(char kgdb_char) -{ - ns16550_cons_put_char(kgdb_char, port); -} - -static struct console ns16550_console = { - .name = "prom", - .setup = NULL, - .write = ns16550_console_write, - .flags = CON_PRINTBUFFER, - .index = -1, -}; - -static int __init ns16550_setup_console(void) -{ - register_console(&ns16550_console); - - return 0; -} - -console_initcall(ns16550_setup_console); diff --git a/arch/mips/cobalt/reset.c b/arch/mips/cobalt/reset.c index 084c8e59f42c..805a0e88507b 100644 --- a/arch/mips/cobalt/reset.c +++ b/arch/mips/cobalt/reset.c @@ -16,48 +16,45 @@ #include <asm/reboot.h> #include <asm/system.h> #include <asm/mipsregs.h> +#include <asm/cobalt/cobalt.h> -void cobalt_machine_restart(char *command) +void cobalt_machine_halt(void) { - *(volatile char *)0xbc000000 = 0x0f; + int state, last, diff; + unsigned long mark; /* - * Ouch, we're still alive ... This time we take the silver bullet ... - * ... and find that we leave the hardware in a state in which the - * kernel in the flush locks up somewhen during of after the PCI - * detection stuff. + * turn off bar on Qube, flash power off LED on RaQ (0.5Hz) + * + * restart if ENTER and SELECT are pressed */ - set_c0_status(ST0_BEV | ST0_ERL); - change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); - flush_cache_all(); - write_c0_wired(0); - __asm__ __volatile__( - "jr\t%0" - : - : "r" (0xbfc00000)); -} -extern int led_state; -#define kLED 0xBC000000 -#define LEDSet(x) (*(volatile unsigned char *) kLED) = (( unsigned char)x) + last = COBALT_KEY_PORT; -void cobalt_machine_halt(void) -{ - int mark; + for (state = 0;;) { + + state ^= COBALT_LED_POWER_OFF; + COBALT_LED_PORT = state; + + diff = COBALT_KEY_PORT ^ last; + last ^= diff; - /* Blink our cute? little LED (number 3)... */ - while (1) { - led_state = led_state | ( 1 << 3 ); - LEDSet(led_state); - mark = jiffies; - while (jiffies<(mark+HZ)); - led_state = led_state & ~( 1 << 3 ); - LEDSet(led_state); - mark = jiffies; - while (jiffies<(mark+HZ)); + if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT))) + COBALT_LED_PORT = COBALT_LED_RESET; + + for (mark = jiffies; jiffies - mark < HZ;) + ; } } +void cobalt_machine_restart(char *command) +{ + COBALT_LED_PORT = COBALT_LED_RESET; + + /* we should never get here */ + cobalt_machine_halt(); +} + /* * This triggers the luser mode device driver for the power switch ;-) */ diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index 6b4737e425ed..d358a118fa31 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -13,6 +13,8 @@ #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/init.h> +#include <linux/serial.h> +#include <linux/serial_core.h> #include <asm/bootinfo.h> #include <asm/time.h> @@ -21,6 +23,7 @@ #include <asm/processor.h> #include <asm/reboot.h> #include <asm/gt64120.h> +#include <asm/serial.h> #include <asm/cobalt/cobalt.h> @@ -30,45 +33,44 @@ extern void cobalt_machine_power_off(void); int cobalt_board_id; -static char my_cmdline[CL_SIZE] = { - "console=ttyS0,115200 " -#ifdef CONFIG_IP_PNP - "ip=on " -#endif -#ifdef CONFIG_ROOT_NFS - "root=/dev/nfs " -#else - "root=/dev/hda1 " -#endif - }; - const char *get_system_type(void) { + switch (cobalt_board_id) { + case COBALT_BRD_ID_QUBE1: + return "Cobalt Qube"; + case COBALT_BRD_ID_RAQ1: + return "Cobalt RaQ"; + case COBALT_BRD_ID_QUBE2: + return "Cobalt Qube2"; + case COBALT_BRD_ID_RAQ2: + return "Cobalt RaQ2"; + } return "MIPS Cobalt"; } static void __init cobalt_timer_setup(struct irqaction *irq) { - /* Load timer value for 150 Hz */ - GALILEO_OUTL(500000, GT_TC0_OFS); + /* Load timer value for 1KHz (TCLK is 50MHz) */ + GALILEO_OUTL(50*1000*1000 / 1000, GT_TC0_OFS); - /* Register our timer interrupt */ - setup_irq(COBALT_TIMER_IRQ, irq); + /* Enable timer */ + GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS); - /* Enable timer ints */ - GALILEO_OUTL((GALILEO_ENTC0 | GALILEO_SELTC0), GT_TC_CONTROL_OFS); - /* Unmask timer int */ - GALILEO_OUTL(0x100, GT_INTRMASK_OFS); + /* Register interrupt */ + setup_irq(COBALT_GALILEO_IRQ, irq); + + /* Enable interrupt */ + GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); } extern struct pci_ops gt64111_pci_ops; static struct resource cobalt_mem_resource = { - "GT64111 PCI MEM", GT64111_IO_BASE, 0xffffffffUL, IORESOURCE_MEM + "PCI memory", GT64111_MEM_BASE, GT64111_MEM_END, IORESOURCE_MEM }; static struct resource cobalt_io_resource = { - "GT64111 IO MEM", 0x00001000UL, 0x0fffffffUL, IORESOURCE_IO + "PCI I/O", 0x1000, 0xffff, IORESOURCE_IO }; static struct resource cobalt_io_resources[] = { @@ -86,11 +88,12 @@ static struct pci_controller cobalt_pci_controller = { .mem_resource = &cobalt_mem_resource, .mem_offset = 0, .io_resource = &cobalt_io_resource, - .io_offset = 0x00001000UL - GT64111_IO_BASE + .io_offset = 0 - GT64111_IO_BASE }; -static void __init cobalt_setup(void) +void __init plat_setup(void) { + static struct uart_port uart; unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0); int i; @@ -100,7 +103,10 @@ static void __init cobalt_setup(void) board_timer_setup = cobalt_timer_setup; - set_io_port_base(KSEG1ADDR(GT64111_IO_BASE)); + set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE)); + + /* I/O port resource must include UART and LCD/buttons */ + ioport_resource.end = 0x0fffffff; /* * This is a prom style console. We just poke at the @@ -120,27 +126,61 @@ static void __init cobalt_setup(void) cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8); cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id); + printk("Cobalt board ID: %d\n", cobalt_board_id); + #ifdef CONFIG_PCI register_pci_controller(&cobalt_pci_controller); #endif -} -early_initcall(cobalt_setup); +#ifdef CONFIG_SERIAL_8250 + if (cobalt_board_id > COBALT_BRD_ID_RAQ1) { + + uart.line = 0; + uart.type = PORT_UNKNOWN; + uart.uartclk = 18432000; + uart.irq = COBALT_SERIAL_IRQ; + uart.flags = STD_COM_FLAGS; + uart.iobase = 0xc800000; + uart.iotype = UPIO_PORT; + + early_serial_setup(&uart); + } +#endif +} /* * Prom init. We read our one and only communication with the firmware. - * Grab the amount of installed memory + * Grab the amount of installed memory. + * Better boot loaders (CoLo) pass a command line too :-) */ void __init prom_init(void) { - int argc = fw_arg0; - - strcpy(arcs_cmdline, my_cmdline); + int narg, indx, posn, nchr; + unsigned long memsz; + char **argv; mips_machgroup = MACH_GROUP_COBALT; - add_memory_region(0x0, argc & 0x7fffffff, BOOT_MEM_RAM); + memsz = fw_arg0 & 0x7fff0000; + narg = fw_arg0 & 0x0000ffff; + + if (narg) { + arcs_cmdline[0] = '\0'; + argv = (char **) fw_arg1; + posn = 0; + for (indx = 1; indx < narg; ++indx) { + nchr = strlen(argv[indx]); + if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline)) + break; + if (posn) + arcs_cmdline[posn++] = ' '; + strcpy(arcs_cmdline + posn, argv[indx]); + posn += nchr; + } + } + + add_memory_region(0x0, memsz, BOOT_MEM_RAM); } unsigned long __init prom_free_prom_memory(void) diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig index 3120a02b8670..132ec3dac63f 100644 --- a/arch/mips/configs/atlas_defconfig +++ b/arch/mips/configs/atlas_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:00 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:13 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,42 +59,72 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set CONFIG_MIPS_ATLAS=y # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_MIPS_BONITO64=y CONFIG_MIPS_MSC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y CONFIG_MIPS_BOARDS_GEN=y CONFIG_MIPS_GT64120=y CONFIG_SWAP_IO_SPACE=y @@ -101,8 +134,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS64 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -118,15 +153,46 @@ CONFIG_CPU_MIPS32=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R1=y +CONFIG_SYS_HAS_CPU_NEVADA=y +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +CONFIG_BOARD_SCACHE=y +CONFIG_RM7000_CPU_SCACHE=y CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -135,7 +201,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -144,10 +209,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -160,199 +221,7 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -CONFIG_BLK_DEV_UMEM=m -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_CRYPTOLOOP=m -CONFIG_BLK_DEV_NBD=m -# CONFIG_BLK_DEV_SX8 is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_ATA_OVER_ETH=m - -# -# ATA/ATAPI/MFM/RLL support -# -CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -CONFIG_BLK_DEV_IDECD=y -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set -# CONFIG_IDE_TASK_IOCTL is not set - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=y -# CONFIG_BLK_DEV_IDEPCI is not set -# CONFIG_IDE_ARM is not set -# CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI device support -# -CONFIG_SCSI=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=m -CONFIG_CHR_DEV_OSST=m -CONFIG_BLK_DEV_SR=m -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=m - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y - -# -# SCSI Transport Attributes -# -CONFIG_SCSI_SPI_ATTRS=y -CONFIG_SCSI_FC_ATTRS=m -CONFIG_SCSI_ISCSI_ATTRS=m - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -CONFIG_SCSI_SYM53C8XX_2=y -CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0 -CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 -CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 -# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -# CONFIG_SCSI_QLOGIC_FC is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -CONFIG_SCSI_QLA2XXX=y -# CONFIG_SCSI_QLA21XX is not set -# CONFIG_SCSI_QLA22XX is not set -# CONFIG_SCSI_QLA2300 is not set -# CONFIG_SCSI_QLA2322 is not set -# CONFIG_SCSI_QLA6312 is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Multi-device support (RAID and LVM) -# -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID5=m -CONFIG_MD_RAID6=m -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -CONFIG_DM_ZERO=m - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Networking support +# Networking # CONFIG_NET=y @@ -361,15 +230,20 @@ CONFIG_NET=y # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m CONFIG_NET_KEY=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_FWMARK=y CONFIG_IP_ROUTE_MULTIPATH=y +# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y @@ -387,8 +261,10 @@ CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -CONFIG_IP_TCPDIAG_IPV6=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y # # IP: Virtual Server Configuration @@ -433,6 +309,9 @@ CONFIG_IPV6_TUNNEL=m CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set CONFIG_BRIDGE_NETFILTER=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m # # IP: Netfilter Configuration @@ -440,11 +319,15 @@ CONFIG_BRIDGE_NETFILTER=y CONFIG_IP_NF_CONNTRACK=m CONFIG_IP_NF_CT_ACCT=y CONFIG_IP_NF_CONNTRACK_MARK=y +CONFIG_IP_NF_CONNTRACK_EVENTS=y +CONFIG_IP_NF_CONNTRACK_NETLINK=m CONFIG_IP_NF_CT_PROTO_SCTP=m CONFIG_IP_NF_FTP=m CONFIG_IP_NF_IRC=m +# CONFIG_IP_NF_NETBIOS_NS is not set CONFIG_IP_NF_TFTP=m CONFIG_IP_NF_AMANDA=m +CONFIG_IP_NF_PPTP=m CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_LIMIT=m @@ -469,9 +352,12 @@ CONFIG_IP_NF_MATCH_PHYSDEV=m CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_REALM=m CONFIG_IP_NF_MATCH_SCTP=m +CONFIG_IP_NF_MATCH_DCCP=m CONFIG_IP_NF_MATCH_COMMENT=m CONFIG_IP_NF_MATCH_CONNMARK=m +CONFIG_IP_NF_MATCH_CONNBYTES=m CONFIG_IP_NF_MATCH_HASHLIMIT=m +CONFIG_IP_NF_MATCH_STRING=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -488,12 +374,14 @@ CONFIG_IP_NF_NAT_IRC=m CONFIG_IP_NF_NAT_FTP=m CONFIG_IP_NF_NAT_TFTP=m CONFIG_IP_NF_NAT_AMANDA=m +CONFIG_IP_NF_NAT_PPTP=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_TOS=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_DSCP=m CONFIG_IP_NF_TARGET_MARK=m CONFIG_IP_NF_TARGET_CLASSIFY=m +CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_TARGET_CONNMARK=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m @@ -503,7 +391,7 @@ CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # -# IPv6: Netfilter Configuration +# IPv6: Netfilter Configuration (EXPERIMENTAL) # CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m @@ -523,8 +411,10 @@ CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_PHYSDEV=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_MARK=m +CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_RAW=m # @@ -550,8 +440,11 @@ CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_ULOG=m -CONFIG_XFRM=y -CONFIG_XFRM_USER=m + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set # # SCTP Configuration (EXPERIMENTAL) @@ -579,10 +472,6 @@ CONFIG_IPDDP_DECAP=y CONFIG_NET_DIVERT=y # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# CONFIG_NET_SCHED=y CONFIG_NET_SCH_CLK_JIFFIES=y # CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set @@ -602,6 +491,7 @@ CONFIG_NET_SCH_INGRESS=m CONFIG_NET_QOS=y CONFIG_NET_ESTIMATOR=y CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_ROUTE=y @@ -612,6 +502,7 @@ CONFIG_NET_CLS_IND=y # CONFIG_CLS_U32_MARK is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_EMATCH is not set # CONFIG_NET_CLS_ACT is not set CONFIG_NET_CLS_POLICE=y @@ -619,17 +510,222 @@ CONFIG_NET_CLS_POLICE=y # Network testing # # CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +CONFIG_BLK_DEV_UMEM=m +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_LBD is not set +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_ATA_OVER_ETH=m + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECD=y +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +# CONFIG_BLK_DEV_IDEPCI is not set +# CONFIG_IDE_ARM is not set +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=m +CONFIG_CHR_DEV_SCH=m + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y + +# +# SCSI Transport Attributes +# +CONFIG_SCSI_SPI_ATTRS=y +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m + +# +# SCSI low-level drivers +# +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_SCSI_SATA is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +CONFIG_SCSI_SYM53C8XX_2=y +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0 +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_FC is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +CONFIG_SCSI_QLA2XXX=y +# CONFIG_SCSI_QLA21XX is not set +# CONFIG_SCSI_QLA22XX is not set +# CONFIG_SCSI_QLA2300 is not set +# CONFIG_SCSI_QLA2322 is not set +# CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_QLA24XX is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID5=m +CONFIG_MD_RAID6=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_EMC=m + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# CONFIG_NETDEVICES=y CONFIG_DUMMY=m CONFIG_BONDING=m CONFIG_EQUALIZER=m CONFIG_TUN=m -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -637,6 +733,21 @@ CONFIG_TUN=m # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -681,13 +792,17 @@ CONFIG_LAN_SAA9730=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -700,6 +815,8 @@ CONFIG_LAN_SAA9730=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # Wan interfaces @@ -712,6 +829,8 @@ CONFIG_LAN_SAA9730=y # CONFIG_NET_FC is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -741,19 +860,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -766,6 +872,17 @@ CONFIG_MOUSE_SERIAL=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -786,6 +903,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -812,6 +930,11 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -822,10 +945,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -845,7 +978,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -855,13 +987,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -879,10 +1007,15 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set @@ -903,12 +1036,14 @@ CONFIG_JFS_SECURITY=y # CONFIG_JFS_STATISTICS is not set CONFIG_FS_POSIX_ACL=y CONFIG_XFS_FS=m -# CONFIG_XFS_RT is not set -CONFIG_XFS_QUOTA=y +CONFIG_XFS_EXPORT=y +CONFIG_XFS_QUOTA=m CONFIG_XFS_SECURITY=y CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set CONFIG_MINIX_FS=m CONFIG_ROMFS_FS=m +CONFIG_INOTIFY=y CONFIG_QUOTA=y # CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=y @@ -916,6 +1051,7 @@ CONFIG_QUOTACTL=y CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=y # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -943,12 +1079,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -974,16 +1108,19 @@ CONFIG_UFS_FS=m # CONFIG_NFS_FS=y CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=y CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set # CONFIG_NFSD_V4 is not set # CONFIG_NFSD_TCP is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -992,6 +1129,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -1051,7 +1189,9 @@ CONFIG_NLS_UTF8=m # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -1073,6 +1213,7 @@ CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_TWOFISH=m @@ -1097,9 +1238,12 @@ CONFIG_CRYPTO_CRC32C=m # Library routines # # CONFIG_CRC_CCITT is not set +CONFIG_CRC16=m CONFIG_CRC32=y CONFIG_LIBCRC32C=m CONFIG_ZLIB_INFLATE=m CONFIG_ZLIB_DEFLATE=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig new file mode 100644 index 000000000000..25e8a08e68be --- /dev/null +++ b/arch/mips/configs/bigsur_defconfig @@ -0,0 +1,881 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:17 2005 +# +CONFIG_MIPS=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +# CONFIG_HOTPLUG is not set +CONFIG_KOBJECT_UEVENT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_CPUSETS is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SHMEM=y +CONFIG_CC_ALIGN_FUNCTIONS=0 +CONFIG_CC_ALIGN_LABELS=0 +CONFIG_CC_ALIGN_LOOPS=0 +CONFIG_CC_ALIGN_JUMPS=0 +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_KMOD=y +CONFIG_STOP_MACHINE=y + +# +# Machine selection +# +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_3 is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +CONFIG_SIBYTE_BIGSUR=y +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +CONFIG_SIBYTE_BCM1x80=y +CONFIG_SIBYTE_SB1xxx_SOC=y +# CONFIG_CPU_SB1_PASS_1 is not set +# CONFIG_CPU_SB1_PASS_2_1250 is not set +# CONFIG_CPU_SB1_PASS_2_2 is not set +# CONFIG_CPU_SB1_PASS_4 is not set +# CONFIG_CPU_SB1_PASS_2_112x is not set +# CONFIG_CPU_SB1_PASS_3 is not set +# CONFIG_SIMULATION is not set +# CONFIG_CONFIG_SB1_CEX_ALWAYS_FATAL is not set +# CONFIG_CONFIG_SB1_CERR_STALL is not set +CONFIG_SIBYTE_CFE=y +# CONFIG_SIBYTE_CFE_CONSOLE is not set +# CONFIG_SIBYTE_BUS_WATCHER is not set +# CONFIG_SIBYTE_SB1250_PROF is not set +# CONFIG_SIBYTE_TBPROF is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_DMA_COHERENT=y +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +CONFIG_CPU_SB1=y +CONFIG_SYS_HAS_CPU_SB1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +# CONFIG_32BIT is not set +CONFIG_64BIT=y +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_SIBYTE_DMA_PAGEOPS is not set +# CONFIG_MIPS_MT is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_PREEMPT_BKL is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_DEBUG=y +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# PCI Hotplug Support +# +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_BUILD_ELF64=y +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_MIPS32_O32=y +# CONFIG_MIPS32_N32 is not set +CONFIG_BINFMT_ELF32=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_RAM is not set +CONFIG_BLK_DEV_RAM_COUNT=16 +# CONFIG_CDROM_PKTCDVD is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_ATA_OVER_ETH is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECD=y +CONFIG_BLK_DEV_IDETAPE=y +CONFIG_BLK_DEV_IDEFLOPPY=y +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +# CONFIG_BLK_DEV_IDEPCI is not set +# CONFIG_BLK_DEV_IDE_SWARM is not set +# CONFIG_IDE_ARM is not set +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set + +# +# PHY device support +# +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +CONFIG_NET_SB1250_MAC=y +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_CHELSIO_T1 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_DIGIEPCA is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_ISI is not set +# CONFIG_SYNCLINKMP is not set +# CONFIG_N_HDLC is not set +# CONFIG_SPECIALIX is not set +# CONFIG_SX is not set +# CONFIG_STALDRV is not set +CONFIG_SIBYTE_SB1250_DUART=y +CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_RTC is not set +CONFIG_GEN_RTC=y +# CONFIG_GEN_RTC_X is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set +CONFIG_I2C_ALGO_SIBYTE=y + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +CONFIG_I2C_SIBYTE=y +# CONFIG_SCx200_ACB is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set +# CONFIG_I2C_PCA_ISA is not set + +# +# Miscellaneous I2C Chip support +# +CONFIG_SENSORS_DS1337=y +CONFIG_SENSORS_DS1374=y +CONFIG_SENSORS_EEPROM=y +CONFIG_SENSORS_PCF8574=y +CONFIG_SENSORS_PCA9539=y +CONFIG_SENSORS_PCF8591=y +CONFIG_SENSORS_RTC8564=y +CONFIG_SENSORS_MAX6875=y +CONFIG_I2C_DEBUG_CORE=y +CONFIG_I2C_DEBUG_ALGO=y +CONFIG_I2C_DEBUG_BUS=y +CONFIG_I2C_DEBUG_CHIP=y + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# +# Misc devices +# + +# +# Multimedia Capabilities Port drivers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB is not set + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# InfiniBand support +# +# CONFIG_INFINIBAND is not set + +# +# SN Devices +# + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_RELAYFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_KERNEL=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_FS is not set +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="" +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_KGDB is not set +# CONFIG_SB1XXX_CORELIS is not set +# CONFIG_RUNTIME_DEBUG is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_TEA=m +# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig index 158e7165f4e3..bfbaa08c47cb 100644 --- a/arch/mips/configs/capcella_defconfig +++ b/arch/mips/configs/capcella_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:00 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:20 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,57 +59,86 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -CONFIG_MACH_VR41XX=y -# CONFIG_NEC_CMBVR4133 is not set -# CONFIG_CASIO_E55 is not set -# CONFIG_IBM_WORKPAD is not set -# CONFIG_TANBAC_TB0226 is not set -# CONFIG_TANBAC_TB0229 is not set -# CONFIG_VICTOR_MPC30X is not set -CONFIG_ZAO_CAPCELLA=y -CONFIG_PCI_VR41XX=y -CONFIG_VRC4173=y -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +CONFIG_MACH_VR41XX=y +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_NEC_CMBVR4133 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_TANBAC_TB022X is not set +# CONFIG_VICTOR_MPC30X is not set +CONFIG_ZAO_CAPCELLA=y +CONFIG_PCI_VR41XX=y +# CONFIG_VRC4173 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set CONFIG_CPU_VR41XX=y @@ -122,12 +154,36 @@ CONFIG_CPU_VR41XX=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_VR41XX=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -136,7 +192,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -145,10 +200,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -161,6 +212,81 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -169,7 +295,12 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) @@ -188,7 +319,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -199,11 +329,8 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_CDROM_PKTCDVD is not set # # IO Schedulers @@ -244,6 +371,7 @@ CONFIG_IDE_GENERIC=y # # SCSI device support # +# CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # @@ -254,6 +382,7 @@ CONFIG_IDE_GENERIC=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -266,79 +395,13 @@ CONFIG_IDE_GENERIC=y # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing +# Network device support # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -346,10 +409,25 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set +CONFIG_MII=y # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set @@ -359,7 +437,30 @@ CONFIG_NET_ETHERNET=y # # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set -# CONFIG_NET_PCI is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +CONFIG_8139TOO=y +CONFIG_8139TOO_PIO=y +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139TOO_8129 is not set +# CONFIG_8139_OLD_RX_RESET is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_LAN_SAA9730 is not set # # Ethernet (1000 Mbit) @@ -371,12 +472,17 @@ CONFIG_NET_ETHERNET=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -389,6 +495,8 @@ CONFIG_NET_ETHERNET=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # Wan interfaces @@ -400,6 +508,8 @@ CONFIG_NET_ETHERNET=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -419,29 +529,13 @@ CONFIG_INPUT=y # # Userland interfaces # -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=m -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -451,6 +545,12 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -461,16 +561,16 @@ CONFIG_HW_CONSOLE=y # # Serial drivers # -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_VR41XX=y +CONFIG_SERIAL_VR41XX_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -483,19 +583,7 @@ CONFIG_LEGACY_PTY_COUNT=256 # # Watchdog Cards # -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set - -# -# PCI-based Watchdog Cards -# -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_WDTPCI is not set +# CONFIG_WATCHDOG is not set # CONFIG_RTC is not set # CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set @@ -506,9 +594,15 @@ CONFIG_WATCHDOG=y # Ftape, the floppy tape device driver # # CONFIG_DRM is not set +CONFIG_GPIO_VR41XX=y # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -519,10 +613,20 @@ CONFIG_WATCHDOG=y # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -542,7 +646,6 @@ CONFIG_WATCHDOG=y # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -552,13 +655,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -576,21 +675,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -611,12 +718,10 @@ CONFIG_AUTOFS4_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -648,6 +753,7 @@ CONFIG_NFSD=y CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -656,6 +762,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -676,9 +783,11 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" +CONFIG_CMDLINE="mem=32M console=ttyVR0,38400" # # Security options @@ -690,7 +799,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -700,7 +833,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set +CONFIG_CRC16=m +CONFIG_CRC32=y CONFIG_LIBCRC32C=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index 4302c6f914f5..4b4d1ddb3d42 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:00 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:23 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -50,41 +53,69 @@ CONFIG_CC_ALIGN_JUMPS=0 # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set CONFIG_MIPS_COBALT=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_I8259=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_GT64111=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -92,8 +123,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -109,14 +142,38 @@ CONFIG_CPU_NEVADA=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_NEVADA=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -125,7 +182,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -134,10 +190,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -150,6 +202,77 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=y +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=y +CONFIG_IEEE80211_CRYPT_CCMP=y +CONFIG_IEEE80211_CRYPT_TKIP=y + +# # Device Drivers # @@ -161,6 +284,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y # +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=y + +# # Memory Technology Devices (MTD) # # CONFIG_MTD is not set @@ -177,7 +305,6 @@ CONFIG_FW_LOADER=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -189,7 +316,6 @@ CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=y CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -234,6 +360,7 @@ CONFIG_IDE_GENERIC=y # # SCSI device support # +CONFIG_RAID_ATTRS=y # CONFIG_SCSI is not set # @@ -244,6 +371,7 @@ CONFIG_IDE_GENERIC=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -256,75 +384,13 @@ CONFIG_IDE_GENERIC=y # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=y -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=y - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing +# Network device support # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -332,6 +398,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=y +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -357,12 +438,16 @@ CONFIG_NET_ETHERNET=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -375,6 +460,8 @@ CONFIG_NET_ETHERNET=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=y # # Wan interfaces @@ -386,6 +473,8 @@ CONFIG_NET_ETHERNET=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -415,19 +504,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -437,6 +513,17 @@ CONFIG_SERIO_RAW=y # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -457,6 +544,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -483,6 +571,11 @@ CONFIG_COBALT_LCD=y # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -493,10 +586,20 @@ CONFIG_COBALT_LCD=y # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -516,7 +619,6 @@ CONFIG_COBALT_LCD=y # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -526,13 +628,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -550,12 +648,17 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set CONFIG_FS_MBCACHE=y @@ -565,10 +668,12 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=y # # CD-ROM/DVD Filesystems @@ -589,12 +694,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=y # # Miscellaneous filesystems @@ -622,7 +725,7 @@ CONFIG_NFS_FS=y # CONFIG_NFS_DIRECTIO is not set # CONFIG_NFSD is not set CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -631,6 +734,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -651,7 +755,9 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -665,7 +771,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_KHAZAD=y +CONFIG_CRYPTO_ANUBIS=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -675,7 +805,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CRC16=y +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index 962fc14b58c2..6501144ec612 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:01 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:26 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,63 +59,79 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +CONFIG_MIPS_DB1000=y +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -CONFIG_SOC_AU1X00=y -CONFIG_SOC_AU1000=y -# CONFIG_SOC_AU1100 is not set -# CONFIG_SOC_AU1500 is not set -# CONFIG_SOC_AU1550 is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -CONFIG_MIPS_DB1000=y -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_MIPS_MTX1 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SOC_AU1000=y +CONFIG_SOC_AU1X00=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS64 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -128,15 +147,39 @@ CONFIG_CPU_MIPS32=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set CONFIG_64BIT_PHYS_ADDR=y # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -152,6 +195,8 @@ CONFIG_MMU=y CONFIG_PCCARD=m # CONFIG_PCMCIA_DEBUG is not set CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y # # PC-card bridges @@ -169,6 +214,100 @@ CONFIG_PCMCIA=m CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +CONFIG_IP_NF_PPTP=m +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m # # Device Drivers @@ -179,12 +318,86 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) # -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_AMDSTD_RETRY=0 +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_ALCHEMY=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set # # Parallel port support @@ -198,14 +411,12 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -228,6 +439,7 @@ CONFIG_ATA_OVER_ETH=m # # SCSI device support # +CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set # @@ -238,6 +450,7 @@ CONFIG_ATA_OVER_ETH=m # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -248,94 +461,28 @@ CONFIG_ATA_OVER_ETH=m # # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration +# Network device support # -# CONFIG_IP_NF_CONNTRACK is not set -CONFIG_IP_NF_CONNTRACK_MARK=y -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set # -# QoS and/or fair queueing +# PHY device support # -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y # -# Network testing +# MII PHY device drivers # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m # # Ethernet (10 or 100Mbit) @@ -389,6 +536,8 @@ CONFIG_PPPOE=m # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -418,18 +567,6 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -439,6 +576,16 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -473,14 +620,14 @@ CONFIG_LEGACY_PTY_COUNT=256 # Watchdog Cards # # CONFIG_WATCHDOG is not set -CONFIG_RTC=y +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # # Ftape, the floppy tape device driver # -# CONFIG_DRM is not set # # PCMCIA character devices @@ -489,6 +636,10 @@ CONFIG_SYNCLINK_CS=m # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -499,10 +650,20 @@ CONFIG_SYNCLINK_CS=m # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -522,7 +683,6 @@ CONFIG_SYNCLINK_CS=m # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -532,12 +692,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB is not set # # USB Gadget Support @@ -552,7 +709,10 @@ CONFIG_DUMMY_CONSOLE=y # # InfiniBand support # -# CONFIG_INFINIBAND is not set + +# +# SN Devices +# # # File systems @@ -561,6 +721,7 @@ CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y # CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y @@ -579,10 +740,12 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -603,13 +766,10 @@ CONFIG_AUTOFS4_FS=m CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -621,6 +781,8 @@ CONFIG_RAMFS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=m # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set @@ -641,6 +803,7 @@ CONFIG_NFSD=m CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -650,6 +813,7 @@ CONFIG_SMB_FS=m # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -709,7 +873,9 @@ CONFIG_NLS_DEFAULT="iso8859-1" # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -725,26 +891,27 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_CRYPTO=y CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_BLOWFISH is not set -CONFIG_CRYPTO_TWOFISH=y -# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_AES=m -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_TEA=m -# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_CRC32C=m # CONFIG_CRYPTO_TEST is not set @@ -756,9 +923,8 @@ CONFIG_CRYPTO_CRC32C=m # Library routines # CONFIG_CRC_CCITT=m +CONFIG_CRC16=m CONFIG_CRC32=y CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index 6a528d479d70..b8cd2cd923dd 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:01 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:29 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,63 +59,79 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +CONFIG_MIPS_DB1100=y +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -CONFIG_SOC_AU1X00=y -# CONFIG_SOC_AU1000 is not set -CONFIG_SOC_AU1100=y -# CONFIG_SOC_AU1500 is not set -# CONFIG_SOC_AU1550 is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_DB1000 is not set -CONFIG_MIPS_DB1100=y -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_MIPS_MTX1 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SOC_AU1100=y +CONFIG_SOC_AU1X00=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS64 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -128,15 +147,39 @@ CONFIG_CPU_MIPS32=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_MIPS_MT is not set +CONFIG_64BIT_PHYS_ADDR=y # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -147,15 +190,7 @@ CONFIG_MMU=y # # PCCARD (PCMCIA/CardBus) support # -CONFIG_PCCARD=m -# CONFIG_PCMCIA_DEBUG is not set -CONFIG_PCMCIA=m - -# -# PC-card bridges -# -# CONFIG_TCIC is not set -# CONFIG_PCMCIA_AU1X00 is not set +# CONFIG_PCCARD is not set # # PCI Hotplug Support @@ -167,6 +202,100 @@ CONFIG_PCMCIA=m CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +CONFIG_IP_NF_PPTP=m +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m # # Device Drivers @@ -180,9 +309,83 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set # +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m + +# # Memory Technology Devices (MTD) # -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_AMDSTD_RETRY=0 +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_ALCHEMY=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set # # Parallel port support @@ -196,14 +399,12 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -226,6 +427,7 @@ CONFIG_ATA_OVER_ETH=m # # SCSI device support # +CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set # @@ -236,6 +438,7 @@ CONFIG_ATA_OVER_ETH=m # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -246,101 +449,35 @@ CONFIG_ATA_OVER_ETH=m # # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration +# Network device support # -# CONFIG_IP_NF_CONNTRACK is not set -CONFIG_IP_NF_CONNTRACK_MARK=y -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set # -# QoS and/or fair queueing +# PHY device support # -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y # -# Network testing +# MII PHY device drivers # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y CONFIG_MII=m -# CONFIG_MIPS_AU1X00_ENET is not set +CONFIG_MIPS_AU1X00_ENET=y # # Ethernet (1000 Mbit) @@ -360,19 +497,6 @@ CONFIG_MII=m # CONFIG_NET_RADIO is not set # -# PCMCIA network device support -# -CONFIG_NET_PCMCIA=y -CONFIG_PCMCIA_3C589=m -CONFIG_PCMCIA_3C574=m -CONFIG_PCMCIA_FMVJ18X=m -CONFIG_PCMCIA_PCNET=m -CONFIG_PCMCIA_NMCLAN=m -CONFIG_PCMCIA_SMC91C92=m -CONFIG_PCMCIA_XIRC2PS=m -CONFIG_PCMCIA_AXNET=m - -# # Wan interfaces # # CONFIG_WAN is not set @@ -387,6 +511,8 @@ CONFIG_PPPOE=m # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -416,18 +542,6 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -CONFIG_SERIO_LIBPS2=m -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -437,6 +551,16 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=m +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -454,7 +578,10 @@ CONFIG_HW_CONSOLE=y # # Non-8250 serial port support # -# CONFIG_SERIAL_AU1X00 is not set +CONFIG_SERIAL_AU1X00=y +CONFIG_SERIAL_AU1X00_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -468,20 +595,19 @@ CONFIG_LEGACY_PTY_COUNT=256 # Watchdog Cards # # CONFIG_WATCHDOG is not set -CONFIG_RTC=y +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # # Ftape, the floppy tape device driver # -# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set # -# PCMCIA character devices +# TPM devices # -CONFIG_SYNCLINK_CS=m -# CONFIG_RAW_DRIVER is not set # # I2C support @@ -494,10 +620,20 @@ CONFIG_SYNCLINK_CS=m # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -510,13 +646,43 @@ CONFIG_SYNCLINK_CS=m # # Graphics support # -# CONFIG_FB is not set +CONFIG_FB=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SOFT_CURSOR=y +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set +CONFIG_FB_AU1100=y +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set # # Console display driver support # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set + +# +# Logo configuration +# +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -527,12 +693,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB is not set # # USB Gadget Support @@ -547,7 +710,10 @@ CONFIG_DUMMY_CONSOLE=y # # InfiniBand support # -# CONFIG_INFINIBAND is not set + +# +# SN Devices +# # # File systems @@ -556,6 +722,7 @@ CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y # CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y @@ -574,10 +741,12 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -598,13 +767,10 @@ CONFIG_AUTOFS4_FS=m CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -616,6 +782,8 @@ CONFIG_RAMFS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=m # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set @@ -636,6 +804,7 @@ CONFIG_NFSD=m CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -645,6 +814,7 @@ CONFIG_SMB_FS=m # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -704,7 +874,9 @@ CONFIG_NLS_DEFAULT="iso8859-1" # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -720,26 +892,27 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_CRYPTO=y CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_BLOWFISH is not set -CONFIG_CRYPTO_TWOFISH=y -# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_AES=m -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_TEA=m -# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_CRC32C=m # CONFIG_CRYPTO_TEST is not set @@ -751,9 +924,8 @@ CONFIG_CRYPTO_CRC32C=m # Library routines # CONFIG_CRC_CCITT=m +CONFIG_CRC16=m CONFIG_CRC32=y CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig new file mode 100644 index 000000000000..530b6c2d99f6 --- /dev/null +++ b/arch/mips/configs/db1200_defconfig @@ -0,0 +1,987 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:32 2005 +# +CONFIG_MIPS=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +CONFIG_HOTPLUG=y +CONFIG_KOBJECT_UEVENT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SHMEM=y +CONFIG_CC_ALIGN_FUNCTIONS=0 +CONFIG_CC_ALIGN_LABELS=0 +CONFIG_CC_ALIGN_LOOPS=0 +CONFIG_CC_ALIGN_JUMPS=0 +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +CONFIG_MIPS_DB1200=y +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_3 is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_DMA_COHERENT=y +CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SOC_AU1200=y +CONFIG_SOC_AU1X00=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set +CONFIG_64BIT_PHYS_ADDR=y +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# +CONFIG_PCCARD=m +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y + +# +# PC-card bridges +# +# CONFIG_TCIC is not set +CONFIG_PCMCIA_AU1X00=m + +# +# PCI Hotplug Support +# + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_NETFILTER_NETLINK is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +CONFIG_IP_NF_PPTP=m +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_AMDSTD_RETRY=0 +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_ALCHEMY=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_AU1550 is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_LBD is not set +# CONFIG_CDROM_PKTCDVD is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_ATA_OVER_ETH is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +CONFIG_IDEDISK_MULTI_MODE=y +CONFIG_BLK_DEV_IDECS=m +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +CONFIG_BLK_DEV_IDE_AU1XXX=y +CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA=y +# CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA is not set +# CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON is not set +CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128 +# CONFIG_IDE_ARM is not set +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI Transport Attributes +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set + +# +# SCSI low-level drivers +# +# CONFIG_SCSI_SATA is not set +# CONFIG_SCSI_DEBUG is not set + +# +# PCMCIA SCSI adapter support +# +# CONFIG_PCMCIA_AHA152X is not set +# CONFIG_PCMCIA_FDOMAIN is not set +# CONFIG_PCMCIA_NINJA_SCSI is not set +# CONFIG_PCMCIA_QLOGIC is not set +# CONFIG_PCMCIA_SYM53C500 is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# I2O device support +# + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# PHY device support +# +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=m +# CONFIG_MIPS_AU1X00_ENET is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# + +# +# Token Ring devices +# + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# PCMCIA network device support +# +# CONFIG_NET_PCMCIA is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_AU1X00_GPIO is not set +# CONFIG_TS_AU1X00_ADS7846 is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_AU1X00=y +CONFIG_SERIAL_AU1X00_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set + +# +# Ftape, the floppy tape device driver +# + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# +# Misc devices +# + +# +# Multimedia Capabilities Port drivers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +CONFIG_FB=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SOFT_CURSOR=y +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set +CONFIG_FB_AU1200=y +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set + +# +# Logo configuration +# +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB is not set + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +# CONFIG_USB_GADGET_DUALSPEED is not set + +# +# MMC/SD Card support +# +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_AU1X=y + +# +# InfiniBand support +# + +# +# SN Devices +# + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +CONFIG_JFS_FS=y +# CONFIG_JFS_POSIX_ACL is not set +# CONFIG_JFS_SECURITY is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_ZISOFS_FS=m +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_RELAYFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=m +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=y +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="mem=48M" + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index fed6f2fab48b..1c2784dee697 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:01 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:36 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,63 +59,81 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +CONFIG_MIPS_DB1500=y +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -CONFIG_SOC_AU1X00=y -# CONFIG_SOC_AU1000 is not set -# CONFIG_SOC_AU1100 is not set -CONFIG_SOC_AU1500=y -# CONFIG_SOC_AU1550 is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -CONFIG_MIPS_DB1500=y -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_MIPS_MTX1 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_DMA_COHERENT=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SOC_AU1500=y +CONFIG_SOC_AU1X00=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS64 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -128,15 +149,39 @@ CONFIG_CPU_MIPS32=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set CONFIG_64BIT_PHYS_ADDR=y # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -145,7 +190,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -154,6 +198,8 @@ CONFIG_MMU=y CONFIG_PCCARD=m # CONFIG_PCMCIA_DEBUG is not set CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y CONFIG_CARDBUS=y # @@ -176,6 +222,100 @@ CONFIG_PCMCIA_AU1X00=m CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +CONFIG_IP_NF_PPTP=m +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m # # Device Drivers @@ -186,15 +326,20 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) # CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set @@ -232,16 +377,14 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_XIP is not set # # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_PHYSMAP is not set -CONFIG_MTD_DB1X00=y -CONFIG_MTD_DB1X00_BOOT=y -CONFIG_MTD_DB1X00_USER=y +CONFIG_MTD_ALCHEMY=y +# CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers @@ -277,7 +420,6 @@ CONFIG_MTD_DB1X00_USER=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -290,7 +432,6 @@ CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_UB is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -336,6 +477,7 @@ CONFIG_BLK_DEV_IDECS=m # # SCSI device support # +CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set # @@ -346,6 +488,7 @@ CONFIG_BLK_DEV_IDECS=m # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -358,94 +501,13 @@ CONFIG_BLK_DEV_IDECS=m # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set - -# -# IP: Virtual Server Configuration +# Network device support # -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration -# -# CONFIG_IP_NF_CONNTRACK is not set -CONFIG_IP_NF_CONNTRACK_MARK=y -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -453,6 +515,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -479,12 +556,16 @@ CONFIG_MIPS_AU1X00_ENET=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -497,6 +578,8 @@ CONFIG_MIPS_AU1X00_ENET=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # PCMCIA network device support @@ -520,6 +603,8 @@ CONFIG_PPPOE=m # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -549,19 +634,6 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -571,6 +643,17 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # # CONFIG_VT is not set @@ -590,6 +673,7 @@ CONFIG_SERIAL_AU1X00=y CONFIG_SERIAL_AU1X00_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -603,7 +687,8 @@ CONFIG_LEGACY_PTY_COUNT=256 # Watchdog Cards # # CONFIG_WATCHDOG is not set -CONFIG_RTC=y +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set @@ -620,6 +705,11 @@ CONFIG_SYNCLINK_CS=m # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -630,10 +720,20 @@ CONFIG_SYNCLINK_CS=m # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -647,7 +747,6 @@ CONFIG_SYNCLINK_CS=m # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -680,7 +779,6 @@ CONFIG_SOUND_AU1000=y # CONFIG_SOUND_MSNDCLAS is not set # CONFIG_SOUND_MSNDPIN is not set # CONFIG_SOUND_VIA82CXXX is not set -# CONFIG_SOUND_OSS is not set # CONFIG_SOUND_ALI5455 is not set # CONFIG_SOUND_FORTE is not set # CONFIG_SOUND_RME96XX is not set @@ -689,6 +787,8 @@ CONFIG_SOUND_AU1000=y # # USB support # +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB=y # CONFIG_USB_DEBUG is not set @@ -699,23 +799,23 @@ CONFIG_USB=y # CONFIG_USB_BANDWIDTH is not set # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y # # USB Host Controller Drivers # # CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # # USB Device Class drivers # -# CONFIG_USB_AUDIO is not set +# CONFIG_OBSOLETE_OSS_USB_DRIVER is not set # CONFIG_USB_BLUETOOTH_TTY is not set -# CONFIG_USB_MIDI is not set # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set @@ -733,12 +833,17 @@ CONFIG_USB_HIDINPUT=y # CONFIG_USB_HIDDEV is not set # CONFIG_USB_AIPTEK is not set # CONFIG_USB_WACOM is not set +# CONFIG_USB_ACECAD is not set # CONFIG_USB_KBTAB is not set # CONFIG_USB_POWERMATE is not set # CONFIG_USB_MTOUCH is not set +# CONFIG_USB_ITMTOUCH is not set # CONFIG_USB_EGALAX is not set +CONFIG_USB_YEALINK=m # CONFIG_USB_XPAD is not set # CONFIG_USB_ATI_REMOTE is not set +# CONFIG_USB_KEYSPAN_REMOTE is not set +# CONFIG_USB_APPLETOUCH is not set # # USB Imaging devices @@ -762,6 +867,7 @@ CONFIG_USB_HIDINPUT=y # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set +CONFIG_USB_MON=y # # USB port drivers @@ -786,9 +892,10 @@ CONFIG_USB_HIDINPUT=y # CONFIG_USB_PHIDGETKIT is not set # CONFIG_USB_PHIDGETSERVO is not set # CONFIG_USB_IDMOUSE is not set +CONFIG_USB_LD=m # -# USB ATM/DSL drivers +# USB DSL modem support # # @@ -807,12 +914,17 @@ CONFIG_USB_HIDINPUT=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y # CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y @@ -831,10 +943,12 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -855,13 +969,10 @@ CONFIG_AUTOFS4_FS=m CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -895,6 +1006,7 @@ CONFIG_NFSD=m CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -904,6 +1016,7 @@ CONFIG_SMB_FS=m # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -963,7 +1076,9 @@ CONFIG_NLS_DEFAULT="iso8859-1" # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -979,26 +1094,27 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_CRYPTO=y CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_BLOWFISH is not set -CONFIG_CRYPTO_TWOFISH=y -# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_AES=m -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_TEA=m -# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_CRC32C=m # CONFIG_CRYPTO_TEST is not set @@ -1010,9 +1126,8 @@ CONFIG_CRYPTO_CRC32C=m # Library routines # CONFIG_CRC_CCITT=m +CONFIG_CRC16=m CONFIG_CRC32=y CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index 178c0ad1af75..64248e2e924a 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:02 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:39 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,63 +59,80 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +CONFIG_MIPS_DB1550=y +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -CONFIG_SOC_AU1X00=y -# CONFIG_SOC_AU1000 is not set -# CONFIG_SOC_AU1100 is not set -# CONFIG_SOC_AU1500 is not set -CONFIG_SOC_AU1550=y -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -CONFIG_MIPS_DB1550=y -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_MIPS_MTX1 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_DMA_COHERENT=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SOC_AU1550=y +CONFIG_SOC_AU1X00=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS64 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -128,15 +148,39 @@ CONFIG_CPU_MIPS32=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set CONFIG_64BIT_PHYS_ADDR=y # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -145,7 +189,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -154,6 +197,8 @@ CONFIG_MMU=y CONFIG_PCCARD=m # CONFIG_PCMCIA_DEBUG is not set CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y CONFIG_CARDBUS=y # @@ -176,6 +221,100 @@ CONFIG_PCMCIA_AU1X00=m CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +CONFIG_IP_NF_PPTP=m +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m # # Device Drivers @@ -186,15 +325,20 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) # CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set @@ -238,9 +382,8 @@ CONFIG_MTD_CFI_UTIL=y # # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_PHYSMAP is not set -CONFIG_MTD_DB1550=y -CONFIG_MTD_DB1550_BOOT=y -CONFIG_MTD_DB1550_USER=y +CONFIG_MTD_ALCHEMY=y +# CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers @@ -281,7 +424,6 @@ CONFIG_MTD_NAND_AU1550=m # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -293,7 +435,6 @@ CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -350,6 +491,7 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y # CONFIG_BLK_DEV_HPT366 is not set # CONFIG_BLK_DEV_SC1200 is not set # CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT821X is not set # CONFIG_BLK_DEV_NS87415 is not set # CONFIG_BLK_DEV_PDC202XX_OLD is not set # CONFIG_BLK_DEV_PDC202XX_NEW is not set @@ -367,6 +509,7 @@ CONFIG_BLK_DEV_IDEDMA=y # # SCSI device support # +CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set # @@ -377,6 +520,7 @@ CONFIG_BLK_DEV_IDEDMA=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -389,94 +533,13 @@ CONFIG_BLK_DEV_IDEDMA=y # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set - -# -# IP: Virtual Server Configuration +# Network device support # -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration -# -# CONFIG_IP_NF_CONNTRACK is not set -CONFIG_IP_NF_CONNTRACK_MARK=y -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -484,6 +547,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -510,12 +588,16 @@ CONFIG_MIPS_AU1X00_ENET=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -528,6 +610,8 @@ CONFIG_MIPS_AU1X00_ENET=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # PCMCIA network device support @@ -559,6 +643,8 @@ CONFIG_PPPOE=m # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -588,19 +674,6 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -610,6 +683,17 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # # CONFIG_VT is not set @@ -629,6 +713,7 @@ CONFIG_SERIAL_AU1X00=y CONFIG_SERIAL_AU1X00_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -660,6 +745,11 @@ CONFIG_SYNCLINK_CS=m # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -670,10 +760,20 @@ CONFIG_SYNCLINK_CS=m # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -687,7 +787,6 @@ CONFIG_SYNCLINK_CS=m # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -697,13 +796,9 @@ CONFIG_SYNCLINK_CS=m # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -721,12 +816,17 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y # CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y @@ -745,10 +845,12 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -769,13 +871,10 @@ CONFIG_AUTOFS4_FS=m CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -809,6 +908,7 @@ CONFIG_NFSD=m CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -818,6 +918,7 @@ CONFIG_SMB_FS=m # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -877,7 +978,9 @@ CONFIG_NLS_DEFAULT="iso8859-1" # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -893,26 +996,27 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_CRYPTO=y CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_BLOWFISH is not set -CONFIG_CRYPTO_TWOFISH=y -# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_AES=m -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_TEA=m -# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_CRC32C=m # CONFIG_CRYPTO_TEST is not set @@ -924,9 +1028,8 @@ CONFIG_CRYPTO_CRC32C=m # Library routines # CONFIG_CRC_CCITT=m +CONFIG_CRC16=m CONFIG_CRC32=y CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/ddb5476_defconfig b/arch/mips/configs/ddb5476_defconfig index 70addc73f699..b260e51eb517 100644 --- a/arch/mips/configs/ddb5476_defconfig +++ b/arch/mips/configs/ddb5476_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:02 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:42 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -50,41 +53,69 @@ CONFIG_CC_ALIGN_JUMPS=0 # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set CONFIG_DDB5476=y # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_I8259=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_DDB5XXX_COMMON=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -93,8 +124,10 @@ CONFIG_HAVE_STD_PC_SERIAL_PORT=y # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -110,14 +143,38 @@ CONFIG_CPU_R5432=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R5432=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -126,7 +183,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_ISA=y CONFIG_MMU=y @@ -136,11 +192,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# -CONFIG_PCMCIA_PROBE=y - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -153,6 +204,80 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=y +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=y +CONFIG_IEEE80211_CRYPT_CCMP=y +CONFIG_IEEE80211_CRYPT_TKIP=y + +# # Device Drivers # @@ -161,7 +286,12 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=y + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=y # # Memory Technology Devices (MTD) @@ -181,8 +311,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -193,7 +321,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=y CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -239,6 +366,7 @@ CONFIG_IDE_GENERIC=y # # SCSI device support # +CONFIG_RAID_ATTRS=y # CONFIG_SCSI is not set # @@ -254,6 +382,7 @@ CONFIG_IDE_GENERIC=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -266,78 +395,13 @@ CONFIG_IDE_GENERIC=y # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=y -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=y - -# -# SCTP Configuration (EXPERIMENTAL) +# Network device support # -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -345,6 +409,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=y +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -352,7 +431,6 @@ CONFIG_NET_ETHERNET=y # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set @@ -377,12 +455,16 @@ CONFIG_NET_ETHERNET=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -395,6 +477,8 @@ CONFIG_NET_ETHERNET=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=y # # Wan interfaces @@ -406,6 +490,8 @@ CONFIG_NET_ETHERNET=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -435,19 +521,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -457,6 +530,17 @@ CONFIG_SERIO_RAW=y # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -477,6 +561,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -503,6 +588,11 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -513,10 +603,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -530,6 +630,11 @@ CONFIG_LEGACY_PTY_COUNT=256 # Graphics support # CONFIG_FB=y +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_SOFT_CURSOR is not set +# CONFIG_FB_MACMODES is not set # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set # CONFIG_FB_CIRRUS is not set @@ -537,6 +642,7 @@ CONFIG_FB=y # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set +# CONFIG_FB_NVIDIA is not set # CONFIG_FB_RIVA is not set # CONFIG_FB_MATROX is not set # CONFIG_FB_RADEON_OLD is not set @@ -549,8 +655,11 @@ CONFIG_FB=y # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set # CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_SMIVGX is not set +# CONFIG_FB_CYBLA is not set # CONFIG_FB_TRIDENT is not set # CONFIG_FB_E1356 is not set +# CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set # @@ -575,13 +684,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -599,21 +704,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=y # # CD-ROM/DVD Filesystems @@ -634,12 +747,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=y # # Miscellaneous filesystems @@ -668,7 +779,7 @@ CONFIG_NFS_FS=y # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -677,6 +788,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -697,7 +809,9 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="ip=any" @@ -711,7 +825,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_KHAZAD=y +CONFIG_CRYPTO_ANUBIS=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -721,7 +859,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CRC16=y +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig index 60292808b384..c2a01df3c8df 100644 --- a/arch/mips/configs/ddb5477_defconfig +++ b/arch/mips/configs/ddb5477_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:02 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:45 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -50,42 +53,70 @@ CONFIG_CC_ALIGN_JUMPS=0 # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set CONFIG_DDB5477=y -CONFIG_DDB5477_BUS_FREQUENCY=0 -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +CONFIG_DDB5477_BUS_FREQUENCY=0 CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_I8259=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_DDB5XXX_COMMON=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -93,8 +124,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -110,14 +143,38 @@ CONFIG_CPU_R5432=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R5432=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -126,7 +183,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -135,10 +191,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -151,6 +203,80 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=y +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=y +CONFIG_IEEE80211_CRYPT_CCMP=y +CONFIG_IEEE80211_CRYPT_TKIP=y + +# # Device Drivers # @@ -159,7 +285,12 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=y + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=y # # Memory Technology Devices (MTD) @@ -178,7 +309,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -189,7 +319,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=y CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -212,6 +341,7 @@ CONFIG_ATA_OVER_ETH=y # # SCSI device support # +CONFIG_RAID_ATTRS=y # CONFIG_SCSI is not set # @@ -222,6 +352,7 @@ CONFIG_ATA_OVER_ETH=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -234,78 +365,13 @@ CONFIG_ATA_OVER_ETH=y # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=y -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=y - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing +# Network device support # -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -313,6 +379,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=y +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -357,13 +438,17 @@ CONFIG_PCNET32=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -376,6 +461,8 @@ CONFIG_PCNET32=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=y # # Wan interfaces @@ -387,6 +474,8 @@ CONFIG_PCNET32=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -416,19 +505,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -438,6 +514,17 @@ CONFIG_SERIO_RAW=y # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -458,6 +545,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -484,6 +572,11 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -494,10 +587,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -517,7 +620,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -527,13 +629,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -551,21 +649,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y # # CD-ROM/DVD Filesystems @@ -586,12 +692,10 @@ CONFIG_AUTOFS4_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=y # # Miscellaneous filesystems @@ -623,6 +727,7 @@ CONFIG_NFSD=y CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -631,6 +736,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -651,7 +757,9 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="ip=any" @@ -665,7 +773,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_KHAZAD=y +CONFIG_CRYPTO_ANUBIS=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -675,7 +807,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index 66ec1f41d122..5bc885b72d14 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:03 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:48 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,30 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -49,48 +53,76 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_OBSOLETE_MODPARM=y -CONFIG_MODVERSIONS=y +# CONFIG_MODVERSIONS is not set CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set CONFIG_MACH_DECSTATION=y # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_EARLY_PRINTK=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=4 @@ -98,8 +130,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=4 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set CONFIG_CPU_R3000=y # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -115,12 +149,37 @@ CONFIG_CPU_R3000=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R3000=y +CONFIG_SYS_HAS_CPU_R4X00=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_WB=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -135,10 +194,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -150,6 +205,80 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -159,6 +288,12 @@ CONFIG_TRAD_SIGNALS=y CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) @@ -177,17 +312,14 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_CDROM_PKTCDVD is not set # # IO Schedulers @@ -196,7 +328,7 @@ CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -CONFIG_ATA_OVER_ETH=m +# CONFIG_ATA_OVER_ETH is not set # # ATA/ATAPI/MFM/RLL support @@ -206,6 +338,7 @@ CONFIG_ATA_OVER_ETH=m # # SCSI device support # +CONFIG_RAID_ATTRS=m CONFIG_SCSI=y CONFIG_SCSI_PROC_FS=y @@ -213,10 +346,12 @@ CONFIG_SCSI_PROC_FS=y # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set +CONFIG_CHR_DEV_ST=m # CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs @@ -228,9 +363,10 @@ CONFIG_SCSI_CONSTANTS=y # # SCSI Transport Attributes # -# CONFIG_SCSI_SPI_ATTRS is not set +CONFIG_SCSI_SPI_ATTRS=m # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set +CONFIG_SCSI_SAS_ATTRS=m # # SCSI low-level drivers @@ -248,6 +384,7 @@ CONFIG_SCSI_DECNCR=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -258,78 +395,28 @@ CONFIG_SCSI_DECNCR=y # # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) +# Network device support # -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set # -# QoS and/or fair queueing +# PHY device support # -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y # -# Network testing +# MII PHY device drivers # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m # # Ethernet (10 or 100Mbit) @@ -363,6 +450,8 @@ CONFIG_DECLANCE=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -377,48 +466,22 @@ CONFIG_DECLANCE=y # # Input device support # -CONFIG_INPUT=y +# CONFIG_INPUT is not set # -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input I/O drivers +# Hardware I/O ports # +# CONFIG_SERIO is not set # CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set # # Character devices # -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y +# CONFIG_VT is not set # CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_SERIAL_DEC=y +CONFIG_SERIAL_DEC_CONSOLE=y +CONFIG_ZS=y # # Serial drivers @@ -445,18 +508,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # Watchdog Cards # # CONFIG_WATCHDOG is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set +CONFIG_RTC=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # # Ftape, the floppy tape device driver # -# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -467,10 +532,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -483,13 +558,29 @@ CONFIG_LEGACY_PTY_COUNT=256 # # Graphics support # -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y +CONFIG_FB=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SOFT_CURSOR=y +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set +# CONFIG_FB_PMAG_AA is not set +CONFIG_FB_PMAG_BA=y +CONFIG_FB_PMAGB_B=y +# CONFIG_FB_MAXINE is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Logo configuration +# +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_LOGO_DEC_CLUT224=y # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -504,10 +595,6 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -520,7 +607,10 @@ CONFIG_DUMMY_CONSOLE=y # # InfiniBand support # -# CONFIG_INFINIBAND is not set + +# +# SN Devices +# # # File systems @@ -529,6 +619,7 @@ CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set CONFIG_FS_MBCACHE=y @@ -538,10 +629,12 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -562,12 +655,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y -# CONFIG_TMPFS is not set +CONFIG_TMPFS=y # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -584,19 +675,31 @@ CONFIG_RAMFS=y # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set +CONFIG_UFS_FS=y +CONFIG_UFS_FS_WRITE=y # # Network File Systems # -# CONFIG_NFS_FS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set # CONFIG_NFSD is not set -# CONFIG_EXPORTFS is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -631,9 +734,24 @@ CONFIG_ULTRIX_PARTITION=y # # Kernel hacking # -# CONFIG_DEBUG_KERNEL is not set +# CONFIG_PRINTK_TIME is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_FS is not set CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_KGDB is not set +# CONFIG_RUNTIME_DEBUG is not set +# CONFIG_MIPS_UNCACHED is not set # # Security options @@ -645,7 +763,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -655,7 +797,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set +CONFIG_CRC16=m CONFIG_CRC32=y CONFIG_LIBCRC32C=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig index ba2ec01defb1..c0d06ea5566c 100644 --- a/arch/mips/configs/e55_defconfig +++ b/arch/mips/configs/e55_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:03 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:51 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,56 +59,84 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -CONFIG_MACH_VR41XX=y -# CONFIG_NEC_CMBVR4133 is not set -CONFIG_CASIO_E55=y -# CONFIG_IBM_WORKPAD is not set -# CONFIG_TANBAC_TB0226 is not set -# CONFIG_TANBAC_TB0229 is not set -# CONFIG_VICTOR_MPC30X is not set -# CONFIG_ZAO_CAPCELLA is not set -# CONFIG_VRC4171 is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +CONFIG_MACH_VR41XX=y +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_NEC_CMBVR4133 is not set +CONFIG_CASIO_E55=y +# CONFIG_IBM_WORKPAD is not set +# CONFIG_TANBAC_TB022X is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set CONFIG_CPU_VR41XX=y @@ -121,12 +152,36 @@ CONFIG_CPU_VR41XX=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_VR41XX=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -141,11 +196,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# -CONFIG_PCMCIA_PROBE=y - -# # PCI Hotplug Support # @@ -157,6 +207,78 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -168,6 +290,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set # +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m + +# # Memory Technology Devices (MTD) # # CONFIG_MTD is not set @@ -185,18 +312,13 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_CDROM_PKTCDVD is not set # # IO Schedulers @@ -205,7 +327,7 @@ CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -CONFIG_ATA_OVER_ETH=m +# CONFIG_ATA_OVER_ETH is not set # # ATA/ATAPI/MFM/RLL support @@ -237,6 +359,7 @@ CONFIG_IDE_GENERIC=y # # SCSI device support # +# CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # @@ -252,6 +375,7 @@ CONFIG_IDE_GENERIC=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -262,76 +386,13 @@ CONFIG_IDE_GENERIC=y # # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing +# Network device support # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -339,12 +400,26 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y # CONFIG_MII is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set # CONFIG_AT1700 is not set @@ -380,6 +455,8 @@ CONFIG_NET_ETHERNET=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -401,26 +478,14 @@ CONFIG_INPUT=y # CONFIG_INPUT_MOUSEDEV=y CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -430,6 +495,16 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -440,16 +515,15 @@ CONFIG_HW_CONSOLE=y # # Serial drivers # -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_VR41XX=y +CONFIG_SERIAL_VR41XX_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -484,10 +558,14 @@ CONFIG_WATCHDOG=y # # Ftape, the floppy tape device driver # -# CONFIG_DRM is not set +CONFIG_GPIO_VR41XX=y # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -498,10 +576,20 @@ CONFIG_WATCHDOG=y # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -522,7 +610,6 @@ CONFIG_WATCHDOG=y # CONFIG_VGA_CONSOLE is not set # CONFIG_MDA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -536,10 +623,6 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -552,24 +635,31 @@ CONFIG_DUMMY_CONSOLE=y # # InfiniBand support # -# CONFIG_INFINIBAND is not set + +# +# SN Devices +# # # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -590,12 +680,10 @@ CONFIG_AUTOFS4_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -617,16 +705,17 @@ CONFIG_RAMFS=y # # Network File Systems # -CONFIG_NFS_FS=y +CONFIG_NFS_FS=m # CONFIG_NFS_V3 is not set # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y +CONFIG_NFSD=m # CONFIG_NFSD_V3 is not set # CONFIG_NFSD_TCP is not set -CONFIG_LOCKD=y -CONFIG_EXPORTFS=y -CONFIG_SUNRPC=y +CONFIG_LOCKD=m +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -634,6 +723,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -654,9 +744,11 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" +CONFIG_CMDLINE="console=ttyVR0,19200 mem=8M" # # Security options @@ -668,7 +760,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -678,7 +794,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set +CONFIG_CRC16=m +CONFIG_CRC32=m CONFIG_LIBCRC32C=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/ev64120_defconfig b/arch/mips/configs/ev64120_defconfig index 17e87f70f602..f1309d84d2fe 100644 --- a/arch/mips/configs/ev64120_defconfig +++ b/arch/mips/configs/ev64120_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:03 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:54 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,41 +59,69 @@ CONFIG_MODULE_SRCVERSION_ALL=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set CONFIG_MIPS_EV64120=y -# CONFIG_EVB_PCI1 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_EVB_PCI1 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_MIPS_GT64120=y # CONFIG_SYSCLK_75 is not set # CONFIG_SYSCLK_83 is not set @@ -100,8 +131,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -117,15 +150,39 @@ CONFIG_CPU_R5000=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R5000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -134,7 +191,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -143,10 +199,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -159,6 +211,79 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -167,7 +292,12 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) @@ -186,7 +316,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -197,7 +326,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -220,6 +348,7 @@ CONFIG_ATA_OVER_ETH=m # # SCSI device support # +CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set # @@ -230,6 +359,7 @@ CONFIG_ATA_OVER_ETH=m # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -242,77 +372,13 @@ CONFIG_ATA_OVER_ETH=m # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_PACKET is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) +# Network device support # -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -320,6 +386,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -345,12 +426,16 @@ CONFIG_NET_ETHERNET=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -363,6 +448,8 @@ CONFIG_NET_ETHERNET=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # Wan interfaces @@ -381,6 +468,8 @@ CONFIG_PPP_ASYNC=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -410,19 +499,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -432,6 +508,17 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -452,6 +539,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -478,6 +566,11 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -488,10 +581,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -511,7 +614,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -521,13 +623,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -545,21 +643,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -580,12 +686,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -614,7 +718,7 @@ CONFIG_NFS_FS=y # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -623,6 +727,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -643,7 +748,9 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs rw nfsroot=192.168.1.1:/mnt/disk2/fs.gal ip=192.168.1.211:192.168.1.1:::gt::" @@ -657,7 +764,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -667,7 +798,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # CONFIG_CRC_CCITT=y -# CONFIG_CRC32 is not set +CONFIG_CRC16=m +CONFIG_CRC32=m CONFIG_LIBCRC32C=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/ev96100_defconfig b/arch/mips/configs/ev96100_defconfig index 9da4140eae00..8ac55b7acc01 100644 --- a/arch/mips/configs/ev96100_defconfig +++ b/arch/mips/configs/ev96100_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:03 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:57 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,40 +59,68 @@ CONFIG_MODULE_SRCVERSION_ALL=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set CONFIG_MIPS_EV96100=y # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_GT64120=y CONFIG_SWAP_IO_SPACE=y @@ -99,8 +130,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -116,6 +149,18 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 CONFIG_CPU_RM7000=y # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R5000=y +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -123,11 +168,25 @@ CONFIG_PAGE_SIZE_4KB=y CONFIG_BOARD_SCACHE=y CONFIG_RM7000_CPU_SCACHE=y CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -143,10 +202,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -158,6 +213,79 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -169,6 +297,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set # +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m + +# # Memory Technology Devices (MTD) # # CONFIG_MTD is not set @@ -185,13 +318,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -214,6 +345,7 @@ CONFIG_ATA_OVER_ETH=m # # SCSI device support # +CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set # @@ -224,6 +356,7 @@ CONFIG_ATA_OVER_ETH=m # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -234,77 +367,28 @@ CONFIG_ATA_OVER_ETH=m # # -# Networking support -# -CONFIG_NET=y - -# -# Networking options +# Network device support # -# CONFIG_PACKET is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set # -# QoS and/or fair queueing +# PHY device support # -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y # -# Network testing +# MII PHY device drivers # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m # # Ethernet (10 or 100Mbit) @@ -338,6 +422,8 @@ CONFIG_MIPS_GT96100ETH=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -367,18 +453,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -388,6 +462,16 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -429,10 +513,13 @@ CONFIG_LEGACY_PTY_COUNT=256 # # Ftape, the floppy tape device driver # -# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -443,10 +530,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -466,7 +563,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -480,10 +576,6 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -496,24 +588,31 @@ CONFIG_DUMMY_CONSOLE=y # # InfiniBand support # -# CONFIG_INFINIBAND is not set + +# +# SN Devices +# # # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -534,12 +633,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -568,7 +665,7 @@ CONFIG_NFS_FS=y # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -577,6 +674,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -597,7 +695,9 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -611,7 +711,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -621,7 +745,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set +CONFIG_CRC16=m +CONFIG_CRC32=m CONFIG_LIBCRC32C=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index 17fa5c4e3ad1..3ae3838f283c 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:04 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:01 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,25 +11,30 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -42,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -57,41 +60,69 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set CONFIG_SGI_IP22=y -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_ARC=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_SWAP_IO_SPACE=y CONFIG_ARC32=y @@ -103,8 +134,10 @@ CONFIG_ARC_PROMLIB=y # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -120,22 +153,48 @@ CONFIG_CPU_R5000=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R4X00=y +CONFIG_SYS_HAS_CPU_R5000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_BOARD_SCACHE=y CONFIG_IP22_CPU_SCACHE=y +# CONFIG_MIPS_MT is not set # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # +CONFIG_HW_HAS_EISA=y # CONFIG_EISA is not set CONFIG_MMU=y @@ -145,10 +204,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -160,115 +215,7 @@ CONFIG_BINFMT_MISC=m CONFIG_TRAD_SIGNALS=y # -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_ATA_OVER_ETH=m - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_SCSI=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=y -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI Transport Attributes -# -CONFIG_SCSI_SPI_ATTRS=m -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set - -# -# SCSI low-level drivers -# -CONFIG_SGIWD93_SCSI=y -# CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Networking support +# Networking # CONFIG_NET=y @@ -277,12 +224,14 @@ CONFIG_NET=y # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m CONFIG_NET_KEY=y CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y CONFIG_IP_PNP=y # CONFIG_IP_PNP_DHCP is not set CONFIG_IP_PNP_BOOTP=y @@ -296,8 +245,10 @@ CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -CONFIG_IP_TCPDIAG_IPV6=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y # # IP: Virtual Server Configuration @@ -341,6 +292,9 @@ CONFIG_INET6_TUNNEL=m CONFIG_IPV6_TUNNEL=m CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m # # IP: Netfilter Configuration @@ -348,11 +302,15 @@ CONFIG_NETFILTER=y CONFIG_IP_NF_CONNTRACK=m CONFIG_IP_NF_CT_ACCT=y CONFIG_IP_NF_CONNTRACK_MARK=y +CONFIG_IP_NF_CONNTRACK_EVENTS=y +CONFIG_IP_NF_CONNTRACK_NETLINK=m # CONFIG_IP_NF_CT_PROTO_SCTP is not set CONFIG_IP_NF_FTP=m CONFIG_IP_NF_IRC=m +# CONFIG_IP_NF_NETBIOS_NS is not set CONFIG_IP_NF_TFTP=m CONFIG_IP_NF_AMANDA=m +CONFIG_IP_NF_PPTP=m CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_LIMIT=m @@ -376,9 +334,12 @@ CONFIG_IP_NF_MATCH_OWNER=m CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_REALM=m CONFIG_IP_NF_MATCH_SCTP=m +CONFIG_IP_NF_MATCH_DCCP=m CONFIG_IP_NF_MATCH_COMMENT=m CONFIG_IP_NF_MATCH_CONNMARK=m +CONFIG_IP_NF_MATCH_CONNBYTES=m CONFIG_IP_NF_MATCH_HASHLIMIT=m +CONFIG_IP_NF_MATCH_STRING=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -395,12 +356,14 @@ CONFIG_IP_NF_NAT_IRC=m CONFIG_IP_NF_NAT_FTP=m CONFIG_IP_NF_NAT_TFTP=m CONFIG_IP_NF_NAT_AMANDA=m +CONFIG_IP_NF_NAT_PPTP=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_TOS=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_DSCP=m CONFIG_IP_NF_TARGET_MARK=m CONFIG_IP_NF_TARGET_CLASSIFY=m +CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_TARGET_CONNMARK=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m @@ -410,7 +373,7 @@ CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # -# IPv6: Netfilter Configuration +# IPv6: Netfilter Configuration (EXPERIMENTAL) # CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m @@ -429,11 +392,16 @@ CONFIG_IP6_NF_MATCH_LENGTH=m CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_MARK=m +CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_RAW=m -CONFIG_XFRM=y -CONFIG_XFRM_USER=m + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set # # SCTP Configuration (EXPERIMENTAL) @@ -456,10 +424,6 @@ CONFIG_SCTP_HMAC_MD5=y CONFIG_NET_DIVERT=y # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# CONFIG_NET_SCHED=y # CONFIG_NET_SCH_CLK_JIFFIES is not set CONFIG_NET_SCH_CLK_GETTIMEOFDAY=y @@ -479,6 +443,7 @@ CONFIG_NET_SCH_INGRESS=m CONFIG_NET_QOS=y CONFIG_NET_ESTIMATOR=y CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_ROUTE=y @@ -489,6 +454,7 @@ CONFIG_NET_CLS_U32=m # CONFIG_CLS_U32_MARK is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_EMATCH is not set # CONFIG_NET_CLS_ACT is not set CONFIG_NET_CLS_POLICE=y @@ -496,17 +462,153 @@ CONFIG_NET_CLS_POLICE=y # Network testing # # CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +CONFIG_BLK_DEV_RAM_COUNT=16 +# CONFIG_LBD is not set +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_ATA_OVER_ETH=m + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=y +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +# CONFIG_CHR_DEV_SG is not set +CONFIG_CHR_DEV_SCH=m + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI Transport Attributes +# +CONFIG_SCSI_SPI_ATTRS=m +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m + +# +# SCSI low-level drivers +# +CONFIG_SGIWD93_SCSI=y +# CONFIG_SCSI_SATA is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# I2O device support +# + +# +# Network device support +# CONFIG_NETDEVICES=y CONFIG_DUMMY=m CONFIG_BONDING=m CONFIG_EQUALIZER=m CONFIG_TUN=m -CONFIG_ETHERTAP=m + +# +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m # # Ethernet (10 or 100Mbit) @@ -540,6 +642,8 @@ CONFIG_SGISEEQ=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -569,18 +673,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y @@ -598,6 +690,16 @@ CONFIG_MOUSE_SERIAL=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -644,11 +746,14 @@ CONFIG_SGI_DS1286=m # # Ftape, the floppy tape device driver # -# CONFIG_DRM is not set CONFIG_RAW_DRIVER=m CONFIG_MAX_RAW_DEVS=256 # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -659,10 +764,20 @@ CONFIG_MAX_RAW_DEVS=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -693,7 +808,6 @@ CONFIG_LOGO=y # CONFIG_LOGO_LINUX_VGA16 is not set # CONFIG_LOGO_LINUX_CLUT224 is not set CONFIG_LOGO_SGI_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -707,10 +821,6 @@ CONFIG_LOGO_SGI_CLUT224=y # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -723,13 +833,17 @@ CONFIG_LOGO_SGI_CLUT224=y # # InfiniBand support # -# CONFIG_INFINIBAND is not set + +# +# SN Devices +# # # File systems # CONFIG_EXT2_FS=m # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y @@ -741,12 +855,14 @@ CONFIG_FS_MBCACHE=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_XFS_FS=m -# CONFIG_XFS_RT is not set -CONFIG_XFS_QUOTA=y +CONFIG_XFS_EXPORT=y +CONFIG_XFS_QUOTA=m CONFIG_XFS_SECURITY=y # CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set CONFIG_MINIX_FS=m # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y CONFIG_QUOTA=y # CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=m @@ -754,6 +870,7 @@ CONFIG_QUOTACTL=y CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -781,12 +898,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -811,15 +926,20 @@ CONFIG_UFS_FS=m # CONFIG_NFS_FS=m CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y # CONFIG_NFSD_V4 is not set CONFIG_NFSD_TCP=y CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=m +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m CONFIG_RPCSEC_GSS_KRB5=m @@ -835,6 +955,7 @@ CONFIG_CIFS=m CONFIG_CODA_FS=m # CONFIG_CODA_FS_OLD_API is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -908,7 +1029,9 @@ CONFIG_NLS_UTF8=m # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -931,6 +1054,7 @@ CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_TWOFISH=m @@ -942,10 +1066,10 @@ CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_TEST=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -955,9 +1079,12 @@ CONFIG_CRYPTO_TEST=m # Library routines # # CONFIG_CRC_CCITT is not set +CONFIG_CRC16=m CONFIG_CRC32=m CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index b2a67da1e031..d962f61d5b98 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -1,11 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:04 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:04 2005 # CONFIG_MIPS=y -CONFIG_64BIT=y -CONFIG_64BIT=y # # Code maturity level options @@ -13,25 +11,31 @@ CONFIG_64BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=15 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_CPUSETS=y +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +45,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -57,55 +62,85 @@ CONFIG_STOP_MACHINE=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set CONFIG_SGI_IP27=y +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set # CONFIG_SGI_SN0_N_MODE is not set CONFIG_ARCH_DISCONTIGMEM_ENABLE=y CONFIG_NUMA=y # CONFIG_MAPPED_KERNEL is not set # CONFIG_REPLICATE_KTEXT is not set # CONFIG_REPLICATE_EXHANDLERS is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set -# CONFIG_SNI_RM200_PCI is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_ARC=y CONFIG_DMA_IP27=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_MIPS_L1_CACHE_SHIFT=7 CONFIG_ARC64=y CONFIG_BOOT_ELF64=y -CONFIG_QL_ISP_A64=y # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -121,17 +156,42 @@ CONFIG_CPU_R10000=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R10000=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +# CONFIG_32BIT is not set +CONFIG_64BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_FLATMEM_MANUAL is not set +CONFIG_DISCONTIGMEM_MANUAL=y +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_DISCONTIGMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_NEED_MULTIPLE_NODES=y +# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SMP=y CONFIG_NR_CPUS=64 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set +CONFIG_PREEMPT_BKL=y # CONFIG_MIPS_INSANE_LARGE is not set # @@ -141,7 +201,6 @@ CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -150,10 +209,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -163,7 +218,7 @@ CONFIG_MMU=y # CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set -# CONFIG_BUILD_ELF64 is not set +CONFIG_BUILD_ELF64=y CONFIG_MIPS32_COMPAT=y CONFIG_COMPAT=y CONFIG_MIPS32_O32=y @@ -171,6 +226,111 @@ CONFIG_MIPS32_O32=y CONFIG_BINFMT_ELF32=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +CONFIG_NET_SCHED=y +# CONFIG_NET_SCH_CLK_JIFFIES is not set +CONFIG_NET_SCH_CLK_GETTIMEOFDAY=y +# CONFIG_NET_SCH_CLK_CPU is not set +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_QOS=y +CONFIG_NET_ESTIMATOR=y +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_CLS_POLICE=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -179,7 +339,12 @@ CONFIG_BINFMT_ELF32=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) @@ -198,7 +363,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -210,7 +374,6 @@ CONFIG_BLK_DEV_CRYPTOLOOP=m # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 # CONFIG_CDROM_PKTCDVD_WCACHE is not set @@ -232,6 +395,7 @@ CONFIG_ATA_OVER_ETH=m # # SCSI device support # +CONFIG_RAID_ATTRS=m CONFIG_SCSI=y CONFIG_SCSI_PROC_FS=y @@ -241,8 +405,10 @@ CONFIG_SCSI_PROC_FS=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y # CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set +CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=m +CONFIG_CHR_DEV_SCH=m # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs @@ -256,7 +422,8 @@ CONFIG_SCSI_LOGGING=y # CONFIG_SCSI_SPI_ATTRS=y # CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m # # SCSI low-level drivers @@ -271,26 +438,24 @@ CONFIG_SCSI_SPI_ATTRS=y # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set -CONFIG_SCSI_QLOGIC_ISP=y # CONFIG_SCSI_QLOGIC_FC is not set -# CONFIG_SCSI_QLOGIC_1280 is not set +CONFIG_SCSI_QLOGIC_1280=y +CONFIG_SCSI_QLOGIC_1280_1040=y CONFIG_SCSI_QLA2XXX=y # CONFIG_SCSI_QLA21XX is not set # CONFIG_SCSI_QLA22XX is not set # CONFIG_SCSI_QLA2300 is not set # CONFIG_SCSI_QLA2322 is not set # CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_QLA24XX is not set +# CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_DEBUG is not set @@ -313,11 +478,15 @@ CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m CONFIG_DM_MIRROR=m CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_EMC=m # # Fusion MPT device support # # CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set # # IEEE 1394 (FireWire) support @@ -330,107 +499,13 @@ CONFIG_DM_ZERO=m # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -CONFIG_NET_SCHED=y -# CONFIG_NET_SCH_CLK_JIFFIES is not set -CONFIG_NET_SCH_CLK_GETTIMEOFDAY=y -# CONFIG_NET_SCH_CLK_CPU is not set -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_QOS=y -CONFIG_NET_ESTIMATOR=y -CONFIG_NET_CLS=y -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_ROUTE=y -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -# CONFIG_CLS_U32_PERF is not set -# CONFIG_NET_CLS_IND is not set -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -# CONFIG_NET_CLS_ACT is not set -CONFIG_NET_CLS_POLICE=y - -# -# Network testing +# Network device support # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -438,13 +513,25 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y CONFIG_MII=y -CONFIG_SGI_IOC3_ETH=y -CONFIG_SGI_IOC3_ETH_HW_RX_CSUM=y -CONFIG_SGI_IOC3_ETH_HW_TX_CSUM=y # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set @@ -466,12 +553,16 @@ CONFIG_SGI_IOC3_ETH_HW_TX_CSUM=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -484,6 +575,8 @@ CONFIG_SGI_IOC3_ETH_HW_TX_CSUM=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # Wan interfaces @@ -496,6 +589,8 @@ CONFIG_SGI_IOC3_ETH_HW_TX_CSUM=y # CONFIG_NET_FC is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -513,25 +608,15 @@ CONFIG_SGI_IOC3_ETH_HW_TX_CSUM=y # CONFIG_INPUT is not set # -# Userland interfaces -# - -# -# Input I/O drivers +# Hardware I/O ports # -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y CONFIG_SERIO=y # CONFIG_SERIO_I8042 is not set CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set # CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_LIBPS2=m CONFIG_SERIO_RAW=m - -# -# Input Device Drivers -# +# CONFIG_GAMEPORT is not set # # Character devices @@ -549,7 +634,6 @@ CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_8250_DETECT_IRQ is not set -# CONFIG_SERIAL_8250_MULTIPORT is not set # CONFIG_SERIAL_8250_RSA is not set # @@ -557,6 +641,7 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -584,6 +669,11 @@ CONFIG_SGI_IP27_RTC=y # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -594,10 +684,20 @@ CONFIG_SGI_IP27_RTC=y # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -611,7 +711,6 @@ CONFIG_SGI_IP27_RTC=y # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -621,13 +720,9 @@ CONFIG_SGI_IP27_RTC=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -645,12 +740,17 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y @@ -662,17 +762,19 @@ CONFIG_FS_MBCACHE=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_XFS_FS=m -# CONFIG_XFS_RT is not set -CONFIG_XFS_QUOTA=y +CONFIG_XFS_QUOTA=m CONFIG_XFS_SECURITY=y CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_QUOTACTL=y CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -693,12 +795,10 @@ CONFIG_AUTOFS_FS=m CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -722,13 +822,14 @@ CONFIG_RAMFS=y # CONFIG_NFS_FS=y CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set # CONFIG_NFSD is not set # CONFIG_ROOT_NFS is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y -# CONFIG_EXPORTFS is not set +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_RPCSEC_GSS_KRB5=y @@ -738,6 +839,7 @@ CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -772,7 +874,9 @@ CONFIG_SGI_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=15 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -788,28 +892,29 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_CRYPTO=y CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=y -CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_TEST=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -819,9 +924,8 @@ CONFIG_CRYPTO_TEST=m # Library routines # # CONFIG_CRC_CCITT is not set +CONFIG_CRC16=m CONFIG_CRC32=y CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index b26e1173365d..bf8fb95b21dc 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -1,11 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:04 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:07 2005 # CONFIG_MIPS=y -CONFIG_64BIT=y -CONFIG_64BIT=y # # Code maturity level options @@ -13,11 +11,13 @@ CONFIG_64BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set @@ -25,13 +25,16 @@ CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -50,42 +54,71 @@ CONFIG_CC_ALIGN_JUMPS=0 # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set CONFIG_SGI_IP32=y -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_ARC=y CONFIG_DMA_IP32=y -CONFIG_OWN_DMA=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_OWN_DMA=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_ARC32=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -95,8 +128,10 @@ CONFIG_ARC_PROMLIB=y # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -112,6 +147,17 @@ CONFIG_CPU_R5000=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R5000=y +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +# CONFIG_32BIT is not set +CONFIG_64BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -119,9 +165,22 @@ CONFIG_PAGE_SIZE_4KB=y CONFIG_BOARD_SCACHE=y CONFIG_R5000_CPU_SCACHE=y CONFIG_RM7000_CPU_SCACHE=y +# CONFIG_MIPS_MT is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set # @@ -130,7 +189,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -139,10 +197,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -160,6 +214,80 @@ CONFIG_MIPS32_O32=y CONFIG_BINFMT_ELF32=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=y +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=y +CONFIG_IEEE80211_CRYPT_CCMP=y +CONFIG_IEEE80211_CRYPT_TKIP=y + +# # Device Drivers # @@ -168,7 +296,12 @@ CONFIG_BINFMT_ELF32=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=y + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=y # # Memory Technology Devices (MTD) @@ -187,7 +320,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -199,7 +331,6 @@ CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" CONFIG_CDROM_PKTCDVD=y CONFIG_CDROM_PKTCDVD_BUFFERS=8 # CONFIG_CDROM_PKTCDVD_WCACHE is not set @@ -221,6 +352,7 @@ CONFIG_ATA_OVER_ETH=y # # SCSI device support # +CONFIG_RAID_ATTRS=y CONFIG_SCSI=y CONFIG_SCSI_PROC_FS=y @@ -233,6 +365,7 @@ CONFIG_CHR_DEV_OSST=y CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs @@ -244,9 +377,10 @@ CONFIG_SCSI_LOGGING=y # # SCSI Transport Attributes # -# CONFIG_SCSI_SPI_ATTRS is not set +CONFIG_SCSI_SPI_ATTRS=y # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set +CONFIG_SCSI_SAS_ATTRS=y # # SCSI low-level drivers @@ -266,18 +400,13 @@ CONFIG_AIC7XXX_REG_PRETTY_PRINT=y # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set CONFIG_SCSI_QLA2XXX=y @@ -286,6 +415,8 @@ CONFIG_SCSI_QLA2XXX=y # CONFIG_SCSI_QLA2300 is not set # CONFIG_SCSI_QLA2322 is not set # CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_QLA24XX is not set +# CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_DEBUG is not set @@ -299,6 +430,8 @@ CONFIG_SCSI_QLA2XXX=y # Fusion MPT device support # # CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set # # IEEE 1394 (FireWire) support @@ -311,78 +444,13 @@ CONFIG_SCSI_QLA2XXX=y # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=y -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=y - -# -# SCTP Configuration (EXPERIMENTAL) +# Network device support # -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -390,6 +458,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=y +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -416,12 +499,16 @@ CONFIG_SGI_O2MACE_ETH=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -434,6 +521,8 @@ CONFIG_SGI_O2MACE_ETH=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=y # # Wan interfaces @@ -446,6 +535,8 @@ CONFIG_SGI_O2MACE_ETH=y # CONFIG_NET_FC is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -475,27 +566,25 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports # -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y CONFIG_SERIO=y # CONFIG_SERIO_I8042 is not set CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set # CONFIG_SERIO_PCIPS2 is not set # CONFIG_SERIO_MACEPS2 is not set # CONFIG_SERIO_LIBPS2 is not set CONFIG_SERIO_RAW=y - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set +# CONFIG_GAMEPORT is not set # # Character devices @@ -518,6 +607,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -544,6 +634,11 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -554,10 +649,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -577,7 +682,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -587,13 +691,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -611,21 +711,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=y # # CD-ROM/DVD Filesystems @@ -646,13 +754,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=y # # Miscellaneous filesystems @@ -676,13 +781,14 @@ CONFIG_RAMFS=y # CONFIG_NFS_FS=y CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y -# CONFIG_EXPORTFS is not set +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -691,6 +797,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -721,7 +828,9 @@ CONFIG_SGI_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -735,7 +844,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_KHAZAD=y +CONFIG_CRYPTO_ANUBIS=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -745,7 +878,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CRC16=y +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/mips/configs/it8172_defconfig b/arch/mips/configs/it8172_defconfig index 08bd3ad64761..0940771bafb1 100644 --- a/arch/mips/configs/it8172_defconfig +++ b/arch/mips/configs/it8172_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:05 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:09 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,11 +11,13 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set @@ -26,13 +25,16 @@ CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -42,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -57,41 +60,69 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set CONFIG_MIPS_ITE8172=y -# CONFIG_IT8172_REVC is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_IT8172_REVC is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_ITE_BOARD_GEN=y CONFIG_IT8172_CIR=y CONFIG_IT8712=y @@ -100,8 +131,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -117,14 +150,39 @@ CONFIG_CPU_NEVADA=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R5432=y +CONFIG_SYS_HAS_CPU_NEVADA=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -140,10 +198,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -155,6 +209,80 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -166,12 +294,17 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set # +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m + +# # Memory Technology Devices (MTD) # CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_PARTITIONS is not set # CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_PARTITIONS is not set # # User Modules And Translation Layers @@ -207,7 +340,6 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_XIP is not set # # Mapping drivers for chip access @@ -217,6 +349,7 @@ CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP_START=0x8000000 CONFIG_MTD_PHYSMAP_LEN=0x2000000 CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers @@ -251,14 +384,12 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2 # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -302,6 +433,7 @@ CONFIG_IDE_GENERIC=y # # SCSI device support # +CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set # @@ -312,6 +444,7 @@ CONFIG_IDE_GENERIC=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -322,78 +455,28 @@ CONFIG_IDE_GENERIC=y # # -# Networking support -# -CONFIG_NET=y - -# -# Networking options +# Network device support # -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set # -# SCTP Configuration (EXPERIMENTAL) +# PHY device support # -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y # -# QoS and/or fair queueing +# MII PHY device drivers # -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m # # Ethernet (10 or 100Mbit) @@ -426,6 +509,8 @@ CONFIG_NET_ETHERNET=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -455,18 +540,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -476,6 +549,16 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -521,10 +604,13 @@ CONFIG_LEGACY_PTY_COUNT=256 # # Ftape, the floppy tape device driver # -# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -535,10 +621,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -558,7 +654,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -574,15 +669,9 @@ CONFIG_SOUND=y # Open Sound System # CONFIG_SOUND_PRIME=y -# CONFIG_SOUND_BT878 is not set -# CONFIG_SOUND_FUSION is not set -# CONFIG_SOUND_CS4281 is not set -# CONFIG_SOUND_SONICVIBES is not set CONFIG_SOUND_IT8172=y -# CONFIG_SOUND_TRIDENT is not set # CONFIG_SOUND_MSNDCLAS is not set # CONFIG_SOUND_MSNDPIN is not set -# CONFIG_SOUND_OSS is not set # CONFIG_SOUND_AD1980 is not set # @@ -592,10 +681,6 @@ CONFIG_SOUND_IT8172=y # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -608,24 +693,31 @@ CONFIG_SOUND_IT8172=y # # InfiniBand support # -# CONFIG_INFINIBAND is not set + +# +# SN Devices +# # # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -646,12 +738,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -682,7 +772,7 @@ CONFIG_NFS_FS=y # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -691,6 +781,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -711,7 +802,9 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -725,7 +818,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -735,7 +852,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set +CONFIG_CRC16=m +CONFIG_CRC32=m CONFIG_LIBCRC32C=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/ivr_defconfig b/arch/mips/configs/ivr_defconfig index 583ef5c5b1cd..9ba61dfc490d 100644 --- a/arch/mips/configs/ivr_defconfig +++ b/arch/mips/configs/ivr_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:05 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:12 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,11 +11,13 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set @@ -26,13 +25,16 @@ CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -42,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -57,40 +60,68 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set CONFIG_MIPS_IVR=y -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_ITE_BOARD_GEN=y CONFIG_IT8172_CIR=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -98,8 +129,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -115,14 +148,38 @@ CONFIG_CPU_NEVADA=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_NEVADA=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -131,7 +188,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -140,10 +196,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -156,6 +208,80 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -164,7 +290,12 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) @@ -183,7 +314,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -194,7 +324,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -239,6 +368,7 @@ CONFIG_IDE_GENERIC=y # # SCSI device support # +CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set # @@ -249,6 +379,7 @@ CONFIG_IDE_GENERIC=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -261,78 +392,13 @@ CONFIG_IDE_GENERIC=y # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) +# Network device support # -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -340,6 +406,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -365,12 +446,16 @@ CONFIG_NET_ETHERNET=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -383,6 +468,8 @@ CONFIG_NET_ETHERNET=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # Wan interfaces @@ -394,6 +481,8 @@ CONFIG_NET_ETHERNET=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -423,19 +512,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -445,6 +521,17 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -467,6 +554,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -492,6 +580,11 @@ CONFIG_RTC=y # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -502,10 +595,20 @@ CONFIG_RTC=y # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -525,7 +628,6 @@ CONFIG_RTC=y # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -535,13 +637,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -559,21 +657,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -594,12 +700,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -628,7 +732,7 @@ CONFIG_NFS_FS=y # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -637,6 +741,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -657,7 +762,9 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -671,7 +778,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -681,7 +812,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set +CONFIG_CRC16=m +CONFIG_CRC32=m CONFIG_LIBCRC32C=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/jaguar-atx_defconfig b/arch/mips/configs/jaguar-atx_defconfig index 8abb5a0c6c12..21b2b8042f91 100644 --- a/arch/mips/configs/jaguar-atx_defconfig +++ b/arch/mips/configs/jaguar-atx_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:05 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:14 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y # CONFIG_EXPERIMENTAL is not set CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -54,36 +57,70 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +CONFIG_MOMENCO_JAGUAR_ATX=y # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -CONFIG_MOMENCO_JAGUAR_ATX=y -CONFIG_JAGUAR_DMALOW=y -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +CONFIG_JAGUAR_DMALOW=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_LIMITED_DMA=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y CONFIG_IRQ_MV64340=y @@ -95,8 +132,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -112,6 +151,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # CONFIG_CPU_RM7000 is not set CONFIG_CPU_RM9000=y # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_RM9000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -119,13 +169,24 @@ CONFIG_PAGE_SIZE_4KB=y CONFIG_BOARD_SCACHE=y CONFIG_RM7000_CPU_SCACHE=y CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y CONFIG_HIGHMEM=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set # CONFIG_SMP is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -134,7 +195,6 @@ CONFIG_HIGHMEM=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -143,10 +203,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -158,6 +214,68 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_INET6_TUNNEL=m +CONFIG_IPV6_TUNNEL=m +# CONFIG_NETFILTER is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -166,7 +284,12 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) @@ -185,7 +308,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -195,7 +317,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -218,6 +339,7 @@ CONFIG_ATA_OVER_ETH=m # # SCSI device support # +CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set # @@ -228,6 +350,7 @@ CONFIG_ATA_OVER_ETH=m # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -240,58 +363,8 @@ CONFIG_ATA_OVER_ETH=m # CONFIG_I2O is not set # -# Networking support +# Network device support # -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_PACKET is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set @@ -304,6 +377,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -343,9 +431,11 @@ CONFIG_EEPRO100=y # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set CONFIG_MV643XX_ETH=y CONFIG_MV643XX_ETH_0=y CONFIG_MV643XX_ETH_1=y @@ -354,6 +444,7 @@ CONFIG_MV643XX_ETH_2=y # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -366,6 +457,8 @@ CONFIG_MV643XX_ETH_2=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # Wan interfaces @@ -374,6 +467,8 @@ CONFIG_MV643XX_ETH_2=y # CONFIG_FDDI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -391,20 +486,10 @@ CONFIG_MV643XX_ETH_2=y # CONFIG_INPUT is not set # -# Userland interfaces -# - -# -# Input I/O drivers +# Hardware I/O ports # -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y # CONFIG_SERIO is not set -# CONFIG_SERIO_I8042 is not set - -# -# Input Device Drivers -# +# CONFIG_GAMEPORT is not set # # Character devices @@ -425,6 +510,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -451,6 +537,10 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -461,10 +551,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -478,7 +578,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -488,13 +587,9 @@ CONFIG_LEGACY_PTY_COUNT=256 # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -512,6 +607,10 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # # CONFIG_EXT2_FS is not set @@ -519,13 +618,16 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -546,10 +648,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVPTS_FS_XATTR is not set # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -570,7 +672,7 @@ CONFIG_NFS_FS=y # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set @@ -591,7 +693,9 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -605,7 +709,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -615,7 +743,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CRC16=m +CONFIG_CRC32=m +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index da5d9ee2ecce..9a728c2d8fd5 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:06 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:17 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -50,40 +53,68 @@ CONFIG_CC_ALIGN_JUMPS=0 # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -CONFIG_TOSHIBA_JMR3927=y +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +CONFIG_TOSHIBA_JMR3927=y # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_MIPS_TX3927=y CONFIG_SWAP_IO_SPACE=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -92,8 +123,10 @@ CONFIG_TOSHIBA_BOARDS=y # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set CONFIG_CPU_TX39XX=y # CONFIG_CPU_VR41XX is not set @@ -109,12 +142,34 @@ CONFIG_CPU_TX39XX=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_TX39XX=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_RTC_DS1742=y @@ -124,7 +179,6 @@ CONFIG_RTC_DS1742=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -133,10 +187,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -149,6 +199,80 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=y +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=y +CONFIG_IEEE80211_CRYPT_CCMP=y +CONFIG_IEEE80211_CRYPT_TKIP=y + +# # Device Drivers # @@ -157,7 +281,12 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=y + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=y # # Memory Technology Devices (MTD) @@ -176,7 +305,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -187,7 +315,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=y CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -210,6 +337,7 @@ CONFIG_ATA_OVER_ETH=y # # SCSI device support # +CONFIG_RAID_ATTRS=y # CONFIG_SCSI is not set # @@ -220,6 +348,7 @@ CONFIG_ATA_OVER_ETH=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -232,78 +361,13 @@ CONFIG_ATA_OVER_ETH=y # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=y -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=y - -# -# SCTP Configuration (EXPERIMENTAL) +# Network device support # -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -311,6 +375,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=y +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -336,12 +415,16 @@ CONFIG_NET_ETHERNET=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -354,6 +437,8 @@ CONFIG_NET_ETHERNET=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=y # # Wan interfaces @@ -365,6 +450,8 @@ CONFIG_NET_ETHERNET=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -394,19 +481,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -416,6 +490,17 @@ CONFIG_SERIO_RAW=y # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -426,11 +511,9 @@ CONFIG_SERIAL_NONSTANDARD=y # CONFIG_ROCKETPORT is not set # CONFIG_CYCLADES is not set # CONFIG_DIGIEPCA is not set -# CONFIG_DIGI is not set # CONFIG_MOXA_INTELLIO is not set # CONFIG_MOXA_SMARTIO is not set # CONFIG_ISI is not set -# CONFIG_SYNCLINK is not set # CONFIG_SYNCLINKMP is not set # CONFIG_N_HDLC is not set # CONFIG_RISCOM8 is not set @@ -438,10 +521,6 @@ CONFIG_SERIAL_NONSTANDARD=y # CONFIG_SX is not set # CONFIG_RIO is not set # CONFIG_STALDRV is not set -# CONFIG_SERIAL_TX3912 is not set -CONFIG_TXX927_SERIAL=y -CONFIG_TXX927_SERIAL_CONSOLE=y -# CONFIG_SERIAL_TXX9 is not set # # Serial drivers @@ -451,6 +530,8 @@ CONFIG_TXX927_SERIAL_CONSOLE=y # # Non-8250 serial port support # +CONFIG_HAS_TXX9_SERIAL=y +# CONFIG_SERIAL_JSM is not set # CONFIG_UNIX98_PTYS is not set CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -477,6 +558,11 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -487,10 +573,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -504,6 +600,11 @@ CONFIG_LEGACY_PTY_COUNT=256 # Graphics support # CONFIG_FB=y +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_SOFT_CURSOR is not set +# CONFIG_FB_MACMODES is not set # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set # CONFIG_FB_CIRRUS is not set @@ -511,6 +612,7 @@ CONFIG_FB=y # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set +# CONFIG_FB_NVIDIA is not set # CONFIG_FB_RIVA is not set # CONFIG_FB_MATROX is not set # CONFIG_FB_RADEON_OLD is not set @@ -523,8 +625,11 @@ CONFIG_FB=y # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set # CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_SMIVGX is not set +# CONFIG_FB_CYBLA is not set # CONFIG_FB_TRIDENT is not set # CONFIG_FB_E1356 is not set +# CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set # @@ -548,13 +653,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -572,6 +673,10 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # # CONFIG_EXT2_FS is not set @@ -579,13 +684,16 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=y # # CD-ROM/DVD Filesystems @@ -606,10 +714,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=y # # Miscellaneous filesystems @@ -638,7 +746,7 @@ CONFIG_NFS_FS=y # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -647,6 +755,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -667,7 +776,9 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -681,7 +792,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_KHAZAD=y +CONFIG_CRYPTO_ANUBIS=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -691,7 +826,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CRC16=y +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/mips/configs/lasat200_defconfig b/arch/mips/configs/lasat200_defconfig index 8d600ae890f4..03cd0ca6e639 100644 --- a/arch/mips/configs/lasat200_defconfig +++ b/arch/mips/configs/lasat200_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:06 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:19 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,53 +59,83 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -CONFIG_LASAT=y -CONFIG_PICVUE=y -CONFIG_PICVUE_PROC=y -CONFIG_DS1603=y -CONFIG_LASAT_SYSCTL=y # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +CONFIG_LASAT=y # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +CONFIG_PICVUE=y +CONFIG_PICVUE_PROC=y +CONFIG_DS1603=y +CONFIG_LASAT_SYSCTL=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_MIPS_NILE4=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_MIPS_GT64120=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -118,17 +151,41 @@ CONFIG_CPU_R5000=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R5000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_BOARD_SCACHE=y CONFIG_R5000_CPU_SCACHE=y +# CONFIG_MIPS_MT is not set # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -137,7 +194,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -# CONFIG_PCI_NAMES is not set CONFIG_MMU=y # @@ -146,10 +202,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -162,6 +214,76 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -170,15 +292,20 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) # CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set @@ -223,6 +350,7 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_PHYSMAP is not set CONFIG_MTD_LASAT=y +# CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers @@ -258,7 +386,6 @@ CONFIG_MTD_LASAT=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -269,7 +396,6 @@ CONFIG_MTD_LASAT=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -326,6 +452,7 @@ CONFIG_BLK_DEV_CMD64X=y # CONFIG_BLK_DEV_HPT366 is not set # CONFIG_BLK_DEV_SC1200 is not set # CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT821X is not set # CONFIG_BLK_DEV_NS87415 is not set # CONFIG_BLK_DEV_PDC202XX_OLD is not set # CONFIG_BLK_DEV_PDC202XX_NEW is not set @@ -343,6 +470,7 @@ CONFIG_IDEDMA_AUTO=y # # SCSI device support # +CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set # @@ -353,6 +481,7 @@ CONFIG_IDEDMA_AUTO=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -365,68 +494,8 @@ CONFIG_IDEDMA_AUTO=y # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_PACKET is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing +# Network device support # -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set @@ -439,6 +508,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -464,12 +548,16 @@ CONFIG_NET_ETHERNET=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -482,6 +570,8 @@ CONFIG_NET_ETHERNET=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # Wan interfaces @@ -493,6 +583,8 @@ CONFIG_NET_ETHERNET=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -522,19 +614,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -544,6 +623,17 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -564,6 +654,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -590,6 +681,11 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -600,10 +696,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -623,7 +729,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -633,13 +738,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -657,10 +758,15 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set @@ -670,13 +776,16 @@ CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -697,12 +806,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -728,12 +835,13 @@ CONFIG_RAMFS=y # CONFIG_NFS_FS=y CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set # CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y -# CONFIG_EXPORTFS is not set +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -742,6 +850,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -762,7 +871,9 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -776,7 +887,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -786,7 +921,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set +CONFIG_CRC16=m CONFIG_CRC32=y CONFIG_LIBCRC32C=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 79519ac5af4a..2acdec959dd0 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:53:14 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:22 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,44 +59,75 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set CONFIG_MIPS_MALTA=y # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_GENERIC_ISA_DMA=y CONFIG_I8259=y CONFIG_MIPS_BONITO64=y CONFIG_MIPS_MSC=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y CONFIG_MIPS_BOARDS_GEN=y CONFIG_MIPS_GT64120=y CONFIG_SWAP_IO_SPACE=y @@ -104,8 +138,10 @@ CONFIG_HAVE_STD_PC_SERIAL_PORT=y # # CPU selection # -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS64 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -121,14 +157,48 @@ CONFIG_CPU_MIPS32=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R1=y +CONFIG_SYS_HAS_CPU_NEVADA=y +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT=y +# CONFIG_MIPS_MT_SMP is not set +CONFIG_MIPS_VPE_LOADER=y +CONFIG_MIPS_VPE_LOADER_TOM=y +CONFIG_MIPS_VPE_APSP_API=y # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -137,7 +207,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -146,10 +215,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -162,229 +227,7 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -CONFIG_BLK_DEV_FD=m -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -CONFIG_BLK_DEV_UMEM=m -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_CRYPTOLOOP=m -CONFIG_BLK_DEV_NBD=m -# CONFIG_BLK_DEV_SX8 is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_ATA_OVER_ETH=m - -# -# ATA/ATAPI/MFM/RLL support -# -CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -CONFIG_BLK_DEV_IDECD=y -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set -# CONFIG_IDE_TASK_IOCTL is not set - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=y -CONFIG_BLK_DEV_IDEPCI=y -# CONFIG_IDEPCI_SHARE_IRQ is not set -# CONFIG_BLK_DEV_OFFBOARD is not set -CONFIG_BLK_DEV_GENERIC=y -# CONFIG_BLK_DEV_OPTI621 is not set -CONFIG_BLK_DEV_IDEDMA_PCI=y -# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -CONFIG_IDEDMA_PCI_AUTO=y -# CONFIG_IDEDMA_ONLYDISK is not set -# CONFIG_BLK_DEV_AEC62XX is not set -# CONFIG_BLK_DEV_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD74XX is not set -# CONFIG_BLK_DEV_CMD64X is not set -# CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_CY82C693 is not set -# CONFIG_BLK_DEV_CS5520 is not set -# CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set -# CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_BLK_DEV_SC1200 is not set -CONFIG_BLK_DEV_PIIX=y -# CONFIG_BLK_DEV_NS87415 is not set -# CONFIG_BLK_DEV_PDC202XX_OLD is not set -# CONFIG_BLK_DEV_PDC202XX_NEW is not set -# CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_SIIMAGE is not set -# CONFIG_BLK_DEV_SLC90E66 is not set -# CONFIG_BLK_DEV_TRM290 is not set -# CONFIG_BLK_DEV_VIA82CXXX is not set -# CONFIG_IDE_ARM is not set -CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_IVB is not set -CONFIG_IDEDMA_AUTO=y -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI device support -# -CONFIG_SCSI=m -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=m -CONFIG_CHR_DEV_ST=m -CONFIG_CHR_DEV_OSST=m -CONFIG_BLK_DEV_SR=m -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=m - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y - -# -# SCSI Transport Attributes -# -CONFIG_SCSI_SPI_ATTRS=m -CONFIG_SCSI_FC_ATTRS=m -CONFIG_SCSI_ISCSI_ATTRS=m - -# -# SCSI low-level drivers -# -CONFIG_BLK_DEV_3W_XXXX_RAID=m -CONFIG_SCSI_3W_9XXX=m -CONFIG_SCSI_ACARD=m -CONFIG_SCSI_AACRAID=m -CONFIG_SCSI_AIC7XXX=m -CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 -CONFIG_AIC7XXX_RESET_DELAY_MS=15000 -# CONFIG_AIC7XXX_DEBUG_ENABLE is not set -CONFIG_AIC7XXX_DEBUG_MASK=0 -CONFIG_AIC7XXX_REG_PRETTY_PRINT=y -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_SYM53C8XX_2 is not set -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -# CONFIG_SCSI_QLOGIC_FC is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -CONFIG_SCSI_QLA2XXX=m -# CONFIG_SCSI_QLA21XX is not set -# CONFIG_SCSI_QLA22XX is not set -# CONFIG_SCSI_QLA2300 is not set -# CONFIG_SCSI_QLA2322 is not set -# CONFIG_SCSI_QLA6312 is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Multi-device support (RAID and LVM) -# -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID5=m -CONFIG_MD_RAID6=m -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -CONFIG_DM_ZERO=m - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Networking support +# Networking # CONFIG_NET=y @@ -393,15 +236,20 @@ CONFIG_NET=y # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m CONFIG_NET_KEY=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_FWMARK=y CONFIG_IP_ROUTE_MULTIPATH=y +# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y @@ -419,8 +267,10 @@ CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -CONFIG_IP_TCPDIAG_IPV6=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y # # IP: Virtual Server Configuration @@ -465,6 +315,9 @@ CONFIG_IPV6_TUNNEL=m CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set CONFIG_BRIDGE_NETFILTER=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m # # IP: Netfilter Configuration @@ -472,11 +325,15 @@ CONFIG_BRIDGE_NETFILTER=y CONFIG_IP_NF_CONNTRACK=m CONFIG_IP_NF_CT_ACCT=y CONFIG_IP_NF_CONNTRACK_MARK=y +CONFIG_IP_NF_CONNTRACK_EVENTS=y +CONFIG_IP_NF_CONNTRACK_NETLINK=m CONFIG_IP_NF_CT_PROTO_SCTP=m CONFIG_IP_NF_FTP=m CONFIG_IP_NF_IRC=m +# CONFIG_IP_NF_NETBIOS_NS is not set CONFIG_IP_NF_TFTP=m CONFIG_IP_NF_AMANDA=m +CONFIG_IP_NF_PPTP=m CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_LIMIT=m @@ -501,9 +358,12 @@ CONFIG_IP_NF_MATCH_PHYSDEV=m CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_REALM=m CONFIG_IP_NF_MATCH_SCTP=m +CONFIG_IP_NF_MATCH_DCCP=m CONFIG_IP_NF_MATCH_COMMENT=m CONFIG_IP_NF_MATCH_CONNMARK=m +CONFIG_IP_NF_MATCH_CONNBYTES=m CONFIG_IP_NF_MATCH_HASHLIMIT=m +CONFIG_IP_NF_MATCH_STRING=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -520,12 +380,14 @@ CONFIG_IP_NF_NAT_IRC=m CONFIG_IP_NF_NAT_FTP=m CONFIG_IP_NF_NAT_TFTP=m CONFIG_IP_NF_NAT_AMANDA=m +CONFIG_IP_NF_NAT_PPTP=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_TOS=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_DSCP=m CONFIG_IP_NF_TARGET_MARK=m CONFIG_IP_NF_TARGET_CLASSIFY=m +CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_TARGET_CONNMARK=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m @@ -535,7 +397,7 @@ CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # -# IPv6: Netfilter Configuration +# IPv6: Netfilter Configuration (EXPERIMENTAL) # CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m @@ -555,8 +417,10 @@ CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_PHYSDEV=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_MARK=m +CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_RAW=m # @@ -582,8 +446,11 @@ CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_ULOG=m -CONFIG_XFRM=y -CONFIG_XFRM_USER=m + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set # # SCTP Configuration (EXPERIMENTAL) @@ -611,10 +478,6 @@ CONFIG_IPDDP_DECAP=y CONFIG_NET_DIVERT=y # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# CONFIG_NET_SCHED=y CONFIG_NET_SCH_CLK_JIFFIES=y # CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set @@ -634,6 +497,7 @@ CONFIG_NET_SCH_INGRESS=m CONFIG_NET_QOS=y CONFIG_NET_ESTIMATOR=y CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_ROUTE=y @@ -644,6 +508,7 @@ CONFIG_NET_CLS_IND=y # CONFIG_CLS_U32_MARK is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_EMATCH is not set # CONFIG_NET_CLS_ACT is not set CONFIG_NET_CLS_POLICE=y @@ -651,17 +516,254 @@ CONFIG_NET_CLS_POLICE=y # Network testing # # CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +CONFIG_BLK_DEV_FD=m +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +CONFIG_BLK_DEV_UMEM=m +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_LBD is not set +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_ATA_OVER_ETH=m + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECD=y +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +CONFIG_BLK_DEV_IDEPCI=y +# CONFIG_IDEPCI_SHARE_IRQ is not set +# CONFIG_BLK_DEV_OFFBOARD is not set +CONFIG_BLK_DEV_GENERIC=y +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_IDEDMA_FORCED is not set +CONFIG_IDEDMA_PCI_AUTO=y +# CONFIG_IDEDMA_ONLYDISK is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT34X is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_SC1200 is not set +CONFIG_BLK_DEV_PIIX=y +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_IDE_ARM is not set +CONFIG_BLK_DEV_IDEDMA=y +# CONFIG_IDEDMA_IVB is not set +CONFIG_IDEDMA_AUTO=y +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=m +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y + +# +# SCSI Transport Attributes +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m + +# +# SCSI low-level drivers +# +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_AIC7XXX=m +CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 +CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +# CONFIG_AIC7XXX_DEBUG_ENABLE is not set +CONFIG_AIC7XXX_DEBUG_MASK=0 +CONFIG_AIC7XXX_REG_PRETTY_PRINT=y +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_SCSI_SATA is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_FC is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +CONFIG_SCSI_QLA2XXX=m +# CONFIG_SCSI_QLA21XX is not set +# CONFIG_SCSI_QLA22XX is not set +# CONFIG_SCSI_QLA2300 is not set +# CONFIG_SCSI_QLA2322 is not set +# CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_QLA24XX is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID5=m +CONFIG_MD_RAID6=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_EMC=m + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# CONFIG_NETDEVICES=y CONFIG_DUMMY=m CONFIG_BONDING=m CONFIG_EQUALIZER=m CONFIG_TUN=m -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -669,6 +771,21 @@ CONFIG_TUN=m # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -713,13 +830,17 @@ CONFIG_PCNET32=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -732,6 +853,8 @@ CONFIG_PCNET32=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # Wan interfaces @@ -744,6 +867,8 @@ CONFIG_PCNET32=y # CONFIG_NET_FC is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -773,19 +898,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -# CONFIG_SERIO_RAW is not set - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -795,6 +907,17 @@ CONFIG_SERIO_SERPORT=y # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -815,6 +938,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -840,6 +964,11 @@ CONFIG_RTC=y # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -850,10 +979,20 @@ CONFIG_RTC=y # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -873,7 +1012,6 @@ CONFIG_RTC=y # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -883,13 +1021,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -907,10 +1041,15 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set @@ -931,12 +1070,14 @@ CONFIG_JFS_SECURITY=y # CONFIG_JFS_STATISTICS is not set CONFIG_FS_POSIX_ACL=y CONFIG_XFS_FS=m -# CONFIG_XFS_RT is not set -CONFIG_XFS_QUOTA=y +CONFIG_XFS_EXPORT=y +CONFIG_XFS_QUOTA=m CONFIG_XFS_SECURITY=y CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set CONFIG_MINIX_FS=m CONFIG_ROMFS_FS=m +CONFIG_INOTIFY=y CONFIG_QUOTA=y # CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=y @@ -944,6 +1085,7 @@ CONFIG_QUOTACTL=y CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=y # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -971,12 +1113,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -1002,16 +1142,19 @@ CONFIG_UFS_FS=m # CONFIG_NFS_FS=y CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=y CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set # CONFIG_NFSD_V4 is not set # CONFIG_NFSD_TCP is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -1020,6 +1163,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -1079,7 +1223,9 @@ CONFIG_NLS_UTF8=m # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -1101,6 +1247,7 @@ CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_TWOFISH=m @@ -1125,9 +1272,12 @@ CONFIG_CRYPTO_CRC32C=m # Library routines # # CONFIG_CRC_CCITT is not set +CONFIG_CRC16=m CONFIG_CRC32=y CONFIG_LIBCRC32C=m CONFIG_ZLIB_INFLATE=m CONFIG_ZLIB_DEFLATE=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig new file mode 100644 index 000000000000..fb9bdd9e3151 --- /dev/null +++ b/arch/mips/configs/mipssim_defconfig @@ -0,0 +1,775 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:25 2005 +# +CONFIG_MIPS=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +CONFIG_HOTPLUG=y +CONFIG_KOBJECT_UEVENT=y +# CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SHMEM=y +CONFIG_CC_ALIGN_FUNCTIONS=0 +CONFIG_CC_ALIGN_LABELS=0 +CONFIG_CC_ALIGN_LOOPS=0 +CONFIG_CC_ALIGN_JUMPS=0 +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +CONFIG_MIPS_SIM=y +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_3 is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT=y +# CONFIG_MIPS_MT_SMP is not set +CONFIG_MIPS_VPE_LOADER=y +CONFIG_MIPS_VPE_LOADER_TOM=y +CONFIG_MIPS_VPE_APSP_API=y +# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# PCI Hotplug Support +# + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +CONFIG_NET_DIVERT=y +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CLK_JIFFIES=y +# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set +# CONFIG_NET_SCH_CLK_CPU is not set +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_QOS=y +CONFIG_NET_ESTIMATOR=y +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +# CONFIG_NET_CLS_POLICE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=y +# CONFIG_BLK_DEV_RAM is not set +CONFIG_BLK_DEV_RAM_COUNT=16 +# CONFIG_LBD is not set +# CONFIG_CDROM_PKTCDVD is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_ATA_OVER_ETH is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# I2O device support +# + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# PHY device support +# + +# +# Ethernet (10 or 100Mbit) +# +# CONFIG_NET_ETHERNET is not set +# CONFIG_MIPS_SIM_NET is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# + +# +# Token Ring devices +# + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=1 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# +# Misc devices +# + +# +# Multimedia Capabilities Port drivers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB_ARCH_HAS_HCD is not set +# CONFIG_USB_ARCH_HAS_OHCI is not set + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# InfiniBand support +# + +# +# SN Devices +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +CONFIG_ROMFS_FS=y +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +# CONFIG_SYSFS is not set +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_RELAYFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_INFO=y +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp" +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_KGDB is not set +# CONFIG_RUNTIME_DEBUG is not set +# CONFIG_MIPS_UNCACHED is not set + +# +# Security options +# +# CONFIG_KEYS is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig index 0fea57ef18f2..e2c082128532 100644 --- a/arch/mips/configs/mpc30x_defconfig +++ b/arch/mips/configs/mpc30x_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:07 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:28 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,57 +59,86 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -CONFIG_MACH_VR41XX=y -# CONFIG_NEC_CMBVR4133 is not set -# CONFIG_CASIO_E55 is not set -# CONFIG_IBM_WORKPAD is not set -# CONFIG_TANBAC_TB0226 is not set -# CONFIG_TANBAC_TB0229 is not set -CONFIG_VICTOR_MPC30X=y -# CONFIG_ZAO_CAPCELLA is not set -CONFIG_PCI_VR41XX=y -CONFIG_VRC4173=y -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +CONFIG_MACH_VR41XX=y +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_NEC_CMBVR4133 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_TANBAC_TB022X is not set +CONFIG_VICTOR_MPC30X=y +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_PCI_VR41XX=y +CONFIG_VRC4173=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set CONFIG_CPU_VR41XX=y @@ -122,12 +154,36 @@ CONFIG_CPU_VR41XX=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_VR41XX=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -136,17 +192,26 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # # PCCARD (PCMCIA/CardBus) support # -# CONFIG_PCCARD is not set +CONFIG_PCCARD=y +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y +# CONFIG_CARDBUS is not set # # PC-card bridges # +# CONFIG_YENTA is not set +# CONFIG_PD6729 is not set +# CONFIG_I82092 is not set +# CONFIG_TCIC is not set +CONFIG_PCMCIA_VRC4173=y # # PCI Hotplug Support @@ -161,6 +226,78 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -169,7 +306,12 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=y + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) @@ -188,7 +330,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -197,13 +338,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_CDROM_PKTCDVD is not set # # IO Schedulers @@ -217,11 +356,35 @@ CONFIG_ATA_OVER_ETH=m # # ATA/ATAPI/MFM/RLL support # -# CONFIG_IDE is not set +CONFIG_IDE=y +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECS=m +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +# CONFIG_BLK_DEV_IDEPCI is not set +# CONFIG_IDE_ARM is not set +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_BLK_DEV_HD is not set # # SCSI device support # +# CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # @@ -232,6 +395,7 @@ CONFIG_ATA_OVER_ETH=m # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -244,79 +408,13 @@ CONFIG_ATA_OVER_ETH=m # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) +# Network device support # -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -324,20 +422,14 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # -# Ethernet (10 or 100Mbit) +# PHY device support # -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set # -# Tulip family network device support +# Ethernet (10 or 100Mbit) # -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -# CONFIG_NET_PCI is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_MII=m # # Ethernet (1000 Mbit) @@ -349,12 +441,16 @@ CONFIG_NET_ETHERNET=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -366,7 +462,59 @@ CONFIG_NET_ETHERNET=y # # Wireless LAN (non-hamradio) # -# CONFIG_NET_RADIO is not set +CONFIG_NET_RADIO=y + +# +# Obsolete Wireless cards support (pre-802.11) +# +# CONFIG_STRIP is not set +# CONFIG_PCMCIA_WAVELAN is not set +# CONFIG_PCMCIA_NETWAVE is not set + +# +# Wireless 802.11 Frequency Hopping cards support +# +# CONFIG_PCMCIA_RAYCS is not set + +# +# Wireless 802.11b ISA/PCI cards support +# +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +CONFIG_HERMES=m +# CONFIG_PLX_HERMES is not set +# CONFIG_TMD_HERMES is not set +# CONFIG_NORTEL_HERMES is not set +# CONFIG_PCI_HERMES is not set +# CONFIG_ATMEL is not set + +# +# Wireless 802.11b Pcmcia/Cardbus cards support +# +CONFIG_PCMCIA_HERMES=m +# CONFIG_PCMCIA_SPECTRUM is not set +# CONFIG_AIRO_CS is not set +# CONFIG_PCMCIA_WL3501 is not set + +# +# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support +# +# CONFIG_PRISM54 is not set +# CONFIG_HOSTAP is not set +CONFIG_NET_WIRELESS=y + +# +# PCMCIA network device support +# +CONFIG_NET_PCMCIA=y +CONFIG_PCMCIA_3C589=m +CONFIG_PCMCIA_3C574=m +CONFIG_PCMCIA_FMVJ18X=m +CONFIG_PCMCIA_PCNET=m +CONFIG_PCMCIA_NMCLAN=m +CONFIG_PCMCIA_SMC91C92=m +CONFIG_PCMCIA_XIRC2PS=m +CONFIG_PCMCIA_AXNET=m # # Wan interfaces @@ -378,6 +526,8 @@ CONFIG_NET_ETHERNET=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -407,19 +557,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -429,6 +566,17 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -439,16 +587,16 @@ CONFIG_HW_CONSOLE=y # # Serial drivers # -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_VR41XX=y +CONFIG_SERIAL_VR41XX_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -472,9 +620,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # Ftape, the floppy tape device driver # # CONFIG_DRM is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +CONFIG_GPIO_VR41XX=y # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -485,10 +644,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -508,7 +677,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -518,13 +686,120 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB=m +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_BANDWIDTH is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=m +# CONFIG_USB_OHCI_BIG_ENDIAN is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_BLUETOOTH_TTY is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information # +# CONFIG_USB_STORAGE is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_AIPTEK is not set +# CONFIG_USB_WACOM is not set +# CONFIG_USB_ACECAD is not set +# CONFIG_USB_KBTAB is not set +# CONFIG_USB_POWERMATE is not set +# CONFIG_USB_MTOUCH is not set +# CONFIG_USB_ITMTOUCH is not set +# CONFIG_USB_EGALAX is not set +# CONFIG_USB_YEALINK is not set +# CONFIG_USB_XPAD is not set +# CONFIG_USB_ATI_REMOTE is not set +# CONFIG_USB_KEYSPAN_REMOTE is not set +# CONFIG_USB_APPLETOUCH is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set + +# +# USB Multimedia devices +# +# CONFIG_USB_DABUSB is not set + +# +# Video4Linux support is needed for USB Multimedia device support +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +CONFIG_USB_PEGASUS=m +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGETKIT is not set +# CONFIG_USB_PHIDGETSERVO is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# # # USB Gadget Support @@ -542,21 +817,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -577,12 +860,10 @@ CONFIG_AUTOFS4_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -609,9 +890,8 @@ CONFIG_NFS_FS=y # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set # CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -620,6 +900,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -640,9 +921,11 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" +CONFIG_CMDLINE="mem=32M console=ttyVR0,19200" # # Security options @@ -656,26 +939,27 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_CRYPTO=y CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_BLOWFISH is not set -CONFIG_CRYPTO_TWOFISH=y -# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_AES=m -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_TEA=m -# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_CRC32C=m # CONFIG_CRYPTO_TEST is not set @@ -687,9 +971,8 @@ CONFIG_CRYPTO_CRC32C=m # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set +CONFIG_CRC16=m +CONFIG_CRC32=y CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/ocelot_3_defconfig b/arch/mips/configs/ocelot_3_defconfig index b4cf97a732bc..ffb23fcab862 100644 --- a/arch/mips/configs/ocelot_3_defconfig +++ b/arch/mips/configs/ocelot_3_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:07 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:30 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,25 +11,30 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -42,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -57,40 +60,68 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set CONFIG_MOMENCO_OCELOT_3=y -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y CONFIG_IRQ_MV64340=y @@ -102,8 +133,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -119,6 +152,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # CONFIG_CPU_RM7000 is not set CONFIG_CPU_RM9000=y # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_RM9000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -126,13 +170,26 @@ CONFIG_PAGE_SIZE_4KB=y CONFIG_BOARD_SCACHE=y CONFIG_RM7000_CPU_SCACHE=y CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y -# CONFIG_HIGHMEM is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set # CONFIG_SMP is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -141,7 +198,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -150,10 +206,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -166,6 +218,110 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_IPV6_TUNNEL is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +CONFIG_IP_NF_PPTP=m +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration (EXPERIMENTAL) +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -174,7 +330,12 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) @@ -193,7 +354,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -205,7 +365,6 @@ CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set # CONFIG_CDROM_PKTCDVD is not set @@ -226,6 +385,7 @@ CONFIG_ATA_OVER_ETH=m # # SCSI device support # +CONFIG_RAID_ATTRS=m CONFIG_SCSI=m CONFIG_SCSI_PROC_FS=y @@ -237,6 +397,7 @@ CONFIG_SCSI_PROC_FS=y # CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set # CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs @@ -251,6 +412,7 @@ CONFIG_SCSI_PROC_FS=y # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set +CONFIG_SCSI_SAS_ATTRS=m # # SCSI low-level drivers @@ -266,18 +428,13 @@ CONFIG_SCSI_PROC_FS=y # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set CONFIG_SCSI_QLA2XXX=m @@ -286,6 +443,8 @@ CONFIG_SCSI_QLA2XXX=m # CONFIG_SCSI_QLA2300 is not set # CONFIG_SCSI_QLA2322 is not set # CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_QLA24XX is not set +# CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set @@ -300,6 +459,8 @@ CONFIG_SCSI_QLA2XXX=m # Fusion MPT device support # # CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set # # IEEE 1394 (FireWire) support @@ -312,105 +473,13 @@ CONFIG_SCSI_QLA2XXX=m # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_IP_TCPDIAG=m -CONFIG_IP_TCPDIAG_IPV6=y - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -CONFIG_IPV6=m -# CONFIG_IPV6_PRIVACY is not set -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_INET6_TUNNEL is not set -# CONFIG_IPV6_TUNNEL is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration -# -# CONFIG_IP_NF_CONNTRACK is not set -# CONFIG_IP_NF_CONNTRACK_MARK is not set -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set - -# -# IPv6: Netfilter Configuration -# -# CONFIG_IP6_NF_QUEUE is not set -# CONFIG_IP6_NF_IPTABLES is not set -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing +# Network device support # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set CONFIG_TUN=m -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -418,6 +487,21 @@ CONFIG_TUN=m # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -440,7 +524,6 @@ CONFIG_NET_PCI=y # CONFIG_DGRS is not set # CONFIG_EEPRO100 is not set CONFIG_E100=y -# CONFIG_E100_NAPI is not set # CONFIG_FEALNX is not set # CONFIG_NATSEMI is not set # CONFIG_NE2K_PCI is not set @@ -463,9 +546,12 @@ CONFIG_E100=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set CONFIG_MV643XX_ETH=y CONFIG_MV643XX_ETH_0=y CONFIG_MV643XX_ETH_1=y @@ -474,6 +560,7 @@ CONFIG_MV643XX_ETH_2=y # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -486,6 +573,8 @@ CONFIG_MV643XX_ETH_2=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # Wan interfaces @@ -505,6 +594,8 @@ CONFIG_PPPOE=m # CONFIG_NET_FC is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -531,19 +622,6 @@ CONFIG_INPUT=y # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -# CONFIG_SERIO_RAW is not set - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -553,6 +631,17 @@ CONFIG_SERIO=y # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -573,6 +662,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -598,6 +688,11 @@ CONFIG_RTC=y # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -608,10 +703,20 @@ CONFIG_RTC=y # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -625,6 +730,11 @@ CONFIG_RTC=y # Graphics support # CONFIG_FB=y +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_SOFT_CURSOR is not set +# CONFIG_FB_MACMODES is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_TILEBLITTING is not set # CONFIG_FB_CIRRUS is not set @@ -632,6 +742,7 @@ CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set +# CONFIG_FB_NVIDIA is not set # CONFIG_FB_RIVA is not set # CONFIG_FB_MATROX is not set # CONFIG_FB_RADEON_OLD is not set @@ -644,8 +755,11 @@ CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set # CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_SMIVGX is not set +# CONFIG_FB_CYBLA is not set # CONFIG_FB_TRIDENT is not set # CONFIG_FB_E1356 is not set +# CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set # @@ -675,13 +789,9 @@ CONFIG_LOGO_LINUX_CLUT224=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -699,10 +809,15 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=m CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set @@ -715,17 +830,21 @@ CONFIG_REISERFS_FS=m # CONFIG_REISERFS_PROC_INFO is not set # CONFIG_REISERFS_FS_XATTR is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set CONFIG_XFS_FS=m -# CONFIG_XFS_RT is not set +CONFIG_XFS_EXPORT=y # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_SECURITY is not set # CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -746,15 +865,10 @@ CONFIG_AUTOFS4_FS=m CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_MOUNT=y -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -778,16 +892,19 @@ CONFIG_CRAMFS=y # CONFIG_NFS_FS=y CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=y CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set # CONFIG_NFSD_V4 is not set # CONFIG_NFSD_TCP is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -797,6 +914,7 @@ CONFIG_SMB_FS=m # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -856,7 +974,9 @@ CONFIG_NLS_DEFAULT="iso8859-1" # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="ip=any root=nfs" @@ -869,7 +989,31 @@ CONFIG_CMDLINE="ip=any root=nfs" # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -879,9 +1023,8 @@ CONFIG_CMDLINE="ip=any root=nfs" # Library routines # CONFIG_CRC_CCITT=m +CONFIG_CRC16=m CONFIG_CRC32=y CONFIG_LIBCRC32C=m CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y diff --git a/arch/mips/configs/ocelot_c_defconfig b/arch/mips/configs/ocelot_c_defconfig index a38903db85a0..d3a5fee02b79 100644 --- a/arch/mips/configs/ocelot_c_defconfig +++ b/arch/mips/configs/ocelot_c_defconfig @@ -1,11 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:07 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:33 2005 # CONFIG_MIPS=y -CONFIG_64BIT=y -CONFIG_64BIT=y # # Code maturity level options @@ -13,24 +11,29 @@ CONFIG_64BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -40,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -49,39 +53,68 @@ CONFIG_CC_ALIGN_JUMPS=0 # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -CONFIG_MOMENCO_OCELOT_C=y # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +CONFIG_MOMENCO_OCELOT_C=y +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_IRQ_MV64340=y CONFIG_PCI_MARVELL=y @@ -91,8 +124,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -108,6 +143,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 CONFIG_CPU_RM7000=y # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +# CONFIG_32BIT is not set +CONFIG_64BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -115,9 +161,23 @@ CONFIG_PAGE_SIZE_4KB=y CONFIG_BOARD_SCACHE=y CONFIG_RM7000_CPU_SCACHE=y CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -126,7 +186,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -135,10 +194,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -156,6 +211,79 @@ CONFIG_MIPS32_N32=y CONFIG_BINFMT_ELF32=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=y +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=y +CONFIG_IEEE80211_CRYPT_CCMP=y +CONFIG_IEEE80211_CRYPT_TKIP=y + +# # Device Drivers # @@ -164,7 +292,12 @@ CONFIG_BINFMT_ELF32=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=y + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=y # # Memory Technology Devices (MTD) @@ -183,7 +316,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -194,7 +326,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" CONFIG_CDROM_PKTCDVD=y CONFIG_CDROM_PKTCDVD_BUFFERS=8 # CONFIG_CDROM_PKTCDVD_WCACHE is not set @@ -216,6 +347,7 @@ CONFIG_ATA_OVER_ETH=y # # SCSI device support # +CONFIG_RAID_ATTRS=y # CONFIG_SCSI is not set # @@ -226,6 +358,7 @@ CONFIG_ATA_OVER_ETH=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -238,77 +371,13 @@ CONFIG_ATA_OVER_ETH=y # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_PACKET is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=y -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=y - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing +# Network device support # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -316,6 +385,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=y +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -341,13 +425,17 @@ CONFIG_NET_ETHERNET=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # CONFIG_MV643XX_ETH is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -360,6 +448,8 @@ CONFIG_NET_ETHERNET=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=y # # Wan interfaces @@ -371,6 +461,8 @@ CONFIG_NET_ETHERNET=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -400,19 +492,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -422,6 +501,17 @@ CONFIG_SERIO_RAW=y # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -442,6 +532,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -468,6 +559,11 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -478,10 +574,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -501,7 +607,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -511,13 +616,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -535,21 +636,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=y # # CD-ROM/DVD Filesystems @@ -570,12 +679,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=y # # Miscellaneous filesystems @@ -607,6 +714,7 @@ CONFIG_NFSD=y CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -615,6 +723,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -635,7 +744,9 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -649,7 +760,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_KHAZAD=y +CONFIG_CRYPTO_ANUBIS=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -659,7 +794,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CRC16=y +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig index 920d59b56a4e..1edde12ebff9 100644 --- a/arch/mips/configs/ocelot_defconfig +++ b/arch/mips/configs/ocelot_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:08 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:35 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -50,40 +53,68 @@ CONFIG_CC_ALIGN_JUMPS=0 # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set CONFIG_MOMENCO_OCELOT=y -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y CONFIG_MIPS_GT64120=y @@ -96,8 +127,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -113,6 +146,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 CONFIG_CPU_RM7000=y # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -120,11 +164,25 @@ CONFIG_PAGE_SIZE_4KB=y CONFIG_BOARD_SCACHE=y CONFIG_RM7000_CPU_SCACHE=y CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -140,10 +198,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -155,6 +209,79 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=y +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=y +CONFIG_IEEE80211_CRYPT_CCMP=y +CONFIG_IEEE80211_CRYPT_TKIP=y + +# # Device Drivers # @@ -166,6 +293,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set # +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=y + +# # Memory Technology Devices (MTD) # # CONFIG_MTD is not set @@ -182,13 +314,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=y CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -211,6 +341,7 @@ CONFIG_ATA_OVER_ETH=y # # SCSI device support # +CONFIG_RAID_ATTRS=y # CONFIG_SCSI is not set # @@ -221,6 +352,7 @@ CONFIG_ATA_OVER_ETH=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -231,77 +363,28 @@ CONFIG_ATA_OVER_ETH=y # # -# Networking support -# -CONFIG_NET=y - -# -# Networking options +# Network device support # -# CONFIG_PACKET is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=y -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=y - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set # -# QoS and/or fair queueing +# PHY device support # -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set +CONFIG_PHYLIB=y +CONFIG_PHYCONTROL=y # -# Network testing +# MII PHY device drivers # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y # # Ethernet (10 or 100Mbit) @@ -334,6 +417,8 @@ CONFIG_NET_ETHERNET=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -363,18 +448,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -384,6 +457,16 @@ CONFIG_SERIO_RAW=y # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -425,10 +508,13 @@ CONFIG_LEGACY_PTY_COUNT=256 # # Ftape, the floppy tape device driver # -# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -439,10 +525,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -462,7 +558,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -476,10 +571,6 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -492,24 +583,31 @@ CONFIG_DUMMY_CONSOLE=y # # InfiniBand support # -# CONFIG_INFINIBAND is not set + +# +# SN Devices +# # # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=y # # CD-ROM/DVD Filesystems @@ -530,12 +628,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=y # # Miscellaneous filesystems @@ -567,6 +663,7 @@ CONFIG_NFSD=y CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -575,6 +672,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -595,7 +693,9 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -609,7 +709,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_KHAZAD=y +CONFIG_CRYPTO_ANUBIS=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -619,7 +743,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CRC16=y +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/ocelot_g_defconfig index ef5ea50893d1..e2d5188cdc15 100644 --- a/arch/mips/configs/ocelot_g_defconfig +++ b/arch/mips/configs/ocelot_g_defconfig @@ -1,11 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:08 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:38 2005 # CONFIG_MIPS=y -CONFIG_64BIT=y -CONFIG_64BIT=y # # Code maturity level options @@ -13,24 +11,29 @@ CONFIG_64BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -40,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -49,39 +53,68 @@ CONFIG_CC_ALIGN_JUMPS=0 # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -CONFIG_MOMENCO_OCELOT_G=y -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +CONFIG_MOMENCO_OCELOT_G=y +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y CONFIG_PCI_MARVELL=y @@ -94,8 +127,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -111,6 +146,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 CONFIG_CPU_RM7000=y # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +# CONFIG_32BIT is not set +CONFIG_64BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -118,9 +164,23 @@ CONFIG_PAGE_SIZE_4KB=y CONFIG_BOARD_SCACHE=y CONFIG_RM7000_CPU_SCACHE=y CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -129,7 +189,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -138,10 +197,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -159,6 +214,79 @@ CONFIG_MIPS32_N32=y CONFIG_BINFMT_ELF32=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=y +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=y +CONFIG_IEEE80211_CRYPT_CCMP=y +CONFIG_IEEE80211_CRYPT_TKIP=y + +# # Device Drivers # @@ -167,7 +295,12 @@ CONFIG_BINFMT_ELF32=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=y + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=y # # Memory Technology Devices (MTD) @@ -186,7 +319,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -197,7 +329,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" CONFIG_CDROM_PKTCDVD=y CONFIG_CDROM_PKTCDVD_BUFFERS=8 # CONFIG_CDROM_PKTCDVD_WCACHE is not set @@ -219,6 +350,7 @@ CONFIG_ATA_OVER_ETH=y # # SCSI device support # +CONFIG_RAID_ATTRS=y # CONFIG_SCSI is not set # @@ -229,6 +361,7 @@ CONFIG_ATA_OVER_ETH=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -241,77 +374,13 @@ CONFIG_ATA_OVER_ETH=y # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_PACKET is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=y -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=y - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing +# Network device support # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -319,6 +388,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=y +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -345,12 +429,16 @@ CONFIG_GALILEO_64240_ETH=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -363,6 +451,8 @@ CONFIG_GALILEO_64240_ETH=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=y # # Wan interfaces @@ -374,6 +464,8 @@ CONFIG_GALILEO_64240_ETH=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -403,19 +495,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -425,6 +504,17 @@ CONFIG_SERIO_RAW=y # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -445,6 +535,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -471,6 +562,11 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -481,10 +577,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -504,7 +610,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -514,13 +619,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -538,21 +639,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=y # # CD-ROM/DVD Filesystems @@ -573,12 +682,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=y # # Miscellaneous filesystems @@ -610,6 +717,7 @@ CONFIG_NFSD=y CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -618,6 +726,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -638,7 +747,9 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -652,7 +763,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_KHAZAD=y +CONFIG_CRYPTO_ANUBIS=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -662,7 +797,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CRC16=y +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index 813e3a8b480b..47247addee1b 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:08 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:41 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,56 +59,70 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +CONFIG_MIPS_PB1100=y +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -CONFIG_SOC_AU1X00=y -# CONFIG_SOC_AU1000 is not set -CONFIG_SOC_AU1100=y -# CONFIG_SOC_AU1500 is not set -# CONFIG_SOC_AU1550 is not set -# CONFIG_MIPS_PB1000 is not set -CONFIG_MIPS_PB1100=y -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_MIPS_MTX1 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SOC_AU1100=y +CONFIG_SOC_AU1X00=y CONFIG_SWAP_IO_SPACE=y # CONFIG_AU1X00_USB_DEVICE is not set CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -113,8 +130,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS64 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -130,15 +149,39 @@ CONFIG_CPU_MIPS32=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_MIPS_MT is not set +CONFIG_64BIT_PHYS_ADDR=y # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -154,6 +197,8 @@ CONFIG_MMU=y CONFIG_PCCARD=m # CONFIG_PCMCIA_DEBUG is not set CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y # # PC-card bridges @@ -171,6 +216,100 @@ CONFIG_PCMCIA=m CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +CONFIG_IP_NF_PPTP=m +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m # # Device Drivers @@ -181,15 +320,20 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) # CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set @@ -233,9 +377,8 @@ CONFIG_MTD_CFI_UTIL=y # # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_PHYSMAP is not set -CONFIG_MTD_PB1100=y -CONFIG_MTD_PB1500_BOOT=y -CONFIG_MTD_PB1500_USER=y +CONFIG_MTD_ALCHEMY=y +# CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers @@ -270,14 +413,12 @@ CONFIG_MTD_PB1500_USER=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -300,6 +441,7 @@ CONFIG_ATA_OVER_ETH=m # # SCSI device support # +CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set # @@ -310,6 +452,7 @@ CONFIG_ATA_OVER_ETH=m # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -320,94 +463,28 @@ CONFIG_ATA_OVER_ETH=m # # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration -# -# CONFIG_IP_NF_CONNTRACK is not set -CONFIG_IP_NF_CONNTRACK_MARK=y -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) +# Network device support # -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set # -# QoS and/or fair queueing +# PHY device support # -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y # -# Network testing +# MII PHY device drivers # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m # # Ethernet (10 or 100Mbit) @@ -453,6 +530,8 @@ CONFIG_PPPOE=m # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -482,18 +561,6 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -503,6 +570,16 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -534,14 +611,14 @@ CONFIG_LEGACY_PTY_COUNT=256 # Watchdog Cards # # CONFIG_WATCHDOG is not set -CONFIG_RTC=y +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # # Ftape, the floppy tape device driver # -# CONFIG_DRM is not set # # PCMCIA character devices @@ -550,6 +627,10 @@ CONFIG_SYNCLINK_CS=m # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -560,10 +641,20 @@ CONFIG_SYNCLINK_CS=m # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -583,7 +674,6 @@ CONFIG_SYNCLINK_CS=m # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -593,12 +683,9 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB is not set # # USB Gadget Support @@ -613,7 +700,10 @@ CONFIG_DUMMY_CONSOLE=y # # InfiniBand support # -# CONFIG_INFINIBAND is not set + +# +# SN Devices +# # # File systems @@ -622,6 +712,7 @@ CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y # CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y @@ -640,10 +731,12 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -664,13 +757,10 @@ CONFIG_AUTOFS4_FS=m CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -704,6 +794,7 @@ CONFIG_NFSD=m CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -713,6 +804,7 @@ CONFIG_SMB_FS=m # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -772,7 +864,9 @@ CONFIG_NLS_DEFAULT="iso8859-1" # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -788,26 +882,27 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_CRYPTO=y CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_BLOWFISH is not set -CONFIG_CRYPTO_TWOFISH=y -# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_AES=m -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_TEA=m -# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_CRC32C=m # CONFIG_CRYPTO_TEST is not set @@ -819,9 +914,8 @@ CONFIG_CRYPTO_CRC32C=m # Library routines # CONFIG_CRC_CCITT=m +CONFIG_CRC16=m CONFIG_CRC32=y CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig index 49e528340a39..f91a4eaae51a 100644 --- a/arch/mips/configs/pb1500_defconfig +++ b/arch/mips/configs/pb1500_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:09 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:44 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,63 +59,80 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +CONFIG_MIPS_PB1500=y +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -CONFIG_SOC_AU1X00=y -# CONFIG_SOC_AU1000 is not set -# CONFIG_SOC_AU1100 is not set -CONFIG_SOC_AU1500=y -# CONFIG_SOC_AU1550 is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -CONFIG_MIPS_PB1500=y -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_MIPS_MTX1 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_DMA_COHERENT=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SOC_AU1500=y +CONFIG_SOC_AU1X00=y # CONFIG_AU1X00_USB_DEVICE is not set CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS64 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -128,15 +148,39 @@ CONFIG_CPU_MIPS32=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set CONFIG_64BIT_PHYS_ADDR=y # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -145,7 +189,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -154,6 +197,8 @@ CONFIG_MMU=y CONFIG_PCCARD=m # CONFIG_PCMCIA_DEBUG is not set CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y CONFIG_CARDBUS=y # @@ -177,6 +222,100 @@ CONFIG_PCCARD_NONSTATIC=m CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +CONFIG_IP_NF_PPTP=m +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m # # Device Drivers @@ -187,12 +326,87 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) # -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_AMDSTD_RETRY=0 +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_ALCHEMY=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set # # Parallel port support @@ -206,7 +420,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -218,7 +431,6 @@ CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -275,6 +487,7 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y CONFIG_BLK_DEV_HPT366=y # CONFIG_BLK_DEV_SC1200 is not set # CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT821X is not set # CONFIG_BLK_DEV_NS87415 is not set # CONFIG_BLK_DEV_PDC202XX_OLD is not set # CONFIG_BLK_DEV_PDC202XX_NEW is not set @@ -292,6 +505,7 @@ CONFIG_BLK_DEV_IDEDMA=y # # SCSI device support # +CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set # @@ -302,6 +516,7 @@ CONFIG_BLK_DEV_IDEDMA=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -314,94 +529,13 @@ CONFIG_BLK_DEV_IDEDMA=y # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration +# Network device support # -# CONFIG_IP_NF_CONNTRACK is not set -CONFIG_IP_NF_CONNTRACK_MARK=y -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -409,6 +543,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -435,12 +584,16 @@ CONFIG_MIPS_AU1X00_ENET=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -453,6 +606,8 @@ CONFIG_MIPS_AU1X00_ENET=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # PCMCIA network device support @@ -484,6 +639,8 @@ CONFIG_PPPOE=m # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -513,19 +670,6 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -535,6 +679,17 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # # CONFIG_VT is not set @@ -554,6 +709,7 @@ CONFIG_SERIAL_AU1X00=y CONFIG_SERIAL_AU1X00_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -585,6 +741,11 @@ CONFIG_SYNCLINK_CS=m # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -595,10 +756,20 @@ CONFIG_SYNCLINK_CS=m # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -612,7 +783,6 @@ CONFIG_SYNCLINK_CS=m # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -622,13 +792,9 @@ CONFIG_SYNCLINK_CS=m # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -646,12 +812,17 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y # CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y @@ -670,10 +841,12 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -694,13 +867,10 @@ CONFIG_AUTOFS4_FS=m CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -712,6 +882,8 @@ CONFIG_RAMFS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=m # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set @@ -732,6 +904,7 @@ CONFIG_NFSD=m CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -741,6 +914,7 @@ CONFIG_SMB_FS=m # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -800,7 +974,9 @@ CONFIG_NLS_DEFAULT="iso8859-1" # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -816,27 +992,28 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_CRYPTO=y CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_BLOWFISH is not set -CONFIG_CRYPTO_TWOFISH=y -# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_AES=m -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_TEA=m -# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y -# CONFIG_CRYPTO_CRC32C is not set +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m # CONFIG_CRYPTO_TEST is not set # @@ -847,9 +1024,8 @@ CONFIG_CRYPTO_MICHAEL_MIC=y # Library routines # CONFIG_CRC_CCITT=m +CONFIG_CRC16=m CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index 8e426776c098..bbad27cb40a2 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:09 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:47 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,63 +59,80 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +CONFIG_MIPS_PB1550=y +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -CONFIG_SOC_AU1X00=y -# CONFIG_SOC_AU1000 is not set -# CONFIG_SOC_AU1100 is not set -# CONFIG_SOC_AU1500 is not set -CONFIG_SOC_AU1550=y -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -CONFIG_MIPS_PB1550=y -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_MIPS_MTX1 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_DMA_COHERENT=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SOC_AU1550=y +CONFIG_SOC_AU1X00=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS64 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -128,15 +148,39 @@ CONFIG_CPU_MIPS32=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set CONFIG_64BIT_PHYS_ADDR=y # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -145,7 +189,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -154,6 +197,8 @@ CONFIG_MMU=y CONFIG_PCCARD=m # CONFIG_PCMCIA_DEBUG is not set CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y CONFIG_CARDBUS=y # @@ -177,6 +222,100 @@ CONFIG_PCCARD_NONSTATIC=m CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +CONFIG_IP_NF_PPTP=m +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m # # Device Drivers @@ -187,12 +326,87 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) # -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_AMDSTD_RETRY=0 +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_ALCHEMY=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set # # Parallel port support @@ -206,7 +420,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -218,7 +431,6 @@ CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -275,6 +487,7 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y CONFIG_BLK_DEV_HPT366=y # CONFIG_BLK_DEV_SC1200 is not set # CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT821X is not set # CONFIG_BLK_DEV_NS87415 is not set # CONFIG_BLK_DEV_PDC202XX_OLD is not set # CONFIG_BLK_DEV_PDC202XX_NEW is not set @@ -292,6 +505,7 @@ CONFIG_BLK_DEV_IDEDMA=y # # SCSI device support # +CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set # @@ -302,6 +516,7 @@ CONFIG_BLK_DEV_IDEDMA=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -314,94 +529,13 @@ CONFIG_BLK_DEV_IDEDMA=y # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration +# Network device support # -# CONFIG_IP_NF_CONNTRACK is not set -CONFIG_IP_NF_CONNTRACK_MARK=y -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -409,6 +543,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -435,12 +584,16 @@ CONFIG_MIPS_AU1X00_ENET=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -453,6 +606,8 @@ CONFIG_MIPS_AU1X00_ENET=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # PCMCIA network device support @@ -476,6 +631,8 @@ CONFIG_PPPOE=m # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -505,19 +662,6 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -527,6 +671,17 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # # CONFIG_VT is not set @@ -546,6 +701,7 @@ CONFIG_SERIAL_AU1X00=y CONFIG_SERIAL_AU1X00_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -577,6 +733,11 @@ CONFIG_SYNCLINK_CS=m # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -587,10 +748,20 @@ CONFIG_SYNCLINK_CS=m # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -604,7 +775,6 @@ CONFIG_SYNCLINK_CS=m # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -614,13 +784,9 @@ CONFIG_SYNCLINK_CS=m # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -638,12 +804,17 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y # CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y @@ -662,10 +833,12 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -686,13 +859,10 @@ CONFIG_AUTOFS4_FS=m CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -704,6 +874,8 @@ CONFIG_RAMFS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=m # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set @@ -724,6 +896,7 @@ CONFIG_NFSD=m CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -733,6 +906,7 @@ CONFIG_SMB_FS=m # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -792,7 +966,9 @@ CONFIG_NLS_DEFAULT="iso8859-1" # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -808,26 +984,27 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_CRYPTO=y CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_BLOWFISH is not set -CONFIG_CRYPTO_TWOFISH=y -# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_AES=m -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_TEA=m -# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_CRC32C=m # CONFIG_CRYPTO_TEST is not set @@ -839,9 +1016,8 @@ CONFIG_CRYPTO_CRC32C=m # Library routines # CONFIG_CRC_CCITT=m +CONFIG_CRC16=m CONFIG_CRC32=y CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig new file mode 100644 index 000000000000..95f84d711912 --- /dev/null +++ b/arch/mips/configs/pnx8550-jbs_defconfig @@ -0,0 +1,1069 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:50 2005 +# +CONFIG_MIPS=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +# CONFIG_HOTPLUG is not set +CONFIG_KOBJECT_UEVENT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SHMEM=y +CONFIG_CC_ALIGN_FUNCTIONS=0 +CONFIG_CC_ALIGN_LABELS=0 +CONFIG_CC_ALIGN_LOOPS=0 +CONFIG_CC_ALIGN_JUMPS=0 +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODULE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_3 is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +CONFIG_PNX8550_JBS=y +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_PNX8550=y +CONFIG_SOC_PNX8550=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +CONFIG_CPU_R4X00=y +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R4X00=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set +# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +# CONFIG_PCI_LEGACY_PROC is not set +# CONFIG_PCI_DEBUG is not set +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# PCI Hotplug Support +# +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_LBD is not set +# CONFIG_CDROM_PKTCDVD is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_ATA_OVER_ETH is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECD=m +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +CONFIG_BLK_DEV_IDESCSI=y +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +CONFIG_BLK_DEV_IDEPCI=y +CONFIG_IDEPCI_SHARE_IRQ=y +CONFIG_BLK_DEV_OFFBOARD=y +CONFIG_BLK_DEV_GENERIC=y +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_IDEDMA_FORCED is not set +# CONFIG_IDEDMA_PCI_AUTO is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT34X is not set +CONFIG_BLK_DEV_HPT366=y +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_IDE_ARM is not set +CONFIG_BLK_DEV_IDEDMA=y +# CONFIG_IDEDMA_IVB is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI Transport Attributes +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set + +# +# SCSI low-level drivers +# +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_SCSI_SATA is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_FC is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +CONFIG_SCSI_QLA2XXX=y +# CONFIG_SCSI_QLA21XX is not set +# CONFIG_SCSI_QLA22XX is not set +# CONFIG_SCSI_QLA2300 is not set +# CONFIG_SCSI_QLA2322 is not set +# CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_QLA24XX is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set + +# +# PHY device support +# +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +CONFIG_8139TOO=y +# CONFIG_8139TOO_PIO is not set +CONFIG_8139TOO_TUNE_TWISTER=y +CONFIG_8139TOO_8129=y +# CONFIG_8139_OLD_RX_RESET is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_LAN_SAA9730 is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_CHELSIO_T1 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_IP3106 is not set +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Misc devices +# + +# +# Multimedia Capabilities Port drivers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_BANDWIDTH is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_BLUETOOTH_TTY is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_DPCM=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_AIPTEK is not set +# CONFIG_USB_WACOM is not set +# CONFIG_USB_ACECAD is not set +# CONFIG_USB_KBTAB is not set +# CONFIG_USB_POWERMATE is not set +# CONFIG_USB_MTOUCH is not set +# CONFIG_USB_ITMTOUCH is not set +# CONFIG_USB_EGALAX is not set +# CONFIG_USB_YEALINK is not set +# CONFIG_USB_XPAD is not set +# CONFIG_USB_ATI_REMOTE is not set +# CONFIG_USB_KEYSPAN_REMOTE is not set +# CONFIG_USB_APPLETOUCH is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB Multimedia devices +# +# CONFIG_USB_DABUSB is not set + +# +# Video4Linux support is needed for USB Multimedia device support +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGETKIT is not set +# CONFIG_USB_PHIDGETSERVO is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_LD is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# InfiniBand support +# +# CONFIG_INFINIBAND is not set + +# +# SN Devices +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +# CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_RELAYFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +CONFIG_NFSD=m +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_SCHEDSTATS is not set +CONFIG_DEBUG_SLAB=y +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_FS is not set +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp" +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_KGDB is not set +# CONFIG_RUNTIME_DEBUG is not set +# CONFIG_MIPS_UNCACHED is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set diff --git a/arch/mips/configs/pnx8550-v2pci_defconfig b/arch/mips/configs/pnx8550-v2pci_defconfig new file mode 100644 index 000000000000..deb24c29ac0a --- /dev/null +++ b/arch/mips/configs/pnx8550-v2pci_defconfig @@ -0,0 +1,1251 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:53 2005 +# +CONFIG_MIPS=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +# CONFIG_HOTPLUG is not set +CONFIG_KOBJECT_UEVENT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SHMEM=y +CONFIG_CC_ALIGN_FUNCTIONS=0 +CONFIG_CC_ALIGN_LABELS=0 +CONFIG_CC_ALIGN_LOOPS=0 +CONFIG_CC_ALIGN_JUMPS=0 +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODULE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_3 is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_PNX8550_V2PCI=y +# CONFIG_PNX8550_JBS is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_PNX8550=y +CONFIG_SOC_PNX8550=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +CONFIG_CPU_R4X00=y +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R4X00=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set +# CONFIG_64BIT_PHYS_ADDR is not set +CONFIG_CPU_ADVANCED=y +CONFIG_CPU_HAS_LLSC=y +# CONFIG_CPU_HAS_LLDSCD is not set +# CONFIG_CPU_HAS_WB is not set +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +# CONFIG_PCI_LEGACY_PROC is not set +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# PCI Hotplug Support +# +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_IPV6_TUNNEL is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_NETFILTER_NETLINK is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +CONFIG_IP_NF_PPTP=m +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration (EXPERIMENTAL) +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_LBD is not set +# CONFIG_CDROM_PKTCDVD is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_ATA_OVER_ETH is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +CONFIG_IDEDISK_MULTI_MODE=y +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +CONFIG_BLK_DEV_IDEPCI=y +CONFIG_IDEPCI_SHARE_IRQ=y +# CONFIG_BLK_DEV_OFFBOARD is not set +# CONFIG_BLK_DEV_GENERIC is not set +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_IDEDMA_FORCED is not set +CONFIG_IDEDMA_PCI_AUTO=y +# CONFIG_IDEDMA_ONLYDISK is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +CONFIG_BLK_DEV_CMD64X=y +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT34X is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_IDE_ARM is not set +CONFIG_BLK_DEV_IDEDMA=y +# CONFIG_IDEDMA_IVB is not set +CONFIG_IDEDMA_AUTO=y +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI Transport Attributes +# +CONFIG_SCSI_SPI_ATTRS=m +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set + +# +# SCSI low-level drivers +# +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +CONFIG_SCSI_AIC7XXX=m +CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 +CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +# CONFIG_AIC7XXX_DEBUG_ENABLE is not set +CONFIG_AIC7XXX_DEBUG_MASK=0 +# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_SCSI_SATA is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_FC is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +CONFIG_SCSI_QLA2XXX=y +# CONFIG_SCSI_QLA21XX is not set +# CONFIG_SCSI_QLA22XX is not set +# CONFIG_SCSI_QLA2300 is not set +# CONFIG_SCSI_QLA2322 is not set +# CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_QLA24XX is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set + +# +# PHY device support +# +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +CONFIG_NATSEMI=y +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +CONFIG_8139TOO=y +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139TOO_8129 is not set +# CONFIG_8139_OLD_RX_RESET is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_LAN_SAA9730 is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_CHELSIO_T1 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPPOE is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_COMPUTONE is not set +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_DIGIEPCA is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_ISI is not set +# CONFIG_SYNCLINKMP is not set +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_SX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_IP3106 is not set +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +CONFIG_I2C=m +CONFIG_I2C_CHARDEV=m + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=m +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +# CONFIG_SCx200_ACB is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set +# CONFIG_I2C_PCA_ISA is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_RTC8564 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_FSCPOS is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Misc devices +# + +# +# Multimedia Capabilities Port drivers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +CONFIG_FB=y +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_SOFT_CURSOR is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON_OLD is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_SMIVGX is not set +# CONFIG_FB_CYBLA is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_E1356 is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set + +# +# Logo configuration +# +# CONFIG_LOGO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_BANDWIDTH is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_BLUETOOTH_TTY is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +CONFIG_USB_HIDINPUT=y +# CONFIG_HID_FF is not set +CONFIG_USB_HIDDEV=y +# CONFIG_USB_AIPTEK is not set +# CONFIG_USB_WACOM is not set +# CONFIG_USB_ACECAD is not set +# CONFIG_USB_KBTAB is not set +# CONFIG_USB_POWERMATE is not set +# CONFIG_USB_MTOUCH is not set +# CONFIG_USB_ITMTOUCH is not set +# CONFIG_USB_EGALAX is not set +# CONFIG_USB_YEALINK is not set +# CONFIG_USB_XPAD is not set +# CONFIG_USB_ATI_REMOTE is not set +# CONFIG_USB_KEYSPAN_REMOTE is not set +# CONFIG_USB_APPLETOUCH is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB Multimedia devices +# +# CONFIG_USB_DABUSB is not set + +# +# Video4Linux support is needed for USB Multimedia device support +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGETKIT is not set +# CONFIG_USB_PHIDGETSERVO is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# InfiniBand support +# +# CONFIG_INFINIBAND is not set + +# +# SN Devices +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +CONFIG_XFS_EXPORT=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_RELAYFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +CONFIG_NFSD=m +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig index b6568e421b99..741a9a971367 100644 --- a/arch/mips/configs/qemu_defconfig +++ b/arch/mips/configs/qemu_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.13-rc6 -# Mon Aug 8 11:49:54 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:56 2005 # CONFIG_MIPS=y @@ -17,6 +17,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32 # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y # CONFIG_SWAP is not set # CONFIG_SYSVIPC is not set # CONFIG_BSD_PROCESS_ACCT is not set @@ -25,6 +26,7 @@ CONFIG_LOCALVERSION="" # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -74,6 +76,7 @@ CONFIG_BASE_SMALL=1 # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set # CONFIG_MOMENCO_OCELOT_3 is not set @@ -91,6 +94,7 @@ CONFIG_QEMU=y # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set @@ -105,7 +109,6 @@ CONFIG_QEMU=y # CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_COHERENT=y CONFIG_GENERIC_ISA_DMA=y CONFIG_I8259=y @@ -119,7 +122,7 @@ CONFIG_HAVE_STD_PC_SERIAL_PORT=y # # CPU selection # -# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set # CONFIG_CPU_MIPS64_R2 is not set @@ -127,7 +130,7 @@ CONFIG_HAVE_STD_PC_SERIAL_PORT=y # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set -CONFIG_CPU_R4X00=y +# CONFIG_CPU_R4X00 is not set # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set @@ -138,9 +141,11 @@ CONFIG_CPU_R4X00=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y # # Kernel type @@ -151,15 +156,18 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y # CONFIG_MIPS_MT is not set # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set @@ -214,8 +222,8 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set # CONFIG_INET_TUNNEL is not set -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_BIC=y # CONFIG_IPV6 is not set @@ -232,9 +240,15 @@ CONFIG_TCP_CONG_BIC=y # # Network testing # +# CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set +CONFIG_IEEE80211=y +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=y +CONFIG_IEEE80211_CRYPT_CCMP=y +CONFIG_IEEE80211_CRYPT_TKIP=y # # Device Drivers @@ -248,6 +262,11 @@ CONFIG_STANDALONE=y # CONFIG_FW_LOADER is not set # +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=y + +# # Memory Technology Devices (MTD) # # CONFIG_MTD is not set @@ -265,13 +284,12 @@ CONFIG_STANDALONE=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" +# CONFIG_LBD is not set # CONFIG_CDROM_PKTCDVD is not set # @@ -291,6 +309,7 @@ CONFIG_IOSCHED_NOOP=y # # SCSI device support # +CONFIG_RAID_ATTRS=y # CONFIG_SCSI is not set # @@ -331,6 +350,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=y +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -470,7 +504,6 @@ CONFIG_SERIAL_CORE_CONSOLE=y # I2C support # # CONFIG_I2C is not set -# CONFIG_I2C_SENSOR is not set # # Dallas's 1-wire bus @@ -481,12 +514,17 @@ CONFIG_SERIAL_CORE_CONSOLE=y # Hardware Monitoring support # # CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set # # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -532,7 +570,6 @@ CONFIG_DUMMY_CONSOLE=y # # InfiniBand support # -# CONFIG_INFINIBAND is not set # # SN Devices @@ -547,10 +584,6 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set - -# -# XFS support -# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -559,6 +592,7 @@ CONFIG_INOTIFY=y # CONFIG_DNOTIFY is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=y # # CD-ROM/DVD Filesystems @@ -576,11 +610,13 @@ CONFIG_INOTIFY=y # # Pseudo filesystems # -# CONFIG_PROC_FS is not set +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y # CONFIG_SYSFS is not set # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=y # # Miscellaneous filesystems @@ -634,12 +670,35 @@ CONFIG_CMDLINE="console=ttyS0 debug ip=172.20.0.2:172.20.0.1::255.255.0.0" # Security options # # CONFIG_KEYS is not set -# CONFIG_SECURITY is not set # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_KHAZAD=y +CONFIG_CRYPTO_ANUBIS=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -649,7 +708,8 @@ CONFIG_CMDLINE="console=ttyS0 debug ip=172.20.0.2:172.20.0.1::255.255.0.0" # Library routines # # CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig new file mode 100644 index 000000000000..2bc61ca4ba08 --- /dev/null +++ b/arch/mips/configs/rbhma4500_defconfig @@ -0,0 +1,1259 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:26:59 2005 +# +CONFIG_MIPS=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +CONFIG_HOTPLUG=y +# CONFIG_KOBJECT_UEVENT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SHMEM=y +CONFIG_CC_ALIGN_FUNCTIONS=0 +CONFIG_CC_ALIGN_LABELS=0 +CONFIG_CC_ALIGN_LOOPS=0 +CONFIG_CC_ALIGN_JUMPS=0 +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODULE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_3 is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +CONFIG_TOSHIBA_RBTX4938=y + +# +# Multiplex Pin Select +# +CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61=y +# CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND is not set +# CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_I8259=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_HAVE_STD_PC_SERIAL_PORT=y +CONFIG_TOSHIBA_BOARDS=y + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +CONFIG_CPU_TX49XX=y +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_TX49XX=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set +CONFIG_CPU_ADVANCED=y +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_WB=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +# CONFIG_PCI_LEGACY_PROC is not set +CONFIG_ISA=y +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# PCI Hotplug Support +# +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_IPV6_TUNNEL is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +CONFIG_IP_NF_PPTP=m +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration (EXPERIMENTAL) +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_AMDSTD_RETRY=0 +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_LBD is not set +# CONFIG_CDROM_PKTCDVD is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_ATA_OVER_ETH is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECD=y +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +CONFIG_BLK_DEV_IDEPCI=y +CONFIG_IDEPCI_SHARE_IRQ=y +# CONFIG_BLK_DEV_OFFBOARD is not set +# CONFIG_BLK_DEV_GENERIC is not set +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_IDEDMA_FORCED is not set +# CONFIG_IDEDMA_PCI_AUTO is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT34X is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_IDE_ARM is not set +# CONFIG_IDE_CHIPSETS is not set +CONFIG_BLK_DEV_IDEDMA=y +# CONFIG_IDEDMA_IVB is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +CONFIG_RAID_ATTRS=m +# CONFIG_SCSI is not set + +# +# Old CD-ROM drivers (not SCSI, not IDE) +# +# CONFIG_CD_NO_IDESCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set + +# +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_NET_VENDOR_RACAL is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_AT1700 is not set +# CONFIG_DEPCA is not set +# CONFIG_HP100 is not set +CONFIG_NET_ISA=y +# CONFIG_E2100 is not set +# CONFIG_EWRK3 is not set +# CONFIG_EEXPRESS is not set +# CONFIG_EEXPRESS_PRO is not set +# CONFIG_HPLAN_PLUS is not set +# CONFIG_HPLAN is not set +# CONFIG_LP486E is not set +# CONFIG_ETH16I is not set +CONFIG_NE2000=y +# CONFIG_SEEQ8005 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_AC3200 is not set +# CONFIG_APRICOT is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_CS89x0 is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_LAN_SAA9730 is not set +# CONFIG_NET_POCKET is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_CHELSIO_T1 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set + +# +# Wireless LAN (non-hamradio) +# +CONFIG_NET_RADIO=y + +# +# Obsolete Wireless cards support (pre-802.11) +# +# CONFIG_STRIP is not set +# CONFIG_ARLAN is not set +# CONFIG_WAVELAN is not set + +# +# Wireless 802.11b ISA/PCI cards support +# +# CONFIG_IPW2100 is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m +# CONFIG_AIRO is not set +# CONFIG_HERMES is not set +# CONFIG_ATMEL is not set + +# +# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support +# +# CONFIG_PRISM54 is not set +# CONFIG_HOSTAP is not set +CONFIG_NET_WIRELESS=y + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_BSDCOMP is not set +CONFIG_PPPOE=m +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_INPORT is not set +# CONFIG_MOUSE_LOGIBM is not set +# CONFIG_MOUSE_PC110PAD is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_HAS_TXX9_SERIAL=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Misc devices +# + +# +# Multimedia Capabilities Port drivers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +CONFIG_FB=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SOFT_CURSOR=y +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON_OLD is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +CONFIG_FB_ATY=y +CONFIG_FB_ATY_CT=y +# CONFIG_FB_ATY_GENERIC_LCD is not set +# CONFIG_FB_ATY_XL_INIT is not set +# CONFIG_FB_ATY_GX is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_SMIVGX is not set +# CONFIG_FB_CYBLA is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_E1356 is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set + +# +# Logo configuration +# +# CONFIG_LOGO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_BANDWIDTH is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_BLUETOOTH_TTY is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information +# +# CONFIG_USB_STORAGE is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +CONFIG_USB_HIDINPUT=y +# CONFIG_HID_FF is not set +CONFIG_USB_HIDDEV=y +# CONFIG_USB_AIPTEK is not set +# CONFIG_USB_WACOM is not set +# CONFIG_USB_ACECAD is not set +# CONFIG_USB_KBTAB is not set +# CONFIG_USB_POWERMATE is not set +# CONFIG_USB_MTOUCH is not set +# CONFIG_USB_ITMTOUCH is not set +# CONFIG_USB_EGALAX is not set +CONFIG_USB_YEALINK=m +# CONFIG_USB_XPAD is not set +# CONFIG_USB_ATI_REMOTE is not set +# CONFIG_USB_KEYSPAN_REMOTE is not set +# CONFIG_USB_APPLETOUCH is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set + +# +# USB Multimedia devices +# +# CONFIG_USB_DABUSB is not set + +# +# Video4Linux support is needed for USB Multimedia device support +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_ZD1201 is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGETKIT is not set +# CONFIG_USB_PHIDGETSERVO is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_LD is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# InfiniBand support +# +# CONFIG_INFINIBAND is not set + +# +# SN Devices +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=m +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_JBD=m +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +CONFIG_XFS_EXPORT=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +# CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +CONFIG_NFSD=m +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +CONFIG_CRC32=y +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index 17d4fce6c4c6..988a05824f01 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:09 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:27:03 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,11 +11,13 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -26,14 +25,17 @@ CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -43,6 +45,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -58,43 +61,73 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set CONFIG_SNI_RM200_PCI=y +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_ARC=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_GENERIC_ISA_DMA=y CONFIG_I8259=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_ARC32=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -106,8 +139,10 @@ CONFIG_ARC_PROMLIB=y # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -123,24 +158,49 @@ CONFIG_CPU_R4X00=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R4X00=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # +CONFIG_HW_HAS_EISA=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -# CONFIG_PCI_NAMES is not set CONFIG_ISA=y # CONFIG_EISA is not set CONFIG_MMU=y @@ -151,11 +211,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# -CONFIG_PCMCIA_PROBE=y - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -168,240 +223,7 @@ CONFIG_BINFMT_MISC=m CONFIG_TRAD_SIGNALS=y # -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -CONFIG_PARPORT=m -CONFIG_PARPORT_PC=m -CONFIG_PARPORT_PC_CML1=m -CONFIG_PARPORT_SERIAL=m -# CONFIG_PARPORT_PC_FIFO is not set -# CONFIG_PARPORT_PC_SUPERIO is not set -# CONFIG_PARPORT_OTHER is not set -CONFIG_PARPORT_1284=y - -# -# Plug and Play support -# -# CONFIG_PNP is not set - -# -# Block devices -# -CONFIG_BLK_DEV_FD=m -# CONFIG_BLK_DEV_XD is not set -CONFIG_PARIDE=m -CONFIG_PARIDE_PARPORT=m - -# -# Parallel IDE high-level drivers -# -CONFIG_PARIDE_PD=m -CONFIG_PARIDE_PCD=m -CONFIG_PARIDE_PF=m -CONFIG_PARIDE_PT=m -CONFIG_PARIDE_PG=m - -# -# Parallel IDE protocol modules -# -CONFIG_PARIDE_ATEN=m -CONFIG_PARIDE_BPCK=m -CONFIG_PARIDE_BPCK6=m -CONFIG_PARIDE_COMM=m -CONFIG_PARIDE_DSTR=m -CONFIG_PARIDE_FIT2=m -CONFIG_PARIDE_FIT3=m -CONFIG_PARIDE_EPAT=m -# CONFIG_PARIDE_EPATC8 is not set -CONFIG_PARIDE_EPIA=m -CONFIG_PARIDE_FRIQ=m -CONFIG_PARIDE_FRPW=m -CONFIG_PARIDE_KBIC=m -CONFIG_PARIDE_KTTI=m -CONFIG_PARIDE_ON20=m -CONFIG_PARIDE_ON26=m -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_CRYPTOLOOP=m -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_SX8=m -CONFIG_BLK_DEV_UB=m -CONFIG_BLK_DEV_RAM=m -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_ATA_OVER_ETH=m - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_SCSI=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=m -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=m -CONFIG_BLK_DEV_SR_VENDOR=y -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI Transport Attributes -# -CONFIG_SCSI_SPI_ATTRS=y -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_IN2000 is not set -CONFIG_MEGARAID_NEWGEN=y -CONFIG_MEGARAID_MM=m -CONFIG_MEGARAID_MAILBOX=m -# CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -CONFIG_SCSI_PPA=m -CONFIG_SCSI_IMM=m -# CONFIG_SCSI_IZIP_EPP16 is not set -# CONFIG_SCSI_IZIP_SLOW_CTR is not set -# CONFIG_SCSI_NCR53C406A is not set -CONFIG_SCSI_SYM53C8XX_2=y -CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 -CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 -CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 -# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -# CONFIG_SCSI_QLOGIC_FC is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -CONFIG_SCSI_QLA2XXX=y -# CONFIG_SCSI_QLA21XX is not set -# CONFIG_SCSI_QLA22XX is not set -# CONFIG_SCSI_QLA2300 is not set -# CONFIG_SCSI_QLA2322 is not set -# CONFIG_SCSI_QLA6312 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Old CD-ROM drivers (not SCSI, not IDE) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Multi-device support (RAID and LVM) -# -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID5=m -# CONFIG_MD_RAID6 is not set -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -# CONFIG_DM_CRYPT is not set -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -CONFIG_DM_ZERO=m - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Networking support +# Networking # CONFIG_NET=y @@ -410,12 +232,14 @@ CONFIG_NET=y # CONFIG_PACKET=m CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=m CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set CONFIG_NET_KEY=m CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y # CONFIG_IP_PNP is not set CONFIG_NET_IPIP=m CONFIG_NET_IPGRE=m @@ -429,8 +253,10 @@ CONFIG_IP_PIMSM_V2=y # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -CONFIG_IP_TCPDIAG_IPV6=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y # # IP: Virtual Server Configuration @@ -446,6 +272,9 @@ CONFIG_IPV6_TUNNEL=m CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set CONFIG_BRIDGE_NETFILTER=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m # # IP: Netfilter Configuration @@ -453,11 +282,15 @@ CONFIG_BRIDGE_NETFILTER=y CONFIG_IP_NF_CONNTRACK=m # CONFIG_IP_NF_CT_ACCT is not set CONFIG_IP_NF_CONNTRACK_MARK=y +CONFIG_IP_NF_CONNTRACK_EVENTS=y +CONFIG_IP_NF_CONNTRACK_NETLINK=m CONFIG_IP_NF_CT_PROTO_SCTP=m CONFIG_IP_NF_FTP=m CONFIG_IP_NF_IRC=m +# CONFIG_IP_NF_NETBIOS_NS is not set CONFIG_IP_NF_TFTP=m CONFIG_IP_NF_AMANDA=m +CONFIG_IP_NF_PPTP=m CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_LIMIT=m @@ -482,9 +315,11 @@ CONFIG_IP_NF_MATCH_PHYSDEV=m CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_REALM=m CONFIG_IP_NF_MATCH_SCTP=m +CONFIG_IP_NF_MATCH_DCCP=m CONFIG_IP_NF_MATCH_COMMENT=m CONFIG_IP_NF_MATCH_CONNMARK=m CONFIG_IP_NF_MATCH_HASHLIMIT=m +CONFIG_IP_NF_MATCH_STRING=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -501,12 +336,14 @@ CONFIG_IP_NF_NAT_IRC=m CONFIG_IP_NF_NAT_FTP=m CONFIG_IP_NF_NAT_TFTP=m CONFIG_IP_NF_NAT_AMANDA=m +CONFIG_IP_NF_NAT_PPTP=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_TOS=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_DSCP=m CONFIG_IP_NF_TARGET_MARK=m CONFIG_IP_NF_TARGET_CLASSIFY=m +CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_TARGET_CONNMARK=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m @@ -516,7 +353,7 @@ CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # -# IPv6: Netfilter Configuration +# IPv6: Netfilter Configuration (EXPERIMENTAL) # CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m @@ -536,8 +373,10 @@ CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_PHYSDEV=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_MARK=m +CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_RAW=m # @@ -567,9 +406,12 @@ CONFIG_BRIDGE_EBT_MARK_T=m CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m -# CONFIG_BRIDGE_EBT_ULOG is not set -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set +CONFIG_BRIDGE_EBT_ULOG=m + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set # # SCTP Configuration (EXPERIMENTAL) @@ -588,10 +430,6 @@ CONFIG_DECNET=m # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# CONFIG_NET_SCHED=y CONFIG_NET_SCH_CLK_JIFFIES=y # CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set @@ -611,6 +449,7 @@ CONFIG_NET_SCH_INGRESS=m CONFIG_NET_QOS=y CONFIG_NET_ESTIMATOR=y CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_ROUTE=y @@ -621,6 +460,7 @@ CONFIG_NET_CLS_U32=m # CONFIG_CLS_U32_MARK is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_EMATCH is not set # CONFIG_NET_CLS_ACT is not set CONFIG_NET_CLS_POLICE=y @@ -628,8 +468,6 @@ CONFIG_NET_CLS_POLICE=y # Network testing # # CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set CONFIG_HAMRADIO=y # @@ -646,8 +484,6 @@ CONFIG_ROSE=m CONFIG_MKISS=m CONFIG_6PACK=m CONFIG_BPQETHER=m -# CONFIG_DMASCC is not set -# CONFIG_SCC is not set # CONFIG_BAYCOM_SER_FDX is not set # CONFIG_BAYCOM_SER_HDX is not set # CONFIG_BAYCOM_PAR is not set @@ -655,12 +491,257 @@ CONFIG_BPQETHER=m # CONFIG_YAM is not set # CONFIG_IRDA is not set # CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +CONFIG_PARPORT=m +CONFIG_PARPORT_PC=m +CONFIG_PARPORT_SERIAL=m +# CONFIG_PARPORT_PC_FIFO is not set +# CONFIG_PARPORT_PC_SUPERIO is not set +CONFIG_PARPORT_NOT_PC=y +# CONFIG_PARPORT_GSC is not set +CONFIG_PARPORT_1284=y + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Block devices +# +CONFIG_BLK_DEV_FD=m +CONFIG_PARIDE=m +CONFIG_PARIDE_PARPORT=m + +# +# Parallel IDE high-level drivers +# +CONFIG_PARIDE_PD=m +CONFIG_PARIDE_PCD=m +CONFIG_PARIDE_PF=m +CONFIG_PARIDE_PT=m +CONFIG_PARIDE_PG=m + +# +# Parallel IDE protocol modules +# +CONFIG_PARIDE_ATEN=m +CONFIG_PARIDE_BPCK=m +CONFIG_PARIDE_BPCK6=m +CONFIG_PARIDE_COMM=m +CONFIG_PARIDE_DSTR=m +CONFIG_PARIDE_FIT2=m +CONFIG_PARIDE_FIT3=m +CONFIG_PARIDE_EPAT=m +# CONFIG_PARIDE_EPATC8 is not set +CONFIG_PARIDE_EPIA=m +CONFIG_PARIDE_FRIQ=m +CONFIG_PARIDE_FRPW=m +CONFIG_PARIDE_KBIC=m +CONFIG_PARIDE_KTTI=m +CONFIG_PARIDE_ON20=m +CONFIG_PARIDE_ON26=m +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_SX8=m +CONFIG_BLK_DEV_UB=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_LBD is not set +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_ATA_OVER_ETH=m + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR_VENDOR=y +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI Transport Attributes +# +CONFIG_SCSI_SPI_ATTRS=y +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m + +# +# SCSI low-level drivers +# +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AHA152X is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_IN2000 is not set +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_MAILBOX=m +# CONFIG_SCSI_SATA is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_DTC3280 is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GENERIC_NCR5380 is not set +# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +CONFIG_SCSI_PPA=m +CONFIG_SCSI_IMM=m +# CONFIG_SCSI_IZIP_EPP16 is not set +# CONFIG_SCSI_IZIP_SLOW_CTR is not set +# CONFIG_SCSI_NCR53C406A is not set +CONFIG_SCSI_SYM53C8XX_2=y +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_PAS16 is not set +# CONFIG_SCSI_PSI240I is not set +# CONFIG_SCSI_QLOGIC_FAS is not set +# CONFIG_SCSI_QLOGIC_FC is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +CONFIG_SCSI_QLA2XXX=y +# CONFIG_SCSI_QLA21XX is not set +# CONFIG_SCSI_QLA22XX is not set +# CONFIG_SCSI_QLA2300 is not set +# CONFIG_SCSI_QLA2322 is not set +# CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_QLA24XX is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_SYM53C416 is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_T128 is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Old CD-ROM drivers (not SCSI, not IDE) +# +# CONFIG_CD_NO_IDESCSI is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID5=m +# CONFIG_MD_RAID6 is not set +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_CRYPT is not set +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_EMC=m + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# CONFIG_NETDEVICES=y CONFIG_DUMMY=m CONFIG_BONDING=m CONFIG_EQUALIZER=m CONFIG_TUN=m -CONFIG_ETHERTAP=m # # ARCnet devices @@ -668,6 +749,21 @@ CONFIG_ETHERTAP=m # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -675,7 +771,6 @@ CONFIG_MII=y # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set @@ -696,7 +791,6 @@ CONFIG_NET_ISA=y # CONFIG_LP486E is not set # CONFIG_ETH16I is not set CONFIG_NE2000=m -# CONFIG_ZNET is not set # CONFIG_SEEQ8005 is not set CONFIG_NET_PCI=y CONFIG_PCNET32=y @@ -733,13 +827,17 @@ CONFIG_EEPRO100=m # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set CONFIG_VIA_VELOCITY=m # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -752,6 +850,8 @@ CONFIG_VIA_VELOCITY=m # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # Wan interfaces @@ -765,6 +865,8 @@ CONFIG_PLIP=m # CONFIG_NET_FC is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -794,20 +896,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -CONFIG_SERIO_PARKBD=m -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y @@ -828,6 +916,18 @@ CONFIG_MOUSE_PS2=y # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_PARKBD=m +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -844,13 +944,13 @@ CONFIG_SERIAL_8250_EXTENDED=y # CONFIG_SERIAL_8250_MANY_PORTS is not set CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_MULTIPORT=y CONFIG_SERIAL_8250_RSA=y # # Non-8250 serial port support # CONFIG_SERIAL_CORE=m +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -881,6 +981,11 @@ CONFIG_RTC=m # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -891,15 +996,26 @@ CONFIG_RTC=m CONFIG_W1=m CONFIG_W1_MATROX=m CONFIG_W1_DS9490=m -CONFIG_W1_DS9490_BRIDGE=m +# CONFIG_W1_DS9490_BRIDGE is not set CONFIG_W1_THERM=m CONFIG_W1_SMEM=m +# CONFIG_W1_DS2433 is not set + +# +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set # # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -920,7 +1036,6 @@ CONFIG_W1_SMEM=m CONFIG_VGA_CONSOLE=y # CONFIG_MDA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -930,6 +1045,8 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB=m # CONFIG_USB_DEBUG is not set @@ -940,8 +1057,6 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_BANDWIDTH is not set # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y # # USB Host Controller Drivers @@ -949,7 +1064,10 @@ CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_EHCI_HCD=m # CONFIG_USB_EHCI_SPLIT_ISO is not set # CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_ISP116X_HCD is not set CONFIG_USB_OHCI_HCD=m +# CONFIG_USB_OHCI_BIG_ENDIAN is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_UHCI_HCD=m # CONFIG_USB_SL811_HCD is not set @@ -965,11 +1083,10 @@ CONFIG_USB_PRINTER=m # CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_RW_DETECT is not set CONFIG_USB_STORAGE_DATAFAB=y CONFIG_USB_STORAGE_FREECOM=y CONFIG_USB_STORAGE_DPCM=y -CONFIG_USB_STORAGE_HP8200e=y +# CONFIG_USB_STORAGE_USBAT is not set CONFIG_USB_STORAGE_SDDR09=y CONFIG_USB_STORAGE_SDDR55=y CONFIG_USB_STORAGE_JUMPSHOT=y @@ -992,12 +1109,17 @@ CONFIG_USB_KBD=m CONFIG_USB_MOUSE=m CONFIG_USB_AIPTEK=m CONFIG_USB_WACOM=m +# CONFIG_USB_ACECAD is not set CONFIG_USB_KBTAB=m CONFIG_USB_POWERMATE=m # CONFIG_USB_MTOUCH is not set +# CONFIG_USB_ITMTOUCH is not set CONFIG_USB_EGALAX=m +CONFIG_USB_YEALINK=m CONFIG_USB_XPAD=m # CONFIG_USB_ATI_REMOTE is not set +# CONFIG_USB_KEYSPAN_REMOTE is not set +# CONFIG_USB_APPLETOUCH is not set # # USB Imaging devices @@ -1022,30 +1144,15 @@ CONFIG_USB_KAWETH=m CONFIG_USB_PEGASUS=m CONFIG_USB_RTL8150=m CONFIG_USB_USBNET=m - -# -# USB Host-to-Host Cables -# -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_BELKIN=y -CONFIG_USB_GENESYS=y -CONFIG_USB_NET1080=y -CONFIG_USB_PL2301=y -CONFIG_USB_KC2190=y - -# -# Intelligent USB Devices/Gadgets -# -CONFIG_USB_ARMLINUX=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_ZAURUS=y -CONFIG_USB_CDCETHER=y - -# -# USB Network Adapters -# -CONFIG_USB_AX8817X=y +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_CDCETHER=m +# CONFIG_USB_NET_GL620A is not set +CONFIG_USB_NET_NET1080=m +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_MON=y # # USB port drivers @@ -1057,9 +1164,11 @@ CONFIG_USB_USS720=m # CONFIG_USB_SERIAL=m CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_AIRPRIME=m CONFIG_USB_SERIAL_BELKIN=m CONFIG_USB_SERIAL_WHITEHEAT=m CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +# CONFIG_USB_SERIAL_CP2101 is not set CONFIG_USB_SERIAL_CYPRESS_M8=m CONFIG_USB_SERIAL_EMPEG=m CONFIG_USB_SERIAL_FTDI_SIO=m @@ -1088,6 +1197,7 @@ CONFIG_USB_SERIAL_KLSI=m CONFIG_USB_SERIAL_KOBIL_SCT=m CONFIG_USB_SERIAL_MCT_U232=m CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_HP4X=m CONFIG_USB_SERIAL_SAFE=m CONFIG_USB_SERIAL_SAFE_PADDED=y # CONFIG_USB_SERIAL_TI is not set @@ -1110,10 +1220,13 @@ CONFIG_USB_CYTHERM=m CONFIG_USB_PHIDGETKIT=m CONFIG_USB_PHIDGETSERVO=m # CONFIG_USB_IDMOUSE is not set +CONFIG_USB_SISUSBVGA=m +# CONFIG_USB_SISUSBVGA_CON is not set +CONFIG_USB_LD=m CONFIG_USB_TEST=m # -# USB ATM/DSL drivers +# USB DSL modem support # # @@ -1132,10 +1245,15 @@ CONFIG_USB_TEST=m # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=m # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set @@ -1152,17 +1270,20 @@ CONFIG_REISERFS_FS_SECURITY=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_XFS_FS=m -# CONFIG_XFS_RT is not set -CONFIG_XFS_QUOTA=y +CONFIG_XFS_EXPORT=y +CONFIG_XFS_QUOTA=m CONFIG_XFS_SECURITY=y # CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set CONFIG_MINIX_FS=m CONFIG_ROMFS_FS=m +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_QUOTACTL=y CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -1192,12 +1313,10 @@ CONFIG_NTFS_FS=m CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -1224,15 +1343,18 @@ CONFIG_UFS_FS=m # CONFIG_NFS_FS=m CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=m CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set # CONFIG_NFSD_V4 is not set CONFIG_NFSD_TCP=y CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m CONFIG_RPCSEC_GSS_KRB5=m @@ -1256,6 +1378,7 @@ CONFIG_CODA_FS=m CONFIG_CODA_FS_OLD_API=y CONFIG_AFS_FS=m CONFIG_RXRPC=m +# CONFIG_9P_FS is not set # # Partition Types @@ -1329,7 +1452,9 @@ CONFIG_NLS_UTF8=m # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -1352,6 +1477,7 @@ CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_TWOFISH=m @@ -1360,13 +1486,13 @@ CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_TEA=m -# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_MICHAEL_MIC=m -# CONFIG_CRYPTO_CRC32C is not set -CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -1376,9 +1502,12 @@ CONFIG_CRYPTO_TEST=m # Library routines # CONFIG_CRC_CCITT=m +CONFIG_CRC16=m CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set +CONFIG_LIBCRC32C=m CONFIG_ZLIB_INFLATE=m CONFIG_ZLIB_DEFLATE=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index 1dc935f37582..4365d9c8c42e 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:10 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:27:05 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,30 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=15 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_CPUSETS=y +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -57,32 +61,49 @@ CONFIG_STOP_MACHINE=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -CONFIG_SIBYTE_SB1xxx_SOC=y +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set CONFIG_SIBYTE_SWARM=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set @@ -91,9 +112,12 @@ CONFIG_SIBYTE_SWARM=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_UNKNOWN is not set -CONFIG_SIBYTE_BOARD=y +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_SIBYTE_SB1250=y +CONFIG_SIBYTE_SB1xxx_SOC=y CONFIG_CPU_SB1_PASS_1=y # CONFIG_CPU_SB1_PASS_2_1250 is not set # CONFIG_CPU_SB1_PASS_2_2 is not set @@ -102,18 +126,20 @@ CONFIG_CPU_SB1_PASS_1=y # CONFIG_CPU_SB1_PASS_3 is not set CONFIG_SIBYTE_HAS_LDT=y # CONFIG_SIMULATION is not set +# CONFIG_CONFIG_SB1_CEX_ALWAYS_FATAL is not set +# CONFIG_CONFIG_SB1_CERR_STALL is not set CONFIG_SIBYTE_CFE=y # CONFIG_SIBYTE_CFE_CONSOLE is not set # CONFIG_SIBYTE_BUS_WATCHER is not set # CONFIG_SIBYTE_SB1250_PROF is not set # CONFIG_SIBYTE_TBPROF is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_COHERENT=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_SWAP_IO_SPACE=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -121,8 +147,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -138,22 +166,46 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set CONFIG_CPU_SB1=y +CONFIG_SYS_HAS_CPU_SB1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +# CONFIG_32BIT is not set +CONFIG_64BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set # CONFIG_SIBYTE_DMA_PAGEOPS is not set CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set CONFIG_SB1_PASS_1_WORKAROUNDS=y -# CONFIG_64BIT_PHYS_ADDR is not set -# CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y -# CONFIG_HIGHMEM is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SMP=y CONFIG_NR_CPUS=2 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set +CONFIG_PREEMPT_BKL=y # # Bus options (PCI, PCMCIA, EISA, ISA, TC) @@ -161,7 +213,6 @@ CONFIG_NR_CPUS=2 CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y CONFIG_MMU=y # @@ -170,10 +221,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -183,7 +230,86 @@ CONFIG_MMU=y # CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y +# CONFIG_BUILD_ELF64 is not set +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_MIPS32_O32=y +# CONFIG_MIPS32_N32 is not set +CONFIG_BINFMT_ELF32=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m # # Device Drivers @@ -194,7 +320,12 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) @@ -213,7 +344,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -226,8 +356,6 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=9220 CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 # CONFIG_CDROM_PKTCDVD_WCACHE is not set @@ -263,7 +391,7 @@ CONFIG_BLK_DEV_IDEFLOPPY=y # CONFIG_IDE_GENERIC=y # CONFIG_BLK_DEV_IDEPCI is not set -CONFIG_BLK_DEV_IDE_SWARM=y +# CONFIG_BLK_DEV_IDE_SWARM is not set # CONFIG_IDE_ARM is not set # CONFIG_BLK_DEV_IDEDMA is not set # CONFIG_IDEDMA_AUTO is not set @@ -272,6 +400,7 @@ CONFIG_BLK_DEV_IDE_SWARM=y # # SCSI device support # +CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set # @@ -282,6 +411,7 @@ CONFIG_BLK_DEV_IDE_SWARM=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -294,78 +424,13 @@ CONFIG_BLK_DEV_IDE_SWARM=y # CONFIG_I2O is not set # -# Networking support +# Network device support # -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -373,6 +438,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -399,12 +479,16 @@ CONFIG_MII=y # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set CONFIG_NET_SB1250_MAC=y +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -417,6 +501,8 @@ CONFIG_NET_SB1250_MAC=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # Wan interfaces @@ -428,6 +514,8 @@ CONFIG_NET_SB1250_MAC=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -445,25 +533,15 @@ CONFIG_NET_SB1250_MAC=y # CONFIG_INPUT is not set # -# Userland interfaces -# - -# -# Input I/O drivers +# Hardware I/O ports # -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y CONFIG_SERIO=y # CONFIG_SERIO_I8042 is not set CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set # CONFIG_SERIO_PCIPS2 is not set # CONFIG_SERIO_LIBPS2 is not set CONFIG_SERIO_RAW=m - -# -# Input Device Drivers -# +# CONFIG_GAMEPORT is not set # # Character devices @@ -472,11 +550,13 @@ CONFIG_SERIO_RAW=m CONFIG_SERIAL_NONSTANDARD=y # CONFIG_ROCKETPORT is not set # CONFIG_CYCLADES is not set +# CONFIG_DIGIEPCA is not set # CONFIG_MOXA_SMARTIO is not set # CONFIG_ISI is not set -# CONFIG_SYNCLINK is not set # CONFIG_SYNCLINKMP is not set # CONFIG_N_HDLC is not set +# CONFIG_SPECIALIX is not set +# CONFIG_SX is not set # CONFIG_STALDRV is not set CONFIG_SIBYTE_SB1250_DUART=y CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y @@ -489,6 +569,7 @@ CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y # # Non-8250 serial port support # +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -515,6 +596,11 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -525,10 +611,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -542,7 +638,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -552,13 +647,9 @@ CONFIG_LEGACY_PTY_COUNT=256 # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -576,12 +667,17 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set CONFIG_FS_MBCACHE=y @@ -591,10 +687,12 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -615,11 +713,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -643,13 +740,14 @@ CONFIG_RAMFS=y # CONFIG_NFS_FS=y CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y -# CONFIG_EXPORTFS is not set +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -658,6 +756,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -678,7 +777,9 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=15 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" # CONFIG_SB1XXX_CORELIS is not set @@ -695,27 +796,28 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_CRYPTO=y CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_AES=m -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_TEA=m -# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y -# CONFIG_CRYPTO_CRC32C is not set +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m # CONFIG_CRYPTO_TEST is not set # @@ -726,9 +828,8 @@ CONFIG_CRYPTO_MICHAEL_MIC=y # Library routines # # CONFIG_CRC_CCITT is not set +CONFIG_CRC16=m CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig index dd07e866b128..d835f6db1f41 100644 --- a/arch/mips/configs/sead_defconfig +++ b/arch/mips/configs/sead_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:10 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:27:07 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,22 +11,26 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" -CONFIG_SWAP=y -# CONFIG_SYSVIPC is not set +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -39,6 +40,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -48,40 +50,69 @@ CONFIG_CC_ALIGN_JUMPS=0 # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set CONFIG_MIPS_SEAD=y +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_BOARDS_GEN=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -89,8 +120,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS64 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -106,15 +139,42 @@ CONFIG_CPU_MIPS32=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -128,10 +188,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -143,6 +199,11 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +# CONFIG_NET is not set + +# # Device Drivers # @@ -154,6 +215,10 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set # +# Connector - unified userspace <-> kernelspace linker +# + +# # Memory Technology Devices (MTD) # # CONFIG_MTD is not set @@ -170,7 +235,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set @@ -178,11 +242,8 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=18432 CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=y -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_CDROM_PKTCDVD is not set # # IO Schedulers @@ -200,6 +261,7 @@ CONFIG_IOSCHED_CFQ=y # # SCSI device support # +CONFIG_RAID_ATTRS=y # CONFIG_SCSI is not set # @@ -210,6 +272,7 @@ CONFIG_IOSCHED_CFQ=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -220,9 +283,8 @@ CONFIG_IOSCHED_CFQ=y # # -# Networking support +# Network device support # -# CONFIG_NET is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set @@ -238,47 +300,18 @@ CONFIG_IOSCHED_CFQ=y # # Input device support # -CONFIG_INPUT=y +# CONFIG_INPUT is not set # -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input I/O drivers +# Hardware I/O ports # +# CONFIG_SERIO is not set # CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set # # Character devices # -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y +# CONFIG_VT is not set # CONFIG_SERIAL_NONSTANDARD is not set # @@ -294,7 +327,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_UNIX98_PTYS is not set +CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -315,10 +348,13 @@ CONFIG_LEGACY_PTY_COUNT=256 # # Ftape, the floppy tape device driver # -# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -329,10 +365,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -347,13 +393,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_FB is not set # -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# # Sound # # CONFIG_SOUND is not set @@ -365,10 +404,6 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -381,28 +416,31 @@ CONFIG_DUMMY_CONSOLE=y # # InfiniBand support # -# CONFIG_INFINIBAND is not set + +# +# SN Devices +# # # File systems # CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set -CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=y # # CD-ROM/DVD Filesystems @@ -423,10 +461,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=y # # Miscellaneous filesystems @@ -448,8 +486,18 @@ CONFIG_RAMFS=y # # Partition Types # -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +# CONFIG_MSDOS_PARTITION is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_EFI_PARTITION is not set # # Native Language Support @@ -464,15 +512,16 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" # # Security options # -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y +# CONFIG_KEYS is not set # CONFIG_SECURITY is not set # @@ -488,7 +537,6 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y # CONFIG_CRC32 is not set # CONFIG_LIBCRC32C is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index c9d3f83caf0f..bf60a17de2b0 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:12 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:27:10 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,55 +59,87 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -CONFIG_MACH_VR41XX=y -# CONFIG_NEC_CMBVR4133 is not set -# CONFIG_CASIO_E55 is not set -# CONFIG_IBM_WORKPAD is not set -CONFIG_TANBAC_TB0226=y -# CONFIG_TANBAC_TB0229 is not set -# CONFIG_VICTOR_MPC30X is not set -# CONFIG_ZAO_CAPCELLA is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +CONFIG_MACH_VR41XX=y +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_NEC_CMBVR4133 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_IBM_WORKPAD is not set +CONFIG_TANBAC_TB022X=y +CONFIG_TANBAC_TB0226=y +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_PCI_VR41XX=y +# CONFIG_VRC4173 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set CONFIG_CPU_VR41XX=y @@ -120,19 +155,44 @@ CONFIG_CPU_VR41XX=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_VR41XX=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_HW_HAS_PCI=y -# CONFIG_PCI is not set +CONFIG_PCI=y +# CONFIG_PCI_LEGACY_PROC is not set CONFIG_MMU=y # @@ -141,12 +201,9 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # +# CONFIG_HOTPLUG_PCI is not set # # Executable file formats @@ -156,6 +213,87 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -167,6 +305,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set # +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m + +# # Memory Technology Devices (MTD) # # CONFIG_MTD is not set @@ -183,19 +326,21 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=m # CONFIG_BLK_DEV_CRYPTOLOOP is not set CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_CDROM_PKTCDVD is not set # # IO Schedulers @@ -209,33 +354,12 @@ CONFIG_ATA_OVER_ETH=m # # ATA/ATAPI/MFM/RLL support # -CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -CONFIG_IDEDISK_MULTI_MODE=y -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -CONFIG_BLK_DEV_IDESCSI=y -# CONFIG_IDE_TASK_IOCTL is not set - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=y -# CONFIG_IDE_ARM is not set -# CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set +# CONFIG_IDE is not set # # SCSI device support # +# CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_PROC_FS=y @@ -245,15 +369,15 @@ CONFIG_SCSI_PROC_FS=y CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set -CONFIG_CHR_DEV_SG=y +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs # CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # @@ -262,11 +386,42 @@ CONFIG_SCSI_CONSTANTS=y # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set # # SCSI low-level drivers # +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set # CONFIG_SCSI_SATA is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_FC is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +CONFIG_SCSI_QLA2XXX=y +# CONFIG_SCSI_QLA21XX is not set +# CONFIG_SCSI_QLA22XX is not set +# CONFIG_SCSI_QLA2300 is not set +# CONFIG_SCSI_QLA2322 is not set +# CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_QLA24XX is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # @@ -277,131 +432,132 @@ CONFIG_SCSI_CONSTANTS=y # # Fusion MPT device support # +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set # # IEEE 1394 (FireWire) support # +# CONFIG_IEEE1394 is not set # # I2O device support # +# CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options +# Network device support # -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=m -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set # -# SCTP Configuration (EXPERIMENTAL) +# ARCnet devices # -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set +# CONFIG_ARCNET is not set # -# QoS and/or fair queueing +# PHY device support # -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y # -# Network testing +# MII PHY device drivers # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +CONFIG_EEPRO100=y +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_LAN_SAA9730 is not set # # Ethernet (1000 Mbit) # +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set # # Token Ring devices # +# CONFIG_TR is not set # # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW2200 is not set # # Wan interfaces # # CONFIG_WAN is not set -CONFIG_PPP=m -CONFIG_PPP_MULTILINK=y -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPPOE=m +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_NET_FC is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -421,28 +577,13 @@ CONFIG_INPUT=y # # Userland interfaces # -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -452,6 +593,12 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -462,16 +609,16 @@ CONFIG_HW_CONSOLE=y # # Serial drivers # -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_VR41XX=y +CONFIG_SERIAL_VR41XX_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -489,14 +636,22 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_TANBAC_TB0219 is not set # # Ftape, the floppy tape device driver # # CONFIG_DRM is not set +CONFIG_GPIO_VR41XX=y # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -507,10 +662,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -523,48 +688,147 @@ CONFIG_LEGACY_PTY_COUNT=256 # # Graphics support # -CONFIG_FB=y -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set -# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB is not set # # Console display driver support # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE is not set # -# Logo configuration +# Sound # -# CONFIG_LOGO is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +# CONFIG_SOUND is not set # -# Sound +# USB support # -CONFIG_SOUND=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set # -# Advanced Linux Sound Architecture +# Miscellaneous USB options # -# CONFIG_SND is not set +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_BANDWIDTH is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set # -# Open Sound System +# USB Host Controller Drivers # -# CONFIG_SOUND_PRIME is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_SPLIT_ISO is not set +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set # -# USB support +# USB Device Class drivers # -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_BLUETOOTH_TTY is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information # +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_AIPTEK is not set +# CONFIG_USB_WACOM is not set +# CONFIG_USB_ACECAD is not set +# CONFIG_USB_KBTAB is not set +# CONFIG_USB_POWERMATE is not set +# CONFIG_USB_MTOUCH is not set +# CONFIG_USB_ITMTOUCH is not set +# CONFIG_USB_EGALAX is not set +# CONFIG_USB_YEALINK is not set +# CONFIG_USB_XPAD is not set +# CONFIG_USB_ATI_REMOTE is not set +# CONFIG_USB_KEYSPAN_REMOTE is not set +# CONFIG_USB_APPLETOUCH is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB Multimedia devices +# +# CONFIG_USB_DABUSB is not set + +# +# Video4Linux support is needed for USB Multimedia device support +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGETKIT is not set +# CONFIG_USB_PHIDGETSERVO is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# # # USB Gadget Support @@ -582,39 +846,41 @@ CONFIG_SOUND=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set CONFIG_ROMFS_FS=m +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems # -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_ZISOFS_FS=y +# CONFIG_ISO9660_FS is not set # CONFIG_UDF_FS is not set # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # @@ -623,13 +889,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -653,16 +916,19 @@ CONFIG_CRAMFS=m # CONFIG_NFS_FS=y CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=m CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set # CONFIG_NFSD_V4 is not set # CONFIG_NFSD_TCP is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -673,6 +939,7 @@ CONFIG_SMB_NLS_REMOTE="cp932" # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -732,9 +999,11 @@ CONFIG_NLS_ISO8859_1=m # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" +CONFIG_CMDLINE="mem=32M console=ttyVR0,115200" # # Security options @@ -746,7 +1015,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -756,9 +1049,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # CONFIG_CRC_CCITT=m -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y +CONFIG_CRC16=m +CONFIG_CRC32=m +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=m CONFIG_ZLIB_DEFLATE=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y diff --git a/arch/mips/configs/tb0229_defconfig b/arch/mips/configs/tb0229_defconfig index 2cb669188aa9..ac8b64e87b8a 100644 --- a/arch/mips/configs/tb0229_defconfig +++ b/arch/mips/configs/tb0229_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:12 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:27:13 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,58 +59,87 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -CONFIG_MACH_VR41XX=y -# CONFIG_NEC_CMBVR4133 is not set -# CONFIG_CASIO_E55 is not set -# CONFIG_IBM_WORKPAD is not set -# CONFIG_TANBAC_TB0226 is not set -CONFIG_TANBAC_TB0229=y -CONFIG_TANBAC_TB0219=y -# CONFIG_VICTOR_MPC30X is not set -# CONFIG_ZAO_CAPCELLA is not set -CONFIG_PCI_VR41XX=y -# CONFIG_VRC4173 is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +CONFIG_MACH_VR41XX=y +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_NEC_CMBVR4133 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_IBM_WORKPAD is not set +CONFIG_TANBAC_TB022X=y +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_PCI_VR41XX=y +# CONFIG_VRC4173 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set CONFIG_CPU_VR41XX=y @@ -123,12 +155,36 @@ CONFIG_CPU_VR41XX=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_VR41XX=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -136,8 +192,7 @@ CONFIG_CPU_HAS_SYNC=y # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y -CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y +# CONFIG_PCI_LEGACY_PROC is not set CONFIG_MMU=y # @@ -146,10 +201,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -162,6 +213,88 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE=m +# CONFIG_NET_IPGRE_BROADCAST is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -170,7 +303,12 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) @@ -189,7 +327,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -199,11 +336,11 @@ CONFIG_BLK_DEV_LOOP=m # CONFIG_BLK_DEV_CRYPTOLOOP is not set CONFIG_BLK_DEV_NBD=m # CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_INITRD is not set -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -226,6 +363,7 @@ CONFIG_ATA_OVER_ETH=m # # SCSI device support # +# CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # @@ -236,6 +374,7 @@ CONFIG_ATA_OVER_ETH=m # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -248,83 +387,13 @@ CONFIG_ATA_OVER_ETH=m # CONFIG_I2O is not set # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=m -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m -# CONFIG_NET_IPGRE_BROADCAST is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing +# Network device support # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y CONFIG_DUMMY=m # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -332,6 +401,21 @@ CONFIG_DUMMY=m # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -346,7 +430,7 @@ CONFIG_MII=y # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set CONFIG_NET_PCI=y -CONFIG_PCNET32=y +# CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set # CONFIG_ADAPTEC_STARFIRE is not set # CONFIG_B44 is not set @@ -358,7 +442,11 @@ CONFIG_EEPRO100=y # CONFIG_NATSEMI is not set # CONFIG_NE2K_PCI is not set # CONFIG_8139CP is not set -# CONFIG_8139TOO is not set +CONFIG_8139TOO=y +CONFIG_8139TOO_PIO=y +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139TOO_8129 is not set +# CONFIG_8139_OLD_RX_RESET is not set # CONFIG_SIS900 is not set # CONFIG_EPIC100 is not set # CONFIG_SUNDANCE is not set @@ -375,14 +463,19 @@ CONFIG_EEPRO100=y # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set +CONFIG_R8169=y +# CONFIG_R8169_NAPI is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -395,6 +488,8 @@ CONFIG_EEPRO100=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # Wan interfaces @@ -416,6 +511,8 @@ CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -435,29 +532,13 @@ CONFIG_INPUT=y # # Userland interfaces # -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -467,6 +548,12 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -477,16 +564,16 @@ CONFIG_HW_CONSOLE=y # # Serial drivers # -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_VR41XX=y +CONFIG_SERIAL_VR41XX_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -505,14 +592,21 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set +CONFIG_TANBAC_TB0219=y # # Ftape, the floppy tape device driver # # CONFIG_DRM is not set +CONFIG_GPIO_VR41XX=y # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -523,10 +617,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -546,7 +650,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -556,13 +659,122 @@ CONFIG_DUMMY_CONSOLE=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB=m +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_BANDWIDTH is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=m +# CONFIG_USB_EHCI_SPLIT_ISO is not set +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=m +# CONFIG_USB_OHCI_BIG_ENDIAN is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_BLUETOOTH_TTY is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information # +# CONFIG_USB_STORAGE is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_AIPTEK is not set +# CONFIG_USB_WACOM is not set +# CONFIG_USB_ACECAD is not set +# CONFIG_USB_KBTAB is not set +# CONFIG_USB_POWERMATE is not set +# CONFIG_USB_MTOUCH is not set +# CONFIG_USB_ITMTOUCH is not set +# CONFIG_USB_EGALAX is not set +# CONFIG_USB_YEALINK is not set +# CONFIG_USB_XPAD is not set +# CONFIG_USB_ATI_REMOTE is not set +# CONFIG_USB_KEYSPAN_REMOTE is not set +# CONFIG_USB_APPLETOUCH is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set + +# +# USB Multimedia devices +# +# CONFIG_USB_DABUSB is not set + +# +# Video4Linux support is needed for USB Multimedia device support +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGETKIT is not set +# CONFIG_USB_PHIDGETSERVO is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# # # USB Gadget Support @@ -580,10 +792,15 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=m CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set @@ -597,18 +814,22 @@ CONFIG_JFS_FS=m # CONFIG_JFS_SECURITY is not set # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set +# CONFIG_FS_POSIX_ACL is not set CONFIG_XFS_FS=y -# CONFIG_XFS_RT is not set +CONFIG_XFS_EXPORT=y CONFIG_XFS_QUOTA=y # CONFIG_XFS_SECURITY is not set CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set # CONFIG_MINIX_FS is not set CONFIG_ROMFS_FS=m +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_QUOTACTL=y CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -635,13 +856,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -665,16 +883,19 @@ CONFIG_CRAMFS=m # CONFIG_NFS_FS=y CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=y CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set # CONFIG_NFSD_V4 is not set CONFIG_NFSD_TCP=y CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -685,6 +906,7 @@ CONFIG_SMB_NLS_REMOTE="cp932" # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -744,9 +966,11 @@ CONFIG_NLS_ISO8859_1=m # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="mem=64M console=ttyS0,38400 ip=bootp root=/dev/nfs" +CONFIG_CMDLINE="mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs" # # Security options @@ -758,7 +982,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -768,9 +1016,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # CONFIG_CRC_CCITT=m +CONFIG_CRC16=m CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set +CONFIG_LIBCRC32C=m CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig index 17b9f2f65ba0..95344832d66e 100644 --- a/arch/mips/configs/tb0287_defconfig +++ b/arch/mips/configs/tb0287_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.13-mm1 -# Thu Sep 1 22:58:34 2005 +# Linux kernel version: 2.6.14-rc5-mm1 +# Tue Oct 25 00:20:22 2005 # CONFIG_MIPS=y @@ -19,6 +19,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y +CONFIG_SWAP_PREFETCH=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set @@ -55,74 +56,91 @@ CONFIG_OBSOLETE_MODPARM=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_KMOD=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set # # Machine selection # -# CONFIG_MACH_JAZZ is not set -CONFIG_MACH_VR41XX=y -# CONFIG_NEC_CMBVR4133 is not set -# CONFIG_CASIO_E55 is not set -# CONFIG_IBM_WORKPAD is not set -CONFIG_TANBAC_TB022X=y -# CONFIG_TANBAC_TB0226 is not set -CONFIG_TANBAC_TB0287=y -# CONFIG_VICTOR_MPC30X is not set -# CONFIG_ZAO_CAPCELLA is not set -CONFIG_PCI_VR41XX=y -# CONFIG_VRC4173 is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set +CONFIG_MACH_VR41XX=y +# CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_NEC_CMBVR4133 is not set +CONFIG_TANBAC_TB022X=y +# CONFIG_TANBAC_TB0226 is not set +CONFIG_TANBAC_TB0287=y +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_PCI_VR41XX=y +# CONFIG_VRC4173 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set CONFIG_CPU_VR41XX=y @@ -138,12 +156,25 @@ CONFIG_CPU_VR41XX=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y @@ -152,6 +183,9 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -262,7 +296,6 @@ CONFIG_TCP_CONG_HTCP=m # Network testing # # CONFIG_NET_PKTGEN is not set -# CONFIG_NETFILTER_NETLINK is not set # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set @@ -280,6 +313,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set # +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# # Memory Technology Devices (MTD) # # CONFIG_MTD is not set @@ -296,7 +334,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -312,6 +349,7 @@ CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_INITRD is not set # CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_CDROM_PKTCDVD is not set # @@ -321,6 +359,11 @@ CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_ATA_OVER_ETH is not set # @@ -410,13 +453,20 @@ CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set + +# +# SCSI Transport Layers +# +# CONFIG_SAS_CLASS is not set # # SCSI low-level drivers # +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_ARCMSR is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_ARCMSR is not set # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set @@ -425,12 +475,10 @@ CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_DPT_I2O is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set # CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set @@ -462,6 +510,7 @@ CONFIG_SCSI_QLA2XXX=y # CONFIG_FUSION is not set # CONFIG_FUSION_SPI is not set # CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set # # IEEE 1394 (FireWire) support @@ -529,6 +578,7 @@ CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set # @@ -572,6 +622,7 @@ CONFIG_R8169=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_HOSTAP is not set # # Wan interfaces @@ -682,6 +733,7 @@ CONFIG_GPIO_VR41XX=y # TPM devices # # CONFIG_TCG_TPM is not set +# CONFIG_TELCLOCK is not set # # I2C support @@ -770,12 +822,15 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # # USB Device Class drivers # -# CONFIG_USB_BLUETOOTH_TTY is not set # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information # CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_DEBUG is not set @@ -891,6 +946,11 @@ CONFIG_USB_MON=y # # +# EDAC - error detection and reporting (RAS) +# +# CONFIG_EDAC is not set + +# # Distributed Lock Manager # # CONFIG_DLM is not set @@ -901,20 +961,22 @@ CONFIG_USB_MON=y CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y # CONFIG_REISER4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set - -# -# XFS support -# CONFIG_XFS_FS=y -# CONFIG_XFS_RT is not set CONFIG_XFS_QUOTA=y # CONFIG_XFS_SECURITY is not set CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set # CONFIG_OCFS2_FS is not set # CONFIG_MINIX_FS is not set CONFIG_ROMFS_FS=m @@ -948,8 +1010,8 @@ CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set # CONFIG_RELAYFS_FS is not set +# CONFIG_CONFIGFS_FS is not set # # Miscellaneous filesystems @@ -1004,6 +1066,11 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_NLS is not set # +# Profiling support +# +# CONFIG_PROFILING is not set + +# # Kernel hacking # # CONFIG_PRINTK_TIME is not set @@ -1036,6 +1103,3 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y CONFIG_CRC32=y # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_ISA_DMA_API=y diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig index 16e07fca446f..ab13621ef3b9 100644 --- a/arch/mips/configs/workpad_defconfig +++ b/arch/mips/configs/workpad_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:12 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:27:16 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,24 +11,29 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,56 +59,84 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -CONFIG_MACH_VR41XX=y -# CONFIG_NEC_CMBVR4133 is not set -# CONFIG_CASIO_E55 is not set -CONFIG_IBM_WORKPAD=y -# CONFIG_TANBAC_TB0226 is not set -# CONFIG_TANBAC_TB0229 is not set -# CONFIG_VICTOR_MPC30X is not set -# CONFIG_ZAO_CAPCELLA is not set -CONFIG_VRC4171=y -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +CONFIG_MACH_VR41XX=y +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_NEC_CMBVR4133 is not set +# CONFIG_CASIO_E55 is not set +CONFIG_IBM_WORKPAD=y +# CONFIG_TANBAC_TB022X is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set CONFIG_CPU_VR41XX=y @@ -121,12 +152,36 @@ CONFIG_CPU_VR41XX=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_VR41XX=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # @@ -138,11 +193,17 @@ CONFIG_MMU=y # # PCCARD (PCMCIA/CardBus) support # -# CONFIG_PCCARD is not set +CONFIG_PCCARD=y +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y # # PC-card bridges # +# CONFIG_I82365 is not set +# CONFIG_TCIC is not set CONFIG_PCMCIA_PROBE=y # @@ -157,6 +218,78 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -165,7 +298,12 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=y + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) @@ -185,18 +323,13 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_CDROM_PKTCDVD is not set # # IO Schedulers @@ -219,6 +352,7 @@ CONFIG_BLK_DEV_IDE=y # CONFIG_BLK_DEV_IDE_SATA is not set CONFIG_BLK_DEV_IDEDISK=y # CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECS=m # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set # CONFIG_BLK_DEV_IDEFLOPPY is not set @@ -237,6 +371,7 @@ CONFIG_IDE_GENERIC=y # # SCSI device support # +# CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # @@ -252,6 +387,7 @@ CONFIG_IDE_GENERIC=y # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -262,76 +398,13 @@ CONFIG_IDE_GENERIC=y # # -# Networking support -# -CONFIG_NET=y - +# Network device support # -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -339,12 +412,26 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set +CONFIG_MII=m # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set # CONFIG_AT1700 is not set @@ -373,6 +460,19 @@ CONFIG_NET_ETHERNET=y # CONFIG_NET_RADIO is not set # +# PCMCIA network device support +# +CONFIG_NET_PCMCIA=y +CONFIG_PCMCIA_3C589=m +CONFIG_PCMCIA_3C574=m +CONFIG_PCMCIA_FMVJ18X=m +CONFIG_PCMCIA_PCNET=m +CONFIG_PCMCIA_NMCLAN=m +CONFIG_PCMCIA_SMC91C92=m +CONFIG_PCMCIA_XIRC2PS=m +CONFIG_PCMCIA_AXNET=m + +# # Wan interfaces # # CONFIG_WAN is not set @@ -380,6 +480,8 @@ CONFIG_NET_ETHERNET=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -409,18 +511,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -430,6 +520,16 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -440,16 +540,15 @@ CONFIG_HW_CONSOLE=y # # Serial drivers # -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_VR41XX=y +CONFIG_SERIAL_VR41XX_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -484,10 +583,19 @@ CONFIG_WATCHDOG=y # # Ftape, the floppy tape device driver # -# CONFIG_DRM is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_GPIO_VR41XX is not set # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -498,10 +606,20 @@ CONFIG_WATCHDOG=y # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -522,7 +640,6 @@ CONFIG_WATCHDOG=y # CONFIG_VGA_CONSOLE is not set # CONFIG_MDA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -536,10 +653,6 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -552,7 +665,10 @@ CONFIG_DUMMY_CONSOLE=y # # InfiniBand support # -# CONFIG_INFINIBAND is not set + +# +# SN Devices +# # # File systems @@ -561,6 +677,7 @@ CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set CONFIG_FS_MBCACHE=y @@ -570,10 +687,12 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -594,12 +713,10 @@ CONFIG_AUTOFS4_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -630,6 +747,7 @@ CONFIG_NFSD=y # CONFIG_NFSD_TCP is not set CONFIG_LOCKD=y CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -638,6 +756,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -658,9 +777,11 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" +CONFIG_CMDLINE="console=ttyVR0,19200 mem=16M" # # Security options @@ -672,7 +793,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -682,7 +827,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CRC16=m +CONFIG_CRC32=y +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig index 6d2290777ad7..5b0b7f30e205 100644 --- a/arch/mips/configs/yosemite_defconfig +++ b/arch/mips/configs/yosemite_defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:13 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:27:18 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,25 +11,31 @@ CONFIG_32BIT=y # CONFIG_EXPERIMENTAL is not set CONFIG_CLEAN_COMPILE=y CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +# CONFIG_CPUSETS is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -42,6 +45,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,34 +60,68 @@ CONFIG_STOP_MACHINE=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -CONFIG_PMC_YOSEMITE=y -# CONFIG_HYPERTRANSPORT is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +CONFIG_PMC_YOSEMITE=y +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_HYPERTRANSPORT is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_COHERENT=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y CONFIG_IRQ_CPU_RM9K=y @@ -93,8 +131,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -110,20 +150,43 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # CONFIG_CPU_RM7000 is not set CONFIG_CPU_RM9000=y # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_RM9000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y CONFIG_HIGHMEM=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SMP=y CONFIG_NR_CPUS=2 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set +CONFIG_PREEMPT_BKL=y # # Bus options (PCI, PCMCIA, EISA, ISA, TC) @@ -131,7 +194,7 @@ CONFIG_NR_CPUS=2 CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y +# CONFIG_PCI_DEBUG is not set CONFIG_MMU=y # @@ -140,10 +203,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -155,6 +214,69 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=m +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_INET6_TUNNEL=m +CONFIG_IPV6_TUNNEL=m +# CONFIG_NETFILTER is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# # Device Drivers # @@ -163,10 +285,15 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m # CONFIG_DEBUG_DRIVER is not set # +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m + +# # Memory Technology Devices (MTD) # # CONFIG_MTD is not set @@ -183,7 +310,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Block devices # -# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -193,7 +319,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 @@ -216,6 +341,7 @@ CONFIG_ATA_OVER_ETH=m # # SCSI device support # +CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set # @@ -226,6 +352,7 @@ CONFIG_ATA_OVER_ETH=m # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -238,59 +365,8 @@ CONFIG_ATA_OVER_ETH=m # CONFIG_I2O is not set # -# Networking support +# Network device support # -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=m -CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=m -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set @@ -303,6 +379,21 @@ CONFIG_NETDEVICES=y # CONFIG_ARCNET is not set # +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -327,13 +418,16 @@ CONFIG_MII=y # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set CONFIG_TITAN_GE=y # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -346,6 +440,8 @@ CONFIG_TITAN_GE=y # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set +# CONFIG_IPW_DEBUG is not set +CONFIG_IPW2200=m # # Wan interfaces @@ -354,6 +450,8 @@ CONFIG_TITAN_GE=y # CONFIG_FDDI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -371,20 +469,10 @@ CONFIG_TITAN_GE=y # CONFIG_INPUT is not set # -# Userland interfaces -# - -# -# Input I/O drivers +# Hardware I/O ports # -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y # CONFIG_SERIO is not set -# CONFIG_SERIO_I8042 is not set - -# -# Input Device Drivers -# +# CONFIG_GAMEPORT is not set # # Character devices @@ -405,6 +493,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -432,6 +521,10 @@ CONFIG_GEN_RTC_X=y # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -442,10 +535,20 @@ CONFIG_GEN_RTC_X=y # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -459,7 +562,6 @@ CONFIG_GEN_RTC_X=y # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -469,13 +571,9 @@ CONFIG_GEN_RTC_X=y # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -493,6 +591,10 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # # CONFIG_EXT2_FS is not set @@ -500,13 +602,16 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -527,11 +632,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVPTS_FS_XATTR is not set CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -552,7 +656,7 @@ CONFIG_NFS_FS=y # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set @@ -573,8 +677,11 @@ CONFIG_MSDOS_PARTITION=y # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set CONFIG_DEBUG_KERNEL=y # CONFIG_MAGIC_SYSRQ is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_DETECT_SOFTLOCKUP=y # CONFIG_SCHEDSTATS is not set # CONFIG_DEBUG_SLAB is not set # CONFIG_DEBUG_SPINLOCK is not set @@ -599,7 +706,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -609,7 +740,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CRC16=m +CONFIG_CRC32=m +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m diff --git a/arch/mips/ddb5xxx/Kconfig b/arch/mips/ddb5xxx/Kconfig new file mode 100644 index 000000000000..e9b5de49f4c2 --- /dev/null +++ b/arch/mips/ddb5xxx/Kconfig @@ -0,0 +1,4 @@ +config DDB5477_BUS_FREQUENCY + int "bus frequency (in kHZ, 0 for auto-detect)" + depends on DDB5477 + default 0 diff --git a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c b/arch/mips/ddb5xxx/ddb5074/nile4_pic.c index 68c127cd70c9..8743ffce8653 100644 --- a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c +++ b/arch/mips/ddb5xxx/ddb5074/nile4_pic.c @@ -209,14 +209,13 @@ static void nile4_irq_end(unsigned int irq) { #define nile4_irq_shutdown nile4_disable_irq static hw_irq_controller nile4_irq_controller = { - "nile4", - nile4_irq_startup, - nile4_irq_shutdown, - nile4_enable_irq, - nile4_disable_irq, - nile4_ack_irq, - nile4_irq_end, - NULL + .typename = "nile4", + .startup = nile4_irq_startup, + .shutdown = nile4_irq_shutdown, + .enable = nile4_enable_irq, + .disable = nile4_disable_irq, + .ack = nile4_ack_irq, + .end = nile4_irq_end, }; void nile4_irq_setup(u32 base) { diff --git a/arch/mips/ddb5xxx/ddb5074/setup.c b/arch/mips/ddb5xxx/ddb5074/setup.c index a73a5978d550..11535be265b9 100644 --- a/arch/mips/ddb5xxx/ddb5074/setup.c +++ b/arch/mips/ddb5xxx/ddb5074/setup.c @@ -85,7 +85,7 @@ static void __init ddb_time_init(void) -static void __init ddb5074_setup(void) +void __init plat_setup(void) { set_io_port_base(NILE4_PCI_IO_BASE); isa_slot_offset = NILE4_PCI_MEM_BASE; @@ -106,8 +106,6 @@ static void __init ddb5074_setup(void) panic_timeout = 180; } -early_initcall(ddb5074_setup); - #define USE_NILE4_SERIAL 0 #if USE_NILE4_SERIAL diff --git a/arch/mips/ddb5xxx/ddb5476/setup.c b/arch/mips/ddb5xxx/ddb5476/setup.c index 71531f8146ea..f4e480a74edf 100644 --- a/arch/mips/ddb5xxx/ddb5476/setup.c +++ b/arch/mips/ddb5xxx/ddb5476/setup.c @@ -124,7 +124,7 @@ static struct { static void ddb5476_board_init(void); -static void __init ddb5476_setup(void) +void __init plat_setup(void) { set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE)); @@ -158,8 +158,6 @@ static void __init ddb5476_setup(void) ddb5476_board_init(); } -early_initcall(ddb5476_setup); - /* * We don't trust bios. We essentially does hardware re-initialization * as complete as possible, as far as we know we can safely do. diff --git a/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c b/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c index a77682be01ac..f66fe5b58636 100644 --- a/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c +++ b/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c @@ -53,14 +53,13 @@ static void vrc5476_irq_end(uint irq) } static hw_irq_controller vrc5476_irq_controller = { - "vrc5476", - vrc5476_irq_startup, - vrc5476_irq_shutdown, - vrc5476_irq_enable, - vrc5476_irq_disable, - vrc5476_irq_ack, - vrc5476_irq_end, - NULL /* no affinity stuff for UP */ + .typename = "vrc5476", + .startup = vrc5476_irq_startup, + .shutdown = vrc5476_irq_shutdown, + .enable = vrc5476_irq_enable, + .disable = vrc5476_irq_disable, + .ack = vrc5476_irq_ack, + .end = vrc5476_irq_end }; void __init diff --git a/arch/mips/ddb5xxx/ddb5477/irq_5477.c b/arch/mips/ddb5xxx/ddb5477/irq_5477.c index 0d5e706207ec..5fcd5f070cdc 100644 --- a/arch/mips/ddb5xxx/ddb5477/irq_5477.c +++ b/arch/mips/ddb5xxx/ddb5477/irq_5477.c @@ -90,14 +90,13 @@ vrc5477_irq_end(unsigned int irq) } hw_irq_controller vrc5477_irq_controller = { - "vrc5477_irq", - vrc5477_irq_startup, - vrc5477_irq_shutdown, - vrc5477_irq_enable, - vrc5477_irq_disable, - vrc5477_irq_ack, - vrc5477_irq_end, - NULL /* no affinity stuff for UP */ + .typename = "vrc5477_irq", + .startup = vrc5477_irq_startup, + .shutdown = vrc5477_irq_shutdown, + .enable = vrc5477_irq_enable, + .disable = vrc5477_irq_disable, + .ack = vrc5477_irq_ack, + .end = vrc5477_irq_end }; void __init vrc5477_irq_init(u32 irq_base) diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c index d62f5a789b05..81163353c4a8 100644 --- a/arch/mips/ddb5xxx/ddb5477/setup.c +++ b/arch/mips/ddb5xxx/ddb5477/setup.c @@ -170,7 +170,7 @@ static void ddb5477_board_init(void); extern struct pci_controller ddb5477_ext_controller; extern struct pci_controller ddb5477_io_controller; -static int ddb5477_setup(void) +void __init plat_setup(void) { /* initialize board - we don't trust the loader */ ddb5477_board_init(); @@ -193,12 +193,8 @@ static int ddb5477_setup(void) register_pci_controller (&ddb5477_ext_controller); register_pci_controller (&ddb5477_io_controller); - - return 0; } -early_initcall(ddb5477_setup); - static void __init ddb5477_board_init(void) { /* ----------- setup PDARs ------------ */ diff --git a/arch/mips/dec/Makefile b/arch/mips/dec/Makefile index 688757a97cb8..ed181fdc3ac9 100644 --- a/arch/mips/dec/Makefile +++ b/arch/mips/dec/Makefile @@ -2,8 +2,8 @@ # Makefile for the DECstation family specific parts of the kernel # -obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn02-irq.o reset.o \ - setup.o time.o +obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \ + kn02-irq.o kn02xa-berr.o reset.o setup.o time.o obj-$(CONFIG_PROM_CONSOLE) += promcon.o obj-$(CONFIG_CPU_HAS_WB) += wbflush.o diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c index 6dbce92eb068..cc24c5ed0c05 100644 --- a/arch/mips/dec/ecc-berr.c +++ b/arch/mips/dec/ecc-berr.c @@ -6,7 +6,7 @@ * 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03), * 5900/260 (KN05) systems. * - * Copyright (c) 2003 Maciej W. Rozycki + * Copyright (c) 2003, 2005 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -15,6 +15,7 @@ */ #include <linux/init.h> +#include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/sched.h> #include <linux/spinlock.h> @@ -57,7 +58,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker) const char *kind, *agent, *cycle, *event; const char *status = "", *xbit = "", *fmt = ""; - dma_addr_t address; + unsigned long address; u16 syn = 0, sngl; int i = 0; @@ -66,7 +67,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker) u32 chksyn = *kn0x_chksyn; int action = MIPS_BE_FATAL; - /* For non-ECC ack ASAP, so any subsequent errors get caught. */ + /* For non-ECC ack ASAP, so that any subsequent errors get caught. */ if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID) dec_ecc_be_ack(); @@ -74,7 +75,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker) if (!(erraddr & KN0X_EAR_VALID)) { /* No idea what happened. */ - printk(KERN_ALERT "Unidentified bus error %s.\n", kind); + printk(KERN_ALERT "Unidentified bus error %s\n", kind); return action; } @@ -126,7 +127,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker) /* Ack now, no rewrite will happen. */ dec_ecc_be_ack(); - fmt = KERN_ALERT "%s" "invalid.\n"; + fmt = KERN_ALERT "%s" "invalid\n"; } else { sngl = syn & KN0X_ESR_SNGLO; syn &= KN0X_ESR_SYNLO; @@ -144,7 +145,8 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker) } else if (!sngl) { status = dbestr; } else { - volatile u32 *ptr = (void *)KSEG1ADDR(address); + volatile u32 *ptr = + (void *)CKSEG1ADDR(address); *ptr = *ptr; /* Rewrite. */ iob(); @@ -160,12 +162,12 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker) if (syn == 0x01) { fmt = KERN_ALERT "%s" "%#04x -- %s bit error " - "at check bit C%s.\n"; + "at check bit C%s\n"; xbit = "X"; } else { fmt = KERN_ALERT "%s" "%#04x -- %s bit error " - "at check bit C%s%u.\n"; + "at check bit C%s%u\n"; } i = syn >> 2; } else { @@ -175,16 +177,16 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker) if (i < 32) fmt = KERN_ALERT "%s" "%#04x -- %s bit error " - "at data bit D%s%u.\n"; + "at data bit D%s%u\n"; else fmt = KERN_ALERT "%s" - "%#04x -- %s bit error.\n"; + "%#04x -- %s bit error\n"; } } } if (action != MIPS_BE_FIXUP) - printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx.\n", + printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n", kind, agent, cycle, event, address); if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR) @@ -203,11 +205,11 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs) int action = dec_ecc_be_backend(regs, 0, 1); if (action == MIPS_BE_DISCARD) - return IRQ_NONE; + return IRQ_HANDLED; /* - * FIXME: Find affected processes and kill them, otherwise we - * must die. + * FIXME: Find the affected processes and kill them, otherwise + * we must die. * * The interrupt is asynchronously delivered thus EPC and RA * may be irrelevant, but are printed for a reference. @@ -225,16 +227,16 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs) */ static inline void dec_kn02_be_init(void) { - volatile u32 *csr = (void *)KN02_CSR_BASE; + volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); unsigned long flags; - kn0x_erraddr = (void *)(KN02_SLOT_BASE + KN02_ERRADDR); - kn0x_chksyn = (void *)(KN02_SLOT_BASE + KN02_CHKSYN); + kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); + kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); spin_lock_irqsave(&kn02_lock, flags); /* Preset write-only bits of the Control Register cache. */ - cached_kn02_csr = *csr | KN03_CSR_LEDS; + cached_kn02_csr = *csr | KN02_CSR_LEDS; /* Set normal ECC detection and generation. */ cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN); @@ -248,11 +250,11 @@ static inline void dec_kn02_be_init(void) static inline void dec_kn03_be_init(void) { - volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR); - volatile u32 *mbcs = (void *)(KN03_SLOT_BASE + KN05_MB_CSR); + volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); + volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); - kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR); - kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN); + kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR); + kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN); /* * Set normal ECC detection and generation, enable ECC correction. @@ -264,7 +266,7 @@ static inline void dec_kn03_be_init(void) *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) | KN03_MCR_CORRECT; if (current_cpu_data.cputype == CPU_R4400SC) - *mbcs |= KN05_MB_CSR_EE; + *mbcs |= KN4K_MB_CSR_EE; fast_iob(); } diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S index c89768d5c4e5..41fa372007bf 100644 --- a/arch/mips/dec/int-handler.S +++ b/arch/mips/dec/int-handler.S @@ -2,9 +2,9 @@ * arch/mips/dec/int-handler.S * * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen - * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki * - * Written by Ralf Baechle and Andreas Busse, modified for DECStation + * Written by Ralf Baechle and Andreas Busse, modified for DECstation * support by Paul Antoine and Harald Koerfgen. * * completly rewritten: @@ -14,11 +14,12 @@ * by Maciej W. Rozycki. */ #include <linux/config.h> + +#include <asm/addrspace.h> #include <asm/asm.h> -#include <asm/regdef.h> #include <asm/mipsregs.h> +#include <asm/regdef.h> #include <asm/stackframe.h> -#include <asm/addrspace.h> #include <asm/dec/interrupts.h> #include <asm/dec/ioasic_addrs.h> @@ -28,11 +29,14 @@ #include <asm/dec/kn02xa.h> #include <asm/dec/kn03.h> +#define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR) +#define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL) +#define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL) .text .set noreorder /* - * decstation_handle_int: Interrupt handler for DECStations + * decstation_handle_int: Interrupt handler for DECstations * * We follow the model in the Indy interrupt code by David Miller, where he * says: a lot of complication here is taken away because: @@ -48,7 +52,7 @@ * 3) Linux only thinks in terms of all IRQs on or all IRQs * off, nothing in between like BSD spl() brain-damage. * - * Furthermore, the IRQs on the DECStations look basically (barring + * Furthermore, the IRQs on the DECstations look basically (barring * software IRQs which we don't use at all) like... * * DS2100/3100's, aka kn01, aka Pmax: @@ -61,7 +65,7 @@ * 3 Lance Ethernet * 4 DZ11 serial * 5 RTC - * 6 Memory Controller + * 6 Memory Controller & Video * 7 FPU * * DS5000/200, aka kn02, aka 3max: diff --git a/arch/mips/dec/kn01-berr.c b/arch/mips/dec/kn01-berr.c new file mode 100644 index 000000000000..b9271db9bc76 --- /dev/null +++ b/arch/mips/dec/kn01-berr.c @@ -0,0 +1,201 @@ +/* + * linux/arch/mips/dec/kn01-berr.c + * + * Bus error event handling code for DECstation/DECsystem 3100 + * and 2100 (KN01) systems equipped with parity error detection + * logic. + * + * Copyright (c) 2005 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/spinlock.h> +#include <linux/types.h> + +#include <asm/inst.h> +#include <asm/mipsregs.h> +#include <asm/page.h> +#include <asm/system.h> +#include <asm/traps.h> +#include <asm/uaccess.h> + +#include <asm/dec/kn01.h> + + +/* CP0 hazard avoidance. */ +#define BARRIER \ + __asm__ __volatile__( \ + ".set push\n\t" \ + ".set noreorder\n\t" \ + "nop\n\t" \ + ".set pop\n\t") + +/* + * Bits 7:0 of the Control Register are write-only -- the + * corresponding bits of the Status Register have a different + * meaning. Hence we use a cache. It speeds up things a bit + * as well. + * + * There is no default value -- it has to be initialized. + */ +u16 cached_kn01_csr; +DEFINE_SPINLOCK(kn01_lock); + + +static inline void dec_kn01_be_ack(void) +{ + volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); + unsigned long flags; + + spin_lock_irqsave(&kn01_lock, flags); + + *csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */ + iob(); + + spin_unlock_irqrestore(&kn01_lock, flags); +} + +static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker) +{ + volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + + KN01_ERRADDR); + + static const char excstr[] = "exception"; + static const char intstr[] = "interrupt"; + static const char cpustr[] = "CPU"; + static const char mreadstr[] = "memory read"; + static const char readstr[] = "read"; + static const char writestr[] = "write"; + static const char timestr[] = "timeout"; + static const char paritystr[] = "parity error"; + + int data = regs->cp0_cause & 4; + unsigned int __user *pc = (unsigned int __user *)regs->cp0_epc + + ((regs->cp0_cause & CAUSEF_BD) != 0); + union mips_instruction insn; + unsigned long entrylo, offset; + long asid, entryhi, vaddr; + + const char *kind, *agent, *cycle, *event; + unsigned long address; + + u32 erraddr = *kn01_erraddr; + int action = MIPS_BE_FATAL; + + /* Ack ASAP, so that any subsequent errors get caught. */ + dec_kn01_be_ack(); + + kind = invoker ? intstr : excstr; + + agent = cpustr; + + if (invoker) + address = erraddr; + else { + /* Bloody hardware doesn't record the address for reads... */ + if (data) { + /* This never faults. */ + __get_user(insn.word, pc); + vaddr = regs->regs[insn.i_format.rs] + + insn.i_format.simmediate; + } else + vaddr = (long)pc; + if (KSEGX(vaddr) == CKSEG0 || KSEGX(vaddr) == CKSEG1) + address = CPHYSADDR(vaddr); + else { + /* Peek at what physical address the CPU used. */ + asid = read_c0_entryhi(); + entryhi = asid & (PAGE_SIZE - 1); + entryhi |= vaddr & ~(PAGE_SIZE - 1); + write_c0_entryhi(entryhi); + BARRIER; + tlb_probe(); + /* No need to check for presence. */ + tlb_read(); + entrylo = read_c0_entrylo0(); + write_c0_entryhi(asid); + offset = vaddr & (PAGE_SIZE - 1); + address = (entrylo & ~(PAGE_SIZE - 1)) | offset; + } + } + + /* Treat low 256MB as memory, high -- as I/O. */ + if (address < 0x10000000) { + cycle = mreadstr; + event = paritystr; + } else { + cycle = invoker ? writestr : readstr; + event = timestr; + } + + if (is_fixup) + action = MIPS_BE_FIXUP; + + if (action != MIPS_BE_FIXUP) + printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n", + kind, agent, cycle, event, address); + + return action; +} + +int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup) +{ + return dec_kn01_be_backend(regs, is_fixup, 0); +} + +irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id, + struct pt_regs *regs) +{ + volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); + int action; + + if (!(*csr & KN01_CSR_MEMERR)) + return IRQ_NONE; /* Must have been video. */ + + action = dec_kn01_be_backend(regs, 0, 1); + + if (action == MIPS_BE_DISCARD) + return IRQ_HANDLED; + + /* + * FIXME: Find the affected processes and kill them, otherwise + * we must die. + * + * The interrupt is asynchronously delivered thus EPC and RA + * may be irrelevant, but are printed for a reference. + */ + printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n", + regs->cp0_epc, regs->regs[31]); + die("Unrecoverable bus error", regs); +} + + +void __init dec_kn01_be_init(void) +{ + volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); + unsigned long flags; + + spin_lock_irqsave(&kn01_lock, flags); + + /* Preset write-only bits of the Control Register cache. */ + cached_kn01_csr = *csr; + cached_kn01_csr &= KN01_CSR_STATUS | KN01_CSR_PARDIS | KN01_CSR_TXDIS; + cached_kn01_csr |= KN01_CSR_LEDS; + + /* Enable parity error detection. */ + cached_kn01_csr &= ~KN01_CSR_PARDIS; + *csr = cached_kn01_csr; + iob(); + + spin_unlock_irqrestore(&kn01_lock, flags); + + /* Clear any leftover errors from the firmware. */ + dec_kn01_be_ack(); +} diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c index e0bfcd1521e2..898bed502a34 100644 --- a/arch/mips/dec/kn02-irq.c +++ b/arch/mips/dec/kn02-irq.c @@ -4,7 +4,7 @@ * DECstation 5000/200 (KN02) Control and Status Register * interrupts. * - * Copyright (c) 2002, 2003 Maciej W. Rozycki + * Copyright (c) 2002, 2003, 2005 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -37,7 +37,8 @@ static int kn02_irq_base; static inline void unmask_kn02_irq(unsigned int irq) { - volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; + volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + + KN02_CSR); cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16)); *csr = cached_kn02_csr; @@ -45,7 +46,8 @@ static inline void unmask_kn02_irq(unsigned int irq) static inline void mask_kn02_irq(unsigned int irq) { - volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; + volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + + KN02_CSR); cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16)); *csr = cached_kn02_csr; @@ -105,13 +107,14 @@ static struct hw_interrupt_type kn02_irq_type = { void __init init_kn02_irqs(int base) { - volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; + volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + + KN02_CSR); unsigned long flags; int i; /* Mask interrupts. */ spin_lock_irqsave(&kn02_lock, flags); - cached_kn02_csr &= ~KN03_CSR_IOINTEN; + cached_kn02_csr &= ~KN02_CSR_IOINTEN; *csr = cached_kn02_csr; iob(); spin_unlock_irqrestore(&kn02_lock, flags); diff --git a/arch/mips/dec/kn02xa-berr.c b/arch/mips/dec/kn02xa-berr.c new file mode 100644 index 000000000000..6cd3f94f79fe --- /dev/null +++ b/arch/mips/dec/kn02xa-berr.c @@ -0,0 +1,139 @@ +/* + * linux/arch/mips/dec/kn02xa-berr.c + * + * Bus error event handling code for 5000-series systems equipped + * with parity error detection logic, i.e. DECstation/DECsystem + * 5000/120, /125, /133 (KN02-BA), 5000/150 (KN04-BA) and Personal + * DECstation/DECsystem 5000/20, /25, /33 (KN02-CA), 5000/50 + * (KN04-CA) systems. + * + * Copyright (c) 2005 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/types.h> + +#include <asm/addrspace.h> +#include <asm/system.h> +#include <asm/traps.h> + +#include <asm/dec/kn02ca.h> +#include <asm/dec/kn02xa.h> +#include <asm/dec/kn05.h> + +static inline void dec_kn02xa_be_ack(void) +{ + volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER); + volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR); + + *mer = KN02CA_MER_INTR; /* Clear errors; keep the ARC IRQ. */ + *mem_intr = 0; /* Any write clears the bus IRQ. */ + iob(); +} + +static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup, + int invoker) +{ + volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER); + volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR); + + static const char excstr[] = "exception"; + static const char intstr[] = "interrupt"; + static const char cpustr[] = "CPU"; + static const char mreadstr[] = "memory read"; + static const char readstr[] = "read"; + static const char writestr[] = "write"; + static const char timestr[] = "timeout"; + static const char paritystr[] = "parity error"; + static const char lanestat[][4] = { " OK", "BAD" }; + + const char *kind, *agent, *cycle, *event; + unsigned long address; + + u32 mer = *kn02xa_mer; + u32 ear = *kn02xa_ear; + int action = MIPS_BE_FATAL; + + /* Ack ASAP, so that any subsequent errors get caught. */ + dec_kn02xa_be_ack(); + + kind = invoker ? intstr : excstr; + + /* No DMA errors? */ + agent = cpustr; + + address = ear & KN02XA_EAR_ADDRESS; + + /* Low 256MB is decoded as memory, high -- as TC. */ + if (address < 0x10000000) { + cycle = mreadstr; + event = paritystr; + } else { + cycle = invoker ? writestr : readstr; + event = timestr; + } + + if (is_fixup) + action = MIPS_BE_FIXUP; + + if (action != MIPS_BE_FIXUP) + printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n", + kind, agent, cycle, event, address); + + if (action != MIPS_BE_FIXUP && address < 0x10000000) + printk(KERN_ALERT " Byte lane status %#3x -- " + "#3: %s, #2: %s, #1: %s, #0: %s\n", + (mer & KN02XA_MER_BYTERR) >> 8, + lanestat[(mer & KN02XA_MER_BYTERR_3) != 0], + lanestat[(mer & KN02XA_MER_BYTERR_2) != 0], + lanestat[(mer & KN02XA_MER_BYTERR_1) != 0], + lanestat[(mer & KN02XA_MER_BYTERR_0) != 0]); + + return action; +} + +int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup) +{ + return dec_kn02xa_be_backend(regs, is_fixup, 0); +} + +irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id, + struct pt_regs *regs) +{ + int action = dec_kn02xa_be_backend(regs, 0, 1); + + if (action == MIPS_BE_DISCARD) + return IRQ_HANDLED; + + /* + * FIXME: Find the affected processes and kill them, otherwise + * we must die. + * + * The interrupt is asynchronously delivered thus EPC and RA + * may be irrelevant, but are printed for a reference. + */ + printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n", + regs->cp0_epc, regs->regs[31]); + die("Unrecoverable bus error", regs); +} + + +void __init dec_kn02xa_be_init(void) +{ + volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); + + /* For KN04 we need to make sure EE (?) is enabled in the MB. */ + if (current_cpu_data.cputype == CPU_R4000SC) + *mbcs |= KN4K_MB_CSR_EE; + fast_iob(); + + /* Clear any leftover errors from the firmware. */ + dec_kn02xa_be_ack(); +} diff --git a/arch/mips/dec/prom/identify.c b/arch/mips/dec/prom/identify.c index 9380588cb15c..81d5e878ddce 100644 --- a/arch/mips/dec/prom/identify.c +++ b/arch/mips/dec/prom/identify.c @@ -2,7 +2,7 @@ * identify.c: machine identification code. * * Copyright (C) 1998 Harald Koerfgen and Paul M. Antoine - * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki + * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki */ #include <linux/init.h> #include <linux/kernel.h> @@ -12,6 +12,7 @@ #include <linux/types.h> #include <asm/bootinfo.h> + #include <asm/dec/ioasic.h> #include <asm/dec/ioasic_addrs.h> #include <asm/dec/kn01.h> @@ -21,6 +22,7 @@ #include <asm/dec/kn03.h> #include <asm/dec/kn230.h> #include <asm/dec/prom.h> +#include <asm/dec/system.h> #include "dectypes.h" @@ -68,34 +70,44 @@ EXPORT_SYMBOL(dec_rtc_base); static inline void prom_init_kn01(void) { - dec_rtc_base = (void *)KN01_RTC_BASE; + dec_kn_slot_base = KN01_SLOT_BASE; dec_kn_slot_size = KN01_SLOT_SIZE; + + dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); } static inline void prom_init_kn230(void) { - dec_rtc_base = (void *)KN01_RTC_BASE; + dec_kn_slot_base = KN01_SLOT_BASE; dec_kn_slot_size = KN01_SLOT_SIZE; + + dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); } static inline void prom_init_kn02(void) { - dec_rtc_base = (void *)KN02_RTC_BASE; + dec_kn_slot_base = KN02_SLOT_BASE; dec_kn_slot_size = KN02_SLOT_SIZE; + + dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC); } static inline void prom_init_kn02xa(void) { - ioasic_base = (void *)KN02XA_IOASIC_BASE; - dec_rtc_base = (void *)KN02XA_RTC_BASE; + dec_kn_slot_base = KN02XA_SLOT_BASE; dec_kn_slot_size = IOASIC_SLOT_SIZE; + + ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); + dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); } static inline void prom_init_kn03(void) { - ioasic_base = (void *)KN03_IOASIC_BASE; - dec_rtc_base = (void *)KN03_RTC_BASE; + dec_kn_slot_base = KN03_SLOT_BASE; dec_kn_slot_size = IOASIC_SLOT_SIZE; + + ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); + dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); } diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c index 60f74256e689..32a7cc7e4c65 100644 --- a/arch/mips/dec/prom/init.c +++ b/arch/mips/dec/prom/init.c @@ -6,6 +6,8 @@ */ #include <linux/config.h> #include <linux/init.h> +#include <linux/kernel.h> +#include <linux/linkage.h> #include <linux/smp.h> #include <linux/string.h> #include <linux/types.h> @@ -85,17 +87,13 @@ void __init which_prom(s32 magic, s32 *prom_vec) void __init prom_init(void) { - extern void dec_machine_halt(void); + extern void ATTRIB_NORET dec_machine_halt(void); static char cpu_msg[] __initdata = "Sorry, this kernel is compiled for a wrong CPU type!\n"; - static char r3k_msg[] __initdata = - "Please recompile with \"CONFIG_CPU_R3000 = y\".\n"; - static char r4k_msg[] __initdata = - "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n"; s32 argc = fw_arg0; - s32 argv = fw_arg1; + s32 *argv = (void *)fw_arg1; u32 magic = fw_arg2; - s32 prom_vec = fw_arg3; + s32 *prom_vec = (void *)fw_arg3; /* * Determine which PROM we have @@ -113,6 +111,8 @@ void __init prom_init(void) #if defined(CONFIG_CPU_R3000) if ((current_cpu_data.cputype == CPU_R4000SC) || (current_cpu_data.cputype == CPU_R4400SC)) { + static char r4k_msg[] __initdata = + "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n"; printk(cpu_msg); printk(r4k_msg); dec_machine_halt(); @@ -122,6 +122,8 @@ void __init prom_init(void) #if defined(CONFIG_CPU_R4X00) if ((current_cpu_data.cputype == CPU_R3000) || (current_cpu_data.cputype == CPU_R3000A)) { + static char r3k_msg[] __initdata = + "Please recompile with \"CONFIG_CPU_R3000 = y\".\n"; printk(cpu_msg); printk(r3k_msg); dec_machine_halt(); diff --git a/arch/mips/dec/prom/memory.c b/arch/mips/dec/prom/memory.c index e4f6f26425ea..83d4556c3cb5 100644 --- a/arch/mips/dec/prom/memory.c +++ b/arch/mips/dec/prom/memory.c @@ -35,22 +35,22 @@ static inline void pmax_setup_memory_region(void) extern char genexcept_early; /* Install exception handler */ - memcpy(&old_handler, (void *)(KSEG0 + 0x80), 0x80); - memcpy((void *)(KSEG0 + 0x80), &genexcept_early, 0x80); + memcpy(&old_handler, (void *)(CKSEG0 + 0x80), 0x80); + memcpy((void *)(CKSEG0 + 0x80), &genexcept_early, 0x80); /* read unmapped and uncached (KSEG1) * DECstations have at least 4MB RAM * Assume less than 480MB of RAM, as this is max for 5000/2xx * FIXME this should be replaced by the first free page! */ - for (memory_page = (unsigned char *) KSEG1 + CHUNK_SIZE; - (mem_err== 0) && (memory_page < ((unsigned char *) KSEG1+0x1E000000)); + for (memory_page = (unsigned char *)CKSEG1 + CHUNK_SIZE; + mem_err == 0 && memory_page < (unsigned char *)CKSEG1 + 0x1e00000; memory_page += CHUNK_SIZE) { dummy = *memory_page; } - memcpy((void *)(KSEG0 + 0x80), &old_handler, 0x80); + memcpy((void *)(CKSEG0 + 0x80), &old_handler, 0x80); - add_memory_region(0, (unsigned long)memory_page - KSEG1 - CHUNK_SIZE, + add_memory_region(0, (unsigned long)memory_page - CKSEG1 - CHUNK_SIZE, BOOT_MEM_RAM); } @@ -65,7 +65,7 @@ static inline void rex_setup_memory_region(void) memmap *bm; /* some free 64k */ - bm = (memmap *)KSEG0ADDR(0x28000); + bm = (memmap *)CKSEG0ADDR(0x28000); bitmap_size = rex_getbitmap(bm); diff --git a/arch/mips/dec/reset.c b/arch/mips/dec/reset.c index 7e4d34d0573d..f78c6da47921 100644 --- a/arch/mips/dec/reset.c +++ b/arch/mips/dec/reset.c @@ -14,7 +14,7 @@ typedef void ATTRIB_NORET (* noret_func_t)(void); static inline void ATTRIB_NORET back_to_prom(void) { - noret_func_t func = (void *) KSEG1ADDR(0x1fc00000); + noret_func_t func = (void *)CKSEG1ADDR(0x1fc00000); func(); } diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c index 6a69309baf40..9ef54fe1feaa 100644 --- a/arch/mips/dec/setup.c +++ b/arch/mips/dec/setup.c @@ -1,19 +1,20 @@ /* - * Setup the interrupt stuff. + * System-specific setup, especially interrupts. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1998 Harald Koerfgen - * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki */ -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/param.h> #include <linux/console.h> #include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> #include <linux/module.h> +#include <linux/param.h> +#include <linux/sched.h> #include <linux/spinlock.h> #include <linux/types.h> @@ -38,6 +39,7 @@ #include <asm/dec/kn02ca.h> #include <asm/dec/kn03.h> #include <asm/dec/kn230.h> +#include <asm/dec/system.h> extern void dec_machine_restart(char *command); @@ -47,10 +49,16 @@ extern irqreturn_t dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs); extern asmlinkage void decstation_handle_int(void); +unsigned long dec_kn_slot_base, dec_kn_slot_size; + +EXPORT_SYMBOL(dec_kn_slot_base); +EXPORT_SYMBOL(dec_kn_slot_size); + spinlock_t ioasic_ssr_lock; volatile u32 *ioasic_base; -unsigned long dec_kn_slot_size; + +EXPORT_SYMBOL(ioasic_base); /* * IRQ routing and priority tables. Priorites are set as follows: @@ -77,6 +85,9 @@ unsigned long dec_kn_slot_size; int dec_interrupt[DEC_NR_INTS] = { [0 ... DEC_NR_INTS - 1] = -1 }; + +EXPORT_SYMBOL(dec_interrupt); + int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = { { { .i = ~0 }, { .p = dec_intr_unimplemented } }, }; @@ -108,11 +119,20 @@ static struct irqaction haltirq = { /* * Bus error (DBE/IBE exceptions and bus interrupts) handling setup. */ -void __init dec_be_init(void) +static void __init dec_be_init(void) { switch (mips_machtype) { case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ + board_be_handler = dec_kn01_be_handler; + busirq.handler = dec_kn01_be_interrupt; busirq.flags |= SA_SHIRQ; + dec_kn01_be_init(); + break; + case MACH_DS5000_1XX: /* DS5000/1xx 3min */ + case MACH_DS5000_XX: /* DS5000/xx Maxine */ + board_be_handler = dec_kn02xa_be_handler; + busirq.handler = dec_kn02xa_be_interrupt; + dec_kn02xa_be_init(); break; case MACH_DS5000_200: /* DS5000/200 3max */ case MACH_DS5000_2X0: /* DS5000/240 3max+ */ @@ -128,7 +148,7 @@ void __init dec_be_init(void) extern void dec_time_init(void); extern void dec_timer_setup(struct irqaction *); -static void __init decstation_setup(void) +void __init plat_setup(void) { board_be_init = dec_be_init; board_time_init = dec_time_init; @@ -139,9 +159,10 @@ static void __init decstation_setup(void) _machine_restart = dec_machine_restart; _machine_halt = dec_machine_halt; _machine_power_off = dec_machine_power_off; -} -early_initcall(decstation_setup); + ioport_resource.start = ~0UL; + ioport_resource.end = 0UL; +} /* * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin) @@ -206,7 +227,7 @@ static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = { { .p = cpu_all_int } }, }; -void __init dec_init_kn01(void) +static void __init dec_init_kn01(void) { /* IRQ routing. */ memcpy(&dec_interrupt, &kn01_interrupt, @@ -281,7 +302,7 @@ static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = { { .p = cpu_all_int } }, }; -void __init dec_init_kn230(void) +static void __init dec_init_kn230(void) { /* IRQ routing. */ memcpy(&dec_interrupt, &kn230_interrupt, @@ -371,7 +392,7 @@ static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = { { .p = kn02_all_int } }, }; -void __init dec_init_kn02(void) +static void __init dec_init_kn02(void) { /* IRQ routing. */ memcpy(&dec_interrupt, &kn02_interrupt, @@ -472,7 +493,7 @@ static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = { { .p = asic_all_int } }, }; -void __init dec_init_kn02ba(void) +static void __init dec_init_kn02ba(void) { /* IRQ routing. */ memcpy(&dec_interrupt, &kn02ba_interrupt, @@ -569,7 +590,7 @@ static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = { { .p = asic_all_int } }, }; -void __init dec_init_kn02ca(void) +static void __init dec_init_kn02ca(void) { /* IRQ routing. */ memcpy(&dec_interrupt, &kn02ca_interrupt, @@ -670,7 +691,7 @@ static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = { { .p = asic_all_int } }, }; -void __init dec_init_kn03(void) +static void __init dec_init_kn03(void) { /* IRQ routing. */ memcpy(&dec_interrupt, &kn03_interrupt, @@ -744,7 +765,3 @@ void __init arch_init_irq(void) if (dec_interrupt[DEC_IRQ_HALT] >= 0) setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq); } - -EXPORT_SYMBOL(ioasic_base); -EXPORT_SYMBOL(dec_kn_slot_size); -EXPORT_SYMBOL(dec_interrupt); diff --git a/arch/mips/defconfig b/arch/mips/defconfig index 20f84b119b4c..4b585e642c2a 100644 --- a/arch/mips/defconfig +++ b/arch/mips/defconfig @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:48:59 2005 +# Linux kernel version: 2.6.14-rc2 +# Thu Oct 20 22:25:09 2005 # CONFIG_MIPS=y -# CONFIG_64BIT is not set -# CONFIG_64BIT is not set -CONFIG_32BIT=y # # Code maturity level options @@ -14,25 +11,30 @@ CONFIG_32BIT=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -42,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -57,41 +60,69 @@ CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set CONFIG_SGI_IP22=y -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_ARC=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_SWAP_IO_SPACE=y CONFIG_ARC32=y @@ -103,8 +134,10 @@ CONFIG_ARC_PROMLIB=y # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set @@ -120,22 +153,48 @@ CONFIG_CPU_R5000=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R4X00=y +CONFIG_SYS_HAS_CPU_R5000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_BOARD_SCACHE=y CONFIG_IP22_CPU_SCACHE=y +# CONFIG_MIPS_MT is not set # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # +CONFIG_HW_HAS_EISA=y # CONFIG_EISA is not set CONFIG_MMU=y @@ -145,10 +204,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -160,115 +215,7 @@ CONFIG_BINFMT_MISC=m CONFIG_TRAD_SIGNALS=y # -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_ATA_OVER_ETH=m - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_SCSI=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=y -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI Transport Attributes -# -CONFIG_SCSI_SPI_ATTRS=m -# CONFIG_SCSI_FC_ATTRS is not set -CONFIG_SCSI_ISCSI_ATTRS=m - -# -# SCSI low-level drivers -# -CONFIG_SGIWD93_SCSI=y -# CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Networking support +# Networking # CONFIG_NET=y @@ -277,12 +224,14 @@ CONFIG_NET=y # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m CONFIG_NET_KEY=y CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y CONFIG_IP_PNP=y # CONFIG_IP_PNP_DHCP is not set CONFIG_IP_PNP_BOOTP=y @@ -296,8 +245,10 @@ CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -CONFIG_IP_TCPDIAG_IPV6=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y # # IP: Virtual Server Configuration @@ -341,6 +292,9 @@ CONFIG_INET6_TUNNEL=m CONFIG_IPV6_TUNNEL=m CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m # # IP: Netfilter Configuration @@ -348,11 +302,15 @@ CONFIG_NETFILTER=y CONFIG_IP_NF_CONNTRACK=m CONFIG_IP_NF_CT_ACCT=y CONFIG_IP_NF_CONNTRACK_MARK=y +CONFIG_IP_NF_CONNTRACK_EVENTS=y +CONFIG_IP_NF_CONNTRACK_NETLINK=m # CONFIG_IP_NF_CT_PROTO_SCTP is not set CONFIG_IP_NF_FTP=m CONFIG_IP_NF_IRC=m +# CONFIG_IP_NF_NETBIOS_NS is not set CONFIG_IP_NF_TFTP=m CONFIG_IP_NF_AMANDA=m +CONFIG_IP_NF_PPTP=m CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_LIMIT=m @@ -376,9 +334,12 @@ CONFIG_IP_NF_MATCH_OWNER=m CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_REALM=m CONFIG_IP_NF_MATCH_SCTP=m +CONFIG_IP_NF_MATCH_DCCP=m CONFIG_IP_NF_MATCH_COMMENT=m CONFIG_IP_NF_MATCH_CONNMARK=m +CONFIG_IP_NF_MATCH_CONNBYTES=m CONFIG_IP_NF_MATCH_HASHLIMIT=m +CONFIG_IP_NF_MATCH_STRING=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -395,12 +356,14 @@ CONFIG_IP_NF_NAT_IRC=m CONFIG_IP_NF_NAT_FTP=m CONFIG_IP_NF_NAT_TFTP=m CONFIG_IP_NF_NAT_AMANDA=m +CONFIG_IP_NF_NAT_PPTP=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_TOS=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_DSCP=m CONFIG_IP_NF_TARGET_MARK=m CONFIG_IP_NF_TARGET_CLASSIFY=m +CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_TARGET_CONNMARK=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m @@ -410,7 +373,7 @@ CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # -# IPv6: Netfilter Configuration +# IPv6: Netfilter Configuration (EXPERIMENTAL) # CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m @@ -429,11 +392,16 @@ CONFIG_IP6_NF_MATCH_LENGTH=m CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_MARK=m +CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_RAW=m -CONFIG_XFRM=y -CONFIG_XFRM_USER=m + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set # # SCTP Configuration (EXPERIMENTAL) @@ -456,10 +424,6 @@ CONFIG_SCTP_HMAC_MD5=y CONFIG_NET_DIVERT=y # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# CONFIG_NET_SCHED=y # CONFIG_NET_SCH_CLK_JIFFIES is not set CONFIG_NET_SCH_CLK_GETTIMEOFDAY=y @@ -479,6 +443,7 @@ CONFIG_NET_SCH_INGRESS=m CONFIG_NET_QOS=y CONFIG_NET_ESTIMATOR=y CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_ROUTE=y @@ -489,6 +454,7 @@ CONFIG_NET_CLS_U32=m # CONFIG_CLS_U32_MARK is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_EMATCH is not set # CONFIG_NET_CLS_ACT is not set CONFIG_NET_CLS_POLICE=y @@ -496,17 +462,153 @@ CONFIG_NET_CLS_POLICE=y # Network testing # # CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +CONFIG_BLK_DEV_RAM_COUNT=16 +# CONFIG_LBD is not set +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_ATA_OVER_ETH=m + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=y +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +# CONFIG_CHR_DEV_SG is not set +CONFIG_CHR_DEV_SCH=m + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI Transport Attributes +# +CONFIG_SCSI_SPI_ATTRS=m +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m + +# +# SCSI low-level drivers +# +CONFIG_SGIWD93_SCSI=y +# CONFIG_SCSI_SATA is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# I2O device support +# + +# +# Network device support +# CONFIG_NETDEVICES=y CONFIG_DUMMY=m CONFIG_BONDING=m CONFIG_EQUALIZER=m CONFIG_TUN=m -CONFIG_ETHERTAP=m + +# +# PHY device support +# +CONFIG_PHYLIB=m +CONFIG_PHYCONTROL=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m # # Ethernet (10 or 100Mbit) @@ -540,6 +642,8 @@ CONFIG_SGISEEQ=y # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -569,18 +673,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y @@ -598,6 +690,16 @@ CONFIG_MOUSE_SERIAL=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -644,11 +746,14 @@ CONFIG_SGI_DS1286=m # # Ftape, the floppy tape device driver # -# CONFIG_DRM is not set CONFIG_RAW_DRIVER=m CONFIG_MAX_RAW_DEVS=256 # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -659,10 +764,20 @@ CONFIG_MAX_RAW_DEVS=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -693,7 +808,6 @@ CONFIG_LOGO=y # CONFIG_LOGO_LINUX_VGA16 is not set # CONFIG_LOGO_LINUX_CLUT224 is not set CONFIG_LOGO_SGI_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -707,10 +821,6 @@ CONFIG_LOGO_SGI_CLUT224=y # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -723,13 +833,17 @@ CONFIG_LOGO_SGI_CLUT224=y # # InfiniBand support # -# CONFIG_INFINIBAND is not set + +# +# SN Devices +# # # File systems # CONFIG_EXT2_FS=m # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y @@ -741,12 +855,14 @@ CONFIG_FS_MBCACHE=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_XFS_FS=m -# CONFIG_XFS_RT is not set -CONFIG_XFS_QUOTA=y +CONFIG_XFS_EXPORT=y +CONFIG_XFS_QUOTA=m CONFIG_XFS_SECURITY=y # CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set CONFIG_MINIX_FS=m # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y CONFIG_QUOTA=y # CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=m @@ -754,6 +870,7 @@ CONFIG_QUOTACTL=y CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m # # CD-ROM/DVD Filesystems @@ -781,12 +898,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +CONFIG_RELAYFS_FS=m # # Miscellaneous filesystems @@ -811,15 +926,20 @@ CONFIG_UFS_FS=m # CONFIG_NFS_FS=m CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y # CONFIG_NFSD_V4 is not set CONFIG_NFSD_TCP=y CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=m +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m CONFIG_RPCSEC_GSS_KRB5=m @@ -835,6 +955,7 @@ CONFIG_CIFS=m CONFIG_CODA_FS=m # CONFIG_CODA_FS_OLD_API is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -908,7 +1029,9 @@ CONFIG_NLS_UTF8=m # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -931,6 +1054,7 @@ CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_TWOFISH=m @@ -942,10 +1066,10 @@ CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_TEST=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices @@ -955,9 +1079,12 @@ CONFIG_CRYPTO_TEST=m # Library routines # # CONFIG_CRC_CCITT is not set +CONFIG_CRC16=m CONFIG_CRC32=m CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m diff --git a/arch/mips/galileo-boards/ev96100/setup.c b/arch/mips/galileo-boards/ev96100/setup.c index 28bd908c6d55..78dbb18edeb8 100644 --- a/arch/mips/galileo-boards/ev96100/setup.c +++ b/arch/mips/galileo-boards/ev96100/setup.c @@ -55,7 +55,7 @@ extern void mips_reboot_setup(void); unsigned char mac_0_1[12]; -static void __init ev96100_setup(void) +void __init plat_setup(void) { unsigned int config = read_c0_config(); unsigned int status = read_c0_status(); @@ -142,8 +142,6 @@ static void __init ev96100_setup(void) tmp = GT_READ(GT_PCI0_CFGDATA_OFS); } -early_initcall(ev96100_setup); - unsigned short get_gt_devid(void) { u32 gt_devid; diff --git a/arch/mips/gt64120/ev64120/Kconfig b/arch/mips/gt64120/ev64120/Kconfig new file mode 100644 index 000000000000..d691762cb0f7 --- /dev/null +++ b/arch/mips/gt64120/ev64120/Kconfig @@ -0,0 +1,3 @@ +config EVB_PCI1 + bool "Enable Second PCI (PCI1)" + depends on MIPS_EV64120 diff --git a/arch/mips/gt64120/ev64120/setup.c b/arch/mips/gt64120/ev64120/setup.c index dba0961400cc..98b5a96cc039 100644 --- a/arch/mips/gt64120/ev64120/setup.c +++ b/arch/mips/gt64120/ev64120/setup.c @@ -69,7 +69,7 @@ unsigned long __init prom_free_prom_memory(void) */ extern void gt64120_time_init(void); -static void __init ev64120_setup(void) +void __init plat_setup(void) { _machine_restart = galileo_machine_restart; _machine_halt = galileo_machine_halt; @@ -79,8 +79,6 @@ static void __init ev64120_setup(void) set_io_port_base(KSEG1); } -early_initcall(ev64120_setup); - const char *get_system_type(void) { return "Galileo EV64120A"; diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c index d610f8c17c81..0d07c33112d0 100644 --- a/arch/mips/gt64120/momenco_ocelot/setup.c +++ b/arch/mips/gt64120/momenco_ocelot/setup.c @@ -150,7 +150,7 @@ void PMON_v2_setup() gt64120_base = 0xe0000000; } -static void __init momenco_ocelot_setup(void) +void __init plat_setup(void) { void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache); unsigned int tmpword; @@ -307,8 +307,6 @@ static void __init momenco_ocelot_setup(void) GT_WRITE(GT_DEV_B3_OFS, 0xfef73); } -early_initcall(momenco_ocelot_setup); - extern int rm7k_tcache_enabled; /* * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache() diff --git a/arch/mips/ite-boards/Kconfig b/arch/mips/ite-boards/Kconfig new file mode 100644 index 000000000000..a6d59ad8f846 --- /dev/null +++ b/arch/mips/ite-boards/Kconfig @@ -0,0 +1,8 @@ +config IT8172_REVC + bool "Support for older IT8172 (Rev C)" + depends on MIPS_ITE8172 + help + Say Y here to support the older, Revision C version of the Integrated + Technology Express, Inc. ITE8172 SBC. Vendor page at + <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the + board at <http://www.mvista.com/partners/semiconductor/ite.html>. diff --git a/arch/mips/ite-boards/generic/irq.c b/arch/mips/ite-boards/generic/irq.c index cb71b9024d6f..e67f96129491 100644 --- a/arch/mips/ite-boards/generic/irq.c +++ b/arch/mips/ite-boards/generic/irq.c @@ -138,14 +138,13 @@ static void end_ite_irq(unsigned int irq) } static struct hw_interrupt_type it8172_irq_type = { - "ITE8172", - startup_ite_irq, - shutdown_ite_irq, - enable_it8172_irq, - disable_it8172_irq, - mask_and_ack_ite_irq, - end_ite_irq, - NULL + .typename = "ITE8172", + .startup = startup_ite_irq, + .shutdown = shutdown_ite_irq, + .enable = enable_it8172_irq, + .disable = disable_it8172_irq, + .ack = mask_and_ack_ite_irq, + .end = end_ite_irq, }; @@ -159,13 +158,13 @@ static void ack_none(unsigned int irq) { } #define end_none enable_none static struct hw_interrupt_type cp0_irq_type = { - "CP0 Count", - startup_none, - shutdown_none, - enable_none, - disable_none, - ack_none, - end_none + .typename = "CP0 Count", + .startup = startup_none, + .shutdown = shutdown_none, + .enable = enable_none, + .disable = disable_none, + .ack = ack_none, + .end = end_none }; void enable_cpu_timer(void) @@ -182,7 +181,6 @@ void __init arch_init_irq(void) int i; unsigned long flags; - memset(irq_desc, 0, sizeof(irq_desc)); set_except_vector(0, it8172_IRQ); /* mask all interrupts */ diff --git a/arch/mips/ite-boards/generic/it8172_setup.c b/arch/mips/ite-boards/generic/it8172_setup.c index a5f6d84bc181..062429dd7ca0 100644 --- a/arch/mips/ite-boards/generic/it8172_setup.c +++ b/arch/mips/ite-boards/generic/it8172_setup.c @@ -105,7 +105,7 @@ void __init it8172_init_ram_resource(unsigned long memsize) it8172_resources.ram.end = memsize; } -static void __init it8172_setup(void) +void __init plat_setup(void) { unsigned short dsr; char *argptr; @@ -251,8 +251,6 @@ static void __init it8172_setup(void) #endif /* CONFIG_IT8172_SCR1 */ } -early_initcall(it8172_setup); - #ifdef CONFIG_SERIO_I8042 /* * According to the ITE Special BIOS Note for waking up the diff --git a/arch/mips/jazz/Kconfig b/arch/mips/jazz/Kconfig new file mode 100644 index 000000000000..1f372b0d2559 --- /dev/null +++ b/arch/mips/jazz/Kconfig @@ -0,0 +1,33 @@ +config ACER_PICA_61 + bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)" + depends on MACH_JAZZ && EXPERIMENTAL + select DMA_NONCOHERENT + select SYS_SUPPORTS_LITTLE_ENDIAN + help + This is a machine with a R4400 133/150 MHz CPU. To compile a Linux + kernel that runs on these, say Y here. For details about Linux on + the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at + <http://www.linux-mips.org/>. + +config MIPS_MAGNUM_4000 + bool "Support for MIPS Magnum 4000" + depends on MACH_JAZZ + select DMA_NONCOHERENT + select SYS_SUPPORTS_BIG_ENDIAN if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN + help + This is a machine with a R4000 100 MHz CPU. To compile a Linux + kernel that runs on these, say Y here. For details about Linux on + the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at + <http://www.linux-mips.org/>. + +config OLIVETTI_M700 + bool "Support for Olivetti M700-10" + depends on MACH_JAZZ + select DMA_NONCOHERENT + select SYS_SUPPORTS_LITTLE_ENDIAN + help + This is a machine with a R4000 100 MHz CPU. To compile a Linux + kernel that runs on these, say Y here. For details about Linux on + the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at + <http://www.linux-mips.org/>. diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index 0b608fa98d5a..b309b1bcf2e8 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c @@ -58,14 +58,13 @@ static void end_r4030_irq(unsigned int irq) } static struct hw_interrupt_type r4030_irq_type = { - "R4030", - startup_r4030_irq, - shutdown_r4030_irq, - enable_r4030_irq, - disable_r4030_irq, - mask_and_ack_r4030_irq, - end_r4030_irq, - NULL + .typename = "R4030", + .startup = startup_r4030_irq, + .shutdown = shutdown_r4030_irq, + .enable = enable_r4030_irq, + .disable = disable_r4030_irq, + .ack = mask_and_ack_r4030_irq, + .end = end_r4030_irq, }; void __init init_r4030_ints(void) diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c index fccb06fe209d..044df9d4ab7c 100644 --- a/arch/mips/jazz/setup.c +++ b/arch/mips/jazz/setup.c @@ -50,7 +50,7 @@ static struct resource jazz_io_resources[] = { { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY }, }; -static void __init jazz_setup(void) +void __init plat_setup(void) { int i; @@ -97,5 +97,3 @@ static void __init jazz_setup(void) vdma_init(); } - -early_initcall(jazz_setup); diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c index b9799b86fc79..7cbe14483f13 100644 --- a/arch/mips/jmr3927/rbhma3100/irq.c +++ b/arch/mips/jmr3927/rbhma3100/irq.c @@ -412,13 +412,13 @@ void __init arch_init_irq(void) } static hw_irq_controller jmr3927_irq_controller = { - "jmr3927_irq", - jmr3927_irq_startup, - jmr3927_irq_shutdown, - jmr3927_irq_enable, - jmr3927_irq_disable, - jmr3927_irq_ack, - jmr3927_irq_end, + .typename = "jmr3927_irq", + .startup = jmr3927_irq_startup, + .shutdown = jmr3927_irq_shutdown, + .enable = jmr3927_irq_enable, + .disable = jmr3927_irq_disable, + .ack = jmr3927_irq_ack, + .end = jmr3927_irq_end, }; void jmr3927_irq_init(u32 irq_base) diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c index 32039bb2f440..3e2fbdc66097 100644 --- a/arch/mips/jmr3927/rbhma3100/setup.c +++ b/arch/mips/jmr3927/rbhma3100/setup.c @@ -44,6 +44,11 @@ #include <linux/ioport.h> #include <linux/param.h> /* for HZ */ #include <linux/delay.h> +#ifdef CONFIG_SERIAL_TXX9 +#include <linux/tty.h> +#include <linux/serial.h> +#include <linux/serial_core.h> +#endif #include <asm/addrspace.h> #include <asm/time.h> @@ -193,7 +198,7 @@ static void jmr3927_board_init(void); extern struct resource pci_io_resource; extern struct resource pci_mem_resource; -static void __init jmr3927_setup(void) +void __init plat_setup(void) { char *argptr; @@ -211,8 +216,8 @@ static void __init jmr3927_setup(void) */ ioport_resource.start = pci_io_resource.start; ioport_resource.end = pci_io_resource.end; - iomem_resource.start = pci_mem_resource.start; - iomem_resource.end = pci_mem_resource.end; + iomem_resource.start = 0; + iomem_resource.end = 0xffffffff; /* Reboot on panic */ panic_timeout = 180; @@ -265,18 +270,35 @@ static void __init jmr3927_setup(void) strcat(argptr, " ip=bootp"); } -#ifdef CONFIG_TXX927_SERIAL_CONSOLE +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + int i; + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (char *)TX3927_SIO_REG(i); + req.mapbase = TX3927_SIO_REG(i); + req.irq = i == 0 ? + JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1; + if (i == 0) + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = JMR3927_IMCLK; + early_serial_txx9_setup(&req); + } + } +#ifdef CONFIG_SERIAL_TXX9_CONSOLE argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "console=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " console=ttyS1,115200"); } #endif +#endif } -early_initcall(jmr3927_setup); - - static void tx3927_setup(void); #ifdef CONFIG_PCI @@ -335,7 +357,7 @@ static void __init jmr3927_board_init(void) jmr3927_io_dipsw()); } -static void __init tx3927_setup(void) +void __init plat_setup(void) { int i; diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index d3303584fbd1..72f2126ad19d 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -11,11 +11,7 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \ irix5sys.o sysirix.o -ifdef CONFIG_MODULES -obj-y += mips_ksyms.o module.o -obj-$(CONFIG_32BIT) += module-elf32.o -obj-$(CONFIG_64BIT) += module-elf64.o -endif +obj-$(CONFIG_MODULES) += mips_ksyms.o module.o obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o @@ -38,12 +34,18 @@ obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_MIPS_MT_SMP) += smp_mt.o + +obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o +obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o + obj-$(CONFIG_NO_ISA) += dma-no-isa.o obj-$(CONFIG_I8259) += i8259.o obj-$(CONFIG_IRQ_CPU) += irq_cpu.o obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o obj-$(CONFIG_IRQ_MV64340) += irq-mv6434x.o +obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o obj-$(CONFIG_32BIT) += scall32-o32.o obj-$(CONFIG_64BIT) += scall64-64.o @@ -57,8 +59,6 @@ obj-$(CONFIG_PROC_FS) += proc.o obj-$(CONFIG_64BIT) += cpu-bugs64.o -obj-$(CONFIG_GEN_RTC) += genrtc.o - CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) CFLAGS_ioctl32.o += -Ifs/ diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index 2c11abb5a406..ca6b03c773be 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -95,6 +95,7 @@ void output_thread_info_defines(void) offset("#define TI_PRE_COUNT ", struct thread_info, preempt_count); offset("#define TI_ADDR_LIMIT ", struct thread_info, addr_limit); offset("#define TI_RESTART_BLOCK ", struct thread_info, restart_block); + offset("#define TI_TP_VALUE ", struct thread_info, tp_value); constant("#define _THREAD_SIZE_ORDER ", THREAD_SIZE_ORDER); constant("#define _THREAD_SIZE ", THREAD_SIZE); constant("#define _THREAD_MASK ", THREAD_MASK); @@ -240,6 +241,7 @@ void output_mm_defines(void) linefeed; } +#ifdef CONFIG_32BIT void output_sc_defines(void) { text("/* Linux sigcontext offsets. */"); @@ -251,10 +253,29 @@ void output_sc_defines(void) offset("#define SC_STATUS ", struct sigcontext, sc_status); offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr); offset("#define SC_FPC_EIR ", struct sigcontext, sc_fpc_eir); - offset("#define SC_CAUSE ", struct sigcontext, sc_cause); - offset("#define SC_BADVADDR ", struct sigcontext, sc_badvaddr); + offset("#define SC_HI1 ", struct sigcontext, sc_hi1); + offset("#define SC_LO1 ", struct sigcontext, sc_lo1); + offset("#define SC_HI2 ", struct sigcontext, sc_hi2); + offset("#define SC_LO2 ", struct sigcontext, sc_lo2); + offset("#define SC_HI3 ", struct sigcontext, sc_hi3); + offset("#define SC_LO3 ", struct sigcontext, sc_lo3); linefeed; } +#endif + +#ifdef CONFIG_64BIT +void output_sc_defines(void) +{ + text("/* Linux sigcontext offsets. */"); + offset("#define SC_REGS ", struct sigcontext, sc_regs); + offset("#define SC_FPREGS ", struct sigcontext, sc_fpregs); + offset("#define SC_MDHI ", struct sigcontext, sc_hi); + offset("#define SC_MDLO ", struct sigcontext, sc_lo); + offset("#define SC_PC ", struct sigcontext, sc_pc); + offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr); + linefeed; +} +#endif #ifdef CONFIG_MIPS32_COMPAT void output_sc32_defines(void) diff --git a/arch/mips/kernel/binfmt_elfn32.c b/arch/mips/kernel/binfmt_elfn32.c index 6b645fbb1ddc..d8e2674a1543 100644 --- a/arch/mips/kernel/binfmt_elfn32.c +++ b/arch/mips/kernel/binfmt_elfn32.c @@ -52,7 +52,6 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #include <asm/processor.h> #include <linux/module.h> -#include <linux/config.h> #include <linux/elfcore.h> #include <linux/compat.h> @@ -116,4 +115,7 @@ MODULE_AUTHOR("Ralf Baechle (ralf@linux-mips.org)"); #undef MODULE_DESCRIPTION #undef MODULE_AUTHOR +#undef TASK_SIZE +#define TASK_SIZE TASK_SIZE32 + #include "../../../fs/binfmt_elf.c" diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c index b4075e99c452..cec5f327e360 100644 --- a/arch/mips/kernel/binfmt_elfo32.c +++ b/arch/mips/kernel/binfmt_elfo32.c @@ -54,7 +54,6 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #include <asm/processor.h> #include <linux/module.h> -#include <linux/config.h> #include <linux/elfcore.h> #include <linux/compat.h> @@ -98,7 +97,7 @@ struct elf_prpsinfo32 #define init_elf_binfmt init_elf32_binfmt #define jiffies_to_timeval jiffies_to_compat_timeval -static __inline__ void +static inline void jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value) { /* @@ -113,21 +112,26 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value) #undef ELF_CORE_COPY_REGS #define ELF_CORE_COPY_REGS(_dest,_regs) elf32_core_copy_regs(_dest,_regs); -void elf32_core_copy_regs(elf_gregset_t _dest, struct pt_regs *_regs) +void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs) { int i; - memset(_dest, 0, sizeof(elf_gregset_t)); - - /* XXXKW the 6 is from EF_REG0 in gdb/gdb/mips-linux-tdep.c, include/asm-mips/reg.h */ - for (i=6; i<38; i++) - _dest[i] = (elf_greg_t) _regs->regs[i-6]; - _dest[i++] = (elf_greg_t) _regs->lo; - _dest[i++] = (elf_greg_t) _regs->hi; - _dest[i++] = (elf_greg_t) _regs->cp0_epc; - _dest[i++] = (elf_greg_t) _regs->cp0_badvaddr; - _dest[i++] = (elf_greg_t) _regs->cp0_status; - _dest[i++] = (elf_greg_t) _regs->cp0_cause; + for (i = 0; i < EF_R0; i++) + grp[i] = 0; + grp[EF_R0] = 0; + for (i = 1; i <= 31; i++) + grp[EF_R0 + i] = (elf_greg_t) regs->regs[i]; + grp[EF_R26] = 0; + grp[EF_R27] = 0; + grp[EF_LO] = (elf_greg_t) regs->lo; + grp[EF_HI] = (elf_greg_t) regs->hi; + grp[EF_CP0_EPC] = (elf_greg_t) regs->cp0_epc; + grp[EF_CP0_BADVADDR] = (elf_greg_t) regs->cp0_badvaddr; + grp[EF_CP0_STATUS] = (elf_greg_t) regs->cp0_status; + grp[EF_CP0_CAUSE] = (elf_greg_t) regs->cp0_cause; +#ifdef EF_UNUSED0 + grp[EF_UNUSED0] = 0; +#endif } MODULE_DESCRIPTION("Binary format loader for compatibility with o32 Linux/MIPS binaries"); @@ -136,4 +140,7 @@ MODULE_AUTHOR("Ralf Baechle (ralf@linux-mips.org)"); #undef MODULE_DESCRIPTION #undef MODULE_AUTHOR +#undef TASK_SIZE +#define TASK_SIZE TASK_SIZE32 + #include "../../../fs/binfmt_elf.c" diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c index 01117e977a7f..374de839558d 100644 --- a/arch/mips/kernel/branch.c +++ b/arch/mips/kernel/branch.c @@ -12,6 +12,7 @@ #include <asm/branch.h> #include <asm/cpu.h> #include <asm/cpu-features.h> +#include <asm/fpu.h> #include <asm/inst.h> #include <asm/ptrace.h> #include <asm/uaccess.h> @@ -21,7 +22,7 @@ */ int __compute_return_epc(struct pt_regs *regs) { - unsigned int *addr, bit, fcr31; + unsigned int *addr, bit, fcr31, dspcontrol; long epc; union mips_instruction insn; @@ -98,6 +99,18 @@ int __compute_return_epc(struct pt_regs *regs) epc += 8; regs->cp0_epc = epc; break; + case bposge32_op: + if (!cpu_has_dsp) + goto sigill; + + dspcontrol = rddsp(0x01); + + if (dspcontrol >= 32) { + epc = epc + 4 + (insn.i_format.simmediate << 2); + } else + epc += 8; + regs->cp0_epc = epc; + break; } break; @@ -161,10 +174,13 @@ int __compute_return_epc(struct pt_regs *regs) * And now the FPA/cp1 branch instructions. */ case cop1_op: - if (!cpu_has_fpu) - fcr31 = current->thread.fpu.soft.fcr31; - else + preempt_disable(); + if (is_fpu_owner()) asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); + else + fcr31 = current->thread.fpu.hard.fcr31; + preempt_enable(); + bit = (insn.i_format.rt >> 2); bit += (bit != 0); bit += 23; @@ -196,4 +212,9 @@ unaligned: printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); force_sig(SIGBUS, current); return -EFAULT; + +sigill: + printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm); + force_sig(SIGBUS, current); + return -EFAULT; } diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 7685f8baf3f0..a263fb7a3971 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -2,9 +2,9 @@ * Processor capabilities determination functions. * * Copyright (C) xxxx the Anonymous - * Copyright (C) 2003 Maciej W. Rozycki + * Copyright (C) 2003, 2004 Maciej W. Rozycki * Copyright (C) 1994 - 2003 Ralf Baechle - * Copyright (C) 2001 MIPS Inc. + * Copyright (C) 2001, 2004 MIPS Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -17,7 +17,6 @@ #include <linux/ptrace.h> #include <linux/stddef.h> -#include <asm/bugs.h> #include <asm/cpu.h> #include <asm/fpu.h> #include <asm/mipsregs.h> @@ -51,36 +50,48 @@ static void r4k_wait(void) ".set\tmips0"); } -/* - * The Au1xxx wait is available only if we run CONFIG_PM and - * the timer setup found we had a 32KHz counter available. - * There are still problems with functions that may call au1k_wait - * directly, but that will be discovered pretty quickly. - */ -extern void (*au1k_wait_ptr)(void); +/* The Au1xxx wait is available only if using 32khz counter or + * external timer source, but specifically not CP0 Counter. */ +int allow_au1k_wait; -void au1k_wait(void) +static void au1k_wait(void) { -#ifdef CONFIG_PM /* using the wait instruction makes CP0 counter unusable */ - __asm__(".set\tmips3\n\t" + __asm__(".set mips3\n\t" + "cache 0x14, 0(%0)\n\t" + "cache 0x14, 32(%0)\n\t" + "sync\n\t" + "nop\n\t" "wait\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" - ".set\tmips0"); -#else - __asm__("nop\n\t" - "nop"); -#endif + ".set mips0\n\t" + : : "r" (au1k_wait)); } +static int __initdata nowait = 0; + +int __init wait_disable(char *s) +{ + nowait = 1; + + return 1; +} + +__setup("nowait", wait_disable); + static inline void check_wait(void) { struct cpuinfo_mips *c = ¤t_cpu_data; printk("Checking for 'wait' instruction... "); + if (nowait) { + printk (" disabled.\n"); + return; + } + switch (c->cputype) { case CPU_R3081: case CPU_R3081E: @@ -109,22 +120,22 @@ static inline void check_wait(void) /* case CPU_20KC:*/ case CPU_24K: case CPU_25KF: + case CPU_34K: + case CPU_PR4450: cpu_wait = r4k_wait; printk(" available.\n"); break; -#ifdef CONFIG_PM case CPU_AU1000: case CPU_AU1100: case CPU_AU1500: - if (au1k_wait_ptr != NULL) { - cpu_wait = au1k_wait_ptr; + case CPU_AU1550: + case CPU_AU1200: + if (allow_au1k_wait) { + cpu_wait = au1k_wait; printk(" available.\n"); - } - else { + } else printk(" unavailable.\n"); - } break; -#endif default: printk(" unavailable.\n"); break; @@ -180,7 +191,7 @@ static inline int __cpu_has_fpu(void) return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); } -#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \ +#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ | MIPS_CPU_COUNTER) static inline void cpu_probe_legacy(struct cpuinfo_mips *c) @@ -189,7 +200,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) case PRID_IMP_R2000: c->cputype = CPU_R2000; c->isa_level = MIPS_CPU_ISA_I; - c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; + c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | + MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) c->options |= MIPS_CPU_FPU; c->tlbsize = 64; @@ -203,7 +215,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) else c->cputype = CPU_R3000; c->isa_level = MIPS_CPU_ISA_I; - c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; + c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | + MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) c->options |= MIPS_CPU_FPU; c->tlbsize = 64; @@ -266,7 +279,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) case PRID_IMP_R4600: c->cputype = CPU_R4600; c->isa_level = MIPS_CPU_ISA_III; - c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; c->tlbsize = 48; break; #if 0 @@ -285,7 +299,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) #endif case PRID_IMP_TX39: c->isa_level = MIPS_CPU_ISA_I; - c->options = MIPS_CPU_TLB; + c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { c->cputype = CPU_TX3927; @@ -421,74 +435,147 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) } } -static inline void decode_config1(struct cpuinfo_mips *c) +static inline unsigned int decode_config0(struct cpuinfo_mips *c) { - unsigned long config0 = read_c0_config(); - unsigned long config1; + unsigned int config0; + int isa; + + config0 = read_c0_config(); - if ((config0 & (1 << 31)) == 0) - return; /* actually wort a panic() */ + if (((config0 & MIPS_CONF_MT) >> 7) == 1) + c->options |= MIPS_CPU_TLB; + isa = (config0 & MIPS_CONF_AT) >> 13; + switch (isa) { + case 0: + c->isa_level = MIPS_CPU_ISA_M32; + break; + case 2: + c->isa_level = MIPS_CPU_ISA_M64; + break; + default: + panic("Unsupported ISA type, cp0.config0.at: %d.", isa); + } + + return config0 & MIPS_CONF_M; +} + +static inline unsigned int decode_config1(struct cpuinfo_mips *c) +{ + unsigned int config1; - /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */ - c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | - MIPS_CPU_LLSC | MIPS_CPU_MCHECK; config1 = read_c0_config1(); - if (config1 & (1 << 3)) + + if (config1 & MIPS_CONF1_MD) + c->ases |= MIPS_ASE_MDMX; + if (config1 & MIPS_CONF1_WR) c->options |= MIPS_CPU_WATCH; - if (config1 & (1 << 2)) - c->options |= MIPS_CPU_MIPS16; - if (config1 & (1 << 1)) + if (config1 & MIPS_CONF1_CA) + c->ases |= MIPS_ASE_MIPS16; + if (config1 & MIPS_CONF1_EP) c->options |= MIPS_CPU_EJTAG; - if (config1 & 1) { + if (config1 & MIPS_CONF1_FP) { c->options |= MIPS_CPU_FPU; c->options |= MIPS_CPU_32FPR; } + if (cpu_has_tlb) + c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; + + return config1 & MIPS_CONF_M; +} + +static inline unsigned int decode_config2(struct cpuinfo_mips *c) +{ + unsigned int config2; + + config2 = read_c0_config2(); + + if (config2 & MIPS_CONF2_SL) + c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; + + return config2 & MIPS_CONF_M; +} + +static inline unsigned int decode_config3(struct cpuinfo_mips *c) +{ + unsigned int config3; + + config3 = read_c0_config3(); + + if (config3 & MIPS_CONF3_SM) + c->ases |= MIPS_ASE_SMARTMIPS; + if (config3 & MIPS_CONF3_DSP) + c->ases |= MIPS_ASE_DSP; + if (config3 & MIPS_CONF3_VINT) + c->options |= MIPS_CPU_VINT; + if (config3 & MIPS_CONF3_VEIC) + c->options |= MIPS_CPU_VEIC; + if (config3 & MIPS_CONF3_MT) + c->ases |= MIPS_ASE_MIPSMT; + + return config3 & MIPS_CONF_M; +} + +static inline void decode_configs(struct cpuinfo_mips *c) +{ + /* MIPS32 or MIPS64 compliant CPU. */ + c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | + MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; + c->scache.flags = MIPS_CACHE_NOT_PRESENT; - c->tlbsize = ((config1 >> 25) & 0x3f) + 1; + /* Read Config registers. */ + if (!decode_config0(c)) + return; /* actually worth a panic() */ + if (!decode_config1(c)) + return; + if (!decode_config2(c)) + return; + if (!decode_config3(c)) + return; } static inline void cpu_probe_mips(struct cpuinfo_mips *c) { - decode_config1(c); + decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_4KC: c->cputype = CPU_4KC; - c->isa_level = MIPS_CPU_ISA_M32; break; case PRID_IMP_4KEC: c->cputype = CPU_4KEC; - c->isa_level = MIPS_CPU_ISA_M32; + break; + case PRID_IMP_4KECR2: + c->cputype = CPU_4KEC; break; case PRID_IMP_4KSC: + case PRID_IMP_4KSD: c->cputype = CPU_4KSC; - c->isa_level = MIPS_CPU_ISA_M32; break; case PRID_IMP_5KC: c->cputype = CPU_5KC; - c->isa_level = MIPS_CPU_ISA_M64; break; case PRID_IMP_20KC: c->cputype = CPU_20KC; - c->isa_level = MIPS_CPU_ISA_M64; break; case PRID_IMP_24K: + case PRID_IMP_24KE: c->cputype = CPU_24K; - c->isa_level = MIPS_CPU_ISA_M32; break; case PRID_IMP_25KF: c->cputype = CPU_25KF; - c->isa_level = MIPS_CPU_ISA_M64; /* Probe for L2 cache */ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; break; + case PRID_IMP_34K: + c->cputype = CPU_34K; + c->isa_level = MIPS_CPU_ISA_M32; + break; } } static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) { - decode_config1(c); + decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_AU1_REV1: case PRID_IMP_AU1_REV2: @@ -505,50 +592,70 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) case 3: c->cputype = CPU_AU1550; break; + case 4: + c->cputype = CPU_AU1200; + break; default: panic("Unknown Au Core!"); break; } - c->isa_level = MIPS_CPU_ISA_M32; break; } } static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) { - decode_config1(c); + decode_configs(c); + + /* + * For historical reasons the SB1 comes with it's own variant of + * cache code which eventually will be folded into c-r4k.c. Until + * then we pretend it's got it's own cache architecture. + */ + c->options &= ~MIPS_CPU_4K_CACHE; + c->options |= MIPS_CPU_SB1_CACHE; + switch (c->processor_id & 0xff00) { case PRID_IMP_SB1: c->cputype = CPU_SB1; - c->isa_level = MIPS_CPU_ISA_M64; - c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | - MIPS_CPU_MCHECK | MIPS_CPU_EJTAG | - MIPS_CPU_WATCH | MIPS_CPU_LLSC; -#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS +#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS /* FPU in pass1 is known to have issues. */ - c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; + c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); #endif break; + case PRID_IMP_SB1A: + c->cputype = CPU_SB1A; + break; } } static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) { - decode_config1(c); + decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_SR71000: c->cputype = CPU_SR71000; - c->isa_level = MIPS_CPU_ISA_M64; - c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_4KTLB | MIPS_CPU_FPU | - MIPS_CPU_COUNTER | MIPS_CPU_MCHECK; c->scache.ways = 8; c->tlbsize = 64; break; } } +static inline void cpu_probe_philips(struct cpuinfo_mips *c) +{ + decode_configs(c); + switch (c->processor_id & 0xff00) { + case PRID_IMP_PR4450: + c->cputype = CPU_PR4450; + c->isa_level = MIPS_CPU_ISA_M32; + break; + default: + panic("Unknown Philips Core!"); /* REVISIT: die? */ + break; + } +} + + __init void cpu_probe(void) { struct cpuinfo_mips *c = ¤t_cpu_data; @@ -571,15 +678,24 @@ __init void cpu_probe(void) case PRID_COMP_SIBYTE: cpu_probe_sibyte(c); break; - case PRID_COMP_SANDCRAFT: cpu_probe_sandcraft(c); break; + case PRID_COMP_PHILIPS: + cpu_probe_philips(c); + break; default: c->cputype = CPU_UNKNOWN; } - if (c->options & MIPS_CPU_FPU) + if (c->options & MIPS_CPU_FPU) { c->fpu_id = cpu_get_fpu_id(); + + if (c->isa_level == MIPS_CPU_ISA_M32 || + c->isa_level == MIPS_CPU_ISA_M64) { + if (c->fpu_id & MIPS_FPIR_3D) + c->ases |= MIPS_ASE_MIPS3D; + } + } } __init void cpu_report(void) diff --git a/arch/mips/kernel/dma-no-isa.c b/arch/mips/kernel/dma-no-isa.c new file mode 100644 index 000000000000..6df8b07741e3 --- /dev/null +++ b/arch/mips/kernel/dma-no-isa.c @@ -0,0 +1,28 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004 by Ralf Baechle + * + * Dummy ISA DMA functions for systems that don't have ISA but share drivers + * with ISA such as legacy free PCI. + */ +#include <linux/errno.h> +#include <linux/module.h> +#include <linux/spinlock.h> + +DEFINE_SPINLOCK(dma_spin_lock); + +int request_dma(unsigned int dmanr, const char * device_id) +{ + return -EINVAL; +} + +void free_dma(unsigned int dmanr) +{ +} + +EXPORT_SYMBOL(dma_spin_lock); +EXPORT_SYMBOL(request_dma); +EXPORT_SYMBOL(free_dma); diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S index 5eb429137e06..83c87fe4ee4f 100644 --- a/arch/mips/kernel/entry.S +++ b/arch/mips/kernel/entry.S @@ -19,11 +19,11 @@ #include <asm/war.h> #ifdef CONFIG_PREEMPT - .macro preempt_stop reg=t0 + .macro preempt_stop .endm #else - .macro preempt_stop reg=t0 - local_irq_disable \reg + .macro preempt_stop + local_irq_disable .endm #define resume_kernel restore_all #endif @@ -37,17 +37,18 @@ FEXPORT(ret_from_irq) andi t0, t0, KU_USER beqz t0, resume_kernel -FEXPORT(resume_userspace) - local_irq_disable t0 # make sure we dont miss an +resume_userspace: + local_irq_disable # make sure we dont miss an # interrupt setting need_resched # between sampling and return LONG_L a2, TI_FLAGS($28) # current->work - andi a2, _TIF_WORK_MASK # (ignoring syscall_trace) - bnez a2, work_pending + andi t0, a2, _TIF_WORK_MASK # (ignoring syscall_trace) + bnez t0, work_pending j restore_all #ifdef CONFIG_PREEMPT -ENTRY(resume_kernel) +resume_kernel: + local_irq_disable lw t0, TI_PRE_COUNT($28) bnez t0, restore_all need_resched: @@ -57,12 +58,7 @@ need_resched: LONG_L t0, PT_STATUS(sp) # Interrupts off? andi t0, 1 beqz t0, restore_all - li t0, PREEMPT_ACTIVE - sw t0, TI_PRE_COUNT($28) - local_irq_enable t0 - jal schedule - sw zero, TI_PRE_COUNT($28) - local_irq_disable t0 + jal preempt_schedule_irq b need_resched #endif @@ -88,13 +84,13 @@ FEXPORT(restore_partial) # restore partial frame RESTORE_SP_AND_RET .set at -FEXPORT(work_pending) - andi t0, a2, _TIF_NEED_RESCHED +work_pending: + andi t0, a2, _TIF_NEED_RESCHED # a2 is preloaded with TI_FLAGS beqz t0, work_notifysig work_resched: jal schedule - local_irq_disable t0 # make sure need_resched and + local_irq_disable # make sure need_resched and # signals dont change between # sampling and return LONG_L a2, TI_FLAGS($28) @@ -109,15 +105,14 @@ work_notifysig: # deal with pending signals and move a0, sp li a1, 0 jal do_notify_resume # a2 already loaded - j restore_all + j resume_userspace FEXPORT(syscall_exit_work_partial) SAVE_STATIC -FEXPORT(syscall_exit_work) - LONG_L t0, TI_FLAGS($28) - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT - and t0, t1 - beqz t0, work_pending # trace bit is set +syscall_exit_work: + li t0, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT + and t0, a2 # a2 is preloaded with TI_FLAGS + beqz t0, work_pending # trace bit set? local_irq_enable # could let do_syscall_trace() # call schedule() instead move a0, sp @@ -128,28 +123,25 @@ FEXPORT(syscall_exit_work) /* * Common spurious interrupt handler. */ - .text - .align 5 LEAF(spurious_interrupt) /* * Someone tried to fool us by sending an interrupt but we * couldn't find a cause for it. */ + PTR_LA t1, irq_err_count #ifdef CONFIG_SMP - lui t1, %hi(irq_err_count) -1: ll t0, %lo(irq_err_count)(t1) +1: ll t0, (t1) addiu t0, 1 - sc t0, %lo(irq_err_count)(t1) + sc t0, (t1) #if R10000_LLSC_WAR beqzl t0, 1b #else beqz t0, 1b #endif #else - lui t1, %hi(irq_err_count) - lw t0, %lo(irq_err_count)(t1) + lw t0, (t1) addiu t0, 1 - sw t0, %lo(irq_err_count)(t1) + sw t0, (t1) #endif j ret_from_irq END(spurious_interrupt) diff --git a/arch/mips/kernel/gdb-low.S b/arch/mips/kernel/gdb-low.S index 512bedbfa7b9..83b8986f9401 100644 --- a/arch/mips/kernel/gdb-low.S +++ b/arch/mips/kernel/gdb-low.S @@ -52,16 +52,15 @@ /* * Called from user mode, go somewhere else. */ - lui k1, %hi(saved_vectors) mfc0 k0, CP0_CAUSE andi k0, k0, 0x7c add k1, k1, k0 - lw k0, %lo(saved_vectors)(k1) + PTR_L k0, saved_vectors(k1) jr k0 nop 1: move k0, sp - subu sp, k1, GDB_FR_SIZE*2 # see comment above + PTR_SUBU sp, k1, GDB_FR_SIZE*2 # see comment above LONG_S k0, GDB_FR_REG29(sp) LONG_S $2, GDB_FR_REG2(sp) diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c index d3fd1ab14274..96d18c43dca0 100644 --- a/arch/mips/kernel/gdb-stub.c +++ b/arch/mips/kernel/gdb-stub.c @@ -176,8 +176,10 @@ int kgdb_enabled; /* * spin locks for smp case */ -static spinlock_t kgdb_lock = SPIN_LOCK_UNLOCKED; -static spinlock_t kgdb_cpulock[NR_CPUS] = { [0 ... NR_CPUS-1] = SPIN_LOCK_UNLOCKED}; +static DEFINE_SPINLOCK(kgdb_lock); +static raw_spinlock_t kgdb_cpulock[NR_CPUS] = { + [0 ... NR_CPUS-1] = __RAW_SPIN_LOCK_UNLOCKED; +}; /* * BUFMAX defines the maximum number of characters in inbound/outbound buffers @@ -637,29 +639,32 @@ static struct gdb_bp_save async_bp; * and only one can be active at a time. */ extern spinlock_t smp_call_lock; + void set_async_breakpoint(unsigned long *epc) { /* skip breaking into userland */ if ((*epc & 0x80000000) == 0) return; +#ifdef CONFIG_SMP /* avoid deadlock if someone is make IPC */ if (spin_is_locked(&smp_call_lock)) return; +#endif async_bp.addr = *epc; *epc = (unsigned long)async_breakpoint; } -void kgdb_wait(void *arg) +static void kgdb_wait(void *arg) { unsigned flags; int cpu = smp_processor_id(); local_irq_save(flags); - spin_lock(&kgdb_cpulock[cpu]); - spin_unlock(&kgdb_cpulock[cpu]); + __raw_spin_lock(&kgdb_cpulock[cpu]); + __raw_spin_unlock(&kgdb_cpulock[cpu]); local_irq_restore(flags); } @@ -707,7 +712,7 @@ void handle_exception (struct gdb_regs *regs) * acquire the CPU spinlocks */ for (i = num_online_cpus()-1; i >= 0; i--) - if (spin_trylock(&kgdb_cpulock[i]) == 0) + if (__raw_spin_trylock(&kgdb_cpulock[i]) == 0) panic("kgdb: couldn't get cpulock %d\n", i); /* @@ -982,7 +987,7 @@ finish_kgdb: exit_kgdb_exception: /* release locks so other CPUs can go */ for (i = num_online_cpus()-1; i >= 0; i--) - spin_unlock(&kgdb_cpulock[i]); + __raw_spin_unlock(&kgdb_cpulock[i]); spin_unlock(&kgdb_lock); __flush_cache_all(); @@ -1036,12 +1041,12 @@ void adel(void) * malloc is needed by gdb client in "call func()", even a private one * will make gdb happy */ -static void *malloc(size_t size) +static void * __attribute_used__ malloc(size_t size) { return kmalloc(size, GFP_ATOMIC); } -static void free(void *where) +static void __attribute_used__ free (void *where) { kfree(where); } diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index e7f6c1b90806..aa18a8b7b380 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -82,7 +82,7 @@ NESTED(except_vec3_r4000, 0, sp) li k0, 14<<2 beq k1, k0, handle_vcei #ifdef CONFIG_64BIT - dsll k1, k1, 1 + dsll k1, k1, 1 #endif .set pop PTR_L k0, exception_handlers(k1) @@ -90,17 +90,17 @@ NESTED(except_vec3_r4000, 0, sp) /* * Big shit, we now may have two dirty primary cache lines for the same - * physical address. We can savely invalidate the line pointed to by + * physical address. We can safely invalidate the line pointed to by * c0_badvaddr because after return from this exception handler the * load / store will be re-executed. */ handle_vced: - DMFC0 k0, CP0_BADVADDR + MFC0 k0, CP0_BADVADDR li k1, -4 # Is this ... and k0, k1 # ... really needed? mtc0 zero, CP0_TAGLO - cache Index_Store_Tag_D,(k0) - cache Hit_Writeback_Inv_SD,(k0) + cache Index_Store_Tag_D, (k0) + cache Hit_Writeback_Inv_SD, (k0) #ifdef CONFIG_PROC_FS PTR_LA k0, vced_count lw k1, (k0) @@ -148,6 +148,38 @@ NESTED(except_vec_ejtag_debug, 0, sp) __FINIT /* + * Vectored interrupt handler. + * This prototype is copied to ebase + n*IntCtl.VS and patched + * to invoke the handler + */ +NESTED(except_vec_vi, 0, sp) + SAVE_SOME + SAVE_AT + .set push + .set noreorder +EXPORT(except_vec_vi_lui) + lui v0, 0 /* Patched */ + j except_vec_vi_handler +EXPORT(except_vec_vi_ori) + ori v0, 0 /* Patched */ + .set pop + END(except_vec_vi) +EXPORT(except_vec_vi_end) + +/* + * Common Vectored Interrupt code + * Complete the register saves and invoke the handler which is passed in $v0 + */ +NESTED(except_vec_vi_handler, 0, sp) + SAVE_TEMP + SAVE_STATIC + CLI + move a0, sp + jalr v0 + j ret_from_irq + END(except_vec_vi_handler) + +/* * EJTAG debug exception handler. */ NESTED(ejtag_debug_handler, PT_SIZE, sp) @@ -291,6 +323,8 @@ NESTED(nmi_handler, PT_SIZE, sp) BUILD_HANDLER mdmx mdmx sti silent /* #22 */ BUILD_HANDLER watch watch sti verbose /* #23 */ BUILD_HANDLER mcheck mcheck cli verbose /* #24 */ + BUILD_HANDLER mt mt sti verbose /* #25 */ + BUILD_HANDLER dsp dsp sti silent /* #26 */ BUILD_HANDLER reserved reserved sti verbose /* others */ #ifdef CONFIG_64BIT diff --git a/arch/mips/kernel/genrtc.c b/arch/mips/kernel/genrtc.c deleted file mode 100644 index 71416e7bbbaa..000000000000 --- a/arch/mips/kernel/genrtc.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * A glue layer that provides RTC read/write to drivers/char/genrtc.c driver - * based on MIPS internal RTC routines. It does take care locking - * issues so that we are SMP/Preemption safe. - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * Please read the COPYING file for all license details. - */ - -#include <linux/spinlock.h> - -#include <asm/rtc.h> -#include <asm/time.h> - -static DEFINE_SPINLOCK(mips_rtc_lock); - -unsigned int get_rtc_time(struct rtc_time *time) -{ - unsigned long nowtime; - - spin_lock(&mips_rtc_lock); - nowtime = rtc_get_time(); - to_tm(nowtime, time); - time->tm_year -= 1900; - spin_unlock(&mips_rtc_lock); - - return RTC_24H; -} - -int set_rtc_time(struct rtc_time *time) -{ - unsigned long nowtime; - int ret; - - spin_lock(&mips_rtc_lock); - nowtime = mktime(time->tm_year+1900, time->tm_mon+1, - time->tm_mday, time->tm_hour, time->tm_min, - time->tm_sec); - ret = rtc_set_time(nowtime); - spin_unlock(&mips_rtc_lock); - - return ret; -} - -unsigned int get_rtc_ss(void) -{ - struct rtc_time h; - - get_rtc_time(&h); - return h.tm_sec; -} - -int get_rtc_pll(struct rtc_pll_info *pll) -{ - return -EINVAL; -} - -int set_rtc_pll(struct rtc_pll_info *pll) -{ - return -EINVAL; -} - diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index 2a1b45d66f04..2e9122a4213a 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -22,11 +22,8 @@ #include <asm/page.h> #include <asm/mipsregs.h> #include <asm/stackframe.h> -#ifdef CONFIG_SGI_IP27 -#include <asm/sn/addrs.h> -#include <asm/sn/sn0/hubni.h> -#include <asm/sn/klkernvars.h> -#endif + +#include <kernel-entry-init.h> .macro ARC64_TWIDDLE_PC #if defined(CONFIG_ARC64) || defined(CONFIG_MAPPED_KERNEL) @@ -38,18 +35,6 @@ #endif .endm -#ifdef CONFIG_SGI_IP27 - /* - * outputs the local nasid into res. IP27 stuff. - */ - .macro GET_NASID_ASM res - dli \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID) - ld \res, (\res) - and \res, NSRI_NODEID_MASK - dsrl \res, NSRI_NODEID_SHFT - .endm -#endif /* CONFIG_SGI_IP27 */ - /* * inputs are the text nasid in t1, data nasid in t2. */ @@ -131,16 +116,21 @@ EXPORT(stext) # used for profiling EXPORT(_stext) +#if defined(CONFIG_QEMU) || defined(CONFIG_MIPS_SIM) + /* + * Give us a fighting chance of running if execution beings at the + * kernel load address. This is needed because this platform does + * not have a ELF loader yet. + */ + j kernel_entry +#endif __INIT NESTED(kernel_entry, 16, sp) # kernel entry point - setup_c0_status_pri -#ifdef CONFIG_SGI_IP27 - GET_NASID_ASM t1 - move t2, t1 # text and data are here - MAPPED_KERNEL_SETUP_TLB -#endif /* IP27 */ + kernel_entry_setup # cpu specific setup + + setup_c0_status_pri ARC64_TWIDDLE_PC @@ -157,6 +147,7 @@ NESTED(kernel_entry, 16, sp) # kernel entry point LONG_S a2, fw_arg2 LONG_S a3, fw_arg3 + MTC0 zero, CP0_CONTEXT # clear context register PTR_LA $28, init_thread_union PTR_ADDIU sp, $28, _THREAD_SIZE - 32 set_saved_sp sp, t0, t1 @@ -165,6 +156,10 @@ NESTED(kernel_entry, 16, sp) # kernel entry point j start_kernel END(kernel_entry) +#ifdef CONFIG_QEMU + __INIT +#endif + #ifdef CONFIG_SMP /* * SMP slave cpus entry point. Board specific code for bootstrap calls this @@ -172,20 +167,7 @@ NESTED(kernel_entry, 16, sp) # kernel entry point */ NESTED(smp_bootstrap, 16, sp) setup_c0_status_sec - -#ifdef CONFIG_SGI_IP27 - GET_NASID_ASM t1 - dli t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \ - KLDIR_OFF_POINTER + CAC_BASE - dsll t1, NASID_SHFT - or t0, t0, t1 - ld t0, 0(t0) # t0 points to kern_vars struct - lh t1, KV_RO_NASID_OFFSET(t0) - lh t2, KV_RW_NASID_OFFSET(t0) - MAPPED_KERNEL_SETUP_TLB - ARC64_TWIDDLE_PC -#endif /* CONFIG_SGI_IP27 */ - + smp_slave_setup j start_secondary END(smp_bootstrap) #endif /* CONFIG_SMP */ @@ -200,19 +182,13 @@ NESTED(smp_bootstrap, 16, sp) .comm fw_arg2, SZREG, SZREG .comm fw_arg3, SZREG, SZREG - .macro page name, order=0 - .globl \name -\name: .size \name, (_PAGE_SIZE << \order) - .org . + (_PAGE_SIZE << \order) - .type \name, @object + .macro page name, order + .comm \name, (_PAGE_SIZE << \order), (_PAGE_SIZE << \order) .endm - .data - .align PAGE_SHIFT - /* - * ... but on 64-bit we've got three-level pagetables with a - * slightly different layout ... + * On 64-bit we've got three-level pagetables with a slightly + * different layout ... */ page swapper_pg_dir, _PGD_ORDER #ifdef CONFIG_64BIT diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index 447759201d1d..b974ac9057f6 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c @@ -31,7 +31,7 @@ void disable_8259A_irq(unsigned int irq); * moves to arch independent land */ -spinlock_t DEFINE_SPINLOCK(i8259A_lock); +DEFINE_SPINLOCK(i8259A_lock); static void end_8259A_irq (unsigned int irq) { @@ -52,14 +52,13 @@ static unsigned int startup_8259A_irq(unsigned int irq) } static struct hw_interrupt_type i8259A_irq_type = { - "XT-PIC", - startup_8259A_irq, - shutdown_8259A_irq, - enable_8259A_irq, - disable_8259A_irq, - mask_and_ack_8259A, - end_8259A_irq, - NULL + .typename = "XT-PIC", + .startup = startup_8259A_irq, + .shutdown = shutdown_8259A_irq, + .enable = enable_8259A_irq, + .disable = disable_8259A_irq, + .ack = mask_and_ack_8259A, + .end = end_8259A_irq, }; /* @@ -308,7 +307,7 @@ static struct resource pic2_io_resource = { /* * On systems with i8259-style interrupt controllers we assume for - * driver compatibility reasons interrupts 0 - 15 to be the i8295 + * driver compatibility reasons interrupts 0 - 15 to be the i8259 * interrupts even if the hardware uses a different interrupt numbering. */ void __init init_i8259_irqs (void) @@ -322,7 +321,7 @@ void __init init_i8259_irqs (void) for (i = 0; i < 16; i++) { irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; + irq_desc[i].action = NULL; irq_desc[i].depth = 1; irq_desc[i].handler = &i8259A_irq_type; } diff --git a/arch/mips/kernel/ioctl32.c b/arch/mips/kernel/ioctl32.c index c069719ff0d8..ed9b2da510be 100644 --- a/arch/mips/kernel/ioctl32.c +++ b/arch/mips/kernel/ioctl32.c @@ -41,12 +41,6 @@ IOCTL_TABLE_START #define DECLARES #include "compat_ioctl.c" -#ifdef CONFIG_SIBYTE_TBPROF -COMPATIBLE_IOCTL(SBPROF_ZBSTART) -COMPATIBLE_IOCTL(SBPROF_ZBSTOP) -COMPATIBLE_IOCTL(SBPROF_ZBWAITFULL) -#endif /* CONFIG_SIBYTE_TBPROF */ - /*HANDLE_IOCTL(RTC_IRQP_READ, w_long) COMPATIBLE_IOCTL(RTC_IRQP_SET) HANDLE_IOCTL(RTC_EPOCH_READ, w_long) diff --git a/arch/mips/kernel/irixelf.c b/arch/mips/kernel/irixelf.c index 4af20cd91f9f..99262fe64560 100644 --- a/arch/mips/kernel/irixelf.c +++ b/arch/mips/kernel/irixelf.c @@ -8,7 +8,7 @@ * * Copyright (C) 1993 - 1994 Eric Youngdale <ericy@cais.com> * Copyright (C) 1996 - 2004 David S. Miller <dm@engr.sgi.com> - * Copyright (C) 2004 Steven J. Hill <sjhill@realitydiluted.com> + * Copyright (C) 2004 - 2005 Steven J. Hill <sjhill@realitydiluted.com> */ #include <linux/module.h> #include <linux/fs.h> @@ -31,15 +31,16 @@ #include <linux/elfcore.h> #include <linux/smp_lock.h> -#include <asm/uaccess.h> #include <asm/mipsregs.h> +#include <asm/namei.h> #include <asm/prctl.h> +#include <asm/uaccess.h> #define DLINFO_ITEMS 12 #include <linux/elf.h> -#undef DEBUG_ELF +#undef DEBUG static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs); static int load_irix_library(struct file *); @@ -55,7 +56,7 @@ static struct linux_binfmt irix_format = { #define elf_addr_t unsigned long #endif -#ifdef DEBUG_ELF +#ifdef DEBUG /* Debugging routines. */ static char *get_elf_p_type(Elf32_Word p_type) { @@ -120,7 +121,7 @@ static void dump_phdrs(struct elf_phdr *ep, int pnum) print_phdr(i, ep); } } -#endif /* (DEBUG_ELF) */ +#endif /* DEBUG */ static void set_brk(unsigned long start, unsigned long end) { @@ -146,20 +147,20 @@ static void padzero(unsigned long elf_bss) nbyte = elf_bss & (PAGE_SIZE-1); if (nbyte) { nbyte = PAGE_SIZE - nbyte; - clear_user((void *) elf_bss, nbyte); + clear_user((void __user *) elf_bss, nbyte); } } -unsigned long * create_irix_tables(char * p, int argc, int envc, - struct elfhdr * exec, unsigned int load_addr, - unsigned int interp_load_addr, - struct pt_regs *regs, struct elf_phdr *ephdr) +static unsigned long * create_irix_tables(char * p, int argc, int envc, + struct elfhdr * exec, unsigned int load_addr, + unsigned int interp_load_addr, struct pt_regs *regs, + struct elf_phdr *ephdr) { elf_addr_t *argv; elf_addr_t *envp; elf_addr_t *sp, *csp; -#ifdef DEBUG_ELF +#ifdef DEBUG printk("create_irix_tables: p[%p] argc[%d] envc[%d] " "load_addr[%08x] interp_load_addr[%08x]\n", p, argc, envc, load_addr, interp_load_addr); @@ -248,14 +249,13 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex, last_bss = 0; error = load_addr = 0; -#ifdef DEBUG_ELF +#ifdef DEBUG print_elfhdr(interp_elf_ex); #endif /* First of all, some simple consistency checks */ if ((interp_elf_ex->e_type != ET_EXEC && interp_elf_ex->e_type != ET_DYN) || - !irix_elf_check_arch(interp_elf_ex) || !interpreter->f_op->mmap) { printk("IRIX interp has bad e_type %d\n", interp_elf_ex->e_type); return 0xffffffff; @@ -290,7 +290,7 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex, (char *) elf_phdata, sizeof(struct elf_phdr) * interp_elf_ex->e_phnum); -#ifdef DEBUG_ELF +#ifdef DEBUG dump_phdrs(elf_phdata, interp_elf_ex->e_phnum); #endif @@ -306,13 +306,11 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex, elf_type |= MAP_FIXED; vaddr = eppnt->p_vaddr; -#ifdef DEBUG_ELF - printk("INTERP do_mmap(%p, %08lx, %08lx, %08lx, %08lx, %08lx) ", + pr_debug("INTERP do_mmap(%p, %08lx, %08lx, %08lx, %08lx, %08lx) ", interpreter, vaddr, (unsigned long) (eppnt->p_filesz + (eppnt->p_vaddr & 0xfff)), (unsigned long) elf_prot, (unsigned long) elf_type, (unsigned long) (eppnt->p_offset & 0xfffff000)); -#endif down_write(¤t->mm->mmap_sem); error = do_mmap(interpreter, vaddr, eppnt->p_filesz + (eppnt->p_vaddr & 0xfff), @@ -324,14 +322,10 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex, printk("Aieee IRIX interp mmap error=%d\n", error); break; /* Real error */ } -#ifdef DEBUG_ELF - printk("error=%08lx ", (unsigned long) error); -#endif + pr_debug("error=%08lx ", (unsigned long) error); if(!load_addr && interp_elf_ex->e_type == ET_DYN) { load_addr = error; -#ifdef DEBUG_ELF - printk("load_addr = error "); -#endif + pr_debug("load_addr = error "); } /* Find the end of the file mapping for this phdr, and keep @@ -345,17 +339,13 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex, */ k = eppnt->p_memsz + eppnt->p_vaddr; if(k > last_bss) last_bss = k; -#ifdef DEBUG_ELF - printk("\n"); -#endif + pr_debug("\n"); } } /* Now use mmap to map the library into memory. */ if(error < 0 && error > -1024) { -#ifdef DEBUG_ELF - printk("got error %d\n", error); -#endif + pr_debug("got error %d\n", error); kfree(elf_phdata); return 0xffffffff; } @@ -365,16 +355,12 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex, * that there are zero-mapped pages up to and including the * last bss page. */ -#ifdef DEBUG_ELF - printk("padzero(%08lx) ", (unsigned long) (elf_bss)); -#endif + pr_debug("padzero(%08lx) ", (unsigned long) (elf_bss)); padzero(elf_bss); len = (elf_bss + 0xfff) & 0xfffff000; /* What we have mapped so far */ -#ifdef DEBUG_ELF - printk("last_bss[%08lx] len[%08lx]\n", (unsigned long) last_bss, - (unsigned long) len); -#endif + pr_debug("last_bss[%08lx] len[%08lx]\n", (unsigned long) last_bss, + (unsigned long) len); /* Map the last of the bss segment */ if (last_bss > len) { @@ -396,12 +382,7 @@ static int verify_binary(struct elfhdr *ehp, struct linux_binprm *bprm) /* First of all, some simple consistency checks */ if((ehp->e_type != ET_EXEC && ehp->e_type != ET_DYN) || - !irix_elf_check_arch(ehp) || !bprm->file->f_op->mmap) { - return -ENOEXEC; - } - - /* Only support MIPS ARCH2 or greater IRIX binaries for now. */ - if(!(ehp->e_flags & EF_MIPS_ARCH) && !(ehp->e_flags & 0x04)) { + !bprm->file->f_op->mmap) { return -ENOEXEC; } @@ -411,16 +392,17 @@ static int verify_binary(struct elfhdr *ehp, struct linux_binprm *bprm) * XXX all registers as 64bits on cpu's capable of this at * XXX exception time plus frob the XTLB exception vector. */ - if((ehp->e_flags & 0x20)) { + if((ehp->e_flags & EF_MIPS_ABI2)) return -ENOEXEC; - } - return 0; /* It's ok. */ + return 0; } -#define IRIX_INTERP_PREFIX "/usr/gnemul/irix" - -/* Look for an IRIX ELF interpreter. */ +/* + * This is where the detailed check is performed. Irix binaries + * use interpreters with 'libc.so' in the name, so this function + * can differentiate between Linux and Irix binaries. + */ static inline int look_for_irix_interpreter(char **name, struct file **interpreter, struct elfhdr *interp_elf_ex, @@ -440,12 +422,11 @@ static inline int look_for_irix_interpreter(char **name, if (*name != NULL) goto out; - *name = kmalloc((epp->p_filesz + strlen(IRIX_INTERP_PREFIX)), - GFP_KERNEL); + *name = kmalloc(epp->p_filesz + strlen(IRIX_EMUL), GFP_KERNEL); if (!*name) return -ENOMEM; - strcpy(*name, IRIX_INTERP_PREFIX); + strcpy(*name, IRIX_EMUL); retval = kernel_read(bprm->file, epp->p_offset, (*name + 16), epp->p_filesz); if (retval < 0) @@ -562,7 +543,7 @@ static inline int map_interpreter(struct elf_phdr *epp, struct elfhdr *ihp, * process and the system, here we map the page and fill the * structure */ -void irix_map_prda_page (void) +static void irix_map_prda_page(void) { unsigned long v; struct prda *pp; @@ -601,14 +582,33 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs) load_addr = 0; has_interp = has_ephdr = 0; - elf_ihdr = elf_ephdr = 0; + elf_ihdr = elf_ephdr = NULL; elf_ex = *((struct elfhdr *) bprm->buf); retval = -ENOEXEC; if (verify_binary(&elf_ex, bprm)) goto out; -#ifdef DEBUG_ELF + /* + * Telling -o32 static binaries from Linux and Irix apart from each + * other is difficult. There are 2 differences to be noted for static + * binaries from the 2 operating systems: + * + * 1) Irix binaries have their .text section before their .init + * section. Linux binaries are just the opposite. + * + * 2) Irix binaries usually have <= 12 sections and Linux + * binaries have > 20. + * + * We will use Method #2 since Method #1 would require us to read in + * the section headers which is way too much overhead. This appears + * to work for everything we have ran into so far. If anyone has a + * better method to tell the binaries apart, I'm listening. + */ + if (elf_ex.e_shnum > 20) + goto out; + +#ifdef DEBUG print_elfhdr(&elf_ex); #endif @@ -623,11 +623,10 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs) } retval = kernel_read(bprm->file, elf_ex.e_phoff, (char *)elf_phdata, size); - if (retval < 0) goto out_free_ph; -#ifdef DEBUG_ELF +#ifdef DEBUG dump_phdrs(elf_phdata, elf_ex.e_phnum); #endif @@ -644,9 +643,8 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs) break; }; } -#ifdef DEBUG_ELF - printk("\n"); -#endif + + pr_debug("\n"); elf_bss = 0; elf_brk = 0; @@ -657,12 +655,19 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs) end_code = 0; end_data = 0; - retval = look_for_irix_interpreter(&elf_interpreter, - &interpreter, + /* + * If we get a return value, we change the value to be ENOEXEC + * so that we can exit gracefully and the main binary format + * search loop in 'fs/exec.c' will move onto the next handler + * which should be the normal ELF binary handler. + */ + retval = look_for_irix_interpreter(&elf_interpreter, &interpreter, &interp_elf_ex, elf_phdata, bprm, elf_ex.e_phnum); - if (retval) + if (retval) { + retval = -ENOEXEC; goto out_free_file; + } if (elf_interpreter) { retval = verify_irix_interpreter(&interp_elf_ex); @@ -746,18 +751,16 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs) * IRIX maps a page at 0x200000 which holds some system * information. Programs depend on this. */ - irix_map_prda_page (); + irix_map_prda_page(); padzero(elf_bss); -#ifdef DEBUG_ELF - printk("(start_brk) %lx\n" , (long) current->mm->start_brk); - printk("(end_code) %lx\n" , (long) current->mm->end_code); - printk("(start_code) %lx\n" , (long) current->mm->start_code); - printk("(end_data) %lx\n" , (long) current->mm->end_data); - printk("(start_stack) %lx\n" , (long) current->mm->start_stack); - printk("(brk) %lx\n" , (long) current->mm->brk); -#endif + pr_debug("(start_brk) %lx\n" , (long) current->mm->start_brk); + pr_debug("(end_code) %lx\n" , (long) current->mm->end_code); + pr_debug("(start_code) %lx\n" , (long) current->mm->start_code); + pr_debug("(end_data) %lx\n" , (long) current->mm->end_data); + pr_debug("(start_stack) %lx\n" , (long) current->mm->start_stack); + pr_debug("(brk) %lx\n" , (long) current->mm->brk); #if 0 /* XXX No fucking way dude... */ /* Why this, you ask??? Well SVr4 maps page 0 as read-only, @@ -782,8 +785,7 @@ out_free_dentry: allow_write_access(interpreter); fput(interpreter); out_free_interp: - if (elf_interpreter) - kfree(elf_interpreter); + kfree(elf_interpreter); out_free_file: out_free_ph: kfree (elf_phdata); @@ -813,7 +815,7 @@ static int load_irix_library(struct file *file) /* First of all, some simple consistency checks. */ if(elf_ex.e_type != ET_EXEC || elf_ex.e_phnum > 2 || - !irix_elf_check_arch(&elf_ex) || !file->f_op->mmap) + !file->f_op->mmap) return -ENOEXEC; /* Now read in all of the header information. */ @@ -874,35 +876,36 @@ static int load_irix_library(struct file *file) * phdrs there are in the USER_PHDRP array. We return the vaddr the * first phdr was successfully mapped to. */ -unsigned long irix_mapelf(int fd, struct elf_phdr *user_phdrp, int cnt) +unsigned long irix_mapelf(int fd, struct elf_phdr __user *user_phdrp, int cnt) { - struct elf_phdr *hp; + unsigned long type, vaddr, filesz, offset, flags; + struct elf_phdr __user *hp; struct file *filp; int i, retval; -#ifdef DEBUG_ELF - printk("irix_mapelf: fd[%d] user_phdrp[%p] cnt[%d]\n", - fd, user_phdrp, cnt); -#endif + pr_debug("irix_mapelf: fd[%d] user_phdrp[%p] cnt[%d]\n", + fd, user_phdrp, cnt); /* First get the verification out of the way. */ hp = user_phdrp; if (!access_ok(VERIFY_READ, hp, (sizeof(struct elf_phdr) * cnt))) { -#ifdef DEBUG_ELF - printk("irix_mapelf: access_ok fails!\n"); -#endif + pr_debug("irix_mapelf: bad pointer to ELF PHDR!\n"); + return -EFAULT; } -#ifdef DEBUG_ELF +#ifdef DEBUG dump_phdrs(user_phdrp, cnt); #endif - for(i = 0; i < cnt; i++, hp++) - if(hp->p_type != PT_LOAD) { + for (i = 0; i < cnt; i++, hp++) { + if (__get_user(type, &hp->p_type)) + return -EFAULT; + if (type != PT_LOAD) { printk("irix_mapelf: One section is not PT_LOAD!\n"); return -ENOEXEC; } + } filp = fget(fd); if (!filp) @@ -917,29 +920,40 @@ unsigned long irix_mapelf(int fd, struct elf_phdr *user_phdrp, int cnt) for(i = 0; i < cnt; i++, hp++) { int prot; - prot = (hp->p_flags & PF_R) ? PROT_READ : 0; - prot |= (hp->p_flags & PF_W) ? PROT_WRITE : 0; - prot |= (hp->p_flags & PF_X) ? PROT_EXEC : 0; + retval = __get_user(vaddr, &hp->p_vaddr); + retval |= __get_user(filesz, &hp->p_filesz); + retval |= __get_user(offset, &hp->p_offset); + retval |= __get_user(flags, &hp->p_flags); + if (retval) + return retval; + + prot = (flags & PF_R) ? PROT_READ : 0; + prot |= (flags & PF_W) ? PROT_WRITE : 0; + prot |= (flags & PF_X) ? PROT_EXEC : 0; + down_write(¤t->mm->mmap_sem); - retval = do_mmap(filp, (hp->p_vaddr & 0xfffff000), - (hp->p_filesz + (hp->p_vaddr & 0xfff)), + retval = do_mmap(filp, (vaddr & 0xfffff000), + (filesz + (vaddr & 0xfff)), prot, (MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE), - (hp->p_offset & 0xfffff000)); + (offset & 0xfffff000)); up_write(¤t->mm->mmap_sem); - if(retval != (hp->p_vaddr & 0xfffff000)) { + if (retval != (vaddr & 0xfffff000)) { printk("irix_mapelf: do_mmap fails with %d!\n", retval); fput(filp); return retval; } } -#ifdef DEBUG_ELF - printk("irix_mapelf: Success, returning %08lx\n", - (unsigned long) user_phdrp->p_vaddr); -#endif + pr_debug("irix_mapelf: Success, returning %08lx\n", + (unsigned long) user_phdrp->p_vaddr); + fput(filp); - return user_phdrp->p_vaddr; + + if (__get_user(vaddr, &user_phdrp->p_vaddr)) + return -EFAULT; + + return vaddr; } /* @@ -952,9 +966,9 @@ unsigned long irix_mapelf(int fd, struct elf_phdr *user_phdrp, int cnt) /* These are the only things you should do on a core-file: use only these * functions to write out all the necessary info. */ -static int dump_write(struct file *file, const void *addr, int nr) +static int dump_write(struct file *file, const void __user *addr, int nr) { - return file->f_op->write(file, addr, nr, &file->f_pos) == nr; + return file->f_op->write(file, (const char __user *) addr, nr, &file->f_pos) == nr; } static int dump_seek(struct file *file, off_t off) @@ -1073,7 +1087,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file) /* Count what's needed to dump, up to the limit of coredump size. */ segs = 0; size = 0; - for(vma = current->mm->mmap; vma != NULL; vma = vma->vm_next) { + for (vma = current->mm->mmap; vma != NULL; vma = vma->vm_next) { if (maydump(vma)) { int sz = vma->vm_end-vma->vm_start; @@ -1187,9 +1201,9 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file) len = current->mm->arg_end - current->mm->arg_start; len = len >= ELF_PRARGSZ ? ELF_PRARGSZ : len; - copy_from_user(&psinfo.pr_psargs, - (const char *)current->mm->arg_start, len); - for(i = 0; i < len; i++) + (void *) copy_from_user(&psinfo.pr_psargs, + (const char __user *)current->mm->arg_start, len); + for (i = 0; i < len; i++) if (psinfo.pr_psargs[i] == 0) psinfo.pr_psargs[i] = ' '; psinfo.pr_psargs[len] = 0; @@ -1256,8 +1270,10 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file) phdr.p_memsz = sz; offset += phdr.p_filesz; phdr.p_flags = vma->vm_flags & VM_READ ? PF_R : 0; - if (vma->vm_flags & VM_WRITE) phdr.p_flags |= PF_W; - if (vma->vm_flags & VM_EXEC) phdr.p_flags |= PF_X; + if (vma->vm_flags & VM_WRITE) + phdr.p_flags |= PF_W; + if (vma->vm_flags & VM_EXEC) + phdr.p_flags |= PF_X; phdr.p_align = PAGE_SIZE; DUMP_WRITE(&phdr, sizeof(phdr)); @@ -1283,7 +1299,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file) #ifdef DEBUG printk("elf_core_dump: writing %08lx %lx\n", addr, len); #endif - DUMP_WRITE((void *)addr, len); + DUMP_WRITE((void __user *)addr, len); } if ((off_t) file->f_pos != offset) { @@ -1299,7 +1315,7 @@ end_coredump: static int __init init_irix_binfmt(void) { - int init_inventory(void); + extern int init_inventory(void); extern asmlinkage unsigned long sys_call_table; extern asmlinkage unsigned long sys_call_table_irix5; @@ -1318,7 +1334,9 @@ static int __init init_irix_binfmt(void) static void __exit exit_irix_binfmt(void) { - /* Remove the IRIX ELF loaders. */ + /* + * Remove the Irix ELF loader. + */ unregister_binfmt(&irix_format); } diff --git a/arch/mips/kernel/irixinv.c b/arch/mips/kernel/irixinv.c index 60aa98cd1791..de8584f62311 100644 --- a/arch/mips/kernel/irixinv.c +++ b/arch/mips/kernel/irixinv.c @@ -30,10 +30,10 @@ void add_to_inventory (int class, int type, int controller, int unit, int state) inventory_items++; } -int dump_inventory_to_user (void *userbuf, int size) +int dump_inventory_to_user (void __user *userbuf, int size) { inventory_t *inv = &inventory [0]; - inventory_t *user = userbuf; + inventory_t __user *user = userbuf; int v; if (!access_ok(VERIFY_WRITE, userbuf, size)) @@ -41,7 +41,8 @@ int dump_inventory_to_user (void *userbuf, int size) for (v = 0; v < inventory_items; v++){ inv = &inventory [v]; - copy_to_user (user, inv, sizeof (inventory_t)); + if (copy_to_user (user, inv, sizeof (inventory_t))) + return -EFAULT; user++; } return inventory_items * sizeof (inventory_t); diff --git a/arch/mips/kernel/irixioctl.c b/arch/mips/kernel/irixioctl.c index 3cdc22346f4c..e2863821a3dd 100644 --- a/arch/mips/kernel/irixioctl.c +++ b/arch/mips/kernel/irixioctl.c @@ -59,7 +59,7 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg) { struct tty_struct *tp, *rtp; mm_segment_t old_fs; - int error = 0; + int i, error = 0; #ifdef DEBUG_IOCTLS printk("[%s:%d] irix_ioctl(%d, ", current->comm, current->pid, fd); @@ -74,12 +74,13 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg) case 0x0000540d: { struct termios kt; - struct irix_termios *it = (struct irix_termios *) arg; + struct irix_termios __user *it = + (struct irix_termios __user *) arg; #ifdef DEBUG_IOCTLS printk("TCGETS, %08lx) ", arg); #endif - if(!access_ok(VERIFY_WRITE, it, sizeof(*it))) { + if (!access_ok(VERIFY_WRITE, it, sizeof(*it))) { error = -EFAULT; break; } @@ -88,13 +89,14 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg) set_fs(old_fs); if (error) break; - __put_user(kt.c_iflag, &it->c_iflag); - __put_user(kt.c_oflag, &it->c_oflag); - __put_user(kt.c_cflag, &it->c_cflag); - __put_user(kt.c_lflag, &it->c_lflag); - for(error = 0; error < NCCS; error++) - __put_user(kt.c_cc[error], &it->c_cc[error]); - error = 0; + + error = __put_user(kt.c_iflag, &it->c_iflag); + error |= __put_user(kt.c_oflag, &it->c_oflag); + error |= __put_user(kt.c_cflag, &it->c_cflag); + error |= __put_user(kt.c_lflag, &it->c_lflag); + + for (i = 0; i < NCCS; i++) + error |= __put_user(kt.c_cc[i], &it->c_cc[i]); break; } @@ -112,14 +114,19 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg) old_fs = get_fs(); set_fs(get_ds()); error = sys_ioctl(fd, TCGETS, (unsigned long) &kt); set_fs(old_fs); - if(error) + if (error) + break; + + error = __get_user(kt.c_iflag, &it->c_iflag); + error |= __get_user(kt.c_oflag, &it->c_oflag); + error |= __get_user(kt.c_cflag, &it->c_cflag); + error |= __get_user(kt.c_lflag, &it->c_lflag); + + for (i = 0; i < NCCS; i++) + error |= __get_user(kt.c_cc[i], &it->c_cc[i]); + + if (error) break; - __get_user(kt.c_iflag, &it->c_iflag); - __get_user(kt.c_oflag, &it->c_oflag); - __get_user(kt.c_cflag, &it->c_cflag); - __get_user(kt.c_lflag, &it->c_lflag); - for(error = 0; error < NCCS; error++) - __get_user(kt.c_cc[error], &it->c_cc[error]); old_fs = get_fs(); set_fs(get_ds()); error = sys_ioctl(fd, TCSETS, (unsigned long) &kt); set_fs(old_fs); @@ -153,7 +160,7 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg) #ifdef DEBUG_IOCTLS printk("rtp->session=%d ", rtp->session); #endif - error = put_user(rtp->session, (unsigned long *) arg); + error = put_user(rtp->session, (unsigned long __user *) arg); break; case 0x746e: @@ -195,50 +202,32 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg) break; case 0x8004667e: -#ifdef DEBUG_IOCTLS - printk("FIONBIO, %08lx) arg=%d ", arg, *(int *)arg); -#endif error = sys_ioctl(fd, FIONBIO, arg); break; case 0x80047476: -#ifdef DEBUG_IOCTLS - printk("TIOCSPGRP, %08lx) arg=%d ", arg, *(int *)arg); -#endif error = sys_ioctl(fd, TIOCSPGRP, arg); break; case 0x8020690c: -#ifdef DEBUG_IOCTLS - printk("SIOCSIFADDR, %08lx) arg=%d ", arg, *(int *)arg); -#endif error = sys_ioctl(fd, SIOCSIFADDR, arg); break; case 0x80206910: -#ifdef DEBUG_IOCTLS - printk("SIOCSIFFLAGS, %08lx) arg=%d ", arg, *(int *)arg); -#endif error = sys_ioctl(fd, SIOCSIFFLAGS, arg); break; case 0xc0206911: -#ifdef DEBUG_IOCTLS - printk("SIOCGIFFLAGS, %08lx) arg=%d ", arg, *(int *)arg); -#endif error = sys_ioctl(fd, SIOCGIFFLAGS, arg); break; case 0xc020691b: -#ifdef DEBUG_IOCTLS - printk("SIOCGIFMETRIC, %08lx) arg=%d ", arg, *(int *)arg); -#endif error = sys_ioctl(fd, SIOCGIFMETRIC, arg); break; default: { #ifdef DEBUG_MISSING_IOCTL - char *msg = "Unimplemented IOCTL cmd tell linux@engr.sgi.com\n"; + char *msg = "Unimplemented IOCTL cmd tell linux-mips@linux-mips.org\n"; #ifdef DEBUG_IOCTLS printk("UNIMP_IOCTL, %08lx)\n", arg); diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c index eff89322ba50..908e63684208 100644 --- a/arch/mips/kernel/irixsig.c +++ b/arch/mips/kernel/irixsig.c @@ -76,36 +76,39 @@ static inline void dump_irix5_sigctx(struct sigctx_irix5 *c) } #endif -static void setup_irix_frame(struct k_sigaction *ka, struct pt_regs *regs, - int signr, sigset_t *oldmask) +static int setup_irix_frame(struct k_sigaction *ka, struct pt_regs *regs, + int signr, sigset_t *oldmask) { + struct sigctx_irix5 __user *ctx; unsigned long sp; - struct sigctx_irix5 *ctx; - int i; + int error, i; sp = regs->regs[29]; sp -= sizeof(struct sigctx_irix5); sp &= ~(0xf); - ctx = (struct sigctx_irix5 *) sp; + ctx = (struct sigctx_irix5 __user *) sp; if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx))) goto segv_and_exit; - __put_user(0, &ctx->weird_fpu_thing); - __put_user(~(0x00000001), &ctx->rmask); - __put_user(0, &ctx->regs[0]); + error = __put_user(0, &ctx->weird_fpu_thing); + error |= __put_user(~(0x00000001), &ctx->rmask); + error |= __put_user(0, &ctx->regs[0]); for(i = 1; i < 32; i++) - __put_user((u64) regs->regs[i], &ctx->regs[i]); + error |= __put_user((u64) regs->regs[i], &ctx->regs[i]); + + error |= __put_user((u64) regs->hi, &ctx->hi); + error |= __put_user((u64) regs->lo, &ctx->lo); + error |= __put_user((u64) regs->cp0_epc, &ctx->pc); + error |= __put_user(!!used_math(), &ctx->usedfp); + error |= __put_user((u64) regs->cp0_cause, &ctx->cp0_cause); + error |= __put_user((u64) regs->cp0_badvaddr, &ctx->cp0_badvaddr); - __put_user((u64) regs->hi, &ctx->hi); - __put_user((u64) regs->lo, &ctx->lo); - __put_user((u64) regs->cp0_epc, &ctx->pc); - __put_user(!!used_math(), &ctx->usedfp); - __put_user((u64) regs->cp0_cause, &ctx->cp0_cause); - __put_user((u64) regs->cp0_badvaddr, &ctx->cp0_badvaddr); + error |= __put_user(0, &ctx->sstk_flags); /* XXX sigstack unimp... todo... */ - __put_user(0, &ctx->sstk_flags); /* XXX sigstack unimp... todo... */ + error |= __copy_to_user(&ctx->sigset, oldmask, sizeof(irix_sigset_t)) ? -EFAULT : 0; - __copy_to_user(&ctx->sigset, oldmask, sizeof(irix_sigset_t)); + if (error) + goto segv_and_exit; #ifdef DEBUG_SIG dump_irix5_sigctx(ctx); @@ -117,13 +120,14 @@ static void setup_irix_frame(struct k_sigaction *ka, struct pt_regs *regs, regs->regs[7] = (unsigned long) ka->sa.sa_handler; regs->regs[25] = regs->cp0_epc = (unsigned long) ka->sa_restorer; - return; + return 1; segv_and_exit: force_sigsegv(signr, current); + return 0; } -static void inline +static int inline setup_irix_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *oldmask, siginfo_t *info) { @@ -131,9 +135,11 @@ setup_irix_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, do_exit(SIGSEGV); } -static inline void handle_signal(unsigned long sig, siginfo_t *info, +static inline int handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka, sigset_t *oldset, struct pt_regs * regs) { + int ret; + switch(regs->regs[0]) { case ERESTARTNOHAND: regs->regs[2] = EINTR; @@ -151,9 +157,9 @@ static inline void handle_signal(unsigned long sig, siginfo_t *info, regs->regs[0] = 0; /* Don't deal with this again. */ if (ka->sa.sa_flags & SA_SIGINFO) - setup_irix_rt_frame(ka, regs, sig, oldset, info); + ret = setup_irix_rt_frame(ka, regs, sig, oldset, info); else - setup_irix_frame(ka, regs, sig, oldset); + ret = setup_irix_frame(ka, regs, sig, oldset); spin_lock_irq(¤t->sighand->siglock); sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); @@ -161,6 +167,8 @@ static inline void handle_signal(unsigned long sig, siginfo_t *info, sigaddset(¤t->blocked,sig); recalc_sigpending(); spin_unlock_irq(¤t->sighand->siglock); + + return ret; } asmlinkage int do_irix_signal(sigset_t *oldset, struct pt_regs *regs) @@ -184,10 +192,8 @@ asmlinkage int do_irix_signal(sigset_t *oldset, struct pt_regs *regs) oldset = ¤t->blocked; signr = get_signal_to_deliver(&info, &ka, regs, NULL); - if (signr > 0) { - handle_signal(signr, &info, &ka, oldset, regs); - return 1; - } + if (signr > 0) + return handle_signal(signr, &info, &ka, oldset, regs); no_signal: /* @@ -208,10 +214,11 @@ no_signal: asmlinkage void irix_sigreturn(struct pt_regs *regs) { - struct sigctx_irix5 *context, *magic; + struct sigctx_irix5 __user *context, *magic; unsigned long umask, mask; u64 *fregs; - int sig, i, base = 0; + u32 usedfp; + int error, sig, i, base = 0; sigset_t blocked; /* Always make any pending restarted system calls return -EINTR */ @@ -220,8 +227,8 @@ irix_sigreturn(struct pt_regs *regs) if (regs->regs[2] == 1000) base = 1; - context = (struct sigctx_irix5 *) regs->regs[base + 4]; - magic = (struct sigctx_irix5 *) regs->regs[base + 5]; + context = (struct sigctx_irix5 __user *) regs->regs[base + 4]; + magic = (struct sigctx_irix5 __user *) regs->regs[base + 5]; sig = (int) regs->regs[base + 6]; #ifdef DEBUG_SIG printk("[%s:%d] IRIX sigreturn(scp[%p],ucp[%p],sig[%d])\n", @@ -236,25 +243,31 @@ irix_sigreturn(struct pt_regs *regs) dump_irix5_sigctx(context); #endif - __get_user(regs->cp0_epc, &context->pc); - umask = context->rmask; mask = 2; + error = __get_user(regs->cp0_epc, &context->pc); + error |= __get_user(umask, &context->rmask); + + mask = 2; for (i = 1; i < 32; i++, mask <<= 1) { - if(umask & mask) - __get_user(regs->regs[i], &context->regs[i]); + if (umask & mask) + error |= __get_user(regs->regs[i], &context->regs[i]); } - __get_user(regs->hi, &context->hi); - __get_user(regs->lo, &context->lo); + error |= __get_user(regs->hi, &context->hi); + error |= __get_user(regs->lo, &context->lo); - if ((umask & 1) && context->usedfp) { + error |= __get_user(usedfp, &context->usedfp); + if ((umask & 1) && usedfp) { fregs = (u64 *) ¤t->thread.fpu; + for(i = 0; i < 32; i++) - fregs[i] = (u64) context->fpregs[i]; - __get_user(current->thread.fpu.hard.fcr31, &context->fpcsr); + error |= __get_user(fregs[i], &context->fpregs[i]); + error |= __get_user(current->thread.fpu.hard.fcr31, &context->fpcsr); } /* XXX do sigstack crapola here... XXX */ - if (__copy_from_user(&blocked, &context->sigset, sizeof(blocked))) + error |= __copy_from_user(&blocked, &context->sigset, sizeof(blocked)) ? -EFAULT : 0; + + if (error) goto badframe; sigdelsetmask(&blocked, ~_BLOCKABLE); @@ -296,8 +309,8 @@ static inline void dump_sigact_irix5(struct sigact_irix5 *p) #endif asmlinkage int -irix_sigaction(int sig, const struct sigaction *act, - struct sigaction *oact, void *trampoline) +irix_sigaction(int sig, const struct sigaction __user *act, + struct sigaction __user *oact, void __user *trampoline) { struct k_sigaction new_ka, old_ka; int ret; @@ -311,12 +324,16 @@ irix_sigaction(int sig, const struct sigaction *act, #endif if (act) { sigset_t mask; - if (!access_ok(VERIFY_READ, act, sizeof(*act)) || - __get_user(new_ka.sa.sa_handler, &act->sa_handler) || - __get_user(new_ka.sa.sa_flags, &act->sa_flags)) + int err; + + if (!access_ok(VERIFY_READ, act, sizeof(*act))) return -EFAULT; + err = __get_user(new_ka.sa.sa_handler, &act->sa_handler); + err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags); - __copy_from_user(&mask, &act->sa_mask, sizeof(sigset_t)); + err |= __copy_from_user(&mask, &act->sa_mask, sizeof(sigset_t)) ? -EFAULT : 0; + if (err) + return err; /* * Hmmm... methinks IRIX libc always passes a valid trampoline @@ -330,30 +347,37 @@ irix_sigaction(int sig, const struct sigaction *act, ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); if (!ret && oact) { - if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) || - __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || - __put_user(old_ka.sa.sa_flags, &oact->sa_flags)) + int err; + + if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact))) + return -EFAULT; + + err = __put_user(old_ka.sa.sa_handler, &oact->sa_handler); + err |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags); + err |= __copy_to_user(&oact->sa_mask, &old_ka.sa.sa_mask, + sizeof(sigset_t)) ? -EFAULT : 0; + if (err) return -EFAULT; - __copy_to_user(&old_ka.sa.sa_mask, &oact->sa_mask, - sizeof(sigset_t)); } return ret; } -asmlinkage int irix_sigpending(irix_sigset_t *set) +asmlinkage int irix_sigpending(irix_sigset_t __user *set) { return do_sigpending(set, sizeof(*set)); } -asmlinkage int irix_sigprocmask(int how, irix_sigset_t *new, irix_sigset_t *old) +asmlinkage int irix_sigprocmask(int how, irix_sigset_t __user *new, + irix_sigset_t __user *old) { sigset_t oldbits, newbits; if (new) { if (!access_ok(VERIFY_READ, new, sizeof(*new))) return -EFAULT; - __copy_from_user(&newbits, new, sizeof(unsigned long)*4); + if (__copy_from_user(&newbits, new, sizeof(unsigned long)*4)) + return -EFAULT; sigdelsetmask(&newbits, ~_BLOCKABLE); spin_lock_irq(¤t->sighand->siglock); @@ -381,20 +405,19 @@ asmlinkage int irix_sigprocmask(int how, irix_sigset_t *new, irix_sigset_t *old) recalc_sigpending(); spin_unlock_irq(¤t->sighand->siglock); } - if(old) { - if (!access_ok(VERIFY_WRITE, old, sizeof(*old))) - return -EFAULT; - __copy_to_user(old, ¤t->blocked, sizeof(unsigned long)*4); - } + if (old) + return copy_to_user(old, ¤t->blocked, + sizeof(unsigned long)*4) ? -EFAULT : 0; return 0; } asmlinkage int irix_sigsuspend(struct pt_regs *regs) { - sigset_t *uset, saveset, newset; + sigset_t saveset, newset; + sigset_t __user *uset; - uset = (sigset_t *) regs->regs[4]; + uset = (sigset_t __user *) regs->regs[4]; if (copy_from_user(&newset, uset, sizeof(sigset_t))) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); @@ -440,12 +463,13 @@ struct irix5_siginfo { } stuff; }; -asmlinkage int irix_sigpoll_sys(unsigned long *set, struct irix5_siginfo *info, - struct timespec *tp) +asmlinkage int irix_sigpoll_sys(unsigned long __user *set, + struct irix5_siginfo __user *info, struct timespec __user *tp) { long expire = MAX_SCHEDULE_TIMEOUT; sigset_t kset; int i, sig, error, timeo = 0; + struct timespec ktp; #ifdef DEBUG_SIG printk("[%s:%d] irix_sigpoll_sys(%p,%p,%p)\n", @@ -456,14 +480,8 @@ asmlinkage int irix_sigpoll_sys(unsigned long *set, struct irix5_siginfo *info, if (!set) return -EINVAL; - if (!access_ok(VERIFY_READ, set, sizeof(kset))) { - error = -EFAULT; - goto out; - } - - __copy_from_user(&kset, set, sizeof(set)); - if (error) - goto out; + if (copy_from_user(&kset, set, sizeof(set))) + return -EFAULT; if (info && clear_user(info, sizeof(*info))) { error = -EFAULT; @@ -471,19 +489,21 @@ asmlinkage int irix_sigpoll_sys(unsigned long *set, struct irix5_siginfo *info, } if (tp) { - if (!access_ok(VERIFY_READ, tp, sizeof(*tp))) + if (copy_from_user(&ktp, tp, sizeof(*tp))) return -EFAULT; - if (!tp->tv_sec && !tp->tv_nsec) { - error = -EINVAL; - goto out; - } - expire = timespec_to_jiffies(tp) + (tp->tv_sec||tp->tv_nsec); + + if (!ktp.tv_sec && !ktp.tv_nsec) + return -EINVAL; + + expire = timespec_to_jiffies(&ktp) + + (ktp.tv_sec || ktp.tv_nsec); } while(1) { long tmp = 0; - expire = schedule_timeout_interruptible(expire); + current->state = TASK_INTERRUPTIBLE; + expire = schedule_timeout(expire); for (i=0; i<=4; i++) tmp |= (current->pending.signal.sig[i] & kset.sig[i]); @@ -500,15 +520,14 @@ asmlinkage int irix_sigpoll_sys(unsigned long *set, struct irix5_siginfo *info, if (timeo) return -EAGAIN; - for(sig = 1; i <= 65 /* IRIX_NSIG */; sig++) { + for (sig = 1; i <= 65 /* IRIX_NSIG */; sig++) { if (sigismember (&kset, sig)) continue; if (sigismember (¤t->pending.signal, sig)) { /* XXX need more than this... */ if (info) - info->sig = sig; - error = 0; - goto out; + return copy_to_user(&info->sig, &sig, sizeof(sig)); + return 0; } } @@ -534,8 +553,9 @@ extern int getrusage(struct task_struct *, int, struct rusage __user *); #define W_MASK (W_EXITED | W_TRAPPED | W_STOPPED | W_CONT | W_NOHANG) -asmlinkage int irix_waitsys(int type, int pid, struct irix5_siginfo *info, - int options, struct rusage *ru) +asmlinkage int irix_waitsys(int type, int pid, + struct irix5_siginfo __user *info, int options, + struct rusage __user *ru) { int flag, retval; DECLARE_WAITQUEUE(wait, current); @@ -543,28 +563,22 @@ asmlinkage int irix_waitsys(int type, int pid, struct irix5_siginfo *info, struct task_struct *p; struct list_head *_p; - if (!info) { - retval = -EINVAL; - goto out; - } - if (!access_ok(VERIFY_WRITE, info, sizeof(*info))) { - retval = -EFAULT; - goto out; - } - if (ru) { - if (!access_ok(VERIFY_WRITE, ru, sizeof(*ru))) { - retval = -EFAULT; - goto out; - } - } - if (options & ~(W_MASK)) { - retval = -EINVAL; - goto out; - } - if (type != IRIX_P_PID && type != IRIX_P_PGID && type != IRIX_P_ALL) { - retval = -EINVAL; - goto out; - } + if (!info) + return -EINVAL; + + if (!access_ok(VERIFY_WRITE, info, sizeof(*info))) + return -EFAULT; + + if (ru) + if (!access_ok(VERIFY_WRITE, ru, sizeof(*ru))) + return -EFAULT; + + if (options & ~W_MASK) + return -EINVAL; + + if (type != IRIX_P_PID && type != IRIX_P_PGID && type != IRIX_P_ALL) + return -EINVAL; + add_wait_queue(¤t->signal->wait_chldexit, &wait); repeat: flag = 0; @@ -595,18 +609,20 @@ repeat: add_parent(p, p->parent); write_unlock_irq(&tasklist_lock); retval = ru ? getrusage(p, RUSAGE_BOTH, ru) : 0; - if (!retval && ru) { - retval |= __put_user(SIGCHLD, &info->sig); - retval |= __put_user(0, &info->code); - retval |= __put_user(p->pid, &info->stuff.procinfo.pid); - retval |= __put_user((p->exit_code >> 8) & 0xff, - &info->stuff.procinfo.procdata.child.status); - retval |= __put_user(p->utime, &info->stuff.procinfo.procdata.child.utime); - retval |= __put_user(p->stime, &info->stuff.procinfo.procdata.child.stime); - } - if (!retval) { - p->exit_code = 0; - } + if (retval) + goto end_waitsys; + + retval = __put_user(SIGCHLD, &info->sig); + retval |= __put_user(0, &info->code); + retval |= __put_user(p->pid, &info->stuff.procinfo.pid); + retval |= __put_user((p->exit_code >> 8) & 0xff, + &info->stuff.procinfo.procdata.child.status); + retval |= __put_user(p->utime, &info->stuff.procinfo.procdata.child.utime); + retval |= __put_user(p->stime, &info->stuff.procinfo.procdata.child.stime); + if (retval) + goto end_waitsys; + + p->exit_code = 0; goto end_waitsys; case EXIT_ZOMBIE: @@ -614,16 +630,18 @@ repeat: current->signal->cstime += p->stime + p->signal->cstime; if (ru != NULL) getrusage(p, RUSAGE_BOTH, ru); - __put_user(SIGCHLD, &info->sig); - __put_user(1, &info->code); /* CLD_EXITED */ - __put_user(p->pid, &info->stuff.procinfo.pid); - __put_user((p->exit_code >> 8) & 0xff, + retval = __put_user(SIGCHLD, &info->sig); + retval |= __put_user(1, &info->code); /* CLD_EXITED */ + retval |= __put_user(p->pid, &info->stuff.procinfo.pid); + retval |= __put_user((p->exit_code >> 8) & 0xff, &info->stuff.procinfo.procdata.child.status); - __put_user(p->utime, + retval |= __put_user(p->utime, &info->stuff.procinfo.procdata.child.utime); - __put_user(p->stime, + retval |= __put_user(p->stime, &info->stuff.procinfo.procdata.child.stime); - retval = 0; + if (retval) + return retval; + if (p->real_parent != p->parent) { write_lock_irq(&tasklist_lock); remove_parent(p); @@ -656,7 +674,6 @@ end_waitsys: current->state = TASK_RUNNING; remove_wait_queue(¤t->signal->wait_chldexit, &wait); -out: return retval; } @@ -675,39 +692,39 @@ struct irix5_context { asmlinkage int irix_getcontext(struct pt_regs *regs) { - int i, base = 0; - struct irix5_context *ctx; + int error, i, base = 0; + struct irix5_context __user *ctx; unsigned long flags; if (regs->regs[2] == 1000) base = 1; - ctx = (struct irix5_context *) regs->regs[base + 4]; + ctx = (struct irix5_context __user *) regs->regs[base + 4]; #ifdef DEBUG_SIG printk("[%s:%d] irix_getcontext(%p)\n", current->comm, current->pid, ctx); #endif - if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx))) + if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx))); return -EFAULT; - __put_user(current->thread.irix_oldctx, &ctx->link); + error = __put_user(current->thread.irix_oldctx, &ctx->link); - __copy_to_user(&ctx->sigmask, ¤t->blocked, sizeof(irix_sigset_t)); + error |= __copy_to_user(&ctx->sigmask, ¤t->blocked, sizeof(irix_sigset_t)) ? -EFAULT : 0; /* XXX Do sigstack stuff someday... */ - __put_user(0, &ctx->stack.sp); - __put_user(0, &ctx->stack.size); - __put_user(0, &ctx->stack.flags); + error |= __put_user(0, &ctx->stack.sp); + error |= __put_user(0, &ctx->stack.size); + error |= __put_user(0, &ctx->stack.flags); - __put_user(0, &ctx->weird_graphics_thing); - __put_user(0, &ctx->regs[0]); + error |= __put_user(0, &ctx->weird_graphics_thing); + error |= __put_user(0, &ctx->regs[0]); for (i = 1; i < 32; i++) - __put_user(regs->regs[i], &ctx->regs[i]); - __put_user(regs->lo, &ctx->regs[32]); - __put_user(regs->hi, &ctx->regs[33]); - __put_user(regs->cp0_cause, &ctx->regs[34]); - __put_user(regs->cp0_epc, &ctx->regs[35]); + error |= __put_user(regs->regs[i], &ctx->regs[i]); + error |= __put_user(regs->lo, &ctx->regs[32]); + error |= __put_user(regs->hi, &ctx->regs[33]); + error |= __put_user(regs->cp0_cause, &ctx->regs[34]); + error |= __put_user(regs->cp0_epc, &ctx->regs[35]); flags = 0x0f; if (!used_math()) { @@ -716,119 +733,124 @@ asmlinkage int irix_getcontext(struct pt_regs *regs) /* XXX wheee... */ printk("Wheee, no code for saving IRIX FPU context yet.\n"); } - __put_user(flags, &ctx->flags); + error |= __put_user(flags, &ctx->flags); - return 0; + return error; } -asmlinkage unsigned long irix_setcontext(struct pt_regs *regs) +asmlinkage void irix_setcontext(struct pt_regs *regs) { - int error, base = 0; - struct irix5_context *ctx; + struct irix5_context __user *ctx; + int err, base = 0; + u32 flags; - if(regs->regs[2] == 1000) + if (regs->regs[2] == 1000) base = 1; - ctx = (struct irix5_context *) regs->regs[base + 4]; + ctx = (struct irix5_context __user *) regs->regs[base + 4]; #ifdef DEBUG_SIG printk("[%s:%d] irix_setcontext(%p)\n", current->comm, current->pid, ctx); #endif - if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx))) { - error = -EFAULT; - goto out; - } + if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx))) + goto segv_and_exit; - if (ctx->flags & 0x02) { + err = __get_user(flags, &ctx->flags); + if (flags & 0x02) { /* XXX sigstack garbage, todo... */ printk("Wheee, cannot do sigstack stuff in setcontext\n"); } - if (ctx->flags & 0x04) { + if (flags & 0x04) { int i; /* XXX extra control block stuff... todo... */ - for(i = 1; i < 32; i++) - regs->regs[i] = ctx->regs[i]; - regs->lo = ctx->regs[32]; - regs->hi = ctx->regs[33]; - regs->cp0_epc = ctx->regs[35]; + for (i = 1; i < 32; i++) + err |= __get_user(regs->regs[i], &ctx->regs[i]); + err |= __get_user(regs->lo, &ctx->regs[32]); + err |= __get_user(regs->hi, &ctx->regs[33]); + err |= __get_user(regs->cp0_epc, &ctx->regs[35]); } - if (ctx->flags & 0x08) { + if (flags & 0x08) /* XXX fpu context, blah... */ - printk("Wheee, cannot restore FPU context yet...\n"); - } - current->thread.irix_oldctx = ctx->link; - error = regs->regs[2]; + printk(KERN_ERR "Wheee, cannot restore FPU context yet...\n"); -out: - return error; + err |= __get_user(current->thread.irix_oldctx, &ctx->link); + if (err) + goto segv_and_exit; + + /* + * Don't let your children do this ... + */ + if (current_thread_info()->flags & TIF_SYSCALL_TRACE) + do_syscall_trace(regs, 1); + __asm__ __volatile__( + "move\t$29,%0\n\t" + "j\tsyscall_exit" + :/* no outputs */ + :"r" (®s)); + /* Unreached */ + +segv_and_exit: + force_sigsegv(SIGSEGV, current); } -struct irix_sigstack { unsigned long sp; int status; }; +struct irix_sigstack { + unsigned long sp; + int status; +}; -asmlinkage int irix_sigstack(struct irix_sigstack *new, struct irix_sigstack *old) +asmlinkage int irix_sigstack(struct irix_sigstack __user *new, + struct irix_sigstack __user *old) { - int error = -EFAULT; - #ifdef DEBUG_SIG printk("[%s:%d] irix_sigstack(%p,%p)\n", current->comm, current->pid, new, old); #endif - if(new) { + if (new) { if (!access_ok(VERIFY_READ, new, sizeof(*new))) - goto out; + return -EFAULT; } - if(old) { + if (old) { if (!access_ok(VERIFY_WRITE, old, sizeof(*old))) - goto out; + return -EFAULT; } - error = 0; -out: - return error; + return 0; } struct irix_sigaltstack { unsigned long sp; int size; int status; }; -asmlinkage int irix_sigaltstack(struct irix_sigaltstack *new, - struct irix_sigaltstack *old) +asmlinkage int irix_sigaltstack(struct irix_sigaltstack __user *new, + struct irix_sigaltstack __user *old) { - int error = -EFAULT; - #ifdef DEBUG_SIG printk("[%s:%d] irix_sigaltstack(%p,%p)\n", current->comm, current->pid, new, old); #endif - if (new) { + if (new) if (!access_ok(VERIFY_READ, new, sizeof(*new))) - goto out; - } + return -EFAULT; if (old) { if (!access_ok(VERIFY_WRITE, old, sizeof(*old))) - goto out; + return -EFAULT; } - error = 0; - -out: - error = 0; - return error; + return 0; } struct irix_procset { int cmd, ltype, lid, rtype, rid; }; -asmlinkage int irix_sigsendset(struct irix_procset *pset, int sig) +asmlinkage int irix_sigsendset(struct irix_procset __user *pset, int sig) { if (!access_ok(VERIFY_READ, pset, sizeof(*pset))) return -EFAULT; - #ifdef DEBUG_SIG printk("[%s:%d] irix_sigsendset([%d,%d,%d,%d,%d],%d)\n", current->comm, current->pid, diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 43c00ac0b88d..3f653c7cfbf3 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c @@ -74,7 +74,7 @@ static void disable_msc_irq(unsigned int irq) static void level_mask_and_ack_msc_irq(unsigned int irq) { mask_msc_irq(irq); - if (!cpu_has_ei) + if (!cpu_has_veic) MSCIC_WRITE(MSC01_IC_EOI, 0); } @@ -84,7 +84,7 @@ static void level_mask_and_ack_msc_irq(unsigned int irq) static void edge_mask_and_ack_msc_irq(unsigned int irq) { mask_msc_irq(irq); - if (!cpu_has_ei) + if (!cpu_has_veic) MSCIC_WRITE(MSC01_IC_EOI, 0); else { u32 r; @@ -129,25 +129,23 @@ msc_bind_eic_interrupt (unsigned int irq, unsigned int set) #define shutdown_msc_irq disable_msc_irq struct hw_interrupt_type msc_levelirq_type = { - "SOC-it-Level", - startup_msc_irq, - shutdown_msc_irq, - enable_msc_irq, - disable_msc_irq, - level_mask_and_ack_msc_irq, - end_msc_irq, - NULL + .typename = "SOC-it-Level", + .startup = startup_msc_irq, + .shutdown = shutdown_msc_irq, + .enable = enable_msc_irq, + .disable = disable_msc_irq, + .ack = level_mask_and_ack_msc_irq, + .end = end_msc_irq, }; struct hw_interrupt_type msc_edgeirq_type = { - "SOC-it-Edge", - startup_msc_irq, - shutdown_msc_irq, - enable_msc_irq, - disable_msc_irq, - edge_mask_and_ack_msc_irq, - end_msc_irq, - NULL + .typename = "SOC-it-Edge", + .startup =startup_msc_irq, + .shutdown = shutdown_msc_irq, + .enable = enable_msc_irq, + .disable = disable_msc_irq, + .ack = edge_mask_and_ack_msc_irq, + .end = end_msc_irq, }; @@ -168,14 +166,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) switch (imp->im_type) { case MSC01_IRQ_EDGE: irq_desc[base+n].handler = &msc_edgeirq_type; - if (cpu_has_ei) + if (cpu_has_veic) MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); else MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); break; case MSC01_IRQ_LEVEL: irq_desc[base+n].handler = &msc_levelirq_type; - if (cpu_has_ei) + if (cpu_has_veic) MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); else MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl); diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c index 088bbbc869e6..0ac067f45cf5 100644 --- a/arch/mips/kernel/irq-mv6434x.c +++ b/arch/mips/kernel/irq-mv6434x.c @@ -135,14 +135,13 @@ void ll_mv64340_irq(struct pt_regs *regs) #define shutdown_mv64340_irq disable_mv64340_irq struct hw_interrupt_type mv64340_irq_type = { - "MV-64340", - startup_mv64340_irq, - shutdown_mv64340_irq, - enable_mv64340_irq, - disable_mv64340_irq, - mask_and_ack_mv64340_irq, - end_mv64340_irq, - NULL + .typename = "MV-64340", + .startup = startup_mv64340_irq, + .shutdown = shutdown_mv64340_irq, + .enable = enable_mv64340_irq, + .disable = disable_mv64340_irq, + .ack = mask_and_ack_mv64340_irq, + .end = end_mv64340_irq, }; void __init mv64340_irq_init(unsigned int base) diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c index f5d779fd0355..0b130c5ac5d9 100644 --- a/arch/mips/kernel/irq-rm7000.c +++ b/arch/mips/kernel/irq-rm7000.c @@ -72,13 +72,13 @@ static void rm7k_cpu_irq_end(unsigned int irq) } static hw_irq_controller rm7k_irq_controller = { - "RM7000", - rm7k_cpu_irq_startup, - rm7k_cpu_irq_shutdown, - rm7k_cpu_irq_enable, - rm7k_cpu_irq_disable, - rm7k_cpu_irq_ack, - rm7k_cpu_irq_end, + .typename = "RM7000", + .startup = rm7k_cpu_irq_startup, + .shutdown = rm7k_cpu_irq_shutdown, + .enable = rm7k_cpu_irq_enable, + .disable = rm7k_cpu_irq_disable, + .ack = rm7k_cpu_irq_ack, + .end = rm7k_cpu_irq_end, }; void __init rm7k_cpu_irq_init(int base) diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c index bdd130296256..9b5f20c32acb 100644 --- a/arch/mips/kernel/irq-rm9000.c +++ b/arch/mips/kernel/irq-rm9000.c @@ -106,23 +106,23 @@ static void rm9k_cpu_irq_end(unsigned int irq) } static hw_irq_controller rm9k_irq_controller = { - "RM9000", - rm9k_cpu_irq_startup, - rm9k_cpu_irq_shutdown, - rm9k_cpu_irq_enable, - rm9k_cpu_irq_disable, - rm9k_cpu_irq_ack, - rm9k_cpu_irq_end, + .typename = "RM9000", + .startup = rm9k_cpu_irq_startup, + .shutdown = rm9k_cpu_irq_shutdown, + .enable = rm9k_cpu_irq_enable, + .disable = rm9k_cpu_irq_disable, + .ack = rm9k_cpu_irq_ack, + .end = rm9k_cpu_irq_end, }; static hw_irq_controller rm9k_perfcounter_irq = { - "RM9000", - rm9k_perfcounter_irq_startup, - rm9k_perfcounter_irq_shutdown, - rm9k_cpu_irq_enable, - rm9k_cpu_irq_disable, - rm9k_cpu_irq_ack, - rm9k_cpu_irq_end, + .typename = "RM9000", + .startup = rm9k_perfcounter_irq_startup, + .shutdown = rm9k_perfcounter_irq_shutdown, + .enable = rm9k_cpu_irq_enable, + .disable = rm9k_cpu_irq_disable, + .ack = rm9k_cpu_irq_ack, + .end = rm9k_cpu_irq_end, }; unsigned int rm9000_perfcount_irq; diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 2b936cf1ef70..5db67e31ec1a 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -3,6 +3,8 @@ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net * * Copyright (C) 2001 Ralf Baechle + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * Author: Maciej W. Rozycki <macro@mips.com> * * This file define the irq handler for MIPS CPU interrupts. * @@ -31,19 +33,21 @@ #include <asm/irq_cpu.h> #include <asm/mipsregs.h> +#include <asm/mipsmtregs.h> #include <asm/system.h> static int mips_cpu_irq_base; static inline void unmask_mips_irq(unsigned int irq) { - clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); set_c0_status(0x100 << (irq - mips_cpu_irq_base)); + irq_enable_hazard(); } static inline void mask_mips_irq(unsigned int irq) { clear_c0_status(0x100 << (irq - mips_cpu_irq_base)); + irq_disable_hazard(); } static inline void mips_cpu_irq_enable(unsigned int irq) @@ -52,6 +56,7 @@ static inline void mips_cpu_irq_enable(unsigned int irq) local_irq_save(flags); unmask_mips_irq(irq); + back_to_back_c0_hazard(); local_irq_restore(flags); } @@ -61,6 +66,7 @@ static void mips_cpu_irq_disable(unsigned int irq) local_irq_save(flags); mask_mips_irq(irq); + back_to_back_c0_hazard(); local_irq_restore(flags); } @@ -71,7 +77,7 @@ static unsigned int mips_cpu_irq_startup(unsigned int irq) return 0; } -#define mips_cpu_irq_shutdown mips_cpu_irq_disable +#define mips_cpu_irq_shutdown mips_cpu_irq_disable /* * While we ack the interrupt interrupts are disabled and thus we don't need @@ -79,9 +85,6 @@ static unsigned int mips_cpu_irq_startup(unsigned int irq) */ static void mips_cpu_irq_ack(unsigned int irq) { - /* Only necessary for soft interrupts */ - clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); - mask_mips_irq(irq); } @@ -92,22 +95,82 @@ static void mips_cpu_irq_end(unsigned int irq) } static hw_irq_controller mips_cpu_irq_controller = { - "MIPS", - mips_cpu_irq_startup, - mips_cpu_irq_shutdown, - mips_cpu_irq_enable, - mips_cpu_irq_disable, - mips_cpu_irq_ack, - mips_cpu_irq_end, - NULL /* no affinity stuff for UP */ + .typename = "MIPS", + .startup = mips_cpu_irq_startup, + .shutdown = mips_cpu_irq_shutdown, + .enable = mips_cpu_irq_enable, + .disable = mips_cpu_irq_disable, + .ack = mips_cpu_irq_ack, + .end = mips_cpu_irq_end, }; +/* + * Basically the same as above but taking care of all the MT stuff + */ + +#define unmask_mips_mt_irq unmask_mips_irq +#define mask_mips_mt_irq mask_mips_irq +#define mips_mt_cpu_irq_enable mips_cpu_irq_enable +#define mips_mt_cpu_irq_disable mips_cpu_irq_disable + +static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) +{ + unsigned int vpflags = dvpe(); + + clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); + evpe(vpflags); + mips_mt_cpu_irq_enable(irq); + + return 0; +} + +#define mips_mt_cpu_irq_shutdown mips_mt_cpu_irq_disable + +/* + * While we ack the interrupt interrupts are disabled and thus we don't need + * to deal with concurrency issues. Same for mips_cpu_irq_end. + */ +static void mips_mt_cpu_irq_ack(unsigned int irq) +{ + unsigned int vpflags = dvpe(); + clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); + evpe(vpflags); + mask_mips_mt_irq(irq); +} + +#define mips_mt_cpu_irq_end mips_cpu_irq_end + +static hw_irq_controller mips_mt_cpu_irq_controller = { + .typename = "MIPS", + .startup = mips_mt_cpu_irq_startup, + .shutdown = mips_mt_cpu_irq_shutdown, + .enable = mips_mt_cpu_irq_enable, + .disable = mips_mt_cpu_irq_disable, + .ack = mips_mt_cpu_irq_ack, + .end = mips_mt_cpu_irq_end, +}; void __init mips_cpu_irq_init(int irq_base) { int i; - for (i = irq_base; i < irq_base + 8; i++) { + /* Mask interrupts. */ + clear_c0_status(ST0_IM); + clear_c0_cause(CAUSEF_IP); + + /* + * Only MT is using the software interrupts currently, so we just + * leave them uninitialized for other processors. + */ + if (cpu_has_mipsmt) + for (i = irq_base; i < irq_base + 2; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 1; + irq_desc[i].handler = &mips_mt_cpu_irq_controller; + } + + for (i = irq_base + 2; i < irq_base + 8; i++) { irq_desc[i].status = IRQ_DISABLED; irq_desc[i].action = NULL; irq_desc[i].depth = 1; diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index ece4564919d8..330cf84d21fe 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -215,81 +215,32 @@ sys32_readdir(unsigned int fd, void * dirent32, unsigned int count) return(n); } -struct rusage32 { - struct compat_timeval ru_utime; - struct compat_timeval ru_stime; - int ru_maxrss; - int ru_ixrss; - int ru_idrss; - int ru_isrss; - int ru_minflt; - int ru_majflt; - int ru_nswap; - int ru_inblock; - int ru_oublock; - int ru_msgsnd; - int ru_msgrcv; - int ru_nsignals; - int ru_nvcsw; - int ru_nivcsw; -}; - -static int -put_rusage (struct rusage32 *ru, struct rusage *r) +asmlinkage int +sys32_waitpid(compat_pid_t pid, unsigned int *stat_addr, int options) { - int err; - - if (!access_ok(VERIFY_WRITE, ru, sizeof *ru)) - return -EFAULT; - - err = __put_user (r->ru_utime.tv_sec, &ru->ru_utime.tv_sec); - err |= __put_user (r->ru_utime.tv_usec, &ru->ru_utime.tv_usec); - err |= __put_user (r->ru_stime.tv_sec, &ru->ru_stime.tv_sec); - err |= __put_user (r->ru_stime.tv_usec, &ru->ru_stime.tv_usec); - err |= __put_user (r->ru_maxrss, &ru->ru_maxrss); - err |= __put_user (r->ru_ixrss, &ru->ru_ixrss); - err |= __put_user (r->ru_idrss, &ru->ru_idrss); - err |= __put_user (r->ru_isrss, &ru->ru_isrss); - err |= __put_user (r->ru_minflt, &ru->ru_minflt); - err |= __put_user (r->ru_majflt, &ru->ru_majflt); - err |= __put_user (r->ru_nswap, &ru->ru_nswap); - err |= __put_user (r->ru_inblock, &ru->ru_inblock); - err |= __put_user (r->ru_oublock, &ru->ru_oublock); - err |= __put_user (r->ru_msgsnd, &ru->ru_msgsnd); - err |= __put_user (r->ru_msgrcv, &ru->ru_msgrcv); - err |= __put_user (r->ru_nsignals, &ru->ru_nsignals); - err |= __put_user (r->ru_nvcsw, &ru->ru_nvcsw); - err |= __put_user (r->ru_nivcsw, &ru->ru_nivcsw); - - return err; + return compat_sys_wait4(pid, stat_addr, options, NULL); } -asmlinkage int -sys32_wait4(compat_pid_t pid, unsigned int * stat_addr, int options, - struct rusage32 * ru) +asmlinkage long +sysn32_waitid(int which, compat_pid_t pid, + siginfo_t __user *uinfo, int options, + struct compat_rusage __user *uru) { - if (!ru) - return sys_wait4(pid, stat_addr, options, NULL); - else { - struct rusage r; - int ret; - unsigned int status; - mm_segment_t old_fs = get_fs(); + struct rusage ru; + long ret; + mm_segment_t old_fs = get_fs(); - set_fs(KERNEL_DS); - ret = sys_wait4(pid, stat_addr ? &status : NULL, options, &r); - set_fs(old_fs); - if (put_rusage (ru, &r)) return -EFAULT; - if (stat_addr && put_user (status, stat_addr)) - return -EFAULT; + set_fs (KERNEL_DS); + ret = sys_waitid(which, pid, uinfo, options, + uru ? (struct rusage __user *) &ru : NULL); + set_fs (old_fs); + + if (ret < 0 || uinfo->si_signo == 0) return ret; - } -} -asmlinkage int -sys32_waitpid(compat_pid_t pid, unsigned int *stat_addr, int options) -{ - return sys32_wait4(pid, stat_addr, options, NULL); + if (uru) + ret = put_compat_rusage(&ru, uru); + return ret; } struct sysinfo32 { @@ -1467,3 +1418,80 @@ asmlinkage long sys32_socketcall(int call, unsigned int *args32) } return err; } + +struct sigevent32 { + u32 sigev_value; + u32 sigev_signo; + u32 sigev_notify; + u32 payload[(64 / 4) - 3]; +}; + +extern asmlinkage long +sys_timer_create(clockid_t which_clock, + struct sigevent __user *timer_event_spec, + timer_t __user * created_timer_id); + +long +sys32_timer_create(u32 clock, struct sigevent32 __user *se32, timer_t __user *timer_id) +{ + struct sigevent __user *p = NULL; + if (se32) { + struct sigevent se; + p = compat_alloc_user_space(sizeof(struct sigevent)); + memset(&se, 0, sizeof(struct sigevent)); + if (get_user(se.sigev_value.sival_int, &se32->sigev_value) || + __get_user(se.sigev_signo, &se32->sigev_signo) || + __get_user(se.sigev_notify, &se32->sigev_notify) || + __copy_from_user(&se._sigev_un._pad, &se32->payload, + sizeof(se32->payload)) || + copy_to_user(p, &se, sizeof(se))) + return -EFAULT; + } + return sys_timer_create(clock, p, timer_id); +} + +asmlinkage long +sysn32_rt_sigtimedwait(const sigset_t __user *uthese, + siginfo_t __user *uinfo, + const struct compat_timespec __user *uts32, + size_t sigsetsize) +{ + struct timespec __user *uts = NULL; + + if (uts32) { + struct timespec ts; + uts = compat_alloc_user_space(sizeof(struct timespec)); + if (get_user(ts.tv_sec, &uts32->tv_sec) || + get_user(ts.tv_nsec, &uts32->tv_nsec) || + copy_to_user (uts, &ts, sizeof (ts))) + return -EFAULT; + } + return sys_rt_sigtimedwait(uthese, uinfo, uts, sigsetsize); +} + +save_static_function(sys32_clone); +__attribute_used__ noinline static int +_sys32_clone(nabi_no_regargs struct pt_regs regs) +{ + unsigned long clone_flags; + unsigned long newsp; + int __user *parent_tidptr, *child_tidptr; + + clone_flags = regs.regs[4]; + newsp = regs.regs[5]; + if (!newsp) + newsp = regs.regs[29]; + parent_tidptr = (int *) regs.regs[6]; + + /* Use __dummy4 instead of getting it off the stack, so that + syscall() works. */ + child_tidptr = (int __user *) __dummy4; + return do_fork(clone_flags, newsp, ®s, 0, + parent_tidptr, child_tidptr); +} + +extern asmlinkage void sys_set_thread_area(u32 addr); +asmlinkage void sys32_set_thread_area(u32 addr) +{ + sys_set_thread_area(AA(addr)); +} diff --git a/arch/mips/kernel/module-elf32.c b/arch/mips/kernel/module-elf32.c deleted file mode 100644 index ffd216d6d6dc..000000000000 --- a/arch/mips/kernel/module-elf32.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Copyright (C) 2001 Rusty Russell. - * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org) - */ - -#undef DEBUG - -#include <linux/moduleloader.h> -#include <linux/elf.h> -#include <linux/vmalloc.h> -#include <linux/slab.h> -#include <linux/fs.h> -#include <linux/string.h> -#include <linux/kernel.h> - -struct mips_hi16 { - struct mips_hi16 *next; - Elf32_Addr *addr; - Elf32_Addr value; -}; - -static struct mips_hi16 *mips_hi16_list; - -void *module_alloc(unsigned long size) -{ - if (size == 0) - return NULL; - return vmalloc(size); -} - - -/* Free memory returned from module_alloc */ -void module_free(struct module *mod, void *module_region) -{ - vfree(module_region); - /* FIXME: If module_region == mod->init_region, trim exception - table entries. */ -} - -int module_frob_arch_sections(Elf_Ehdr *hdr, - Elf_Shdr *sechdrs, - char *secstrings, - struct module *mod) -{ - return 0; -} - -static int apply_r_mips_none(struct module *me, uint32_t *location, - Elf32_Addr v) -{ - return 0; -} - -static int apply_r_mips_32(struct module *me, uint32_t *location, - Elf32_Addr v) -{ - *location += v; - - return 0; -} - -static int apply_r_mips_26(struct module *me, uint32_t *location, - Elf32_Addr v) -{ - if (v % 4) { - printk(KERN_ERR "module %s: dangerous relocation\n", me->name); - return -ENOEXEC; - } - - if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { - printk(KERN_ERR - "module %s: relocation overflow\n", - me->name); - return -ENOEXEC; - } - - *location = (*location & ~0x03ffffff) | - ((*location + (v >> 2)) & 0x03ffffff); - - return 0; -} - -static int apply_r_mips_hi16(struct module *me, uint32_t *location, - Elf32_Addr v) -{ - struct mips_hi16 *n; - - /* - * We cannot relocate this one now because we don't know the value of - * the carry we need to add. Save the information, and let LO16 do the - * actual relocation. - */ - n = kmalloc(sizeof *n, GFP_KERNEL); - if (!n) - return -ENOMEM; - - n->addr = location; - n->value = v; - n->next = mips_hi16_list; - mips_hi16_list = n; - - return 0; -} - -static int apply_r_mips_lo16(struct module *me, uint32_t *location, - Elf32_Addr v) -{ - unsigned long insnlo = *location; - Elf32_Addr val, vallo; - - /* Sign extend the addend we extract from the lo insn. */ - vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; - - if (mips_hi16_list != NULL) { - struct mips_hi16 *l; - - l = mips_hi16_list; - while (l != NULL) { - struct mips_hi16 *next; - unsigned long insn; - - /* - * The value for the HI16 had best be the same. - */ - if (v != l->value) - goto out_danger; - - /* - * Do the HI16 relocation. Note that we actually don't - * need to know anything about the LO16 itself, except - * where to find the low 16 bits of the addend needed - * by the LO16. - */ - insn = *l->addr; - val = ((insn & 0xffff) << 16) + vallo; - val += v; - - /* - * Account for the sign extension that will happen in - * the low bits. - */ - val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff; - - insn = (insn & ~0xffff) | val; - *l->addr = insn; - - next = l->next; - kfree(l); - l = next; - } - - mips_hi16_list = NULL; - } - - /* - * Ok, we're done with the HI16 relocs. Now deal with the LO16. - */ - val = v + vallo; - insnlo = (insnlo & ~0xffff) | (val & 0xffff); - *location = insnlo; - - return 0; - -out_danger: - printk(KERN_ERR "module %s: dangerous " "relocation\n", me->name); - - return -ENOEXEC; -} - -static int (*reloc_handlers[]) (struct module *me, uint32_t *location, - Elf32_Addr v) = { - [R_MIPS_NONE] = apply_r_mips_none, - [R_MIPS_32] = apply_r_mips_32, - [R_MIPS_26] = apply_r_mips_26, - [R_MIPS_HI16] = apply_r_mips_hi16, - [R_MIPS_LO16] = apply_r_mips_lo16 -}; - -int apply_relocate(Elf32_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - Elf32_Rel *rel = (void *) sechdrs[relsec].sh_addr; - Elf32_Sym *sym; - uint32_t *location; - unsigned int i; - Elf32_Addr v; - int res; - - pr_debug("Applying relocate section %u to %u\n", relsec, - sechdrs[relsec].sh_info); - - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { - Elf32_Word r_info = rel[i].r_info; - - /* This is where to make the change */ - location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr - + rel[i].r_offset; - /* This is the symbol it is referring to */ - sym = (Elf32_Sym *)sechdrs[symindex].sh_addr - + ELF32_R_SYM(r_info); - if (!sym->st_value) { - printk(KERN_WARNING "%s: Unknown symbol %s\n", - me->name, strtab + sym->st_name); - return -ENOENT; - } - - v = sym->st_value; - - res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v); - if (res) - return res; - } - - return 0; -} - -int apply_relocate_add(Elf32_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - /* - * Current binutils always generate .rela relocations. Keep smiling - * if it's empty, abort otherwise. - */ - if (!sechdrs[relsec].sh_size) - return 0; - - printk(KERN_ERR "module %s: ADD RELOCATION unsupported\n", - me->name); - return -ENOEXEC; -} diff --git a/arch/mips/kernel/module-elf64.c b/arch/mips/kernel/module-elf64.c deleted file mode 100644 index e804792ee1ee..000000000000 --- a/arch/mips/kernel/module-elf64.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Copyright (C) 2001 Rusty Russell. - * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org) - */ - -#undef DEBUG - -#include <linux/moduleloader.h> -#include <linux/elf.h> -#include <linux/vmalloc.h> -#include <linux/slab.h> -#include <linux/fs.h> -#include <linux/string.h> -#include <linux/kernel.h> - -struct mips_hi16 { - struct mips_hi16 *next; - Elf32_Addr *addr; - Elf64_Addr value; -}; - -static struct mips_hi16 *mips_hi16_list; - -void *module_alloc(unsigned long size) -{ - if (size == 0) - return NULL; - return vmalloc(size); -} - - -/* Free memory returned from module_alloc */ -void module_free(struct module *mod, void *module_region) -{ - vfree(module_region); - /* FIXME: If module_region == mod->init_region, trim exception - table entries. */ -} - -int module_frob_arch_sections(Elf_Ehdr *hdr, - Elf_Shdr *sechdrs, - char *secstrings, - struct module *mod) -{ - return 0; -} - -int apply_relocate(Elf64_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - /* - * We don't want to deal with REL relocations - RELA is so much saner. - */ - if (!sechdrs[relsec].sh_size) - return 0; - - printk(KERN_ERR "module %s: REL relocation unsupported\n", - me->name); - return -ENOEXEC; -} - -static int apply_r_mips_none(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - return 0; -} - -static int apply_r_mips_32(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - *location = v; - - return 0; -} - -static int apply_r_mips_26(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - if (v % 4) { - printk(KERN_ERR "module %s: dangerous relocation\n", me->name); - return -ENOEXEC; - } - - if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { - printk(KERN_ERR - "module %s: relocation overflow\n", - me->name); - return -ENOEXEC; - } - - *location = (*location & ~0x03ffffff) | ((v >> 2) & 0x03ffffff); - - return 0; -} - -static int apply_r_mips_hi16(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - struct mips_hi16 *n; - - /* - * We cannot relocate this one now because we don't know the value of - * the carry we need to add. Save the information, and let LO16 do the - * actual relocation. - */ - n = kmalloc(sizeof *n, GFP_KERNEL); - if (!n) - return -ENOMEM; - - n->addr = location; - n->value = v; - n->next = mips_hi16_list; - mips_hi16_list = n; - - return 0; -} - -static int apply_r_mips_lo16(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - unsigned long insnlo = *location; - Elf32_Addr val, vallo; - - /* Sign extend the addend we extract from the lo insn. */ - vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; - - if (mips_hi16_list != NULL) { - struct mips_hi16 *l; - - l = mips_hi16_list; - while (l != NULL) { - struct mips_hi16 *next; - unsigned long insn; - - /* - * The value for the HI16 had best be the same. - */ - if (v != l->value) - goto out_danger; - - /* - * Do the HI16 relocation. Note that we actually don't - * need to know anything about the LO16 itself, except - * where to find the low 16 bits of the addend needed - * by the LO16. - */ - insn = *l->addr; - val = ((insn & 0xffff) << 16) + vallo; - val += v; - - /* - * Account for the sign extension that will happen in - * the low bits. - */ - val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff; - - insn = (insn & ~0xffff) | val; - *l->addr = insn; - - next = l->next; - kfree(l); - l = next; - } - - mips_hi16_list = NULL; - } - - /* - * Ok, we're done with the HI16 relocs. Now deal with the LO16. - */ - insnlo = (insnlo & ~0xffff) | (v & 0xffff); - *location = insnlo; - - return 0; - -out_danger: - printk(KERN_ERR "module %s: dangerous " "relocation\n", me->name); - - return -ENOEXEC; -} - -static int apply_r_mips_64(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - *(uint64_t *) location = v; - - return 0; -} - - -static int apply_r_mips_higher(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - *location = (*location & 0xffff0000) | - ((((long long) v + 0x80008000LL) >> 32) & 0xffff); - - return 0; -} - -static int apply_r_mips_highest(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - *location = (*location & 0xffff0000) | - ((((long long) v + 0x800080008000LL) >> 48) & 0xffff); - - return 0; -} - -static int (*reloc_handlers[]) (struct module *me, uint32_t *location, - Elf64_Addr v) = { - [R_MIPS_NONE] = apply_r_mips_none, - [R_MIPS_32] = apply_r_mips_32, - [R_MIPS_26] = apply_r_mips_26, - [R_MIPS_HI16] = apply_r_mips_hi16, - [R_MIPS_LO16] = apply_r_mips_lo16, - [R_MIPS_64] = apply_r_mips_64, - [R_MIPS_HIGHER] = apply_r_mips_higher, - [R_MIPS_HIGHEST] = apply_r_mips_highest -}; - -int apply_relocate_add(Elf64_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - Elf64_Mips_Rela *rel = (void *) sechdrs[relsec].sh_addr; - Elf64_Sym *sym; - uint32_t *location; - unsigned int i; - Elf64_Addr v; - int res; - - pr_debug("Applying relocate section %u to %u\n", relsec, - sechdrs[relsec].sh_info); - - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { - /* This is where to make the change */ - location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr - + rel[i].r_offset; - /* This is the symbol it is referring to */ - sym = (Elf64_Sym *)sechdrs[symindex].sh_addr + rel[i].r_sym; - if (!sym->st_value) { - printk(KERN_WARNING "%s: Unknown symbol %s\n", - me->name, strtab + sym->st_name); - return -ENOENT; - } - - v = sym->st_value; - - res = reloc_handlers[rel[i].r_type](me, location, v); - if (res) - return res; - } - - return 0; -} diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c index 458af3c7a639..e54a7f442f8a 100644 --- a/arch/mips/kernel/module.c +++ b/arch/mips/kernel/module.c @@ -1,9 +1,345 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (C) 2001 Rusty Russell. + * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2005 Thiemo Seufer + */ + +#undef DEBUG + +#include <linux/moduleloader.h> +#include <linux/elf.h> +#include <linux/vmalloc.h> +#include <linux/slab.h> +#include <linux/fs.h> +#include <linux/string.h> +#include <linux/kernel.h> #include <linux/module.h> #include <linux/spinlock.h> +struct mips_hi16 { + struct mips_hi16 *next; + Elf_Addr *addr; + Elf_Addr value; +}; + +static struct mips_hi16 *mips_hi16_list; + static LIST_HEAD(dbe_list); static DEFINE_SPINLOCK(dbe_lock); +void *module_alloc(unsigned long size) +{ + if (size == 0) + return NULL; + return vmalloc(size); +} + +/* Free memory returned from module_alloc */ +void module_free(struct module *mod, void *module_region) +{ + vfree(module_region); + /* FIXME: If module_region == mod->init_region, trim exception + table entries. */ +} + +int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, + char *secstrings, struct module *mod) +{ + return 0; +} + +static int apply_r_mips_none(struct module *me, u32 *location, Elf_Addr v) +{ + return 0; +} + +static int apply_r_mips_32_rel(struct module *me, u32 *location, Elf_Addr v) +{ + *location += v; + + return 0; +} + +static int apply_r_mips_32_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *location = v; + + return 0; +} + +static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v) +{ + if (v % 4) { + printk(KERN_ERR "module %s: dangerous relocation\n", me->name); + return -ENOEXEC; + } + + if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { + printk(KERN_ERR + "module %s: relocation overflow\n", + me->name); + return -ENOEXEC; + } + + *location = (*location & ~0x03ffffff) | + ((*location + (v >> 2)) & 0x03ffffff); + + return 0; +} + +static int apply_r_mips_26_rela(struct module *me, u32 *location, Elf_Addr v) +{ + if (v % 4) { + printk(KERN_ERR "module %s: dangerous relocation\n", me->name); + return -ENOEXEC; + } + + if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { + printk(KERN_ERR + "module %s: relocation overflow\n", + me->name); + return -ENOEXEC; + } + + *location = (*location & ~0x03ffffff) | ((v >> 2) & 0x03ffffff); + + return 0; +} + +static int apply_r_mips_hi16_rel(struct module *me, u32 *location, Elf_Addr v) +{ + struct mips_hi16 *n; + + /* + * We cannot relocate this one now because we don't know the value of + * the carry we need to add. Save the information, and let LO16 do the + * actual relocation. + */ + n = kmalloc(sizeof *n, GFP_KERNEL); + if (!n) + return -ENOMEM; + + n->addr = (Elf_Addr *)location; + n->value = v; + n->next = mips_hi16_list; + mips_hi16_list = n; + + return 0; +} + +static int apply_r_mips_hi16_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *location = (*location & 0xffff0000) | + ((((long long) v + 0x8000LL) >> 16) & 0xffff); + + return 0; +} + +static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v) +{ + unsigned long insnlo = *location; + Elf_Addr val, vallo; + + /* Sign extend the addend we extract from the lo insn. */ + vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; + + if (mips_hi16_list != NULL) { + struct mips_hi16 *l; + + l = mips_hi16_list; + while (l != NULL) { + struct mips_hi16 *next; + unsigned long insn; + + /* + * The value for the HI16 had best be the same. + */ + if (v != l->value) + goto out_danger; + + /* + * Do the HI16 relocation. Note that we actually don't + * need to know anything about the LO16 itself, except + * where to find the low 16 bits of the addend needed + * by the LO16. + */ + insn = *l->addr; + val = ((insn & 0xffff) << 16) + vallo; + val += v; + + /* + * Account for the sign extension that will happen in + * the low bits. + */ + val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff; + + insn = (insn & ~0xffff) | val; + *l->addr = insn; + + next = l->next; + kfree(l); + l = next; + } + + mips_hi16_list = NULL; + } + + /* + * Ok, we're done with the HI16 relocs. Now deal with the LO16. + */ + val = v + vallo; + insnlo = (insnlo & ~0xffff) | (val & 0xffff); + *location = insnlo; + + return 0; + +out_danger: + printk(KERN_ERR "module %s: dangerous " "relocation\n", me->name); + + return -ENOEXEC; +} + +static int apply_r_mips_lo16_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *location = (*location & 0xffff0000) | (v & 0xffff); + + return 0; +} + +static int apply_r_mips_64_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(Elf_Addr *)location = v; + + return 0; +} + +static int apply_r_mips_higher_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *location = (*location & 0xffff0000) | + ((((long long) v + 0x80008000LL) >> 32) & 0xffff); + + return 0; +} + +static int apply_r_mips_highest_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *location = (*location & 0xffff0000) | + ((((long long) v + 0x800080008000LL) >> 48) & 0xffff); + + return 0; +} + +static int (*reloc_handlers_rel[]) (struct module *me, u32 *location, + Elf_Addr v) = { + [R_MIPS_NONE] = apply_r_mips_none, + [R_MIPS_32] = apply_r_mips_32_rel, + [R_MIPS_26] = apply_r_mips_26_rel, + [R_MIPS_HI16] = apply_r_mips_hi16_rel, + [R_MIPS_LO16] = apply_r_mips_lo16_rel +}; + +static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, + Elf_Addr v) = { + [R_MIPS_NONE] = apply_r_mips_none, + [R_MIPS_32] = apply_r_mips_32_rela, + [R_MIPS_26] = apply_r_mips_26_rela, + [R_MIPS_HI16] = apply_r_mips_hi16_rela, + [R_MIPS_LO16] = apply_r_mips_lo16_rela, + [R_MIPS_64] = apply_r_mips_64_rela, + [R_MIPS_HIGHER] = apply_r_mips_higher_rela, + [R_MIPS_HIGHEST] = apply_r_mips_highest_rela +}; + +int apply_relocate(Elf_Shdr *sechdrs, const char *strtab, + unsigned int symindex, unsigned int relsec, + struct module *me) +{ + Elf_Mips_Rel *rel = (void *) sechdrs[relsec].sh_addr; + Elf_Sym *sym; + u32 *location; + unsigned int i; + Elf_Addr v; + int res; + + pr_debug("Applying relocate section %u to %u\n", relsec, + sechdrs[relsec].sh_info); + + for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { + /* This is where to make the change */ + location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr + + rel[i].r_offset; + /* This is the symbol it is referring to */ + sym = (Elf_Sym *)sechdrs[symindex].sh_addr + + ELF_MIPS_R_SYM(rel[i]); + if (!sym->st_value) { + printk(KERN_WARNING "%s: Unknown symbol %s\n", + me->name, strtab + sym->st_name); + return -ENOENT; + } + + v = sym->st_value; + + res = reloc_handlers_rel[ELF_MIPS_R_TYPE(rel[i])](me, location, v); + if (res) + return res; + } + + return 0; +} + +int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, + unsigned int symindex, unsigned int relsec, + struct module *me) +{ + Elf_Mips_Rela *rel = (void *) sechdrs[relsec].sh_addr; + Elf_Sym *sym; + u32 *location; + unsigned int i; + Elf_Addr v; + int res; + + pr_debug("Applying relocate section %u to %u\n", relsec, + sechdrs[relsec].sh_info); + + for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { + /* This is where to make the change */ + location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr + + rel[i].r_offset; + /* This is the symbol it is referring to */ + sym = (Elf_Sym *)sechdrs[symindex].sh_addr + + ELF_MIPS_R_SYM(rel[i]); + if (!sym->st_value) { + printk(KERN_WARNING "%s: Unknown symbol %s\n", + me->name, strtab + sym->st_name); + return -ENOENT; + } + + v = sym->st_value + rel[i].r_addend; + + res = reloc_handlers_rela[ELF_MIPS_R_TYPE(rel[i])](me, location, v); + if (res) + return res; + } + + return 0; +} + /* Given an address, look for it in the module exception tables. */ const struct exception_table_entry *search_module_dbetables(unsigned long addr) { diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 0f159f30e894..86fe15b273cd 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -2,7 +2,8 @@ * linux/arch/mips/kernel/proc.c * * Copyright (C) 1995, 1996, 2001 Ralf Baechle - * Copyright (C) 2001 MIPS Technologies, Inc. + * Copyright (C) 2001, 2004 MIPS Technologies, Inc. + * Copyright (C) 2004 Maciej W. Rozycki */ #include <linux/config.h> #include <linux/delay.h> @@ -19,63 +20,69 @@ unsigned int vced_count, vcei_count; static const char *cpu_name[] = { - [CPU_UNKNOWN] "unknown", - [CPU_R2000] "R2000", - [CPU_R3000] "R3000", - [CPU_R3000A] "R3000A", - [CPU_R3041] "R3041", - [CPU_R3051] "R3051", - [CPU_R3052] "R3052", - [CPU_R3081] "R3081", - [CPU_R3081E] "R3081E", - [CPU_R4000PC] "R4000PC", - [CPU_R4000SC] "R4000SC", - [CPU_R4000MC] "R4000MC", - [CPU_R4200] "R4200", - [CPU_R4400PC] "R4400PC", - [CPU_R4400SC] "R4400SC", - [CPU_R4400MC] "R4400MC", - [CPU_R4600] "R4600", - [CPU_R6000] "R6000", - [CPU_R6000A] "R6000A", - [CPU_R8000] "R8000", - [CPU_R10000] "R10000", - [CPU_R12000] "R12000", - [CPU_R4300] "R4300", - [CPU_R4650] "R4650", - [CPU_R4700] "R4700", - [CPU_R5000] "R5000", - [CPU_R5000A] "R5000A", - [CPU_R4640] "R4640", - [CPU_NEVADA] "Nevada", - [CPU_RM7000] "RM7000", - [CPU_RM9000] "RM9000", - [CPU_R5432] "R5432", - [CPU_4KC] "MIPS 4Kc", - [CPU_5KC] "MIPS 5Kc", - [CPU_R4310] "R4310", - [CPU_SB1] "SiByte SB1", - [CPU_TX3912] "TX3912", - [CPU_TX3922] "TX3922", - [CPU_TX3927] "TX3927", - [CPU_AU1000] "Au1000", - [CPU_AU1500] "Au1500", - [CPU_4KEC] "MIPS 4KEc", - [CPU_4KSC] "MIPS 4KSc", - [CPU_VR41XX] "NEC Vr41xx", - [CPU_R5500] "R5500", - [CPU_TX49XX] "TX49xx", - [CPU_20KC] "MIPS 20Kc", - [CPU_24K] "MIPS 24K", - [CPU_25KF] "MIPS 25Kf", - [CPU_VR4111] "NEC VR4111", - [CPU_VR4121] "NEC VR4121", - [CPU_VR4122] "NEC VR4122", - [CPU_VR4131] "NEC VR4131", - [CPU_VR4133] "NEC VR4133", - [CPU_VR4181] "NEC VR4181", - [CPU_VR4181A] "NEC VR4181A", - [CPU_SR71000] "Sandcraft SR71000" + [CPU_UNKNOWN] = "unknown", + [CPU_R2000] = "R2000", + [CPU_R3000] = "R3000", + [CPU_R3000A] = "R3000A", + [CPU_R3041] = "R3041", + [CPU_R3051] = "R3051", + [CPU_R3052] = "R3052", + [CPU_R3081] = "R3081", + [CPU_R3081E] = "R3081E", + [CPU_R4000PC] = "R4000PC", + [CPU_R4000SC] = "R4000SC", + [CPU_R4000MC] = "R4000MC", + [CPU_R4200] = "R4200", + [CPU_R4400PC] = "R4400PC", + [CPU_R4400SC] = "R4400SC", + [CPU_R4400MC] = "R4400MC", + [CPU_R4600] = "R4600", + [CPU_R6000] = "R6000", + [CPU_R6000A] = "R6000A", + [CPU_R8000] = "R8000", + [CPU_R10000] = "R10000", + [CPU_R12000] = "R12000", + [CPU_R4300] = "R4300", + [CPU_R4650] = "R4650", + [CPU_R4700] = "R4700", + [CPU_R5000] = "R5000", + [CPU_R5000A] = "R5000A", + [CPU_R4640] = "R4640", + [CPU_NEVADA] = "Nevada", + [CPU_RM7000] = "RM7000", + [CPU_RM9000] = "RM9000", + [CPU_R5432] = "R5432", + [CPU_4KC] = "MIPS 4Kc", + [CPU_5KC] = "MIPS 5Kc", + [CPU_R4310] = "R4310", + [CPU_SB1] = "SiByte SB1", + [CPU_SB1A] = "SiByte SB1A", + [CPU_TX3912] = "TX3912", + [CPU_TX3922] = "TX3922", + [CPU_TX3927] = "TX3927", + [CPU_AU1000] = "Au1000", + [CPU_AU1500] = "Au1500", + [CPU_AU1100] = "Au1100", + [CPU_AU1550] = "Au1550", + [CPU_AU1200] = "Au1200", + [CPU_4KEC] = "MIPS 4KEc", + [CPU_4KSC] = "MIPS 4KSc", + [CPU_VR41XX] = "NEC Vr41xx", + [CPU_R5500] = "R5500", + [CPU_TX49XX] = "TX49xx", + [CPU_20KC] = "MIPS 20Kc", + [CPU_24K] = "MIPS 24K", + [CPU_25KF] = "MIPS 25Kf", + [CPU_34K] = "MIPS 34K", + [CPU_VR4111] = "NEC VR4111", + [CPU_VR4121] = "NEC VR4121", + [CPU_VR4122] = "NEC VR4122", + [CPU_VR4131] = "NEC VR4131", + [CPU_VR4133] = "NEC VR4133", + [CPU_VR4181] = "NEC VR4181", + [CPU_VR4181A] = "NEC VR4181A", + [CPU_SR71000] = "Sandcraft SR71000", + [CPU_PR4450] = "Philips PR4450", }; @@ -105,8 +112,8 @@ static int show_cpuinfo(struct seq_file *m, void *v) (version >> 4) & 0x0f, version & 0x0f, (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n", - loops_per_jiffy / (500000/HZ), - (loops_per_jiffy / (5000/HZ)) % 100); + cpu_data[n].udelay_val / (500000/HZ), + (cpu_data[n].udelay_val / (5000/HZ)) % 100); seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); seq_printf(m, "microsecond timers\t: %s\n", cpu_has_counter ? "yes" : "no"); @@ -115,6 +122,14 @@ static int show_cpuinfo(struct seq_file *m, void *v) cpu_has_divec ? "yes" : "no"); seq_printf(m, "hardware watchpoint\t: %s\n", cpu_has_watch ? "yes" : "no"); + seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n", + cpu_has_mips16 ? " mips16" : "", + cpu_has_mdmx ? " mdmx" : "", + cpu_has_mips3d ? " mips3d" : "", + cpu_has_smartmips ? " smartmips" : "", + cpu_has_dsp ? " dsp" : "", + cpu_has_mipsmt ? " mt" : "" + ); sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", cpu_has_vce ? "%u" : "not available"); diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index e4f2f8011387..4fe3d5715c41 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -25,8 +25,10 @@ #include <linux/init.h> #include <linux/completion.h> +#include <asm/abi.h> #include <asm/bootinfo.h> #include <asm/cpu.h> +#include <asm/dsp.h> #include <asm/fpu.h> #include <asm/pgtable.h> #include <asm/system.h> @@ -39,14 +41,6 @@ #include <asm/inst.h> /* - * We use this if we don't have any better idle routine.. - * (This to kill: kernel/platform.c. - */ -void default_idle (void) -{ -} - -/* * The idle thread. There's no useful work to be done, so just try to conserve * power and have a low exit latency (ie sit in a loop waiting for somebody to * say that they'd like to reschedule) @@ -62,6 +56,54 @@ ATTRIB_NORET void cpu_idle(void) } } +extern int do_signal(sigset_t *oldset, struct pt_regs *regs); +extern int do_signal32(sigset_t *oldset, struct pt_regs *regs); + +/* + * Native o32 and N64 ABI without DSP ASE + */ +extern int setup_frame(struct k_sigaction * ka, struct pt_regs *regs, + int signr, sigset_t *set); +extern int setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, + int signr, sigset_t *set, siginfo_t *info); + +struct mips_abi mips_abi = { + .do_signal = do_signal, +#ifdef CONFIG_TRAD_SIGNALS + .setup_frame = setup_frame, +#endif + .setup_rt_frame = setup_rt_frame +}; + +#ifdef CONFIG_MIPS32_O32 +/* + * o32 compatibility on 64-bit kernels, without DSP ASE + */ +extern int setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs, + int signr, sigset_t *set); +extern int setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs, + int signr, sigset_t *set, siginfo_t *info); + +struct mips_abi mips_abi_32 = { + .do_signal = do_signal32, + .setup_frame = setup_frame_32, + .setup_rt_frame = setup_rt_frame_32 +}; +#endif /* CONFIG_MIPS32_O32 */ + +#ifdef CONFIG_MIPS32_N32 +/* + * N32 on 64-bit kernels, without DSP ASE + */ +extern int setup_rt_frame_n32(struct k_sigaction * ka, struct pt_regs *regs, + int signr, sigset_t *set, siginfo_t *info); + +struct mips_abi mips_abi_n32 = { + .do_signal = do_signal, + .setup_rt_frame = setup_rt_frame_n32 +}; +#endif /* CONFIG_MIPS32_N32 */ + asmlinkage void ret_from_fork(void); void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) @@ -78,6 +120,8 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) regs->cp0_status = status; clear_used_math(); lose_fpu(); + if (cpu_has_dsp) + __init_dsp(); regs->cp0_epc = pc; regs->regs[29] = sp; current_thread_info()->addr_limit = USER_DS; @@ -97,14 +141,17 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp, struct thread_info *ti = p->thread_info; struct pt_regs *childregs; long childksp; + p->set_child_tid = p->clear_child_tid = NULL; childksp = (unsigned long)ti + THREAD_SIZE - 32; preempt_disable(); - if (is_fpu_owner()) { + if (is_fpu_owner()) save_fp(p); - } + + if (cpu_has_dsp) + save_dsp(p); preempt_enable(); @@ -142,6 +189,9 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp, childregs->cp0_status &= ~(ST0_CU2|ST0_CU1); clear_tsk_thread_flag(p, TIF_USEDFPU); + if (clone_flags & CLONE_SETTLS) + ti->tp_value = regs->regs[7]; + return 0; } @@ -175,6 +225,14 @@ void dump_regs(elf_greg_t *gp, struct pt_regs *regs) #endif } +int dump_task_regs (struct task_struct *tsk, elf_gregset_t *regs) +{ + struct thread_info *ti = tsk->thread_info; + long ksp = (unsigned long)ti + THREAD_SIZE - 32; + dump_regs(&(*regs)[0], (struct pt_regs *) ksp - 1); + return 1; +} + int dump_task_fpu (struct task_struct *t, elf_fpregset_t *fpr) { memcpy(fpr, &t->thread.fpu, sizeof(current->thread.fpu)); @@ -211,22 +269,48 @@ long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL); } -struct mips_frame_info { +static struct mips_frame_info { + void *func; + int omit_fp; /* compiled without fno-omit-frame-pointer */ int frame_offset; int pc_offset; +} schedule_frame, mfinfo[] = { + { schedule, 0 }, /* must be first */ + /* arch/mips/kernel/semaphore.c */ + { __down, 1 }, + { __down_interruptible, 1 }, + /* kernel/sched.c */ +#ifdef CONFIG_PREEMPT + { preempt_schedule, 0 }, +#endif + { wait_for_completion, 0 }, + { interruptible_sleep_on, 0 }, + { interruptible_sleep_on_timeout, 0 }, + { sleep_on, 0 }, + { sleep_on_timeout, 0 }, + { yield, 0 }, + { io_schedule, 0 }, + { io_schedule_timeout, 0 }, +#if defined(CONFIG_SMP) && defined(CONFIG_PREEMPT) + { __preempt_spin_lock, 0 }, + { __preempt_write_lock, 0 }, +#endif + /* kernel/timer.c */ + { schedule_timeout, 1 }, +/* { nanosleep_restart, 1 }, */ + /* lib/rwsem-spinlock.c */ + { __down_read, 1 }, + { __down_write, 1 }, }; -static struct mips_frame_info schedule_frame; -static struct mips_frame_info schedule_timeout_frame; -static struct mips_frame_info sleep_on_frame; -static struct mips_frame_info sleep_on_timeout_frame; -static struct mips_frame_info wait_for_completion_frame; + static int mips_frame_info_initialized; -static int __init get_frame_info(struct mips_frame_info *info, void *func) +static int __init get_frame_info(struct mips_frame_info *info) { int i; + void *func = info->func; union mips_instruction *ip = (union mips_instruction *)func; info->pc_offset = -1; - info->frame_offset = -1; + info->frame_offset = info->omit_fp ? 0 : -1; for (i = 0; i < 128; i++, ip++) { /* if jal, jalr, jr, stop. */ if (ip->j_format.opcode == jal_op || @@ -247,14 +331,16 @@ static int __init get_frame_info(struct mips_frame_info *info, void *func) /* sw / sd $ra, offset($sp) */ if (ip->i_format.rt == 31) { if (info->pc_offset != -1) - break; + continue; info->pc_offset = ip->i_format.simmediate / sizeof(long); } /* sw / sd $s8, offset($sp) */ if (ip->i_format.rt == 30) { +//#if 0 /* gcc 3.4 does aggressive optimization... */ if (info->frame_offset != -1) - break; + continue; +//#endif info->frame_offset = ip->i_format.simmediate / sizeof(long); } @@ -272,13 +358,25 @@ static int __init get_frame_info(struct mips_frame_info *info, void *func) static int __init frame_info_init(void) { - mips_frame_info_initialized = - !get_frame_info(&schedule_frame, schedule) && - !get_frame_info(&schedule_timeout_frame, schedule_timeout) && - !get_frame_info(&sleep_on_frame, sleep_on) && - !get_frame_info(&sleep_on_timeout_frame, sleep_on_timeout) && - !get_frame_info(&wait_for_completion_frame, wait_for_completion); - + int i, found; + for (i = 0; i < ARRAY_SIZE(mfinfo); i++) + if (get_frame_info(&mfinfo[i])) + return -1; + schedule_frame = mfinfo[0]; + /* bubble sort */ + do { + struct mips_frame_info tmp; + found = 0; + for (i = 1; i < ARRAY_SIZE(mfinfo); i++) { + if (mfinfo[i-1].func > mfinfo[i].func) { + tmp = mfinfo[i]; + mfinfo[i] = mfinfo[i-1]; + mfinfo[i-1] = tmp; + found = 1; + } + } + } while (found); + mips_frame_info_initialized = 1; return 0; } @@ -303,60 +401,39 @@ unsigned long thread_saved_pc(struct task_struct *tsk) /* get_wchan - a maintenance nightmare^W^Wpain in the ass ... */ unsigned long get_wchan(struct task_struct *p) { + unsigned long stack_page; unsigned long frame, pc; if (!p || p == current || p->state == TASK_RUNNING) return 0; - if (!mips_frame_info_initialized) + stack_page = (unsigned long)p->thread_info; + if (!stack_page || !mips_frame_info_initialized) return 0; + pc = thread_saved_pc(p); if (!in_sched_functions(pc)) - goto out; - - if (pc >= (unsigned long) sleep_on_timeout) - goto schedule_timeout_caller; - if (pc >= (unsigned long) sleep_on) - goto schedule_caller; - if (pc >= (unsigned long) interruptible_sleep_on_timeout) - goto schedule_timeout_caller; - if (pc >= (unsigned long)interruptible_sleep_on) - goto schedule_caller; - if (pc >= (unsigned long)wait_for_completion) - goto schedule_caller; - goto schedule_timeout_caller; - -schedule_caller: - frame = ((unsigned long *)p->thread.reg30)[schedule_frame.frame_offset]; - if (pc >= (unsigned long) sleep_on) - pc = ((unsigned long *)frame)[sleep_on_frame.pc_offset]; - else - pc = ((unsigned long *)frame)[wait_for_completion_frame.pc_offset]; - goto out; + return pc; -schedule_timeout_caller: - /* - * The schedule_timeout frame - */ frame = ((unsigned long *)p->thread.reg30)[schedule_frame.frame_offset]; + do { + int i; - /* - * frame now points to sleep_on_timeout's frame - */ - pc = ((unsigned long *)frame)[schedule_timeout_frame.pc_offset]; - - if (in_sched_functions(pc)) { - /* schedule_timeout called by [interruptible_]sleep_on_timeout */ - frame = ((unsigned long *)frame)[schedule_timeout_frame.frame_offset]; - pc = ((unsigned long *)frame)[sleep_on_timeout_frame.pc_offset]; - } + if (frame < stack_page || frame > stack_page + THREAD_SIZE - 32) + return 0; -out: + for (i = ARRAY_SIZE(mfinfo) - 1; i >= 0; i--) { + if (pc >= (unsigned long) mfinfo[i].func) + break; + } + if (i < 0) + break; -#ifdef CONFIG_64BIT - if (current->thread.mflags & MF_32BIT_REGS) /* Kludge for 32-bit ps */ - pc &= 0xffffffffUL; -#endif + if (mfinfo[i].omit_fp) + break; + pc = ((unsigned long *)frame)[mfinfo[i].pc_offset]; + frame = ((unsigned long *)frame)[mfinfo[i].frame_offset]; + } while (in_sched_functions(pc)); return pc; } diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 0b571a5b4b83..fcceab8f2e00 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -28,14 +28,18 @@ #include <linux/security.h> #include <linux/signal.h> +#include <asm/byteorder.h> #include <asm/cpu.h> +#include <asm/dsp.h> #include <asm/fpu.h> #include <asm/mipsregs.h> +#include <asm/mipsmtregs.h> #include <asm/pgtable.h> #include <asm/page.h> #include <asm/system.h> #include <asm/uaccess.h> #include <asm/bootinfo.h> +#include <asm/reg.h> /* * Called by kernel/ptrace.c when detaching.. @@ -47,6 +51,129 @@ void ptrace_disable(struct task_struct *child) /* Nothing to do.. */ } +/* + * Read a general register set. We always use the 64-bit format, even + * for 32-bit kernels and for 32-bit processes on a 64-bit kernel. + * Registers are sign extended to fill the available space. + */ +int ptrace_getregs (struct task_struct *child, __s64 __user *data) +{ + struct pt_regs *regs; + int i; + + if (!access_ok(VERIFY_WRITE, data, 38 * 8)) + return -EIO; + + regs = (struct pt_regs *) ((unsigned long) child->thread_info + + THREAD_SIZE - 32 - sizeof(struct pt_regs)); + + for (i = 0; i < 32; i++) + __put_user (regs->regs[i], data + i); + __put_user (regs->lo, data + EF_LO - EF_R0); + __put_user (regs->hi, data + EF_HI - EF_R0); + __put_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0); + __put_user (regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0); + __put_user (regs->cp0_status, data + EF_CP0_STATUS - EF_R0); + __put_user (regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0); + + return 0; +} + +/* + * Write a general register set. As for PTRACE_GETREGS, we always use + * the 64-bit format. On a 32-bit kernel only the lower order half + * (according to endianness) will be used. + */ +int ptrace_setregs (struct task_struct *child, __s64 __user *data) +{ + struct pt_regs *regs; + int i; + + if (!access_ok(VERIFY_READ, data, 38 * 8)) + return -EIO; + + regs = (struct pt_regs *) ((unsigned long) child->thread_info + + THREAD_SIZE - 32 - sizeof(struct pt_regs)); + + for (i = 0; i < 32; i++) + __get_user (regs->regs[i], data + i); + __get_user (regs->lo, data + EF_LO - EF_R0); + __get_user (regs->hi, data + EF_HI - EF_R0); + __get_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0); + + /* badvaddr, status, and cause may not be written. */ + + return 0; +} + +int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) +{ + int i; + + if (!access_ok(VERIFY_WRITE, data, 33 * 8)) + return -EIO; + + if (tsk_used_math(child)) { + fpureg_t *fregs = get_fpu_regs(child); + for (i = 0; i < 32; i++) + __put_user (fregs[i], i + (__u64 __user *) data); + } else { + for (i = 0; i < 32; i++) + __put_user ((__u64) -1, i + (__u64 __user *) data); + } + + if (cpu_has_fpu) { + unsigned int flags, tmp; + + __put_user (child->thread.fpu.hard.fcr31, data + 64); + + preempt_disable(); + if (cpu_has_mipsmt) { + unsigned int vpflags = dvpe(); + flags = read_c0_status(); + __enable_fpu(); + __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); + write_c0_status(flags); + evpe(vpflags); + } else { + flags = read_c0_status(); + __enable_fpu(); + __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); + write_c0_status(flags); + } + preempt_enable(); + __put_user (tmp, data + 65); + } else { + __put_user (child->thread.fpu.soft.fcr31, data + 64); + __put_user ((__u32) 0, data + 65); + } + + return 0; +} + +int ptrace_setfpregs (struct task_struct *child, __u32 __user *data) +{ + fpureg_t *fregs; + int i; + + if (!access_ok(VERIFY_READ, data, 33 * 8)) + return -EIO; + + fregs = get_fpu_regs(child); + + for (i = 0; i < 32; i++) + __get_user (fregs[i], i + (__u64 __user *) data); + + if (cpu_has_fpu) + __get_user (child->thread.fpu.hard.fcr31, data + 64); + else + __get_user (child->thread.fpu.soft.fcr31, data + 64); + + /* FIR may not be written. */ + + return 0; +} + asmlinkage int sys_ptrace(long request, long pid, long addr, long data) { struct task_struct *child; @@ -103,7 +230,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) ret = -EIO; if (copied != sizeof(tmp)) break; - ret = put_user(tmp,(unsigned long *) data); + ret = put_user(tmp,(unsigned long __user *) data); break; } @@ -169,18 +296,53 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) if (!cpu_has_fpu) break; - flags = read_c0_status(); - __enable_fpu(); - __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); - write_c0_status(flags); + preempt_disable(); + if (cpu_has_mipsmt) { + unsigned int vpflags = dvpe(); + flags = read_c0_status(); + __enable_fpu(); + __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); + write_c0_status(flags); + evpe(vpflags); + } else { + flags = read_c0_status(); + __enable_fpu(); + __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); + write_c0_status(flags); + } + preempt_enable(); + break; + } + case DSP_BASE ... DSP_BASE + 5: { + dspreg_t *dregs; + + if (!cpu_has_dsp) { + tmp = 0; + ret = -EIO; + goto out_tsk; + } + if (child->thread.dsp.used_dsp) { + dregs = __get_dsp_regs(child); + tmp = (unsigned long) (dregs[addr - DSP_BASE]); + } else { + tmp = -1; /* DSP registers yet used */ + } break; } + case DSP_CONTROL: + if (!cpu_has_dsp) { + tmp = 0; + ret = -EIO; + goto out_tsk; + } + tmp = child->thread.dsp.dspcontrol; + break; default: tmp = 0; ret = -EIO; goto out_tsk; } - ret = put_user(tmp, (unsigned long *) data); + ret = put_user(tmp, (unsigned long __user *) data); break; } @@ -247,6 +409,25 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) else child->thread.fpu.soft.fcr31 = data; break; + case DSP_BASE ... DSP_BASE + 5: { + dspreg_t *dregs; + + if (!cpu_has_dsp) { + ret = -EIO; + break; + } + + dregs = __get_dsp_regs(child); + dregs[addr - DSP_BASE] = data; + break; + } + case DSP_CONTROL: + if (!cpu_has_dsp) { + ret = -EIO; + break; + } + child->thread.dsp.dspcontrol = data; + break; default: /* The rest are not allowed. */ ret = -EIO; @@ -255,6 +436,22 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) break; } + case PTRACE_GETREGS: + ret = ptrace_getregs (child, (__u64 __user *) data); + break; + + case PTRACE_SETREGS: + ret = ptrace_setregs (child, (__u64 __user *) data); + break; + + case PTRACE_GETFPREGS: + ret = ptrace_getfpregs (child, (__u32 __user *) data); + break; + + case PTRACE_SETFPREGS: + ret = ptrace_setfpregs (child, (__u32 __user *) data); + break; + case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ case PTRACE_CONT: { /* restart after signal. */ ret = -EIO; @@ -289,6 +486,11 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) ret = ptrace_detach(child, data); break; + case PTRACE_GET_THREAD_AREA: + ret = put_user(child->thread_info->tp_value, + (unsigned long __user *) data); + break; + default: ret = ptrace_request(child, request, addr, data); break; @@ -303,21 +505,14 @@ out: static inline int audit_arch(void) { -#ifdef CONFIG_CPU_LITTLE_ENDIAN -#ifdef CONFIG_64BIT - if (!(current->thread.mflags & MF_32BIT_REGS)) - return AUDIT_ARCH_MIPSEL64; -#endif /* MIPS64 */ - return AUDIT_ARCH_MIPSEL; - -#else /* big endian... */ + int arch = EM_MIPS; #ifdef CONFIG_64BIT - if (!(current->thread.mflags & MF_32BIT_REGS)) - return AUDIT_ARCH_MIPS64; -#endif /* MIPS64 */ - return AUDIT_ARCH_MIPS; - -#endif /* endian */ + arch |= __AUDIT_ARCH_64BIT; +#endif +#if defined(__LITTLE_ENDIAN) + arch |= __AUDIT_ARCH_LE; +#endif + return arch; } /* @@ -327,12 +522,13 @@ static inline int audit_arch(void) asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit) { if (unlikely(current->audit_context) && entryexit) - audit_syscall_exit(current, AUDITSC_RESULT(regs->regs[2]), regs->regs[2]); + audit_syscall_exit(current, AUDITSC_RESULT(regs->regs[2]), + regs->regs[2]); - if (!test_thread_flag(TIF_SYSCALL_TRACE)) - goto out; if (!(current->ptrace & PT_PTRACED)) goto out; + if (!test_thread_flag(TIF_SYSCALL_TRACE)) + goto out; /* The 0x80 provides a way for the tracing parent to distinguish between a syscall stop and SIGTRAP delivery */ diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c index eee207969c21..9a9b04972132 100644 --- a/arch/mips/kernel/ptrace32.c +++ b/arch/mips/kernel/ptrace32.c @@ -24,17 +24,24 @@ #include <linux/smp_lock.h> #include <linux/user.h> #include <linux/security.h> -#include <linux/signal.h> #include <asm/cpu.h> +#include <asm/dsp.h> #include <asm/fpu.h> #include <asm/mipsregs.h> +#include <asm/mipsmtregs.h> #include <asm/pgtable.h> #include <asm/page.h> #include <asm/system.h> #include <asm/uaccess.h> #include <asm/bootinfo.h> +int ptrace_getregs (struct task_struct *child, __s64 __user *data); +int ptrace_setregs (struct task_struct *child, __s64 __user *data); + +int ptrace_getfpregs (struct task_struct *child, __u32 __user *data); +int ptrace_setfpregs (struct task_struct *child, __u32 __user *data); + /* * Tracing a 32-bit process with a 64-bit strace and vice versa will not * work. I don't know how to fix this. @@ -99,6 +106,35 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) break; } + /* + * Read 4 bytes of the other process' storage + * data is a pointer specifying where the user wants the + * 4 bytes copied into + * addr is a pointer in the user's storage that contains an 8 byte + * address in the other process of the 4 bytes that is to be read + * (this is run in a 32-bit process looking at a 64-bit process) + * when I and D space are separate, these will need to be fixed. + */ + case PTRACE_PEEKTEXT_3264: + case PTRACE_PEEKDATA_3264: { + u32 tmp; + int copied; + u32 __user * addrOthers; + + ret = -EIO; + + /* Get the addr in the other process that we want to read */ + if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0) + break; + + copied = access_process_vm(child, (u64)addrOthers, &tmp, + sizeof(tmp), 0); + if (copied != sizeof(tmp)) + break; + ret = put_user(tmp, (u32 __user *) (unsigned long) data); + break; + } + /* Read the word at location addr in the USER area. */ case PTRACE_PEEKUSR: { struct pt_regs *regs; @@ -156,12 +192,44 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) if (!cpu_has_fpu) break; - flags = read_c0_status(); - __enable_fpu(); - __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); - write_c0_status(flags); + preempt_disable(); + if (cpu_has_mipsmt) { + unsigned int vpflags = dvpe(); + flags = read_c0_status(); + __enable_fpu(); + __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); + write_c0_status(flags); + evpe(vpflags); + } else { + flags = read_c0_status(); + __enable_fpu(); + __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); + write_c0_status(flags); + } + preempt_enable(); break; } + case DSP_BASE ... DSP_BASE + 5: + if (!cpu_has_dsp) { + tmp = 0; + ret = -EIO; + goto out_tsk; + } + if (child->thread.dsp.used_dsp) { + dspreg_t *dregs = __get_dsp_regs(child); + tmp = (unsigned long) (dregs[addr - DSP_BASE]); + } else { + tmp = -1; /* DSP registers yet used */ + } + break; + case DSP_CONTROL: + if (!cpu_has_dsp) { + tmp = 0; + ret = -EIO; + goto out_tsk; + } + tmp = child->thread.dsp.dspcontrol; + break; default: tmp = 0; ret = -EIO; @@ -181,6 +249,31 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) ret = -EIO; break; + /* + * Write 4 bytes into the other process' storage + * data is the 4 bytes that the user wants written + * addr is a pointer in the user's storage that contains an + * 8 byte address in the other process where the 4 bytes + * that is to be written + * (this is run in a 32-bit process looking at a 64-bit process) + * when I and D space are separate, these will need to be fixed. + */ + case PTRACE_POKETEXT_3264: + case PTRACE_POKEDATA_3264: { + u32 __user * addrOthers; + + /* Get the addr in the other process that we want to write into */ + ret = -EIO; + if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0) + break; + ret = 0; + if (access_process_vm(child, (u64)addrOthers, &data, + sizeof(data), 1) == sizeof(data)) + break; + ret = -EIO; + break; + } + case PTRACE_POKEUSR: { struct pt_regs *regs; ret = 0; @@ -231,6 +324,22 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) else child->thread.fpu.soft.fcr31 = data; break; + case DSP_BASE ... DSP_BASE + 5: + if (!cpu_has_dsp) { + ret = -EIO; + break; + } + + dspreg_t *dregs = __get_dsp_regs(child); + dregs[addr - DSP_BASE] = data; + break; + case DSP_CONTROL: + if (!cpu_has_dsp) { + ret = -EIO; + break; + } + child->thread.dsp.dspcontrol = data; + break; default: /* The rest are not allowed. */ ret = -EIO; @@ -239,6 +348,22 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) break; } + case PTRACE_GETREGS: + ret = ptrace_getregs (child, (__u64 __user *) (__u64) data); + break; + + case PTRACE_SETREGS: + ret = ptrace_setregs (child, (__u64 __user *) (__u64) data); + break; + + case PTRACE_GETFPREGS: + ret = ptrace_getfpregs (child, (__u32 __user *) (__u64) data); + break; + + case PTRACE_SETFPREGS: + ret = ptrace_setfpregs (child, (__u32 __user *) (__u64) data); + break; + case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ case PTRACE_CONT: { /* restart after signal. */ ret = -EIO; @@ -269,10 +394,25 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) wake_up_process(child); break; + case PTRACE_GET_THREAD_AREA: + ret = put_user(child->thread_info->tp_value, + (unsigned int __user *) (unsigned long) data); + break; + case PTRACE_DETACH: /* detach a process that was attached. */ ret = ptrace_detach(child, data); break; + case PTRACE_GETEVENTMSG: + ret = put_user(child->ptrace_message, + (unsigned int __user *) (unsigned long) data); + break; + + case PTRACE_GET_THREAD_AREA_3264: + ret = put_user(child->thread_info->tp_value, + (unsigned long __user *) (unsigned long) data); + break; + default: ret = ptrace_request(child, request, addr, data); break; diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S index 1a14c6b18829..283a98508fc8 100644 --- a/arch/mips/kernel/r4k_fpu.S +++ b/arch/mips/kernel/r4k_fpu.S @@ -32,7 +32,7 @@ .set noreorder .set mips3 - /* Save floating point context */ + LEAF(_save_fp_context) cfc1 t1, fcr31 @@ -74,9 +74,6 @@ LEAF(_save_fp_context) EX sdc1 $f28, SC_FPREGS+224(a0) EX sdc1 $f30, SC_FPREGS+240(a0) EX sw t1, SC_FPC_CSR(a0) - cfc1 t0, $0 # implementation/version - EX sw t0, SC_FPC_EIR(a0) - jr ra li v0, 0 # success END(_save_fp_context) diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c new file mode 100644 index 000000000000..8c81f3cb4e2d --- /dev/null +++ b/arch/mips/kernel/rtlx.c @@ -0,0 +1,341 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/fs.h> +#include <linux/init.h> +#include <asm/uaccess.h> +#include <linux/slab.h> +#include <linux/list.h> +#include <linux/vmalloc.h> +#include <linux/elf.h> +#include <linux/seq_file.h> +#include <linux/syscalls.h> +#include <linux/moduleloader.h> +#include <linux/interrupt.h> +#include <linux/poll.h> +#include <linux/sched.h> +#include <linux/wait.h> +#include <asm/mipsmtregs.h> +#include <asm/cacheflush.h> +#include <asm/atomic.h> +#include <asm/cpu.h> +#include <asm/processor.h> +#include <asm/system.h> +#include <asm/rtlx.h> + +#define RTLX_MAJOR 64 +#define RTLX_TARG_VPE 1 + +struct rtlx_info *rtlx; +static int major; +static char module_name[] = "rtlx"; +static inline int spacefree(int read, int write, int size); + +static struct chan_waitqueues { + wait_queue_head_t rt_queue; + wait_queue_head_t lx_queue; +} channel_wqs[RTLX_CHANNELS]; + +static struct irqaction irq; +static int irq_num; + +extern void *vpe_get_shared(int index); + +static void rtlx_dispatch(struct pt_regs *regs) +{ + do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ, regs); +} + +irqreturn_t rtlx_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + irqreturn_t r = IRQ_HANDLED; + int i; + + for (i = 0; i < RTLX_CHANNELS; i++) { + struct rtlx_channel *chan = &rtlx->channel[i]; + + if (chan->lx_read != chan->lx_write) + wake_up_interruptible(&channel_wqs[i].lx_queue); + } + + return r; +} + +void dump_rtlx(void) +{ + int i; + + printk("id 0x%lx state %d\n", rtlx->id, rtlx->state); + + for (i = 0; i < RTLX_CHANNELS; i++) { + struct rtlx_channel *chan = &rtlx->channel[i]; + + printk(" rt_state %d lx_state %d buffer_size %d\n", + chan->rt_state, chan->lx_state, chan->buffer_size); + + printk(" rt_read %d rt_write %d\n", + chan->rt_read, chan->rt_write); + + printk(" lx_read %d lx_write %d\n", + chan->lx_read, chan->lx_write); + + printk(" rt_buffer <%s>\n", chan->rt_buffer); + printk(" lx_buffer <%s>\n", chan->lx_buffer); + } +} + +/* call when we have the address of the shared structure from the SP side. */ +static int rtlx_init(struct rtlx_info *rtlxi) +{ + int i; + + if (rtlxi->id != RTLX_ID) { + printk(KERN_WARNING "no valid RTLX id at 0x%p\n", rtlxi); + return (-ENOEXEC); + } + + /* initialise the wait queues */ + for (i = 0; i < RTLX_CHANNELS; i++) { + init_waitqueue_head(&channel_wqs[i].rt_queue); + init_waitqueue_head(&channel_wqs[i].lx_queue); + } + + /* set up for interrupt handling */ + memset(&irq, 0, sizeof(struct irqaction)); + + if (cpu_has_vint) { + set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch); + } + + irq_num = MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ; + irq.handler = rtlx_interrupt; + irq.flags = SA_INTERRUPT; + irq.name = "RTLX"; + irq.dev_id = rtlx; + setup_irq(irq_num, &irq); + + rtlx = rtlxi; + return (0); +} + +/* only allow one open process at a time to open each channel */ +static int rtlx_open(struct inode *inode, struct file *filp) +{ + int minor, ret; + struct rtlx_channel *chan; + + /* assume only 1 device at the mo. */ + minor = MINOR(inode->i_rdev); + + if (rtlx == NULL) { + struct rtlx_info **p; + if( (p = vpe_get_shared(RTLX_TARG_VPE)) == NULL) { + printk(" vpe_get_shared is NULL. Has an SP program been loaded?\n"); + return (-EFAULT); + } + + if (*p == NULL) { + printk(" vpe_shared %p %p\n", p, *p); + return (-EFAULT); + } + + if ((ret = rtlx_init(*p)) < 0) + return (ret); + } + + chan = &rtlx->channel[minor]; + + /* already open? */ + if (chan->lx_state == RTLX_STATE_OPENED) + return (-EBUSY); + + chan->lx_state = RTLX_STATE_OPENED; + return (0); +} + +static int rtlx_release(struct inode *inode, struct file *filp) +{ + int minor; + + minor = MINOR(inode->i_rdev); + rtlx->channel[minor].lx_state = RTLX_STATE_UNUSED; + return (0); +} + +static unsigned int rtlx_poll(struct file *file, poll_table * wait) +{ + int minor; + unsigned int mask = 0; + struct rtlx_channel *chan; + + minor = MINOR(file->f_dentry->d_inode->i_rdev); + chan = &rtlx->channel[minor]; + + poll_wait(file, &channel_wqs[minor].rt_queue, wait); + poll_wait(file, &channel_wqs[minor].lx_queue, wait); + + /* data available to read? */ + if (chan->lx_read != chan->lx_write) + mask |= POLLIN | POLLRDNORM; + + /* space to write */ + if (spacefree(chan->rt_read, chan->rt_write, chan->buffer_size)) + mask |= POLLOUT | POLLWRNORM; + + return (mask); +} + +static ssize_t rtlx_read(struct file *file, char __user * buffer, size_t count, + loff_t * ppos) +{ + size_t fl = 0L; + int minor; + struct rtlx_channel *lx; + DECLARE_WAITQUEUE(wait, current); + + minor = MINOR(file->f_dentry->d_inode->i_rdev); + lx = &rtlx->channel[minor]; + + /* data available? */ + if (lx->lx_write == lx->lx_read) { + if (file->f_flags & O_NONBLOCK) + return (0); // -EAGAIN makes cat whinge + + /* go to sleep */ + add_wait_queue(&channel_wqs[minor].lx_queue, &wait); + set_current_state(TASK_INTERRUPTIBLE); + + while (lx->lx_write == lx->lx_read) + schedule(); + + set_current_state(TASK_RUNNING); + remove_wait_queue(&channel_wqs[minor].lx_queue, &wait); + + /* back running */ + } + + /* find out how much in total */ + count = min( count, + (size_t)(lx->lx_write + lx->buffer_size - lx->lx_read) % lx->buffer_size); + + /* then how much from the read pointer onwards */ + fl = min( count, (size_t)lx->buffer_size - lx->lx_read); + + copy_to_user (buffer, &lx->lx_buffer[lx->lx_read], fl); + + /* and if there is anything left at the beginning of the buffer */ + if ( count - fl ) + copy_to_user (buffer + fl, lx->lx_buffer, count - fl); + + /* update the index */ + lx->lx_read += count; + lx->lx_read %= lx->buffer_size; + + return (count); +} + +static inline int spacefree(int read, int write, int size) +{ + if (read == write) { + /* never fill the buffer completely, so indexes are always equal if empty + and only empty, or !equal if data available */ + return (size - 1); + } + + return ((read + size - write) % size) - 1; +} + +static ssize_t rtlx_write(struct file *file, const char __user * buffer, + size_t count, loff_t * ppos) +{ + int minor; + struct rtlx_channel *rt; + size_t fl; + DECLARE_WAITQUEUE(wait, current); + + minor = MINOR(file->f_dentry->d_inode->i_rdev); + rt = &rtlx->channel[minor]; + + /* any space left... */ + if (!spacefree(rt->rt_read, rt->rt_write, rt->buffer_size)) { + + if (file->f_flags & O_NONBLOCK) + return (-EAGAIN); + + add_wait_queue(&channel_wqs[minor].rt_queue, &wait); + set_current_state(TASK_INTERRUPTIBLE); + + while (!spacefree(rt->rt_read, rt->rt_write, rt->buffer_size)) + schedule(); + + set_current_state(TASK_RUNNING); + remove_wait_queue(&channel_wqs[minor].rt_queue, &wait); + } + + /* total number of bytes to copy */ + count = min( count, (size_t)spacefree(rt->rt_read, rt->rt_write, rt->buffer_size) ); + + /* first bit from write pointer to the end of the buffer, or count */ + fl = min(count, (size_t) rt->buffer_size - rt->rt_write); + + copy_from_user(&rt->rt_buffer[rt->rt_write], buffer, fl); + + /* if there's any left copy to the beginning of the buffer */ + if( count - fl ) + copy_from_user(rt->rt_buffer, buffer + fl, count - fl); + + rt->rt_write += count; + rt->rt_write %= rt->buffer_size; + + return(count); +} + +static struct file_operations rtlx_fops = { + .owner = THIS_MODULE, + .open = rtlx_open, + .release = rtlx_release, + .write = rtlx_write, + .read = rtlx_read, + .poll = rtlx_poll +}; + +static int rtlx_module_init(void) +{ + if ((major = register_chrdev(RTLX_MAJOR, module_name, &rtlx_fops)) < 0) { + printk("rtlx_module_init: unable to register device\n"); + return (-EBUSY); + } + + if (major == 0) + major = RTLX_MAJOR; + + return (0); +} + +static void rtlx_module_exit(void) +{ + unregister_chrdev(major, module_name); +} + +module_init(rtlx_module_init); +module_exit(rtlx_module_exit); +MODULE_DESCRIPTION("MIPS RTLX"); +MODULE_AUTHOR("Elizabeth Clarke, MIPS Technologies, Inc"); +MODULE_LICENSE("GPL"); diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index 17b5030fb6ea..4dd8e8b4fbc2 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -578,7 +578,7 @@ einval: li v0, -EINVAL sys sys_fremovexattr 2 /* 4235 */ sys sys_tkill 2 sys sys_sendfile64 5 - sys sys_futex 2 + sys sys_futex 6 sys sys_sched_setaffinity 3 sys sys_sched_getaffinity 3 /* 4240 */ sys sys_io_setup 2 @@ -587,7 +587,7 @@ einval: li v0, -EINVAL sys sys_io_submit 3 sys sys_io_cancel 3 /* 4245 */ sys sys_exit_group 1 - sys sys_lookup_dcookie 3 + sys sys_lookup_dcookie 4 sys sys_epoll_create 1 sys sys_epoll_ctl 4 sys sys_epoll_wait 3 /* 4250 */ @@ -618,12 +618,15 @@ einval: li v0, -EINVAL sys sys_mq_notify 2 /* 4275 */ sys sys_mq_getsetattr 3 sys sys_ni_syscall 0 /* sys_vserver */ - sys sys_waitid 4 + sys sys_waitid 5 sys sys_ni_syscall 0 /* available, was setaltroot */ - sys sys_add_key 5 + sys sys_add_key 5 /* 4280 */ sys sys_request_key 4 sys sys_keyctl 5 - + sys sys_set_thread_area 1 + sys sys_inotify_init 0 + sys sys_inotify_add_watch 3 /* 4285 */ + sys sys_inotify_rm_watch 2 .endm /* We pre-compute the number of _instruction_ bytes needed to diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index ffb22a2068bf..9085838d6ce3 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -449,3 +449,7 @@ sys_call_table: PTR sys_add_key PTR sys_request_key /* 5240 */ PTR sys_keyctl + PTR sys_set_thread_area + PTR sys_inotify_init + PTR sys_inotify_add_watch + PTR sys_inotify_rm_watch /* 5245 */ diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index e52049c87bc3..7e66eb823bf6 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -176,7 +176,7 @@ EXPORT(sysn32_call_table) PTR sys_fork PTR sys32_execve PTR sys_exit - PTR sys32_wait4 + PTR compat_sys_wait4 PTR sys_kill /* 6060 */ PTR sys32_newuname PTR sys_semget @@ -216,7 +216,7 @@ EXPORT(sysn32_call_table) PTR compat_sys_getrusage PTR sys32_sysinfo PTR compat_sys_times - PTR sys_ptrace + PTR sys32_ptrace PTR sys_getuid /* 6100 */ PTR sys_syslog PTR sys_getgid @@ -243,14 +243,14 @@ EXPORT(sysn32_call_table) PTR sys_capget PTR sys_capset PTR sys32_rt_sigpending /* 6125 */ - PTR compat_sys_rt_sigtimedwait - PTR sys32_rt_sigqueueinfo + PTR sysn32_rt_sigtimedwait + PTR sys_rt_sigqueueinfo PTR sys32_rt_sigsuspend PTR sys32_sigaltstack PTR compat_sys_utime /* 6130 */ PTR sys_mknod PTR sys32_personality - PTR sys_ustat + PTR sys32_ustat PTR compat_sys_statfs PTR compat_sys_fstatfs /* 6135 */ PTR sys_sysfs @@ -329,7 +329,7 @@ EXPORT(sysn32_call_table) PTR sys_epoll_wait PTR sys_remap_file_pages /* 6210 */ PTR sysn32_rt_sigreturn - PTR sys_fcntl + PTR compat_sys_fcntl64 PTR sys_set_tid_address PTR sys_restart_syscall PTR sys_semtimedop /* 6215 */ @@ -337,15 +337,15 @@ EXPORT(sysn32_call_table) PTR compat_sys_statfs64 PTR compat_sys_fstatfs64 PTR sys_sendfile64 - PTR sys_timer_create /* 6220 */ - PTR sys_timer_settime - PTR sys_timer_gettime + PTR sys32_timer_create /* 6220 */ + PTR compat_sys_timer_settime + PTR compat_sys_timer_gettime PTR sys_timer_getoverrun PTR sys_timer_delete - PTR sys_clock_settime /* 6225 */ - PTR sys_clock_gettime - PTR sys_clock_getres - PTR sys_clock_nanosleep + PTR compat_sys_clock_settime /* 6225 */ + PTR compat_sys_clock_gettime + PTR compat_sys_clock_getres + PTR compat_sys_clock_nanosleep PTR sys_tgkill PTR compat_sys_utimes /* 6230 */ PTR sys_ni_syscall /* sys_mbind */ @@ -358,8 +358,12 @@ EXPORT(sysn32_call_table) PTR compat_sys_mq_notify PTR compat_sys_mq_getsetattr PTR sys_ni_syscall /* 6240, sys_vserver */ - PTR sys_waitid + PTR sysn32_waitid PTR sys_ni_syscall /* available, was setaltroot */ PTR sys_add_key PTR sys_request_key PTR sys_keyctl /* 6245 */ + PTR sys_set_thread_area + PTR sys_inotify_init + PTR sys_inotify_add_watch + PTR sys_inotify_rm_watch diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 739f3998d76b..5a16401e443a 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -316,13 +316,13 @@ sys_call_table: PTR sys_vhangup PTR sys_ni_syscall /* was sys_idle */ PTR sys_ni_syscall /* sys_vm86 */ - PTR sys32_wait4 + PTR compat_sys_wait4 PTR sys_swapoff /* 4115 */ PTR sys32_sysinfo PTR sys32_ipc PTR sys_fsync PTR sys32_sigreturn - PTR sys_clone /* 4120 */ + PTR sys32_clone /* 4120 */ PTR sys_setdomainname PTR sys32_newuname PTR sys_ni_syscall /* sys_modify_ldt */ @@ -391,7 +391,7 @@ sys_call_table: PTR sys_getresuid PTR sys_ni_syscall /* was query_module */ PTR sys_poll - PTR sys_nfsservctl + PTR compat_sys_nfsservctl PTR sys_setresgid /* 4190 */ PTR sys_getresgid PTR sys_prctl @@ -459,7 +459,7 @@ sys_call_table: PTR sys_fadvise64_64 PTR compat_sys_statfs64 /* 4255 */ PTR compat_sys_fstatfs64 - PTR sys_timer_create + PTR sys32_timer_create PTR compat_sys_timer_settime PTR compat_sys_timer_gettime PTR sys_timer_getoverrun /* 4260 */ @@ -480,9 +480,13 @@ sys_call_table: PTR compat_sys_mq_notify /* 4275 */ PTR compat_sys_mq_getsetattr PTR sys_ni_syscall /* sys_vserver */ - PTR sys_waitid + PTR sys32_waitid PTR sys_ni_syscall /* available, was setaltroot */ PTR sys_add_key /* 4280 */ PTR sys_request_key PTR sys_keyctl + PTR sys_set_thread_area + PTR sys_inotify_init + PTR sys_inotify_add_watch /* 4285 */ + PTR sys_inotify_rm_watch .size sys_call_table,.-sys_call_table diff --git a/arch/mips/kernel/semaphore.c b/arch/mips/kernel/semaphore.c index 9c40fe5a8e8d..1265358cdca1 100644 --- a/arch/mips/kernel/semaphore.c +++ b/arch/mips/kernel/semaphore.c @@ -42,24 +42,28 @@ static inline int __sem_update_count(struct semaphore *sem, int incr) if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( - "1: ll %0, %2 \n" + " .set mips3 \n" + "1: ll %0, %2 # __sem_update_count \n" " sra %1, %0, 31 \n" " not %1 \n" " and %1, %0, %1 \n" - " add %1, %1, %3 \n" + " addu %1, %1, %3 \n" " sc %1, %2 \n" " beqzl %1, 1b \n" + " .set mips0 \n" : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) : "r" (incr), "m" (sem->count)); } else if (cpu_has_llsc) { __asm__ __volatile__( - "1: ll %0, %2 \n" + " .set mips3 \n" + "1: ll %0, %2 # __sem_update_count \n" " sra %1, %0, 31 \n" " not %1 \n" " and %1, %0, %1 \n" - " add %1, %1, %3 \n" + " addu %1, %1, %3 \n" " sc %1, %2 \n" " beqz %1, 1b \n" + " .set mips0 \n" : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) : "r" (incr), "m" (sem->count)); } else { diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 12b531c295c4..d86affa21278 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -37,12 +37,13 @@ #include <asm/addrspace.h> #include <asm/bootinfo.h> +#include <asm/cache.h> #include <asm/cpu.h> #include <asm/sections.h> #include <asm/setup.h> #include <asm/system.h> -struct cpuinfo_mips cpu_data[NR_CPUS]; +struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly; EXPORT_SYMBOL(cpu_data); @@ -62,8 +63,8 @@ EXPORT_SYMBOL(PCI_DMA_BUS_IS_PHYS); * * These are initialized so they are in the .data section */ -unsigned long mips_machtype = MACH_UNKNOWN; -unsigned long mips_machgroup = MACH_GROUP_UNKNOWN; +unsigned long mips_machtype __read_mostly = MACH_UNKNOWN; +unsigned long mips_machgroup __read_mostly = MACH_GROUP_UNKNOWN; EXPORT_SYMBOL(mips_machtype); EXPORT_SYMBOL(mips_machgroup); @@ -77,7 +78,7 @@ static char command_line[CL_SIZE]; * mips_io_port_base is the begin of the address space to which x86 style * I/O ports are mapped. */ -const unsigned long mips_io_port_base = -1; +const unsigned long mips_io_port_base __read_mostly = -1; EXPORT_SYMBOL(mips_io_port_base); /* @@ -510,31 +511,7 @@ static inline void resource_init(void) #undef MAXMEM #undef MAXMEM_PFN -static int __initdata earlyinit_debug; - -static int __init earlyinit_debug_setup(char *str) -{ - earlyinit_debug = 1; - return 1; -} -__setup("earlyinit_debug", earlyinit_debug_setup); - -extern initcall_t __earlyinitcall_start, __earlyinitcall_end; - -static void __init do_earlyinitcalls(void) -{ - initcall_t *call, *start, *end; - - start = &__earlyinitcall_start; - end = &__earlyinitcall_end; - - for (call = start; call < end; call++) { - if (earlyinit_debug) - printk("calling earlyinitcall 0x%p\n", *call); - - (*call)(); - } -} +extern void plat_setup(void); void __init setup_arch(char **cmdline_p) { @@ -551,7 +528,7 @@ void __init setup_arch(char **cmdline_p) #endif /* call board setup routine */ - do_earlyinitcalls(); + plat_setup(); strlcpy(command_line, arcs_cmdline, sizeof(command_line)); strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE); @@ -573,3 +550,12 @@ int __init fpu_disable(char *s) } __setup("nofpu", fpu_disable); + +int __init dsp_disable(char *s) +{ + cpu_data[0].ases &= ~MIPS_ASE_DSP; + + return 1; +} + +__setup("nodsp", dsp_disable); diff --git a/arch/mips/kernel/signal-common.h b/arch/mips/kernel/signal-common.h index f9234df53253..0f66ae5838b9 100644 --- a/arch/mips/kernel/signal-common.h +++ b/arch/mips/kernel/signal-common.h @@ -8,13 +8,14 @@ * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ +#include <linux/config.h> + static inline int setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc) { int err = 0; err |= __put_user(regs->cp0_epc, &sc->sc_pc); - err |= __put_user(regs->cp0_status, &sc->sc_status); #define save_gp_reg(i) do { \ err |= __put_user(regs->regs[i], &sc->sc_regs[i]); \ @@ -30,10 +31,32 @@ setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc) save_gp_reg(31); #undef save_gp_reg +#ifdef CONFIG_32BIT err |= __put_user(regs->hi, &sc->sc_mdhi); err |= __put_user(regs->lo, &sc->sc_mdlo); - err |= __put_user(regs->cp0_cause, &sc->sc_cause); - err |= __put_user(regs->cp0_badvaddr, &sc->sc_badvaddr); + if (cpu_has_dsp) { + err |= __put_user(mfhi1(), &sc->sc_hi1); + err |= __put_user(mflo1(), &sc->sc_lo1); + err |= __put_user(mfhi2(), &sc->sc_hi2); + err |= __put_user(mflo2(), &sc->sc_lo2); + err |= __put_user(mfhi3(), &sc->sc_hi3); + err |= __put_user(mflo3(), &sc->sc_lo3); + err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp); + } +#endif +#ifdef CONFIG_64BIT + err |= __put_user(regs->hi, &sc->sc_hi[0]); + err |= __put_user(regs->lo, &sc->sc_lo[0]); + if (cpu_has_dsp) { + err |= __put_user(mfhi1(), &sc->sc_hi[1]); + err |= __put_user(mflo1(), &sc->sc_lo[1]); + err |= __put_user(mfhi2(), &sc->sc_hi[2]); + err |= __put_user(mflo2(), &sc->sc_lo[2]); + err |= __put_user(mfhi3(), &sc->sc_hi[3]); + err |= __put_user(mflo3(), &sc->sc_lo[3]); + err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp); + } +#endif err |= __put_user(!!used_math(), &sc->sc_used_math); @@ -61,15 +84,40 @@ out: static inline int restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) { - int err = 0; unsigned int used_math; + unsigned long treg; + int err = 0; /* Always make any pending restarted system calls return -EINTR */ current_thread_info()->restart_block.fn = do_no_restart_syscall; err |= __get_user(regs->cp0_epc, &sc->sc_pc); +#ifdef CONFIG_32BIT err |= __get_user(regs->hi, &sc->sc_mdhi); err |= __get_user(regs->lo, &sc->sc_mdlo); + if (cpu_has_dsp) { + err |= __get_user(treg, &sc->sc_hi1); mthi1(treg); + err |= __get_user(treg, &sc->sc_lo1); mtlo1(treg); + err |= __get_user(treg, &sc->sc_hi2); mthi2(treg); + err |= __get_user(treg, &sc->sc_lo2); mtlo2(treg); + err |= __get_user(treg, &sc->sc_hi3); mthi3(treg); + err |= __get_user(treg, &sc->sc_lo3); mtlo3(treg); + err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK); + } +#endif +#ifdef CONFIG_64BIT + err |= __get_user(regs->hi, &sc->sc_hi[0]); + err |= __get_user(regs->lo, &sc->sc_lo[0]); + if (cpu_has_dsp) { + err |= __get_user(treg, &sc->sc_hi[1]); mthi1(treg); + err |= __get_user(treg, &sc->sc_lo[1]); mthi1(treg); + err |= __get_user(treg, &sc->sc_hi[2]); mthi2(treg); + err |= __get_user(treg, &sc->sc_lo[2]); mthi2(treg); + err |= __get_user(treg, &sc->sc_hi[3]); mthi3(treg); + err |= __get_user(treg, &sc->sc_lo[3]); mthi3(treg); + err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK); + } +#endif #define restore_gp_reg(i) do { \ err |= __get_user(regs->regs[i], &sc->sc_regs[i]); \ @@ -112,7 +160,7 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) static inline void * get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) { - unsigned long sp, almask; + unsigned long sp; /* Default to using normal stack */ sp = regs->regs[29]; @@ -128,10 +176,32 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0)) sp = current->sas_ss_sp + current->sas_ss_size; - if (PLAT_TRAMPOLINE_STUFF_LINE) - almask = ~(PLAT_TRAMPOLINE_STUFF_LINE - 1); - else - almask = ALMASK; + return (void *)((sp - frame_size) & (ICACHE_REFILLS_WORKAROUND_WAR ? 32 : ALMASK)); +} + +static inline int install_sigtramp(unsigned int __user *tramp, + unsigned int syscall) +{ + int err; + + /* + * Set up the return code ... + * + * li v0, __NR__foo_sigreturn + * syscall + */ + + err = __put_user(0x24020000 + syscall, tramp + 0); + err |= __put_user(0x0000000c , tramp + 1); + if (ICACHE_REFILLS_WORKAROUND_WAR) { + err |= __put_user(0, tramp + 2); + err |= __put_user(0, tramp + 3); + err |= __put_user(0, tramp + 4); + err |= __put_user(0, tramp + 5); + err |= __put_user(0, tramp + 6); + err |= __put_user(0, tramp + 7); + } + flush_cache_sigtramp((unsigned long) tramp); - return (void *)((sp - frame_size) & almask); + return err; } diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index 0209c1dd1429..9202a17db8f7 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -8,6 +8,7 @@ * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ #include <linux/config.h> +#include <linux/cache.h> #include <linux/sched.h> #include <linux/mm.h> #include <linux/personality.h> @@ -21,6 +22,7 @@ #include <linux/unistd.h> #include <linux/compiler.h> +#include <asm/abi.h> #include <asm/asm.h> #include <linux/bitops.h> #include <asm/cacheflush.h> @@ -29,6 +31,7 @@ #include <asm/uaccess.h> #include <asm/ucontext.h> #include <asm/cpu-features.h> +#include <asm/war.h> #include "signal-common.h" @@ -36,7 +39,7 @@ #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) -static int do_signal(sigset_t *oldset, struct pt_regs *regs); +int do_signal(sigset_t *oldset, struct pt_regs *regs); /* * Atomically swap in the new signal mask, and wait for a signal. @@ -47,9 +50,10 @@ save_static_function(sys_sigsuspend); __attribute_used__ noinline static int _sys_sigsuspend(nabi_no_regargs struct pt_regs regs) { - sigset_t *uset, saveset, newset; + sigset_t saveset, newset; + sigset_t __user *uset; - uset = (sigset_t *) regs.regs[4]; + uset = (sigset_t __user *) regs.regs[4]; if (copy_from_user(&newset, uset, sizeof(sigset_t))) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); @@ -75,7 +79,8 @@ save_static_function(sys_rt_sigsuspend); __attribute_used__ noinline static int _sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) { - sigset_t *unewset, saveset, newset; + sigset_t saveset, newset; + sigset_t __user *unewset; size_t sigsetsize; /* XXX Don't preclude handling different sized sigset_t's. */ @@ -83,7 +88,7 @@ _sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) if (sigsetsize != sizeof(sigset_t)) return -EINVAL; - unewset = (sigset_t *) regs.regs[4]; + unewset = (sigset_t __user *) regs.regs[4]; if (copy_from_user(&newset, unewset, sizeof(newset))) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); @@ -147,33 +152,46 @@ asmlinkage int sys_sigaction(int sig, const struct sigaction *act, asmlinkage int sys_sigaltstack(nabi_no_regargs struct pt_regs regs) { - const stack_t *uss = (const stack_t *) regs.regs[4]; - stack_t *uoss = (stack_t *) regs.regs[5]; + const stack_t __user *uss = (const stack_t __user *) regs.regs[4]; + stack_t __user *uoss = (stack_t __user *) regs.regs[5]; unsigned long usp = regs.regs[29]; return do_sigaltstack(uss, uoss, usp); } -#if PLAT_TRAMPOLINE_STUFF_LINE -#define __tramp __attribute__((aligned(PLAT_TRAMPOLINE_STUFF_LINE))) -#else -#define __tramp -#endif - +/* + * Horribly complicated - with the bloody RM9000 workarounds enabled + * the signal trampolines is moving to the end of the structure so we can + * increase the alignment without breaking software compatibility. + */ #ifdef CONFIG_TRAD_SIGNALS struct sigframe { u32 sf_ass[4]; /* argument save space for o32 */ - u32 sf_code[2] __tramp; /* signal trampoline */ - struct sigcontext sf_sc __tramp; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 sf_pad[2]; +#else + u32 sf_code[2]; /* signal trampoline */ +#endif + struct sigcontext sf_sc; sigset_t sf_mask; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 sf_code[8] ____cacheline_aligned; /* signal trampoline */ +#endif }; #endif struct rt_sigframe { u32 rs_ass[4]; /* argument save space for o32 */ - u32 rs_code[2] __tramp; /* signal trampoline */ - struct siginfo rs_info __tramp; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_pad[2]; +#else + u32 rs_code[2]; /* signal trampoline */ +#endif + struct siginfo rs_info; struct ucontext rs_uc; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_code[8] ____cacheline_aligned; /* signal trampoline */ +#endif }; #ifdef CONFIG_TRAD_SIGNALS @@ -214,7 +232,7 @@ _sys_sigreturn(nabi_no_regargs struct pt_regs regs) badframe: force_sig(SIGSEGV, current); } -#endif +#endif /* CONFIG_TRAD_SIGNALS */ save_static_function(sys_rt_sigreturn); __attribute_used__ noinline static void @@ -260,7 +278,7 @@ badframe: } #ifdef CONFIG_TRAD_SIGNALS -static void inline setup_frame(struct k_sigaction * ka, struct pt_regs *regs, +int setup_frame(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set) { struct sigframe *frame; @@ -270,17 +288,7 @@ static void inline setup_frame(struct k_sigaction * ka, struct pt_regs *regs, if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - /* - * Set up the return code ... - * - * li v0, __NR_sigreturn - * syscall - */ - if (PLAT_TRAMPOLINE_STUFF_LINE) - __clear_user(frame->sf_code, PLAT_TRAMPOLINE_STUFF_LINE); - err |= __put_user(0x24020000 + __NR_sigreturn, frame->sf_code + 0); - err |= __put_user(0x0000000c , frame->sf_code + 1); - flush_cache_sigtramp((unsigned long) frame->sf_code); + install_sigtramp(frame->sf_code, __NR_sigreturn); err |= setup_sigcontext(regs, &frame->sf_sc); err |= __copy_to_user(&frame->sf_mask, set, sizeof(*set)); @@ -309,14 +317,15 @@ static void inline setup_frame(struct k_sigaction * ka, struct pt_regs *regs, current->comm, current->pid, frame, regs->cp0_epc, frame->regs[31]); #endif - return; + return 1; give_sigsegv: force_sigsegv(signr, current); + return 0; } #endif -static void inline setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, +int setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info) { struct rt_sigframe *frame; @@ -326,17 +335,7 @@ static void inline setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - /* - * Set up the return code ... - * - * li v0, __NR_rt_sigreturn - * syscall - */ - if (PLAT_TRAMPOLINE_STUFF_LINE) - __clear_user(frame->rs_code, PLAT_TRAMPOLINE_STUFF_LINE); - err |= __put_user(0x24020000 + __NR_rt_sigreturn, frame->rs_code + 0); - err |= __put_user(0x0000000c , frame->rs_code + 1); - flush_cache_sigtramp((unsigned long) frame->rs_code); + install_sigtramp(frame->rs_code, __NR_rt_sigreturn); /* Create siginfo. */ err |= copy_siginfo_to_user(&frame->rs_info, info); @@ -378,18 +377,21 @@ static void inline setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, current->comm, current->pid, frame, regs->cp0_epc, regs->regs[31]); #endif - return; + return 1; give_sigsegv: force_sigsegv(signr, current); + return 0; } extern void setup_rt_frame_n32(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info); -static inline void handle_signal(unsigned long sig, siginfo_t *info, +static inline int handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka, sigset_t *oldset, struct pt_regs *regs) { + int ret; + switch(regs->regs[0]) { case ERESTART_RESTARTBLOCK: case ERESTARTNOHAND: @@ -408,22 +410,10 @@ static inline void handle_signal(unsigned long sig, siginfo_t *info, regs->regs[0] = 0; /* Don't deal with this again. */ -#ifdef CONFIG_TRAD_SIGNALS - if (ka->sa.sa_flags & SA_SIGINFO) { -#else - if (1) { -#endif -#ifdef CONFIG_MIPS32_N32 - if ((current->thread.mflags & MF_ABI_MASK) == MF_N32) - setup_rt_frame_n32 (ka, regs, sig, oldset, info); - else -#endif - setup_rt_frame(ka, regs, sig, oldset, info); - } -#ifdef CONFIG_TRAD_SIGNALS + if (sig_uses_siginfo(ka)) + ret = current->thread.abi->setup_rt_frame(ka, regs, sig, oldset, info); else - setup_frame(ka, regs, sig, oldset); -#endif + ret = current->thread.abi->setup_frame(ka, regs, sig, oldset); spin_lock_irq(¤t->sighand->siglock); sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); @@ -431,23 +421,16 @@ static inline void handle_signal(unsigned long sig, siginfo_t *info, sigaddset(¤t->blocked,sig); recalc_sigpending(); spin_unlock_irq(¤t->sighand->siglock); -} -extern int do_signal32(sigset_t *oldset, struct pt_regs *regs); -extern int do_irix_signal(sigset_t *oldset, struct pt_regs *regs); + return ret; +} -static int do_signal(sigset_t *oldset, struct pt_regs *regs) +int do_signal(sigset_t *oldset, struct pt_regs *regs) { struct k_sigaction ka; siginfo_t info; int signr; -#ifdef CONFIG_BINFMT_ELF32 - if ((current->thread.mflags & MF_ABI_MASK) == MF_O32) { - return do_signal32(oldset, regs); - } -#endif - /* * We want the common case to go fast, which is why we may in certain * cases get here from kernel mode. Just return without doing anything @@ -463,10 +446,8 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs) oldset = ¤t->blocked; signr = get_signal_to_deliver(&info, &ka, regs, NULL); - if (signr > 0) { - handle_signal(signr, &info, &ka, oldset, regs); - return 1; - } + if (signr > 0) + return handle_signal(signr, &info, &ka, oldset, regs); no_signal: /* @@ -499,18 +480,6 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, sigset_t *oldset, { /* deal with pending signal delivery */ if (thread_info_flags & _TIF_SIGPENDING) { -#ifdef CONFIG_BINFMT_ELF32 - if (likely((current->thread.mflags & MF_ABI_MASK) == MF_O32)) { - do_signal32(oldset, regs); - return; - } -#endif -#ifdef CONFIG_BINFMT_IRIX - if (unlikely(current->personality != PER_LINUX)) { - do_irix_signal(oldset, regs); - return; - } -#endif - do_signal(oldset, regs); + current->thread.abi->do_signal(oldset, regs); } } diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 8ddfbd8d425a..dbe821303125 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -7,6 +7,7 @@ * Copyright (C) 1994 - 2000 Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ +#include <linux/cache.h> #include <linux/sched.h> #include <linux/mm.h> #include <linux/smp.h> @@ -21,6 +22,7 @@ #include <linux/suspend.h> #include <linux/compiler.h> +#include <asm/abi.h> #include <asm/asm.h> #include <linux/bitops.h> #include <asm/cacheflush.h> @@ -29,6 +31,7 @@ #include <asm/ucontext.h> #include <asm/system.h> #include <asm/fpu.h> +#include <asm/war.h> #define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3) @@ -76,8 +79,10 @@ typedef struct compat_siginfo { /* POSIX.1b timers */ struct { - unsigned int _timer1; - unsigned int _timer2; + timer_t _tid; /* timer id */ + int _overrun; /* overrun count */ + compat_sigval_t _sigval;/* same as below */ + int _sys_private; /* not to be passed to user */ } _timer; /* POSIX.1b signals */ @@ -259,11 +264,12 @@ asmlinkage int sys32_sigaction(int sig, const struct sigaction32 *act, if (act) { old_sigset_t mask; + s32 handler; if (!access_ok(VERIFY_READ, act, sizeof(*act))) return -EFAULT; - err |= __get_user((u32)(u64)new_ka.sa.sa_handler, - &act->sa_handler); + err |= __get_user(handler, &act->sa_handler); + new_ka.sa.sa_handler = (void*)(s64)handler; err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags); err |= __get_user(mask, &act->sa_mask.sig[0]); if (err) @@ -331,8 +337,9 @@ asmlinkage int sys32_sigaltstack(nabi_no_regargs struct pt_regs regs) static int restore_sigcontext32(struct pt_regs *regs, struct sigcontext32 *sc) { + u32 used_math; int err = 0; - __u32 used_math; + s32 treg; /* Always make any pending restarted system calls return -EINTR */ current_thread_info()->restart_block.fn = do_no_restart_syscall; @@ -340,6 +347,15 @@ static int restore_sigcontext32(struct pt_regs *regs, struct sigcontext32 *sc) err |= __get_user(regs->cp0_epc, &sc->sc_pc); err |= __get_user(regs->hi, &sc->sc_mdhi); err |= __get_user(regs->lo, &sc->sc_mdlo); + if (cpu_has_dsp) { + err |= __get_user(treg, &sc->sc_hi1); mthi1(treg); + err |= __get_user(treg, &sc->sc_lo1); mtlo1(treg); + err |= __get_user(treg, &sc->sc_hi2); mthi2(treg); + err |= __get_user(treg, &sc->sc_lo2); mtlo2(treg); + err |= __get_user(treg, &sc->sc_hi3); mthi3(treg); + err |= __get_user(treg, &sc->sc_lo3); mtlo3(treg); + err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK); + } #define restore_gp_reg(i) do { \ err |= __get_user(regs->regs[i], &sc->sc_regs[i]); \ @@ -378,16 +394,30 @@ static int restore_sigcontext32(struct pt_regs *regs, struct sigcontext32 *sc) struct sigframe { u32 sf_ass[4]; /* argument save space for o32 */ +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 sf_pad[2]; +#else u32 sf_code[2]; /* signal trampoline */ +#endif struct sigcontext32 sf_sc; sigset_t sf_mask; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 sf_code[8] ____cacheline_aligned; /* signal trampoline */ +#endif }; struct rt_sigframe32 { u32 rs_ass[4]; /* argument save space for o32 */ +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_pad[2]; +#else u32 rs_code[2]; /* signal trampoline */ +#endif compat_siginfo_t rs_info; struct ucontext32 rs_uc; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_code[8] __attribute__((aligned(32))); /* signal trampoline */ +#endif }; int copy_siginfo_to_user32(compat_siginfo_t *to, siginfo_t *from) @@ -411,6 +441,11 @@ int copy_siginfo_to_user32(compat_siginfo_t *to, siginfo_t *from) err |= __copy_to_user(&to->_sifields._pad, &from->_sifields._pad, SI_PAD_SIZE); else { switch (from->si_code >> 16) { + case __SI_TIMER >> 16: + err |= __put_user(from->si_tid, &to->si_tid); + err |= __put_user(from->si_overrun, &to->si_overrun); + err |= __put_user(from->si_int, &to->si_int); + break; case __SI_CHLD >> 16: err |= __put_user(from->si_utime, &to->si_utime); err |= __put_user(from->si_stime, &to->si_stime); @@ -480,6 +515,7 @@ __attribute_used__ noinline static void _sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) { struct rt_sigframe32 *frame; + mm_segment_t old_fs; sigset_t set; stack_t st; s32 sp; @@ -510,7 +546,10 @@ _sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) /* It is more difficult to avoid calling this function than to call it and ignore errors. */ + old_fs = get_fs(); + set_fs (KERNEL_DS); do_sigaltstack(&st, NULL, regs.regs[29]); + set_fs (old_fs); /* * Don't let your children do this ... @@ -550,8 +589,15 @@ static inline int setup_sigcontext32(struct pt_regs *regs, err |= __put_user(regs->hi, &sc->sc_mdhi); err |= __put_user(regs->lo, &sc->sc_mdlo); - err |= __put_user(regs->cp0_cause, &sc->sc_cause); - err |= __put_user(regs->cp0_badvaddr, &sc->sc_badvaddr); + if (cpu_has_dsp) { + err |= __put_user(rddsp(DSP_MASK), &sc->sc_hi1); + err |= __put_user(mfhi1(), &sc->sc_hi1); + err |= __put_user(mflo1(), &sc->sc_lo1); + err |= __put_user(mfhi2(), &sc->sc_hi2); + err |= __put_user(mflo2(), &sc->sc_lo2); + err |= __put_user(mfhi3(), &sc->sc_hi3); + err |= __put_user(mflo3(), &sc->sc_lo3); + } err |= __put_user(!!used_math(), &sc->sc_used_math); @@ -601,7 +647,7 @@ static inline void *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, return (void *)((sp - frame_size) & ALMASK); } -static inline void setup_frame(struct k_sigaction * ka, struct pt_regs *regs, +void setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set) { struct sigframe *frame; @@ -654,9 +700,7 @@ give_sigsegv: force_sigsegv(signr, current); } -static inline void setup_rt_frame(struct k_sigaction * ka, - struct pt_regs *regs, int signr, - sigset_t *set, siginfo_t *info) +void setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info) { struct rt_sigframe32 *frame; int err = 0; @@ -725,9 +769,11 @@ give_sigsegv: force_sigsegv(signr, current); } -static inline void handle_signal(unsigned long sig, siginfo_t *info, +static inline int handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka, sigset_t *oldset, struct pt_regs * regs) { + int ret; + switch (regs->regs[0]) { case ERESTART_RESTARTBLOCK: case ERESTARTNOHAND: @@ -747,9 +793,9 @@ static inline void handle_signal(unsigned long sig, siginfo_t *info, regs->regs[0] = 0; /* Don't deal with this again. */ if (ka->sa.sa_flags & SA_SIGINFO) - setup_rt_frame(ka, regs, sig, oldset, info); + ret = current->thread.abi->setup_rt_frame(ka, regs, sig, oldset, info); else - setup_frame(ka, regs, sig, oldset); + ret = current->thread.abi->setup_frame(ka, regs, sig, oldset); spin_lock_irq(¤t->sighand->siglock); sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); @@ -757,6 +803,8 @@ static inline void handle_signal(unsigned long sig, siginfo_t *info, sigaddset(¤t->blocked,sig); recalc_sigpending(); spin_unlock_irq(¤t->sighand->siglock); + + return ret; } int do_signal32(sigset_t *oldset, struct pt_regs *regs) @@ -780,10 +828,8 @@ int do_signal32(sigset_t *oldset, struct pt_regs *regs) oldset = ¤t->blocked; signr = get_signal_to_deliver(&info, &ka, regs, NULL); - if (signr > 0) { - handle_signal(signr, &info, &ka, oldset, regs); - return 1; - } + if (signr > 0) + return handle_signal(signr, &info, &ka, oldset, regs); no_signal: /* @@ -819,12 +865,13 @@ asmlinkage int sys32_rt_sigaction(int sig, const struct sigaction32 *act, goto out; if (act) { + s32 handler; int err = 0; if (!access_ok(VERIFY_READ, act, sizeof(*act))) return -EFAULT; - err |= __get_user((u32)(u64)new_sa.sa.sa_handler, - &act->sa_handler); + err |= __get_user(handler, &act->sa_handler); + new_sa.sa.sa_handler = (void*)(s64)handler; err |= __get_user(new_sa.sa.sa_flags, &act->sa_flags); err |= get_sigset(&new_sa.sa.sa_mask, &act->sa_mask); if (err) @@ -902,3 +949,30 @@ asmlinkage int sys32_rt_sigqueueinfo(int pid, int sig, compat_siginfo_t *uinfo) set_fs (old_fs); return ret; } + +asmlinkage long +sys32_waitid(int which, compat_pid_t pid, + compat_siginfo_t __user *uinfo, int options, + struct compat_rusage __user *uru) +{ + siginfo_t info; + struct rusage ru; + long ret; + mm_segment_t old_fs = get_fs(); + + info.si_signo = 0; + set_fs (KERNEL_DS); + ret = sys_waitid(which, pid, (siginfo_t __user *) &info, options, + uru ? (struct rusage __user *) &ru : NULL); + set_fs (old_fs); + + if (ret < 0 || info.si_signo == 0) + return ret; + + if (uru && (ret = put_compat_rusage(&ru, uru))) + return ret; + + BUG_ON(info.si_code & __SI_MASK); + info.si_code |= __SI_CHLD; + return copy_siginfo_to_user32(uinfo, &info); +} diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c index 3544208d4b4b..ec61b2670ba6 100644 --- a/arch/mips/kernel/signal_n32.c +++ b/arch/mips/kernel/signal_n32.c @@ -15,6 +15,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#include <linux/cache.h> +#include <linux/sched.h> #include <linux/sched.h> #include <linux/mm.h> #include <linux/smp.h> @@ -36,6 +38,7 @@ #include <asm/system.h> #include <asm/fpu.h> #include <asm/cpu-features.h> +#include <asm/war.h> #include "signal-common.h" @@ -62,17 +65,18 @@ struct ucontextn32 { sigset_t uc_sigmask; /* mask last for extensibility */ }; -#if PLAT_TRAMPOLINE_STUFF_LINE -#define __tramp __attribute__((aligned(PLAT_TRAMPOLINE_STUFF_LINE))) -#else -#define __tramp -#endif - struct rt_sigframe_n32 { u32 rs_ass[4]; /* argument save space for o32 */ - u32 rs_code[2] __tramp; /* signal trampoline */ - struct siginfo rs_info __tramp; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_pad[2]; +#else + u32 rs_code[2]; /* signal trampoline */ +#endif + struct siginfo rs_info; struct ucontextn32 rs_uc; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_code[8] ____cacheline_aligned; /* signal trampoline */ +#endif }; save_static_function(sysn32_rt_sigreturn); @@ -126,7 +130,7 @@ badframe: force_sig(SIGSEGV, current); } -void setup_rt_frame_n32(struct k_sigaction * ka, +int setup_rt_frame_n32(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info) { struct rt_sigframe_n32 *frame; @@ -137,17 +141,7 @@ void setup_rt_frame_n32(struct k_sigaction * ka, if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - /* - * Set up the return code ... - * - * li v0, __NR_rt_sigreturn - * syscall - */ - if (PLAT_TRAMPOLINE_STUFF_LINE) - __clear_user(frame->rs_code, PLAT_TRAMPOLINE_STUFF_LINE); - err |= __put_user(0x24020000 + __NR_N32_rt_sigreturn, frame->rs_code + 0); - err |= __put_user(0x0000000c , frame->rs_code + 1); - flush_cache_sigtramp((unsigned long) frame->rs_code); + install_sigtramp(frame->rs_code, __NR_N32_rt_sigreturn); /* Create siginfo. */ err |= copy_siginfo_to_user(&frame->rs_info, info); @@ -190,8 +184,9 @@ void setup_rt_frame_n32(struct k_sigaction * ka, current->comm, current->pid, frame, regs->cp0_epc, regs->regs[31]); #endif - return; + return 1; give_sigsegv: force_sigsegv(signr, current); + return 0; } diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index af5cd3b8a396..fcacf1aae98a 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -50,7 +50,6 @@ static void smp_tune_scheduling (void) { struct cache_desc *cd = ¤t_cpu_data.scache; unsigned long cachesize; /* kB */ - unsigned long bandwidth = 350; /* MB/s */ unsigned long cpu_khz; /* @@ -121,7 +120,19 @@ struct call_data_struct *call_data; * or are or have executed. * * You must not call this function with disabled interrupts or from a - * hardware interrupt handler or from a bottom half handler. + * hardware interrupt handler or from a bottom half handler: + * + * CPU A CPU B + * Disable interrupts + * smp_call_function() + * Take call_lock + * Send IPIs + * Wait for all cpus to acknowledge IPI + * CPU A has not responded, spin waiting + * for cpu A to respond, holding call_lock + * smp_call_function() + * Spin waiting for call_lock + * Deadlock Deadlock */ int smp_call_function (void (*func) (void *info), void *info, int retry, int wait) @@ -130,6 +141,11 @@ int smp_call_function (void (*func) (void *info), void *info, int retry, int i, cpus = num_online_cpus() - 1; int cpu = smp_processor_id(); + /* + * Can die spectacularly if this CPU isn't yet marked online + */ + BUG_ON(!cpu_online(cpu)); + if (!cpus) return 0; @@ -214,7 +230,6 @@ void __init smp_cpus_done(unsigned int max_cpus) /* called from main before smp_init() */ void __init smp_prepare_cpus(unsigned int max_cpus) { - cpu_data[0].udelay_val = loops_per_jiffy; init_new_context(current, &init_mm); current_thread_info()->cpu = 0; smp_tune_scheduling(); @@ -236,23 +251,28 @@ void __devinit smp_prepare_boot_cpu(void) } /* - * Startup the CPU with this logical number + * Called once for each "cpu_possible(cpu)". Needs to spin up the cpu + * and keep control until "cpu_online(cpu)" is set. Note: cpu is + * physical, not logical. */ -static int __init do_boot_cpu(int cpu) +int __devinit __cpu_up(unsigned int cpu) { struct task_struct *idle; /* + * Processor goes to start_secondary(), sets online flag * The following code is purely to make sure * Linux can schedule processes on this slave. */ idle = fork_idle(cpu); if (IS_ERR(idle)) - panic("failed fork for CPU %d\n", cpu); + panic(KERN_ERR "Fork failed for CPU %d", cpu); prom_boot_secondary(cpu, idle); - /* XXXKW timeout */ + /* + * Trust is futile. We should really have timeouts ... + */ while (!cpu_isset(cpu, cpu_callin_map)) udelay(100); @@ -261,23 +281,6 @@ static int __init do_boot_cpu(int cpu) return 0; } -/* - * Called once for each "cpu_possible(cpu)". Needs to spin up the cpu - * and keep control until "cpu_online(cpu)" is set. Note: cpu is - * physical, not logical. - */ -int __devinit __cpu_up(unsigned int cpu) -{ - int ret; - - /* Processor goes to start_secondary(), sets online flag */ - ret = do_boot_cpu(cpu); - if (ret < 0) - return ret; - - return 0; -} - /* Not really SMP stuff ... */ int setup_profiling_timer(unsigned int multiplier) { diff --git a/arch/mips/kernel/smp_mt.c b/arch/mips/kernel/smp_mt.c new file mode 100644 index 000000000000..d429544ba4bc --- /dev/null +++ b/arch/mips/kernel/smp_mt.c @@ -0,0 +1,366 @@ +/* + * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. + * + * Elizabeth Clarke (beth@mips.com) + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/cpumask.h> +#include <linux/interrupt.h> +#include <linux/compiler.h> + +#include <asm/atomic.h> +#include <asm/cpu.h> +#include <asm/processor.h> +#include <asm/system.h> +#include <asm/hardirq.h> +#include <asm/mmu_context.h> +#include <asm/smp.h> +#include <asm/time.h> +#include <asm/mipsregs.h> +#include <asm/mipsmtregs.h> +#include <asm/cacheflush.h> +#include <asm/mips-boards/maltaint.h> + +#define MIPS_CPU_IPI_RESCHED_IRQ 0 +#define MIPS_CPU_IPI_CALL_IRQ 1 + +static int cpu_ipi_resched_irq, cpu_ipi_call_irq; + +#if 0 +static void dump_mtregisters(int vpe, int tc) +{ + printk("vpe %d tc %d\n", vpe, tc); + + settc(tc); + + printk(" c0 status 0x%lx\n", read_vpe_c0_status()); + printk(" vpecontrol 0x%lx\n", read_vpe_c0_vpecontrol()); + printk(" vpeconf0 0x%lx\n", read_vpe_c0_vpeconf0()); + printk(" tcstatus 0x%lx\n", read_tc_c0_tcstatus()); + printk(" tcrestart 0x%lx\n", read_tc_c0_tcrestart()); + printk(" tcbind 0x%lx\n", read_tc_c0_tcbind()); + printk(" tchalt 0x%lx\n", read_tc_c0_tchalt()); +} +#endif + +void __init sanitize_tlb_entries(void) +{ + int i, tlbsiz; + unsigned long mvpconf0, ncpu; + + if (!cpu_has_mipsmt) + return; + + set_c0_mvpcontrol(MVPCONTROL_VPC); + + /* Disable TLB sharing */ + clear_c0_mvpcontrol(MVPCONTROL_STLB); + + mvpconf0 = read_c0_mvpconf0(); + + printk(KERN_INFO "MVPConf0 0x%lx TLBS %lx PTLBE %ld\n", mvpconf0, + (mvpconf0 & MVPCONF0_TLBS) >> MVPCONF0_TLBS_SHIFT, + (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT); + + tlbsiz = (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT; + ncpu = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; + + printk(" tlbsiz %d ncpu %ld\n", tlbsiz, ncpu); + + if (tlbsiz > 0) { + /* share them out across the vpe's */ + tlbsiz /= ncpu; + + printk(KERN_INFO "setting Config1.MMU_size to %d\n", tlbsiz); + + for (i = 0; i < ncpu; i++) { + settc(i); + + if (i == 0) + write_c0_config1((read_c0_config1() & ~(0x3f << 25)) | (tlbsiz << 25)); + else + write_vpe_c0_config1((read_vpe_c0_config1() & ~(0x3f << 25)) | + (tlbsiz << 25)); + } + } + + clear_c0_mvpcontrol(MVPCONTROL_VPC); +} + +#if 0 +/* + * Use c0_MVPConf0 to find out how many CPUs are available, setting up + * phys_cpu_present_map and the logical/physical mappings. + */ +void __init prom_build_cpu_map(void) +{ + int i, num, ncpus; + + cpus_clear(phys_cpu_present_map); + + /* assume we boot on cpu 0.... */ + cpu_set(0, phys_cpu_present_map); + __cpu_number_map[0] = 0; + __cpu_logical_map[0] = 0; + + if (cpu_has_mipsmt) { + ncpus = ((read_c0_mvpconf0() & (MVPCONF0_PVPE)) >> MVPCONF0_PVPE_SHIFT) + 1; + for (i=1, num=0; i< NR_CPUS && i<ncpus; i++) { + cpu_set(i, phys_cpu_present_map); + __cpu_number_map[i] = ++num; + __cpu_logical_map[num] = i; + } + + printk(KERN_INFO "%i available secondary CPU(s)\n", num); + } +} +#endif + +static void ipi_resched_dispatch (struct pt_regs *regs) +{ + do_IRQ(MIPS_CPU_IPI_RESCHED_IRQ, regs); +} + +static void ipi_call_dispatch (struct pt_regs *regs) +{ + do_IRQ(MIPS_CPU_IPI_CALL_IRQ, regs); +} + +irqreturn_t ipi_resched_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + return IRQ_HANDLED; +} + +irqreturn_t ipi_call_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + smp_call_function_interrupt(); + + return IRQ_HANDLED; +} + +static struct irqaction irq_resched = { + .handler = ipi_resched_interrupt, + .flags = SA_INTERRUPT, + .name = "IPI_resched" +}; + +static struct irqaction irq_call = { + .handler = ipi_call_interrupt, + .flags = SA_INTERRUPT, + .name = "IPI_call" +}; + +/* + * Common setup before any secondaries are started + * Make sure all CPU's are in a sensible state before we boot any of the + * secondarys + */ +void prom_prepare_cpus(unsigned int max_cpus) +{ + unsigned long val; + int i, num; + + if (!cpu_has_mipsmt) + return; + + /* disable MT so we can configure */ + dvpe(); + dmt(); + + /* Put MVPE's into 'configuration state' */ + set_c0_mvpcontrol(MVPCONTROL_VPC); + + val = read_c0_mvpconf0(); + + /* we'll always have more TC's than VPE's, so loop setting everything + to a sensible state */ + for (i = 0, num = 0; i <= ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT); i++) { + settc(i); + + /* VPE's */ + if (i <= ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)) { + + /* deactivate all but vpe0 */ + if (i != 0) { + unsigned long tmp = read_vpe_c0_vpeconf0(); + + tmp &= ~VPECONF0_VPA; + + /* master VPE */ + tmp |= VPECONF0_MVP; + write_vpe_c0_vpeconf0(tmp); + + /* Record this as available CPU */ + if (i < max_cpus) { + cpu_set(i, phys_cpu_present_map); + __cpu_number_map[i] = ++num; + __cpu_logical_map[num] = i; + } + } + + /* disable multi-threading with TC's */ + write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); + + if (i != 0) { + write_vpe_c0_status((read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0); + write_vpe_c0_cause(read_vpe_c0_cause() & ~CAUSEF_IP); + + /* set config to be the same as vpe0, particularly kseg0 coherency alg */ + write_vpe_c0_config( read_c0_config()); + } + + } + + /* TC's */ + + if (i != 0) { + unsigned long tmp; + + /* bind a TC to each VPE, May as well put all excess TC's + on the last VPE */ + if ( i >= (((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1) ) + write_tc_c0_tcbind(read_tc_c0_tcbind() | ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) ); + else { + write_tc_c0_tcbind( read_tc_c0_tcbind() | i); + + /* and set XTC */ + write_vpe_c0_vpeconf0( read_vpe_c0_vpeconf0() | (i << VPECONF0_XTC_SHIFT)); + } + + tmp = read_tc_c0_tcstatus(); + + /* mark not allocated and not dynamically allocatable */ + tmp &= ~(TCSTATUS_A | TCSTATUS_DA); + tmp |= TCSTATUS_IXMT; /* interrupt exempt */ + write_tc_c0_tcstatus(tmp); + + write_tc_c0_tchalt(TCHALT_H); + } + } + + /* Release config state */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); + + /* We'll wait until starting the secondaries before starting MVPE */ + + printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); + + /* set up ipi interrupts */ + if (cpu_has_vint) { + set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); + set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); + } + + cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ; + cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ; + + setup_irq(cpu_ipi_resched_irq, &irq_resched); + setup_irq(cpu_ipi_call_irq, &irq_call); + + /* need to mark IPI's as IRQ_PER_CPU */ + irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU; + irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU; +} + +/* + * Setup the PC, SP, and GP of a secondary processor and start it + * running! + * smp_bootstrap is the place to resume from + * __KSTK_TOS(idle) is apparently the stack pointer + * (unsigned long)idle->thread_info the gp + * assumes a 1:1 mapping of TC => VPE + */ +void prom_boot_secondary(int cpu, struct task_struct *idle) +{ + dvpe(); + set_c0_mvpcontrol(MVPCONTROL_VPC); + + settc(cpu); + + /* restart */ + write_tc_c0_tcrestart((unsigned long)&smp_bootstrap); + + /* enable the tc this vpe/cpu will be running */ + write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A); + + write_tc_c0_tchalt(0); + + /* enable the VPE */ + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); + + /* stack pointer */ + write_tc_gpr_sp( __KSTK_TOS(idle)); + + /* global pointer */ + write_tc_gpr_gp((unsigned long)idle->thread_info); + + flush_icache_range((unsigned long)idle->thread_info, + (unsigned long)idle->thread_info + + sizeof(struct thread_info)); + + /* finally out of configuration and into chaos */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); + + evpe(EVPE_ENABLE); +} + +void prom_init_secondary(void) +{ + write_c0_status((read_c0_status() & ~ST0_IM ) | + (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7)); +} + +void prom_smp_finish(void) +{ + write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); + + local_irq_enable(); +} + +void prom_cpus_done(void) +{ +} + +void core_send_ipi(int cpu, unsigned int action) +{ + int i; + unsigned long flags; + int vpflags; + + local_irq_save (flags); + + vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */ + + switch (action) { + case SMP_CALL_FUNCTION: + i = C_SW1; + break; + + case SMP_RESCHEDULE_YOURSELF: + default: + i = C_SW0; + break; + } + + /* 1:1 mapping of vpe and tc... */ + settc(cpu); + write_vpe_c0_cause(read_vpe_c0_cause() | i); + evpe(vpflags); + + local_irq_restore(flags); +} diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index 21e3e13a4b44..ee98eeb65e85 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -7,6 +7,7 @@ * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 2001 MIPS Technologies, Inc. */ +#include <linux/config.h> #include <linux/a.out.h> #include <linux/errno.h> #include <linux/linkage.h> @@ -26,6 +27,7 @@ #include <linux/msg.h> #include <linux/shm.h> #include <linux/compiler.h> +#include <linux/module.h> #include <asm/branch.h> #include <asm/cachectl.h> @@ -56,6 +58,8 @@ out: unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */ +EXPORT_SYMBOL(shm_align_mask); + #define COLOUR_ALIGN(addr,pgoff) \ ((((addr) + shm_align_mask) & ~shm_align_mask) + \ (((pgoff) << PAGE_SHIFT) & shm_align_mask)) @@ -173,14 +177,28 @@ _sys_clone(nabi_no_regargs struct pt_regs regs) { unsigned long clone_flags; unsigned long newsp; - int *parent_tidptr, *child_tidptr; + int __user *parent_tidptr, *child_tidptr; clone_flags = regs.regs[4]; newsp = regs.regs[5]; if (!newsp) newsp = regs.regs[29]; - parent_tidptr = (int *) regs.regs[6]; - child_tidptr = (int *) regs.regs[7]; + parent_tidptr = (int __user *) regs.regs[6]; +#ifdef CONFIG_32BIT + /* We need to fetch the fifth argument off the stack. */ + child_tidptr = NULL; + if (clone_flags & (CLONE_CHILD_SETTID | CLONE_CHILD_CLEARTID)) { + int __user *__user *usp = (int __user *__user *) regs.regs[29]; + if (regs.regs[2] == __NR_syscall) { + if (get_user (child_tidptr, &usp[5])) + return -EFAULT; + } + else if (get_user (child_tidptr, &usp[4])) + return -EFAULT; + } +#else + child_tidptr = (int __user *) regs.regs[8]; +#endif return do_fork(clone_flags, newsp, ®s, 0, parent_tidptr, child_tidptr); } @@ -242,6 +260,16 @@ asmlinkage int sys_olduname(struct oldold_utsname * name) return error; } +void sys_set_thread_area(unsigned long addr) +{ + struct thread_info *ti = current->thread_info; + + ti->tp_value = addr; + + /* If some future MIPS implementation has this register in hardware, + * we will need to update it here (and in context switches). */ +} + asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3) { int tmp, len; diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c index 7ae4af476974..52924f8ce23c 100644 --- a/arch/mips/kernel/sysirix.c +++ b/arch/mips/kernel/sysirix.c @@ -73,32 +73,30 @@ asmlinkage int irix_sysmp(struct pt_regs *regs) } /* The prctl commands. */ -#define PR_MAXPROCS 1 /* Tasks/user. */ -#define PR_ISBLOCKED 2 /* If blocked, return 1. */ -#define PR_SETSTACKSIZE 3 /* Set largest task stack size. */ -#define PR_GETSTACKSIZE 4 /* Get largest task stack size. */ -#define PR_MAXPPROCS 5 /* Num parallel tasks. */ -#define PR_UNBLKONEXEC 6 /* When task exec/exit's, unblock. */ -#define PR_SETEXITSIG 8 /* When task exit's, set signal. */ -#define PR_RESIDENT 9 /* Make task unswappable. */ -#define PR_ATTACHADDR 10 /* (Re-)Connect a vma to a task. */ -#define PR_DETACHADDR 11 /* Disconnect a vma from a task. */ -#define PR_TERMCHILD 12 /* When parent sleeps with fishes, kill child. */ -#define PR_GETSHMASK 13 /* Get the sproc() share mask. */ -#define PR_GETNSHARE 14 /* Number of share group members. */ -#define PR_COREPID 15 /* Add task pid to name when it core. */ -#define PR_ATTACHADDRPERM 16 /* (Re-)Connect vma, with specified prot. */ -#define PR_PTHREADEXIT 17 /* Kill a pthread without prejudice. */ - -asmlinkage int irix_prctl(struct pt_regs *regs) -{ - unsigned long cmd; - int error = 0, base = 0; +#define PR_MAXPROCS 1 /* Tasks/user. */ +#define PR_ISBLOCKED 2 /* If blocked, return 1. */ +#define PR_SETSTACKSIZE 3 /* Set largest task stack size. */ +#define PR_GETSTACKSIZE 4 /* Get largest task stack size. */ +#define PR_MAXPPROCS 5 /* Num parallel tasks. */ +#define PR_UNBLKONEXEC 6 /* When task exec/exit's, unblock. */ +#define PR_SETEXITSIG 8 /* When task exit's, set signal. */ +#define PR_RESIDENT 9 /* Make task unswappable. */ +#define PR_ATTACHADDR 10 /* (Re-)Connect a vma to a task. */ +#define PR_DETACHADDR 11 /* Disconnect a vma from a task. */ +#define PR_TERMCHILD 12 /* Kill child if the parent dies. */ +#define PR_GETSHMASK 13 /* Get the sproc() share mask. */ +#define PR_GETNSHARE 14 /* Number of share group members. */ +#define PR_COREPID 15 /* Add task pid to name when it core. */ +#define PR_ATTACHADDRPERM 16 /* (Re-)Connect vma, with specified prot. */ +#define PR_PTHREADEXIT 17 /* Kill a pthread, only for IRIX 6.[234] */ + +asmlinkage int irix_prctl(unsigned option, ...) +{ + va_list args; + int error = 0; - if (regs->regs[2] == 1000) - base = 1; - cmd = regs->regs[base + 4]; - switch (cmd) { + va_start(args, option); + switch (option) { case PR_MAXPROCS: printk("irix_prctl[%s:%d]: Wants PR_MAXPROCS\n", current->comm, current->pid); @@ -111,7 +109,7 @@ asmlinkage int irix_prctl(struct pt_regs *regs) printk("irix_prctl[%s:%d]: Wants PR_ISBLOCKED\n", current->comm, current->pid); read_lock(&tasklist_lock); - task = find_task_by_pid(regs->regs[base + 5]); + task = find_task_by_pid(va_arg(args, pid_t)); error = -ESRCH; if (error) error = (task->run_list.next != NULL); @@ -121,7 +119,7 @@ asmlinkage int irix_prctl(struct pt_regs *regs) } case PR_SETSTACKSIZE: { - long value = regs->regs[base + 5]; + long value = va_arg(args, long); printk("irix_prctl[%s:%d]: Wants PR_SETSTACKSIZE<%08lx>\n", current->comm, current->pid, (unsigned long) value); @@ -222,24 +220,20 @@ asmlinkage int irix_prctl(struct pt_regs *regs) error = -EINVAL; break; - case PR_PTHREADEXIT: - printk("irix_prctl[%s:%d]: Wants PR_PTHREADEXIT\n", - current->comm, current->pid); - do_exit(regs->regs[base + 5]); - default: printk("irix_prctl[%s:%d]: Non-existant opcode %d\n", - current->comm, current->pid, (int)cmd); + current->comm, current->pid, option); error = -EINVAL; break; } + va_end(args); return error; } #undef DEBUG_PROCGRPS -extern unsigned long irix_mapelf(int fd, struct elf_phdr *user_phdrp, int cnt); +extern unsigned long irix_mapelf(int fd, struct elf_phdr __user *user_phdrp, int cnt); extern int getrusage(struct task_struct *p, int who, struct rusage __user *ru); extern char *prom_getenv(char *name); extern long prom_setenv(char *name, char *value); @@ -276,23 +270,19 @@ asmlinkage int irix_syssgi(struct pt_regs *regs) cmd = regs->regs[base + 4]; switch(cmd) { case SGI_SYSID: { - char *buf = (char *) regs->regs[base + 5]; + char __user *buf = (char __user *) regs->regs[base + 5]; /* XXX Use ethernet addr.... */ - retval = clear_user(buf, 64); + retval = clear_user(buf, 64) ? -EFAULT : 0; break; } #if 0 case SGI_RDNAME: { int pid = (int) regs->regs[base + 5]; - char *buf = (char *) regs->regs[base + 6]; + char __user *buf = (char __user *) regs->regs[base + 6]; struct task_struct *p; char tcomm[sizeof(current->comm)]; - if (!access_ok(VERIFY_WRITE, buf, sizeof(tcomm))) { - retval = -EFAULT; - break; - } read_lock(&tasklist_lock); p = find_task_by_pid(pid); if (!p) { @@ -304,34 +294,28 @@ asmlinkage int irix_syssgi(struct pt_regs *regs) read_unlock(&tasklist_lock); /* XXX Need to check sizes. */ - copy_to_user(buf, tcomm, sizeof(tcomm)); - retval = 0; + retval = copy_to_user(buf, tcomm, sizeof(tcomm)) ? -EFAULT : 0; break; } case SGI_GETNVRAM: { - char *name = (char *) regs->regs[base+5]; - char *buf = (char *) regs->regs[base+6]; + char __user *name = (char __user *) regs->regs[base+5]; + char __user *buf = (char __user *) regs->regs[base+6]; char *value; return -EINVAL; /* til I fix it */ - if (!access_ok(VERIFY_WRITE, buf, 128)) { - retval = -EFAULT; - break; - } value = prom_getenv(name); /* PROM lock? */ if (!value) { retval = -EINVAL; break; } /* Do I strlen() for the length? */ - copy_to_user(buf, value, 128); - retval = 0; + retval = copy_to_user(buf, value, 128) ? -EFAULT : 0; break; } case SGI_SETNVRAM: { - char *name = (char *) regs->regs[base+5]; - char *value = (char *) regs->regs[base+6]; + char __user *name = (char __user *) regs->regs[base+5]; + char __user *value = (char __user *) regs->regs[base+6]; return -EINVAL; /* til I fix it */ retval = prom_setenv(name, value); /* XXX make sure retval conforms to syssgi(2) */ @@ -407,16 +391,16 @@ asmlinkage int irix_syssgi(struct pt_regs *regs) case SGI_SETGROUPS: retval = sys_setgroups((int) regs->regs[base + 5], - (gid_t *) regs->regs[base + 6]); + (gid_t __user *) regs->regs[base + 6]); break; case SGI_GETGROUPS: retval = sys_getgroups((int) regs->regs[base + 5], - (gid_t *) regs->regs[base + 6]); + (gid_t __user *) regs->regs[base + 6]); break; case SGI_RUSAGE: { - struct rusage *ru = (struct rusage *) regs->regs[base + 6]; + struct rusage __user *ru = (struct rusage __user *) regs->regs[base + 6]; switch((int) regs->regs[base + 5]) { case 0: @@ -453,7 +437,7 @@ asmlinkage int irix_syssgi(struct pt_regs *regs) case SGI_ELFMAP: retval = irix_mapelf((int) regs->regs[base + 5], - (struct elf_phdr *) regs->regs[base + 6], + (struct elf_phdr __user *) regs->regs[base + 6], (int) regs->regs[base + 7]); break; @@ -468,24 +452,24 @@ asmlinkage int irix_syssgi(struct pt_regs *regs) case SGI_PHYSP: { unsigned long addr = regs->regs[base + 5]; - int *pageno = (int *) (regs->regs[base + 6]); + int __user *pageno = (int __user *) (regs->regs[base + 6]); struct mm_struct *mm = current->mm; pgd_t *pgdp; + pud_t *pudp; pmd_t *pmdp; pte_t *ptep; - if (!access_ok(VERIFY_WRITE, pageno, sizeof(int))) - return -EFAULT; - down_read(&mm->mmap_sem); pgdp = pgd_offset(mm, addr); - pmdp = pmd_offset(pgdp, addr); + pudp = pud_offset(pgdp, addr); + pmdp = pmd_offset(pudp, addr); ptep = pte_offset(pmdp, addr); retval = -EINVAL; if (ptep) { pte_t pte = *ptep; if (pte_val(pte) & (_PAGE_VALID | _PAGE_PRESENT)) { + /* b0rked on 64-bit */ retval = put_user((pte_val(pte) & PAGE_MASK) >> PAGE_SHIFT, pageno); } @@ -496,7 +480,7 @@ asmlinkage int irix_syssgi(struct pt_regs *regs) case SGI_INVENT: { int arg1 = (int) regs->regs [base + 5]; - void *buffer = (void *) regs->regs [base + 6]; + void __user *buffer = (void __user *) regs->regs [base + 6]; int count = (int) regs->regs [base + 7]; switch (arg1) { @@ -692,8 +676,8 @@ asmlinkage int irix_pause(void) } /* XXX need more than this... */ -asmlinkage int irix_mount(char *dev_name, char *dir_name, unsigned long flags, - char *type, void *data, int datalen) +asmlinkage int irix_mount(char __user *dev_name, char __user *dir_name, + unsigned long flags, char __user *type, void __user *data, int datalen) { printk("[%s:%d] irix_mount(%p,%p,%08lx,%p,%p,%d)\n", current->comm, current->pid, @@ -708,8 +692,8 @@ struct irix_statfs { char f_fname[6], f_fpack[6]; }; -asmlinkage int irix_statfs(const char *path, struct irix_statfs *buf, - int len, int fs_type) +asmlinkage int irix_statfs(const char __user *path, + struct irix_statfs __user *buf, int len, int fs_type) { struct nameidata nd; struct kstatfs kbuf; @@ -724,6 +708,7 @@ asmlinkage int irix_statfs(const char *path, struct irix_statfs *buf, error = -EFAULT; goto out; } + error = user_path_walk(path, &nd); if (error) goto out; @@ -732,18 +717,17 @@ asmlinkage int irix_statfs(const char *path, struct irix_statfs *buf, if (error) goto dput_and_out; - __put_user(kbuf.f_type, &buf->f_type); - __put_user(kbuf.f_bsize, &buf->f_bsize); - __put_user(kbuf.f_frsize, &buf->f_frsize); - __put_user(kbuf.f_blocks, &buf->f_blocks); - __put_user(kbuf.f_bfree, &buf->f_bfree); - __put_user(kbuf.f_files, &buf->f_files); - __put_user(kbuf.f_ffree, &buf->f_ffree); + error = __put_user(kbuf.f_type, &buf->f_type); + error |= __put_user(kbuf.f_bsize, &buf->f_bsize); + error |= __put_user(kbuf.f_frsize, &buf->f_frsize); + error |= __put_user(kbuf.f_blocks, &buf->f_blocks); + error |= __put_user(kbuf.f_bfree, &buf->f_bfree); + error |= __put_user(kbuf.f_files, &buf->f_files); + error |= __put_user(kbuf.f_ffree, &buf->f_ffree); for (i = 0; i < 6; i++) { - __put_user(0, &buf->f_fname[i]); - __put_user(0, &buf->f_fpack[i]); + error |= __put_user(0, &buf->f_fname[i]); + error |= __put_user(0, &buf->f_fpack[i]); } - error = 0; dput_and_out: path_release(&nd); @@ -751,7 +735,7 @@ out: return error; } -asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs *buf) +asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs __user *buf) { struct kstatfs kbuf; struct file *file; @@ -761,6 +745,7 @@ asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs *buf) error = -EFAULT; goto out; } + if (!(file = fget(fd))) { error = -EBADF; goto out; @@ -770,16 +755,17 @@ asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs *buf) if (error) goto out_f; - __put_user(kbuf.f_type, &buf->f_type); - __put_user(kbuf.f_bsize, &buf->f_bsize); - __put_user(kbuf.f_frsize, &buf->f_frsize); - __put_user(kbuf.f_blocks, &buf->f_blocks); - __put_user(kbuf.f_bfree, &buf->f_bfree); - __put_user(kbuf.f_files, &buf->f_files); - __put_user(kbuf.f_ffree, &buf->f_ffree); - for(i = 0; i < 6; i++) { - __put_user(0, &buf->f_fname[i]); - __put_user(0, &buf->f_fpack[i]); + error = __put_user(kbuf.f_type, &buf->f_type); + error |= __put_user(kbuf.f_bsize, &buf->f_bsize); + error |= __put_user(kbuf.f_frsize, &buf->f_frsize); + error |= __put_user(kbuf.f_blocks, &buf->f_blocks); + error |= __put_user(kbuf.f_bfree, &buf->f_bfree); + error |= __put_user(kbuf.f_files, &buf->f_files); + error |= __put_user(kbuf.f_ffree, &buf->f_ffree); + + for (i = 0; i < 6; i++) { + error |= __put_user(0, &buf->f_fname[i]); + error |= __put_user(0, &buf->f_fpack[i]); } out_f: @@ -806,14 +792,15 @@ asmlinkage int irix_setpgrp(int flags) return error; } -asmlinkage int irix_times(struct tms * tbuf) +asmlinkage int irix_times(struct tms __user *tbuf) { int err = 0; if (tbuf) { if (!access_ok(VERIFY_WRITE,tbuf,sizeof *tbuf)) return -EFAULT; - err |= __put_user(current->utime, &tbuf->tms_utime); + + err = __put_user(current->utime, &tbuf->tms_utime); err |= __put_user(current->stime, &tbuf->tms_stime); err |= __put_user(current->signal->cutime, &tbuf->tms_cutime); err |= __put_user(current->signal->cstime, &tbuf->tms_cstime); @@ -829,13 +816,13 @@ asmlinkage int irix_exec(struct pt_regs *regs) if(regs->regs[2] == 1000) base = 1; - filename = getname((char *) (long)regs->regs[base + 4]); + filename = getname((char __user *) (long)regs->regs[base + 4]); error = PTR_ERR(filename); if (IS_ERR(filename)) return error; - error = do_execve(filename, (char **) (long)regs->regs[base + 5], - (char **) 0, regs); + error = do_execve(filename, (char __user * __user *) (long)regs->regs[base + 5], + NULL, regs); putname(filename); return error; @@ -848,12 +835,12 @@ asmlinkage int irix_exece(struct pt_regs *regs) if (regs->regs[2] == 1000) base = 1; - filename = getname((char *) (long)regs->regs[base + 4]); + filename = getname((char __user *) (long)regs->regs[base + 4]); error = PTR_ERR(filename); if (IS_ERR(filename)) return error; - error = do_execve(filename, (char **) (long)regs->regs[base + 5], - (char **) (long)regs->regs[base + 6], regs); + error = do_execve(filename, (char __user * __user *) (long)regs->regs[base + 5], + (char __user * __user *) (long)regs->regs[base + 6], regs); putname(filename); return error; @@ -909,22 +896,17 @@ asmlinkage int irix_socket(int family, int type, int protocol) return sys_socket(family, type, protocol); } -asmlinkage int irix_getdomainname(char *name, int len) +asmlinkage int irix_getdomainname(char __user *name, int len) { - int error; - - if (!access_ok(VERIFY_WRITE, name, len)) - return -EFAULT; + int err; down_read(&uts_sem); if (len > __NEW_UTS_LEN) len = __NEW_UTS_LEN; - error = 0; - if (copy_to_user(name, system_utsname.domainname, len)) - error = -EFAULT; + err = copy_to_user(name, system_utsname.domainname, len) ? -EFAULT : 0; up_read(&uts_sem); - return error; + return err; } asmlinkage unsigned long irix_getpagesize(void) @@ -940,12 +922,13 @@ asmlinkage int irix_msgsys(int opcode, unsigned long arg0, unsigned long arg1, case 0: return sys_msgget((key_t) arg0, (int) arg1); case 1: - return sys_msgctl((int) arg0, (int) arg1, (struct msqid_ds *)arg2); + return sys_msgctl((int) arg0, (int) arg1, + (struct msqid_ds __user *)arg2); case 2: - return sys_msgrcv((int) arg0, (struct msgbuf *) arg1, + return sys_msgrcv((int) arg0, (struct msgbuf __user *) arg1, (size_t) arg2, (long) arg3, (int) arg4); case 3: - return sys_msgsnd((int) arg0, (struct msgbuf *) arg1, + return sys_msgsnd((int) arg0, (struct msgbuf __user *) arg1, (size_t) arg2, (int) arg3); default: return -EINVAL; @@ -957,12 +940,13 @@ asmlinkage int irix_shmsys(int opcode, unsigned long arg0, unsigned long arg1, { switch (opcode) { case 0: - return do_shmat((int) arg0, (char *)arg1, (int) arg2, + return do_shmat((int) arg0, (char __user *) arg1, (int) arg2, (unsigned long *) arg3); case 1: - return sys_shmctl((int)arg0, (int)arg1, (struct shmid_ds *)arg2); + return sys_shmctl((int)arg0, (int)arg1, + (struct shmid_ds __user *)arg2); case 2: - return sys_shmdt((char *)arg0); + return sys_shmdt((char __user *)arg0); case 3: return sys_shmget((key_t) arg0, (int) arg1, (int) arg2); default: @@ -980,7 +964,7 @@ asmlinkage int irix_semsys(int opcode, unsigned long arg0, unsigned long arg1, case 1: return sys_semget((key_t) arg0, (int) arg1, (int) arg2); case 2: - return sys_semop((int) arg0, (struct sembuf *)arg1, + return sys_semop((int) arg0, (struct sembuf __user *)arg1, (unsigned int) arg2); default: return -EINVAL; @@ -998,15 +982,16 @@ static inline loff_t llseek(struct file *file, loff_t offset, int origin) lock_kernel(); retval = fn(file, offset, origin); unlock_kernel(); + return retval; } asmlinkage int irix_lseek64(int fd, int _unused, int offhi, int offlow, int origin) { - int retval; struct file * file; loff_t offset; + int retval; retval = -EBADF; file = fget(fd); @@ -1031,12 +1016,12 @@ asmlinkage int irix_sginap(int ticks) return 0; } -asmlinkage int irix_sgikopt(char *istring, char *ostring, int len) +asmlinkage int irix_sgikopt(char __user *istring, char __user *ostring, int len) { return -EINVAL; } -asmlinkage int irix_gettimeofday(struct timeval *tv) +asmlinkage int irix_gettimeofday(struct timeval __user *tv) { time_t sec; long nsec, seq; @@ -1077,7 +1062,7 @@ asmlinkage unsigned long irix_mmap32(unsigned long addr, size_t len, int prot, if (max_size > file->f_dentry->d_inode->i_size) { old_pos = sys_lseek (fd, max_size - 1, 0); - sys_write (fd, "", 1); + sys_write (fd, (void __user *) "", 1); sys_lseek (fd, old_pos, 0); } } @@ -1102,7 +1087,7 @@ asmlinkage int irix_madvise(unsigned long addr, int len, int behavior) return -EINVAL; } -asmlinkage int irix_pagelock(char *addr, int len, int op) +asmlinkage int irix_pagelock(char __user *addr, int len, int op) { printk("[%s:%d] Wheee.. irix_pagelock(%p,%d,%d)\n", current->comm, current->pid, addr, len, op); @@ -1142,7 +1127,7 @@ asmlinkage int irix_BSDsetpgrp(int pid, int pgrp) return error; } -asmlinkage int irix_systeminfo(int cmd, char *buf, int cnt) +asmlinkage int irix_systeminfo(int cmd, char __user *buf, int cnt) { printk("[%s:%d] Wheee.. irix_systeminfo(%d,%p,%d)\n", current->comm, current->pid, cmd, buf, cnt); @@ -1158,14 +1143,14 @@ struct iuname { char _unused3[257], _unused4[257], _unused5[257]; }; -asmlinkage int irix_uname(struct iuname *buf) +asmlinkage int irix_uname(struct iuname __user *buf) { down_read(&uts_sem); - if (copy_to_user(system_utsname.sysname, buf->sysname, 65) - || copy_to_user(system_utsname.nodename, buf->nodename, 65) - || copy_to_user(system_utsname.release, buf->release, 65) - || copy_to_user(system_utsname.version, buf->version, 65) - || copy_to_user(system_utsname.machine, buf->machine, 65)) { + if (copy_from_user(system_utsname.sysname, buf->sysname, 65) + || copy_from_user(system_utsname.nodename, buf->nodename, 65) + || copy_from_user(system_utsname.release, buf->release, 65) + || copy_from_user(system_utsname.version, buf->version, 65) + || copy_from_user(system_utsname.machine, buf->machine, 65)) { return -EFAULT; } up_read(&uts_sem); @@ -1175,7 +1160,7 @@ asmlinkage int irix_uname(struct iuname *buf) #undef DEBUG_XSTAT -static int irix_xstat32_xlate(struct kstat *stat, void *ubuf) +static int irix_xstat32_xlate(struct kstat *stat, void __user *ubuf) { struct xstat32 { u32 st_dev, st_pad1[3], st_ino, st_mode, st_nlink, st_uid, st_gid; @@ -1215,7 +1200,7 @@ static int irix_xstat32_xlate(struct kstat *stat, void *ubuf) return copy_to_user(ubuf, &ub, sizeof(ub)) ? -EFAULT : 0; } -static int irix_xstat64_xlate(struct kstat *stat, void *ubuf) +static int irix_xstat64_xlate(struct kstat *stat, void __user *ubuf) { struct xstat64 { u32 st_dev; s32 st_pad1[3]; @@ -1265,7 +1250,7 @@ static int irix_xstat64_xlate(struct kstat *stat, void *ubuf) return copy_to_user(ubuf, &ks, sizeof(ks)) ? -EFAULT : 0; } -asmlinkage int irix_xstat(int version, char *filename, struct stat *statbuf) +asmlinkage int irix_xstat(int version, char __user *filename, struct stat __user *statbuf) { int retval; struct kstat stat; @@ -1291,7 +1276,7 @@ asmlinkage int irix_xstat(int version, char *filename, struct stat *statbuf) return retval; } -asmlinkage int irix_lxstat(int version, char *filename, struct stat *statbuf) +asmlinkage int irix_lxstat(int version, char __user *filename, struct stat __user *statbuf) { int error; struct kstat stat; @@ -1318,7 +1303,7 @@ asmlinkage int irix_lxstat(int version, char *filename, struct stat *statbuf) return error; } -asmlinkage int irix_fxstat(int version, int fd, struct stat *statbuf) +asmlinkage int irix_fxstat(int version, int fd, struct stat __user *statbuf) { int error; struct kstat stat; @@ -1344,7 +1329,7 @@ asmlinkage int irix_fxstat(int version, int fd, struct stat *statbuf) return error; } -asmlinkage int irix_xmknod(int ver, char *filename, int mode, unsigned dev) +asmlinkage int irix_xmknod(int ver, char __user *filename, int mode, unsigned dev) { int retval; printk("[%s:%d] Wheee.. irix_xmknod(%d,%s,%x,%x)\n", @@ -1364,7 +1349,7 @@ asmlinkage int irix_xmknod(int ver, char *filename, int mode, unsigned dev) return retval; } -asmlinkage int irix_swapctl(int cmd, char *arg) +asmlinkage int irix_swapctl(int cmd, char __user *arg) { printk("[%s:%d] Wheee.. irix_swapctl(%d,%p)\n", current->comm, current->pid, cmd, arg); @@ -1380,7 +1365,7 @@ struct irix_statvfs { char f_fstr[32]; u32 f_filler[16]; }; -asmlinkage int irix_statvfs(char *fname, struct irix_statvfs *buf) +asmlinkage int irix_statvfs(char __user *fname, struct irix_statvfs __user *buf) { struct nameidata nd; struct kstatfs kbuf; @@ -1388,10 +1373,9 @@ asmlinkage int irix_statvfs(char *fname, struct irix_statvfs *buf) printk("[%s:%d] Wheee.. irix_statvfs(%s,%p)\n", current->comm, current->pid, fname, buf); - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) { - error = -EFAULT; - goto out; - } + if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) + return -EFAULT; + error = user_path_walk(fname, &nd); if (error) goto out; @@ -1399,27 +1383,25 @@ asmlinkage int irix_statvfs(char *fname, struct irix_statvfs *buf) if (error) goto dput_and_out; - __put_user(kbuf.f_bsize, &buf->f_bsize); - __put_user(kbuf.f_frsize, &buf->f_frsize); - __put_user(kbuf.f_blocks, &buf->f_blocks); - __put_user(kbuf.f_bfree, &buf->f_bfree); - __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - __put_user(kbuf.f_files, &buf->f_files); - __put_user(kbuf.f_ffree, &buf->f_ffree); - __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ + error |= __put_user(kbuf.f_bsize, &buf->f_bsize); + error |= __put_user(kbuf.f_frsize, &buf->f_frsize); + error |= __put_user(kbuf.f_blocks, &buf->f_blocks); + error |= __put_user(kbuf.f_bfree, &buf->f_bfree); + error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ + error |= __put_user(kbuf.f_files, &buf->f_files); + error |= __put_user(kbuf.f_ffree, &buf->f_ffree); + error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ #ifdef __MIPSEB__ - __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); #else - __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); #endif for (i = 0; i < 16; i++) - __put_user(0, &buf->f_basetype[i]); - __put_user(0, &buf->f_flag); - __put_user(kbuf.f_namelen, &buf->f_namemax); + error |= __put_user(0, &buf->f_basetype[i]); + error |= __put_user(0, &buf->f_flag); + error |= __put_user(kbuf.f_namelen, &buf->f_namemax); for (i = 0; i < 32; i++) - __put_user(0, &buf->f_fstr[i]); - - error = 0; + error |= __put_user(0, &buf->f_fstr[i]); dput_and_out: path_release(&nd); @@ -1427,7 +1409,7 @@ out: return error; } -asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs *buf) +asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs __user *buf) { struct kstatfs kbuf; struct file *file; @@ -1436,10 +1418,9 @@ asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs *buf) printk("[%s:%d] Wheee.. irix_fstatvfs(%d,%p)\n", current->comm, current->pid, fd, buf); - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) { - error = -EFAULT; - goto out; - } + if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) + return -EFAULT; + if (!(file = fget(fd))) { error = -EBADF; goto out; @@ -1448,24 +1429,24 @@ asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs *buf) if (error) goto out_f; - __put_user(kbuf.f_bsize, &buf->f_bsize); - __put_user(kbuf.f_frsize, &buf->f_frsize); - __put_user(kbuf.f_blocks, &buf->f_blocks); - __put_user(kbuf.f_bfree, &buf->f_bfree); - __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - __put_user(kbuf.f_files, &buf->f_files); - __put_user(kbuf.f_ffree, &buf->f_ffree); - __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ + error = __put_user(kbuf.f_bsize, &buf->f_bsize); + error |= __put_user(kbuf.f_frsize, &buf->f_frsize); + error |= __put_user(kbuf.f_blocks, &buf->f_blocks); + error |= __put_user(kbuf.f_bfree, &buf->f_bfree); + error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ + error |= __put_user(kbuf.f_files, &buf->f_files); + error |= __put_user(kbuf.f_ffree, &buf->f_ffree); + error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ #ifdef __MIPSEB__ - __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); #else - __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); #endif for(i = 0; i < 16; i++) - __put_user(0, &buf->f_basetype[i]); - __put_user(0, &buf->f_flag); - __put_user(kbuf.f_namelen, &buf->f_namemax); - __clear_user(&buf->f_fstr, sizeof(buf->f_fstr)); + error |= __put_user(0, &buf->f_basetype[i]); + error |= __put_user(0, &buf->f_flag); + error |= __put_user(kbuf.f_namelen, &buf->f_namemax); + error |= __clear_user(&buf->f_fstr, sizeof(buf->f_fstr)) ? -EFAULT : 0; out_f: fput(file); @@ -1489,7 +1470,7 @@ asmlinkage int irix_sigqueue(int pid, int sig, int code, int val) return -EINVAL; } -asmlinkage int irix_truncate64(char *name, int pad, int size1, int size2) +asmlinkage int irix_truncate64(char __user *name, int pad, int size1, int size2) { int retval; @@ -1522,6 +1503,7 @@ asmlinkage int irix_mmap64(struct pt_regs *regs) int len, prot, flags, fd, off1, off2, error, base = 0; unsigned long addr, pgoff, *sp; struct file *file = NULL; + int err; if (regs->regs[2] == 1000) base = 1; @@ -1531,36 +1513,31 @@ asmlinkage int irix_mmap64(struct pt_regs *regs) prot = regs->regs[base + 6]; if (!base) { flags = regs->regs[base + 7]; - if (!access_ok(VERIFY_READ, sp, (4 * sizeof(unsigned long)))) { - error = -EFAULT; - goto out; - } + if (!access_ok(VERIFY_READ, sp, (4 * sizeof(unsigned long)))) + return -EFAULT; fd = sp[0]; - __get_user(off1, &sp[1]); - __get_user(off2, &sp[2]); + err = __get_user(off1, &sp[1]); + err |= __get_user(off2, &sp[2]); } else { - if (!access_ok(VERIFY_READ, sp, (5 * sizeof(unsigned long)))) { - error = -EFAULT; - goto out; - } - __get_user(flags, &sp[0]); - __get_user(fd, &sp[1]); - __get_user(off1, &sp[2]); - __get_user(off2, &sp[3]); + if (!access_ok(VERIFY_READ, sp, (5 * sizeof(unsigned long)))) + return -EFAULT; + err = __get_user(flags, &sp[0]); + err |= __get_user(fd, &sp[1]); + err |= __get_user(off1, &sp[2]); + err |= __get_user(off2, &sp[3]); } - if (off1 & PAGE_MASK) { - error = -EOVERFLOW; - goto out; - } + if (err) + return err; + + if (off1 & PAGE_MASK) + return -EOVERFLOW; pgoff = (off1 << (32 - PAGE_SHIFT)) | (off2 >> PAGE_SHIFT); if (!(flags & MAP_ANONYMOUS)) { - if (!(file = fget(fd))) { - error = -EBADF; - goto out; - } + if (!(file = fget(fd))) + return -EBADF; /* Ok, bad taste hack follows, try to think in something else when reading this */ @@ -1570,7 +1547,7 @@ asmlinkage int irix_mmap64(struct pt_regs *regs) if (max_size > file->f_dentry->d_inode->i_size) { old_pos = sys_lseek (fd, max_size - 1, 0); - sys_write (fd, "", 1); + sys_write (fd, (void __user *) "", 1); sys_lseek (fd, old_pos, 0); } } @@ -1585,7 +1562,6 @@ asmlinkage int irix_mmap64(struct pt_regs *regs) if (file) fput(file); -out: return error; } @@ -1597,7 +1573,7 @@ asmlinkage int irix_dmi(struct pt_regs *regs) return -EINVAL; } -asmlinkage int irix_pread(int fd, char *buf, int cnt, int off64, +asmlinkage int irix_pread(int fd, char __user *buf, int cnt, int off64, int off1, int off2) { printk("[%s:%d] Wheee.. irix_pread(%d,%p,%d,%d,%d,%d)\n", @@ -1606,7 +1582,7 @@ asmlinkage int irix_pread(int fd, char *buf, int cnt, int off64, return -EINVAL; } -asmlinkage int irix_pwrite(int fd, char *buf, int cnt, int off64, +asmlinkage int irix_pwrite(int fd, char __user *buf, int cnt, int off64, int off1, int off2) { printk("[%s:%d] Wheee.. irix_pwrite(%d,%p,%d,%d,%d,%d)\n", @@ -1638,7 +1614,7 @@ struct irix_statvfs64 { u32 f_filler[16]; }; -asmlinkage int irix_statvfs64(char *fname, struct irix_statvfs64 *buf) +asmlinkage int irix_statvfs64(char __user *fname, struct irix_statvfs64 __user *buf) { struct nameidata nd; struct kstatfs kbuf; @@ -1650,6 +1626,7 @@ asmlinkage int irix_statvfs64(char *fname, struct irix_statvfs64 *buf) error = -EFAULT; goto out; } + error = user_path_walk(fname, &nd); if (error) goto out; @@ -1657,27 +1634,25 @@ asmlinkage int irix_statvfs64(char *fname, struct irix_statvfs64 *buf) if (error) goto dput_and_out; - __put_user(kbuf.f_bsize, &buf->f_bsize); - __put_user(kbuf.f_frsize, &buf->f_frsize); - __put_user(kbuf.f_blocks, &buf->f_blocks); - __put_user(kbuf.f_bfree, &buf->f_bfree); - __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - __put_user(kbuf.f_files, &buf->f_files); - __put_user(kbuf.f_ffree, &buf->f_ffree); - __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ + error = __put_user(kbuf.f_bsize, &buf->f_bsize); + error |= __put_user(kbuf.f_frsize, &buf->f_frsize); + error |= __put_user(kbuf.f_blocks, &buf->f_blocks); + error |= __put_user(kbuf.f_bfree, &buf->f_bfree); + error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ + error |= __put_user(kbuf.f_files, &buf->f_files); + error |= __put_user(kbuf.f_ffree, &buf->f_ffree); + error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ #ifdef __MIPSEB__ - __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); #else - __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); #endif for(i = 0; i < 16; i++) - __put_user(0, &buf->f_basetype[i]); - __put_user(0, &buf->f_flag); - __put_user(kbuf.f_namelen, &buf->f_namemax); + error |= __put_user(0, &buf->f_basetype[i]); + error |= __put_user(0, &buf->f_flag); + error |= __put_user(kbuf.f_namelen, &buf->f_namemax); for(i = 0; i < 32; i++) - __put_user(0, &buf->f_fstr[i]); - - error = 0; + error |= __put_user(0, &buf->f_fstr[i]); dput_and_out: path_release(&nd); @@ -1685,7 +1660,7 @@ out: return error; } -asmlinkage int irix_fstatvfs64(int fd, struct irix_statvfs *buf) +asmlinkage int irix_fstatvfs64(int fd, struct irix_statvfs __user *buf) { struct kstatfs kbuf; struct file *file; @@ -1706,24 +1681,24 @@ asmlinkage int irix_fstatvfs64(int fd, struct irix_statvfs *buf) if (error) goto out_f; - __put_user(kbuf.f_bsize, &buf->f_bsize); - __put_user(kbuf.f_frsize, &buf->f_frsize); - __put_user(kbuf.f_blocks, &buf->f_blocks); - __put_user(kbuf.f_bfree, &buf->f_bfree); - __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - __put_user(kbuf.f_files, &buf->f_files); - __put_user(kbuf.f_ffree, &buf->f_ffree); - __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ + error = __put_user(kbuf.f_bsize, &buf->f_bsize); + error |= __put_user(kbuf.f_frsize, &buf->f_frsize); + error |= __put_user(kbuf.f_blocks, &buf->f_blocks); + error |= __put_user(kbuf.f_bfree, &buf->f_bfree); + error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ + error |= __put_user(kbuf.f_files, &buf->f_files); + error |= __put_user(kbuf.f_ffree, &buf->f_ffree); + error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ #ifdef __MIPSEB__ - __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); #else - __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); #endif for(i = 0; i < 16; i++) - __put_user(0, &buf->f_basetype[i]); - __put_user(0, &buf->f_flag); - __put_user(kbuf.f_namelen, &buf->f_namemax); - __clear_user(buf->f_fstr, sizeof(buf->f_fstr[i])); + error |= __put_user(0, &buf->f_basetype[i]); + error |= __put_user(0, &buf->f_flag); + error |= __put_user(kbuf.f_namelen, &buf->f_namemax); + error |= __clear_user(buf->f_fstr, sizeof(buf->f_fstr[i])) ? -EFAULT : 0; out_f: fput(file); @@ -1731,9 +1706,9 @@ out: return error; } -asmlinkage int irix_getmountid(char *fname, unsigned long *midbuf) +asmlinkage int irix_getmountid(char __user *fname, unsigned long __user *midbuf) { - int err = 0; + int err; printk("[%s:%d] irix_getmountid(%s, %p)\n", current->comm, current->pid, fname, midbuf); @@ -1746,7 +1721,7 @@ asmlinkage int irix_getmountid(char *fname, unsigned long *midbuf) * fsid of the filesystem to try and make the right decision, but * we don't have this so for now. XXX */ - err |= __put_user(0, &midbuf[0]); + err = __put_user(0, &midbuf[0]); err |= __put_user(0, &midbuf[1]); err |= __put_user(0, &midbuf[2]); err |= __put_user(0, &midbuf[3]); @@ -1773,8 +1748,8 @@ struct irix_dirent32 { }; struct irix_dirent32_callback { - struct irix_dirent32 *current_dir; - struct irix_dirent32 *previous; + struct irix_dirent32 __user *current_dir; + struct irix_dirent32 __user *previous; int count; int error; }; @@ -1782,13 +1757,13 @@ struct irix_dirent32_callback { #define NAME_OFFSET32(de) ((int) ((de)->d_name - (char *) (de))) #define ROUND_UP32(x) (((x)+sizeof(u32)-1) & ~(sizeof(u32)-1)) -static int irix_filldir32(void *__buf, const char *name, int namlen, - loff_t offset, ino_t ino, unsigned int d_type) +static int irix_filldir32(void *__buf, const char *name, + int namlen, loff_t offset, ino_t ino, unsigned int d_type) { - struct irix_dirent32 *dirent; - struct irix_dirent32_callback *buf = - (struct irix_dirent32_callback *)__buf; + struct irix_dirent32 __user *dirent; + struct irix_dirent32_callback *buf = __buf; unsigned short reclen = ROUND_UP32(NAME_OFFSET32(dirent) + namlen + 1); + int err = 0; #ifdef DEBUG_GETDENTS printk("\nirix_filldir32[reclen<%d>namlen<%d>count<%d>]", @@ -1799,25 +1774,26 @@ static int irix_filldir32(void *__buf, const char *name, int namlen, return -EINVAL; dirent = buf->previous; if (dirent) - __put_user(offset, &dirent->d_off); + err = __put_user(offset, &dirent->d_off); dirent = buf->current_dir; - buf->previous = dirent; - __put_user(ino, &dirent->d_ino); - __put_user(reclen, &dirent->d_reclen); - copy_to_user(dirent->d_name, name, namlen); - __put_user(0, &dirent->d_name[namlen]); - ((char *) dirent) += reclen; + err |= __put_user(dirent, &buf->previous); + err |= __put_user(ino, &dirent->d_ino); + err |= __put_user(reclen, &dirent->d_reclen); + err |= copy_to_user((char __user *)dirent->d_name, name, namlen) ? -EFAULT : 0; + err |= __put_user(0, &dirent->d_name[namlen]); + dirent = (struct irix_dirent32 __user *) ((char __user *) dirent + reclen); + buf->current_dir = dirent; buf->count -= reclen; - return 0; + return err; } -asmlinkage int irix_ngetdents(unsigned int fd, void * dirent, - unsigned int count, int *eob) +asmlinkage int irix_ngetdents(unsigned int fd, void __user * dirent, + unsigned int count, int __user *eob) { struct file *file; - struct irix_dirent32 *lastdirent; + struct irix_dirent32 __user *lastdirent; struct irix_dirent32_callback buf; int error; @@ -1830,7 +1806,7 @@ asmlinkage int irix_ngetdents(unsigned int fd, void * dirent, if (!file) goto out; - buf.current_dir = (struct irix_dirent32 *) dirent; + buf.current_dir = (struct irix_dirent32 __user *) dirent; buf.previous = NULL; buf.count = count; buf.error = 0; @@ -1870,8 +1846,8 @@ struct irix_dirent64 { }; struct irix_dirent64_callback { - struct irix_dirent64 *curr; - struct irix_dirent64 *previous; + struct irix_dirent64 __user *curr; + struct irix_dirent64 __user *previous; int count; int error; }; @@ -1879,37 +1855,44 @@ struct irix_dirent64_callback { #define NAME_OFFSET64(de) ((int) ((de)->d_name - (char *) (de))) #define ROUND_UP64(x) (((x)+sizeof(u64)-1) & ~(sizeof(u64)-1)) -static int irix_filldir64(void * __buf, const char * name, int namlen, - loff_t offset, ino_t ino, unsigned int d_type) +static int irix_filldir64(void *__buf, const char *name, + int namlen, loff_t offset, ino_t ino, unsigned int d_type) { - struct irix_dirent64 *dirent; - struct irix_dirent64_callback * buf = - (struct irix_dirent64_callback *) __buf; + struct irix_dirent64 __user *dirent; + struct irix_dirent64_callback * buf = __buf; unsigned short reclen = ROUND_UP64(NAME_OFFSET64(dirent) + namlen + 1); + int err = 0; - buf->error = -EINVAL; /* only used if we fail.. */ + if (!access_ok(VERIFY_WRITE, buf, sizeof(*buf))) + return -EFAULT; + + if (__put_user(-EINVAL, &buf->error)) /* only used if we fail.. */ + return -EFAULT; if (reclen > buf->count) return -EINVAL; dirent = buf->previous; if (dirent) - __put_user(offset, &dirent->d_off); + err = __put_user(offset, &dirent->d_off); dirent = buf->curr; buf->previous = dirent; - __put_user(ino, &dirent->d_ino); - __put_user(reclen, &dirent->d_reclen); - __copy_to_user(dirent->d_name, name, namlen); - __put_user(0, &dirent->d_name[namlen]); - ((char *) dirent) += reclen; + err |= __put_user(ino, &dirent->d_ino); + err |= __put_user(reclen, &dirent->d_reclen); + err |= __copy_to_user((char __user *)dirent->d_name, name, namlen) + ? -EFAULT : 0; + err |= __put_user(0, &dirent->d_name[namlen]); + + dirent = (struct irix_dirent64 __user *) ((char __user *) dirent + reclen); + buf->curr = dirent; buf->count -= reclen; - return 0; + return err; } -asmlinkage int irix_getdents64(int fd, void *dirent, int cnt) +asmlinkage int irix_getdents64(int fd, void __user *dirent, int cnt) { struct file *file; - struct irix_dirent64 *lastdirent; + struct irix_dirent64 __user *lastdirent; struct irix_dirent64_callback buf; int error; @@ -1929,7 +1912,7 @@ asmlinkage int irix_getdents64(int fd, void *dirent, int cnt) if (cnt < (sizeof(struct irix_dirent64) + 255)) goto out_f; - buf.curr = (struct irix_dirent64 *) dirent; + buf.curr = (struct irix_dirent64 __user *) dirent; buf.previous = NULL; buf.count = cnt; buf.error = 0; @@ -1941,7 +1924,8 @@ asmlinkage int irix_getdents64(int fd, void *dirent, int cnt) error = buf.error; goto out_f; } - lastdirent->d_off = (u64) file->f_pos; + if (put_user(file->f_pos, &lastdirent->d_off)) + return -EFAULT; #ifdef DEBUG_GETDENTS printk("returning %d\n", cnt - buf.count); #endif @@ -1953,10 +1937,10 @@ out: return error; } -asmlinkage int irix_ngetdents64(int fd, void *dirent, int cnt, int *eob) +asmlinkage int irix_ngetdents64(int fd, void __user *dirent, int cnt, int *eob) { struct file *file; - struct irix_dirent64 *lastdirent; + struct irix_dirent64 __user *lastdirent; struct irix_dirent64_callback buf; int error; @@ -1978,7 +1962,7 @@ asmlinkage int irix_ngetdents64(int fd, void *dirent, int cnt, int *eob) goto out_f; *eob = 0; - buf.curr = (struct irix_dirent64 *) dirent; + buf.curr = (struct irix_dirent64 __user *) dirent; buf.previous = NULL; buf.count = cnt; buf.error = 0; @@ -1990,7 +1974,8 @@ asmlinkage int irix_ngetdents64(int fd, void *dirent, int cnt, int *eob) error = buf.error; goto out_f; } - lastdirent->d_off = (u64) file->f_pos; + if (put_user(file->f_pos, &lastdirent->d_off)) + return -EFAULT; #ifdef DEBUG_GETDENTS printk("eob=%d returning %d\n", *eob, cnt - buf.count); #endif @@ -2053,14 +2038,14 @@ out: return retval; } -asmlinkage int irix_utssys(char *inbuf, int arg, int type, char *outbuf) +asmlinkage int irix_utssys(char __user *inbuf, int arg, int type, char __user *outbuf) { int retval; switch(type) { case 0: /* uname() */ - retval = irix_uname((struct iuname *)inbuf); + retval = irix_uname((struct iuname __user *)inbuf); goto out; case 2: diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 0dd0df7a3b04..a24651dfaaba 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -11,6 +11,7 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ +#include <linux/config.h> #include <linux/types.h> #include <linux/kernel.h> #include <linux/init.h> @@ -25,6 +26,7 @@ #include <linux/module.h> #include <asm/bootinfo.h> +#include <asm/cache.h> #include <asm/compiler.h> #include <asm/cpu.h> #include <asm/cpu-features.h> @@ -76,7 +78,7 @@ int (*rtc_set_mmss)(unsigned long); static unsigned int sll32_usecs_per_cycle; /* how many counter cycles in a jiffy */ -static unsigned long cycles_per_jiffy; +static unsigned long cycles_per_jiffy __read_mostly; /* Cycle counter value at the previous timer interrupt.. */ static unsigned int timerhi, timerlo; @@ -98,7 +100,10 @@ static unsigned int null_hpt_read(void) return 0; } -static void null_hpt_init(unsigned int count) { /* nothing */ } +static void null_hpt_init(unsigned int count) +{ + /* nothing */ +} /* @@ -108,8 +113,10 @@ static void c0_timer_ack(void) { unsigned int count; +#ifndef CONFIG_SOC_PNX8550 /* pnx8550 resets to zero */ /* Ack this timer interrupt and set the next one. */ expirelo += cycles_per_jiffy; +#endif write_c0_compare(expirelo); /* Check to see if we have missed any timer interrupts. */ @@ -224,7 +231,6 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); ntp_clear(); - write_sequnlock_irq(&xtime_lock); clock_was_set(); return 0; diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index a53b1ed7b386..6f3ff9690686 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -9,7 +9,7 @@ * Copyright (C) 1999 Silicon Graphics, Inc. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000, 01 MIPS Technologies, Inc. - * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki + * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki */ #include <linux/config.h> #include <linux/init.h> @@ -20,12 +20,16 @@ #include <linux/smp_lock.h> #include <linux/spinlock.h> #include <linux/kallsyms.h> +#include <linux/bootmem.h> #include <asm/bootinfo.h> #include <asm/branch.h> #include <asm/break.h> #include <asm/cpu.h> +#include <asm/dsp.h> #include <asm/fpu.h> +#include <asm/mipsregs.h> +#include <asm/mipsmtregs.h> #include <asm/module.h> #include <asm/pgtable.h> #include <asm/ptrace.h> @@ -54,14 +58,19 @@ extern asmlinkage void handle_tr(void); extern asmlinkage void handle_fpe(void); extern asmlinkage void handle_mdmx(void); extern asmlinkage void handle_watch(void); +extern asmlinkage void handle_mt(void); +extern asmlinkage void handle_dsp(void); extern asmlinkage void handle_mcheck(void); extern asmlinkage void handle_reserved(void); -extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, +extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx); void (*board_be_init)(void); int (*board_be_handler)(struct pt_regs *regs, int is_fixup); +void (*board_nmi_handler_setup)(void); +void (*board_ejtag_handler_setup)(void); +void (*board_bind_eic_interrupt)(int irq, int regset); /* * These constant is for searching for possible module text segments. @@ -201,32 +210,47 @@ void show_regs(struct pt_regs *regs) printk("Status: %08x ", (uint32_t) regs->cp0_status); - if (regs->cp0_status & ST0_KX) - printk("KX "); - if (regs->cp0_status & ST0_SX) - printk("SX "); - if (regs->cp0_status & ST0_UX) - printk("UX "); - switch (regs->cp0_status & ST0_KSU) { - case KSU_USER: - printk("USER "); - break; - case KSU_SUPERVISOR: - printk("SUPERVISOR "); - break; - case KSU_KERNEL: - printk("KERNEL "); - break; - default: - printk("BAD_MODE "); - break; + if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { + if (regs->cp0_status & ST0_KUO) + printk("KUo "); + if (regs->cp0_status & ST0_IEO) + printk("IEo "); + if (regs->cp0_status & ST0_KUP) + printk("KUp "); + if (regs->cp0_status & ST0_IEP) + printk("IEp "); + if (regs->cp0_status & ST0_KUC) + printk("KUc "); + if (regs->cp0_status & ST0_IEC) + printk("IEc "); + } else { + if (regs->cp0_status & ST0_KX) + printk("KX "); + if (regs->cp0_status & ST0_SX) + printk("SX "); + if (regs->cp0_status & ST0_UX) + printk("UX "); + switch (regs->cp0_status & ST0_KSU) { + case KSU_USER: + printk("USER "); + break; + case KSU_SUPERVISOR: + printk("SUPERVISOR "); + break; + case KSU_KERNEL: + printk("KERNEL "); + break; + default: + printk("BAD_MODE "); + break; + } + if (regs->cp0_status & ST0_ERL) + printk("ERL "); + if (regs->cp0_status & ST0_EXL) + printk("EXL "); + if (regs->cp0_status & ST0_IE) + printk("IE "); } - if (regs->cp0_status & ST0_ERL) - printk("ERL "); - if (regs->cp0_status & ST0_EXL) - printk("EXL "); - if (regs->cp0_status & ST0_IE) - printk("IE "); printk("\n"); printk("Cause : %08x\n", cause); @@ -252,29 +276,18 @@ void show_registers(struct pt_regs *regs) static DEFINE_SPINLOCK(die_lock); -NORET_TYPE void __die(const char * str, struct pt_regs * regs, - const char * file, const char * func, unsigned long line) +NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs) { static int die_counter; console_verbose(); spin_lock_irq(&die_lock); - printk("%s", str); - if (file && func) - printk(" in %s:%s, line %ld", file, func, line); - printk("[#%d]:\n", ++die_counter); + printk("%s[#%d]:\n", str, ++die_counter); show_registers(regs); spin_unlock_irq(&die_lock); do_exit(SIGSEGV); } -void __die_if_kernel(const char * str, struct pt_regs * regs, - const char * file, const char * func, unsigned long line) -{ - if (!user_mode(regs)) - __die(str, regs, file, func, line); -} - extern const struct exception_table_entry __start___dbe_table[]; extern const struct exception_table_entry __stop___dbe_table[]; @@ -339,9 +352,9 @@ asmlinkage void do_be(struct pt_regs *regs) static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode) { - unsigned int *epc; + unsigned int __user *epc; - epc = (unsigned int *) regs->cp0_epc + + epc = (unsigned int __user *) regs->cp0_epc + ((regs->cp0_cause & CAUSEF_BD) != 0); if (!get_user(*opcode, epc)) return 0; @@ -360,6 +373,10 @@ static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode) #define OFFSET 0x0000ffff #define LL 0xc0000000 #define SC 0xe0000000 +#define SPEC3 0x7c000000 +#define RD 0x0000f800 +#define FUNC 0x0000003f +#define RDHWR 0x0000003b /* * The ll_bit is cleared by r*_switch.S @@ -371,7 +388,7 @@ static struct task_struct *ll_task = NULL; static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) { - unsigned long value, *vaddr; + unsigned long value, __user *vaddr; long offset; int signal = 0; @@ -385,7 +402,8 @@ static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) offset <<= 16; offset >>= 16; - vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset); + vaddr = (unsigned long __user *) + ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); if ((unsigned long)vaddr & 3) { signal = SIGBUS; @@ -407,9 +425,10 @@ static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) preempt_enable(); + compute_return_epc(regs); + regs->regs[(opcode & RT) >> 16] = value; - compute_return_epc(regs); return; sig: @@ -418,7 +437,8 @@ sig: static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) { - unsigned long *vaddr, reg; + unsigned long __user *vaddr; + unsigned long reg; long offset; int signal = 0; @@ -432,7 +452,8 @@ static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) offset <<= 16; offset >>= 16; - vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset); + vaddr = (unsigned long __user *) + ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); reg = (opcode & RT) >> 16; if ((unsigned long)vaddr & 3) { @@ -443,9 +464,9 @@ static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) preempt_disable(); if (ll_bit == 0 || ll_task != current) { + compute_return_epc(regs); regs->regs[reg] = 0; preempt_enable(); - compute_return_epc(regs); return; } @@ -456,9 +477,9 @@ static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) goto sig; } + compute_return_epc(regs); regs->regs[reg] = 1; - compute_return_epc(regs); return; sig: @@ -491,6 +512,37 @@ static inline int simulate_llsc(struct pt_regs *regs) return -EFAULT; /* Strange things going on ... */ } +/* + * Simulate trapping 'rdhwr' instructions to provide user accessible + * registers not implemented in hardware. The only current use of this + * is the thread area pointer. + */ +static inline int simulate_rdhwr(struct pt_regs *regs) +{ + struct thread_info *ti = current->thread_info; + unsigned int opcode; + + if (unlikely(get_insn_opcode(regs, &opcode))) + return -EFAULT; + + if (unlikely(compute_return_epc(regs))) + return -EFAULT; + + if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { + int rd = (opcode & RD) >> 11; + int rt = (opcode & RT) >> 16; + switch (rd) { + case 29: + regs->regs[rt] = ti->tp_value; + break; + default: + return -EFAULT; + } + } + + return 0; +} + asmlinkage void do_ov(struct pt_regs *regs) { siginfo_t info; @@ -498,7 +550,7 @@ asmlinkage void do_ov(struct pt_regs *regs) info.si_code = FPE_INTOVF; info.si_signo = SIGFPE; info.si_errno = 0; - info.si_addr = (void *)regs->cp0_epc; + info.si_addr = (void __user *) regs->cp0_epc; force_sig_info(SIGFPE, &info, current); } @@ -512,6 +564,14 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) preempt_disable(); +#ifdef CONFIG_PREEMPT + if (!is_fpu_owner()) { + /* We might lose fpu before disabling preempt... */ + own_fpu(); + BUG_ON(!used_math()); + restore_fp(current); + } +#endif /* * Unimplemented operation exception. If we've got the full * software emulator on-board, let's use it... @@ -523,11 +583,18 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) * a bit extreme for what should be an infrequent event. */ save_fp(current); + /* Ensure 'resume' not overwrite saved fp context again. */ + lose_fpu(); + + preempt_enable(); /* Run the emulator */ - sig = fpu_emulator_cop1Handler (0, regs, + sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu.soft); + preempt_disable(); + + own_fpu(); /* Using the FPU again. */ /* * We can't allow the emulated instruction to leave any of * the cause bit set in $fcr31. @@ -584,7 +651,7 @@ asmlinkage void do_bp(struct pt_regs *regs) info.si_code = FPE_INTOVF; info.si_signo = SIGFPE; info.si_errno = 0; - info.si_addr = (void *)regs->cp0_epc; + info.si_addr = (void __user *) regs->cp0_epc; force_sig_info(SIGFPE, &info, current); break; default: @@ -621,7 +688,7 @@ asmlinkage void do_tr(struct pt_regs *regs) info.si_code = FPE_INTOVF; info.si_signo = SIGFPE; info.si_errno = 0; - info.si_addr = (void *)regs->cp0_epc; + info.si_addr = (void __user *) regs->cp0_epc; force_sig_info(SIGFPE, &info, current); break; default: @@ -637,6 +704,9 @@ asmlinkage void do_ri(struct pt_regs *regs) if (!simulate_llsc(regs)) return; + if (!simulate_rdhwr(regs)) + return; + force_sig(SIGILL, current); } @@ -650,11 +720,13 @@ asmlinkage void do_cpu(struct pt_regs *regs) switch (cpid) { case 0: - if (cpu_has_llsc) - break; + if (!cpu_has_llsc) + if (!simulate_llsc(regs)) + return; - if (!simulate_llsc(regs)) + if (!simulate_rdhwr(regs)) return; + break; case 1: @@ -668,15 +740,15 @@ asmlinkage void do_cpu(struct pt_regs *regs) set_used_math(); } + preempt_enable(); + if (!cpu_has_fpu) { - int sig = fpu_emulator_cop1Handler(0, regs, + int sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu.soft); if (sig) force_sig(sig, current); } - preempt_enable(); - return; case 2: @@ -716,6 +788,22 @@ asmlinkage void do_mcheck(struct pt_regs *regs) (regs->cp0_status & ST0_TS) ? "" : "not "); } +asmlinkage void do_mt(struct pt_regs *regs) +{ + die_if_kernel("MIPS MT Thread exception in kernel", regs); + + force_sig(SIGILL, current); +} + + +asmlinkage void do_dsp(struct pt_regs *regs) +{ + if (cpu_has_dsp) + panic("Unexpected DSP exception\n"); + + force_sig(SIGILL, current); +} + asmlinkage void do_reserved(struct pt_regs *regs) { /* @@ -728,6 +816,12 @@ asmlinkage void do_reserved(struct pt_regs *regs) (regs->cp0_cause & 0x7f) >> 2); } +asmlinkage void do_default_vi(struct pt_regs *regs) +{ + show_regs(regs); + panic("Caught unexpected vectored interrupt."); +} + /* * Some MIPS CPUs can enable/disable for cache parity detection, but do * it different ways. @@ -736,16 +830,12 @@ static inline void parity_protection_init(void) { switch (current_cpu_data.cputype) { case CPU_24K: - /* 24K cache parity not currently implemented in FPGA */ - printk(KERN_INFO "Disable cache parity protection for " - "MIPS 24K CPU.\n"); - write_c0_ecc(read_c0_ecc() & ~0x80000000); - break; case CPU_5KC: - /* Set the PE bit (bit 31) in the c0_ecc register. */ - printk(KERN_INFO "Enable cache parity protection for " - "MIPS 5KC/24K CPUs.\n"); - write_c0_ecc(read_c0_ecc() | 0x80000000); + write_c0_ecc(0x80000000); + back_to_back_c0_hazard(); + /* Set the PE bit (bit 31) in the c0_errctl register. */ + printk(KERN_INFO "Cache parity protection %sabled\n", + (read_c0_ecc() & 0x80000000) ? "en" : "dis"); break; case CPU_20KC: case CPU_25KF: @@ -783,7 +873,7 @@ asmlinkage void cache_parity_error(void) reg_val & (1<<22) ? "E0 " : ""); printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); -#if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64) +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) if (reg_val & (1<<22)) printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); @@ -840,7 +930,11 @@ void nmi_exception_handler(struct pt_regs *regs) while(1) ; } +#define VECTORSPACING 0x100 /* for EI/VI mode */ + +unsigned long ebase; unsigned long exception_handlers[32]; +unsigned long vi_handlers[64]; /* * As a side effect of the way this is implemented we're limited @@ -854,13 +948,156 @@ void *set_except_vector(int n, void *addr) exception_handlers[n] = handler; if (n == 0 && cpu_has_divec) { - *(volatile u32 *)(CAC_BASE + 0x200) = 0x08000000 | + *(volatile u32 *)(ebase + 0x200) = 0x08000000 | (0x03ffffff & (handler >> 2)); - flush_icache_range(CAC_BASE + 0x200, CAC_BASE + 0x204); + flush_icache_range(ebase + 0x200, ebase + 0x204); } return (void *)old_handler; } +#ifdef CONFIG_CPU_MIPSR2 +/* + * Shadow register allocation + * FIXME: SMP... + */ + +/* MIPSR2 shadow register sets */ +struct shadow_registers { + spinlock_t sr_lock; /* */ + int sr_supported; /* Number of shadow register sets supported */ + int sr_allocated; /* Bitmap of allocated shadow registers */ +} shadow_registers; + +void mips_srs_init(void) +{ +#ifdef CONFIG_CPU_MIPSR2_SRS + shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; + printk ("%d MIPSR2 register sets available\n", shadow_registers.sr_supported); +#else + shadow_registers.sr_supported = 1; +#endif + shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ + spin_lock_init(&shadow_registers.sr_lock); +} + +int mips_srs_max(void) +{ + return shadow_registers.sr_supported; +} + +int mips_srs_alloc (void) +{ + struct shadow_registers *sr = &shadow_registers; + unsigned long flags; + int set; + + spin_lock_irqsave(&sr->sr_lock, flags); + + for (set = 0; set < sr->sr_supported; set++) { + if ((sr->sr_allocated & (1 << set)) == 0) { + sr->sr_allocated |= 1 << set; + spin_unlock_irqrestore(&sr->sr_lock, flags); + return set; + } + } + + /* None available */ + spin_unlock_irqrestore(&sr->sr_lock, flags); + return -1; +} + +void mips_srs_free (int set) +{ + struct shadow_registers *sr = &shadow_registers; + unsigned long flags; + + spin_lock_irqsave(&sr->sr_lock, flags); + sr->sr_allocated &= ~(1 << set); + spin_unlock_irqrestore(&sr->sr_lock, flags); +} + +void *set_vi_srs_handler (int n, void *addr, int srs) +{ + unsigned long handler; + unsigned long old_handler = vi_handlers[n]; + u32 *w; + unsigned char *b; + + if (!cpu_has_veic && !cpu_has_vint) + BUG(); + + if (addr == NULL) { + handler = (unsigned long) do_default_vi; + srs = 0; + } + else + handler = (unsigned long) addr; + vi_handlers[n] = (unsigned long) addr; + + b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); + + if (srs >= mips_srs_max()) + panic("Shadow register set %d not supported", srs); + + if (cpu_has_veic) { + if (board_bind_eic_interrupt) + board_bind_eic_interrupt (n, srs); + } + else if (cpu_has_vint) { + /* SRSMap is only defined if shadow sets are implemented */ + if (mips_srs_max() > 1) + change_c0_srsmap (0xf << n*4, srs << n*4); + } + + if (srs == 0) { + /* + * If no shadow set is selected then use the default handler + * that does normal register saving and a standard interrupt exit + */ + + extern char except_vec_vi, except_vec_vi_lui; + extern char except_vec_vi_ori, except_vec_vi_end; + const int handler_len = &except_vec_vi_end - &except_vec_vi; + const int lui_offset = &except_vec_vi_lui - &except_vec_vi; + const int ori_offset = &except_vec_vi_ori - &except_vec_vi; + + if (handler_len > VECTORSPACING) { + /* + * Sigh... panicing won't help as the console + * is probably not configured :( + */ + panic ("VECTORSPACING too small"); + } + + memcpy (b, &except_vec_vi, handler_len); + w = (u32 *)(b + lui_offset); + *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); + w = (u32 *)(b + ori_offset); + *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); + flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); + } + else { + /* + * In other cases jump directly to the interrupt handler + * + * It is the handlers responsibility to save registers if required + * (eg hi/lo) and return from the exception using "eret" + */ + w = (u32 *)b; + *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ + *w = 0; + flush_icache_range((unsigned long)b, (unsigned long)(b+8)); + } + + return (void *)old_handler; +} + +void *set_vi_handler (int n, void *addr) +{ + return set_vi_srs_handler (n, addr, 0); +} +#endif + /* * This is used by native signal handling */ @@ -912,6 +1149,7 @@ static inline void signal32_init(void) extern void cpu_cache_init(void); extern void tlb_init(void); +extern void flush_tlb_handlers(void); void __init per_cpu_trap_init(void) { @@ -929,15 +1167,32 @@ void __init per_cpu_trap_init(void) #endif if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) status_set |= ST0_XX; - change_c0_status(ST0_CU|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, + change_c0_status(ST0_CU|ST0_MX|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, status_set); + if (cpu_has_dsp) + set_c0_status(ST0_MX); + +#ifdef CONFIG_CPU_MIPSR2 + write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */ +#endif + /* - * Some MIPS CPUs have a dedicated interrupt vector which reduces the - * interrupt processing overhead. Use it where available. + * Interrupt handling. */ - if (cpu_has_divec) - set_c0_cause(CAUSEF_IV); + if (cpu_has_veic || cpu_has_vint) { + write_c0_ebase (ebase); + /* Setting vector spacing enables EI/VI mode */ + change_c0_intctl (0x3e0, VECTORSPACING); + } + if (cpu_has_divec) { + if (cpu_has_mipsmt) { + unsigned int vpflags = dvpe(); + set_c0_cause(CAUSEF_IV); + evpe(vpflags); + } else + set_c0_cause(CAUSEF_IV); + } cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; TLBMISS_HANDLER_SETUP(); @@ -951,13 +1206,41 @@ void __init per_cpu_trap_init(void) tlb_init(); } +/* Install CPU exception handler */ +void __init set_handler (unsigned long offset, void *addr, unsigned long size) +{ + memcpy((void *)(ebase + offset), addr, size); + flush_icache_range(ebase + offset, ebase + offset + size); +} + +/* Install uncached CPU exception handler */ +void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) +{ +#ifdef CONFIG_32BIT + unsigned long uncached_ebase = KSEG1ADDR(ebase); +#endif +#ifdef CONFIG_64BIT + unsigned long uncached_ebase = TO_UNCAC(ebase); +#endif + + memcpy((void *)(uncached_ebase + offset), addr, size); +} + void __init trap_init(void) { extern char except_vec3_generic, except_vec3_r4000; - extern char except_vec_ejtag_debug; extern char except_vec4; unsigned long i; + if (cpu_has_veic || cpu_has_vint) + ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64); + else + ebase = CAC_BASE; + +#ifdef CONFIG_CPU_MIPSR2 + mips_srs_init(); +#endif + per_cpu_trap_init(); /* @@ -965,7 +1248,7 @@ void __init trap_init(void) * This will be overriden later as suitable for a particular * configuration. */ - memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); + set_handler(0x180, &except_vec3_generic, 0x80); /* * Setup default vectors @@ -977,8 +1260,8 @@ void __init trap_init(void) * Copy the EJTAG debug exception vector handler code to it's final * destination. */ - if (cpu_has_ejtag) - memcpy((void *)(CAC_BASE + 0x300), &except_vec_ejtag_debug, 0x80); + if (cpu_has_ejtag && board_ejtag_handler_setup) + board_ejtag_handler_setup (); /* * Only some CPUs have the watch exceptions. @@ -987,11 +1270,15 @@ void __init trap_init(void) set_except_vector(23, handle_watch); /* - * Some MIPS CPUs have a dedicated interrupt vector which reduces the - * interrupt processing overhead. Use it where available. + * Initialise interrupt handlers */ - if (cpu_has_divec) - memcpy((void *)(CAC_BASE + 0x200), &except_vec4, 0x8); + if (cpu_has_veic || cpu_has_vint) { + int nvec = cpu_has_veic ? 64 : 8; + for (i = 0; i < nvec; i++) + set_vi_handler (i, NULL); + } + else if (cpu_has_divec) + set_handler(0x200, &except_vec4, 0x8); /* * Some CPUs can enable/disable for cache parity detection, but does @@ -1023,21 +1310,6 @@ void __init trap_init(void) set_except_vector(11, handle_cpu); set_except_vector(12, handle_ov); set_except_vector(13, handle_tr); - set_except_vector(22, handle_mdmx); - - if (cpu_has_fpu && !cpu_has_nofpuex) - set_except_vector(15, handle_fpe); - - if (cpu_has_mcheck) - set_except_vector(24, handle_mcheck); - - if (cpu_has_vce) - /* Special exception: R4[04]00 uses also the divec space. */ - memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); - else if (cpu_has_4kex) - memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); - else - memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); if (current_cpu_data.cputype == CPU_R6000 || current_cpu_data.cputype == CPU_R6000A) { @@ -1053,10 +1325,37 @@ void __init trap_init(void) //set_except_vector(15, handle_ndc); } + + if (board_nmi_handler_setup) + board_nmi_handler_setup(); + + if (cpu_has_fpu && !cpu_has_nofpuex) + set_except_vector(15, handle_fpe); + + set_except_vector(22, handle_mdmx); + + if (cpu_has_mcheck) + set_except_vector(24, handle_mcheck); + + if (cpu_has_mipsmt) + set_except_vector(25, handle_mt); + + if (cpu_has_dsp) + set_except_vector(26, handle_dsp); + + if (cpu_has_vce) + /* Special exception: R4[04]00 uses also the divec space. */ + memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); + else if (cpu_has_4kex) + memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); + else + memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); + signal_init(); #ifdef CONFIG_MIPS32_COMPAT signal32_init(); #endif - flush_icache_range(CAC_BASE, CAC_BASE + 0x400); + flush_icache_range(ebase, ebase + 0x400); + flush_tlb_handlers(); } diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 36c5212e0928..5b5a3736cbbc 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -94,7 +94,7 @@ unsigned long unaligned_instructions; #endif static inline int emulate_load_store_insn(struct pt_regs *regs, - void *addr, unsigned long pc, + void __user *addr, unsigned int __user *pc, unsigned long **regptr, unsigned long *newvalue) { union mips_instruction insn; @@ -107,7 +107,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, /* * This load never faults. */ - __get_user(insn.word, (unsigned int *)pc); + __get_user(insn.word, pc); switch (insn.i_format.opcode) { /* @@ -494,8 +494,8 @@ asmlinkage void do_ade(struct pt_regs *regs) { unsigned long *regptr, newval; extern int do_dsemulret(struct pt_regs *); + unsigned int __user *pc; mm_segment_t seg; - unsigned long pc; /* * Address errors may be deliberately induced by the FPU emulator to @@ -515,7 +515,7 @@ asmlinkage void do_ade(struct pt_regs *regs) if ((regs->cp0_badvaddr == regs->cp0_epc) || (regs->cp0_epc & 0x1)) goto sigbus; - pc = exception_epc(regs); + pc = (unsigned int __user *) exception_epc(regs); if ((current->thread.mflags & MF_FIXADE) == 0) goto sigbus; @@ -526,7 +526,7 @@ asmlinkage void do_ade(struct pt_regs *regs) seg = get_fs(); if (!user_mode(regs)) set_fs(KERNEL_DS); - if (!emulate_load_store_insn(regs, (void *)regs->cp0_badvaddr, pc, + if (!emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc, ®ptr, &newval)) { compute_return_epc(regs); /* diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 482ac310c937..25cc856d8e7e 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -54,13 +54,6 @@ SECTIONS *(.data) - /* Align the initial ramdisk image (INITRD) on page boundaries. */ - . = ALIGN(4096); - __rd_start = .; - *(.initrd) - . = ALIGN(4096); - __rd_end = .; - CONSTRUCTORS } _gp = . + 0x8000; @@ -96,12 +89,6 @@ SECTIONS .init.setup : { *(.init.setup) } __setup_end = .; - .early_initcall.init : { - __earlyinitcall_start = .; - *(.initcall.early1.init) - } - __earlyinitcall_end = .; - __initcall_start = .; .initcall.init : { *(.initcall1.init) diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c new file mode 100644 index 000000000000..97fefcc9dbe7 --- /dev/null +++ b/arch/mips/kernel/vpe.c @@ -0,0 +1,1296 @@ +/* + * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +/* + * VPE support module + * + * Provides support for loading a MIPS SP program on VPE1. + * The SP enviroment is rather simple, no tlb's. It needs to be relocatable + * (or partially linked). You should initialise your stack in the startup + * code. This loader looks for the symbol __start and sets up + * execution to resume from there. The MIPS SDE kit contains suitable examples. + * + * To load and run, simply cat a SP 'program file' to /dev/vpe1. + * i.e cat spapp >/dev/vpe1. + * + * You'll need to have the following device files. + * mknod /dev/vpe0 c 63 0 + * mknod /dev/vpe1 c 63 1 + */ +#include <linux/config.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/fs.h> +#include <linux/init.h> +#include <asm/uaccess.h> +#include <linux/slab.h> +#include <linux/list.h> +#include <linux/vmalloc.h> +#include <linux/elf.h> +#include <linux/seq_file.h> +#include <linux/syscalls.h> +#include <linux/moduleloader.h> +#include <linux/interrupt.h> +#include <linux/poll.h> +#include <linux/bootmem.h> +#include <asm/mipsregs.h> +#include <asm/mipsmtregs.h> +#include <asm/cacheflush.h> +#include <asm/atomic.h> +#include <asm/cpu.h> +#include <asm/processor.h> +#include <asm/system.h> + +typedef void *vpe_handle; + +// defined here because the kernel module loader doesn't have +// anything to do with it. +#define SHN_MIPS_SCOMMON 0xff03 + +#ifndef ARCH_SHF_SMALL +#define ARCH_SHF_SMALL 0 +#endif + +/* If this is set, the section belongs in the init part of the module */ +#define INIT_OFFSET_MASK (1UL << (BITS_PER_LONG-1)) + +// temp number, +#define VPE_MAJOR 63 + +static char module_name[] = "vpe"; +static int major = 0; + +/* grab the likely amount of memory we will need. */ +#ifdef CONFIG_MIPS_VPE_LOADER_TOM +#define P_SIZE (2 * 1024 * 1024) +#else +/* add an overhead to the max kmalloc size for non-striped symbols/etc */ +#define P_SIZE (256 * 1024) +#endif + +#define MAX_VPES 16 + +enum vpe_state { + VPE_STATE_UNUSED = 0, + VPE_STATE_INUSE, + VPE_STATE_RUNNING +}; + +enum tc_state { + TC_STATE_UNUSED = 0, + TC_STATE_INUSE, + TC_STATE_RUNNING, + TC_STATE_DYNAMIC +}; + +struct vpe; +typedef struct tc { + enum tc_state state; + int index; + + /* parent VPE */ + struct vpe *pvpe; + + /* The list of TC's with this VPE */ + struct list_head tc; + + /* The global list of tc's */ + struct list_head list; +} tc_t; + +typedef struct vpe { + enum vpe_state state; + + /* (device) minor associated with this vpe */ + int minor; + + /* elfloader stuff */ + void *load_addr; + u32 len; + char *pbuffer; + u32 plen; + + unsigned long __start; + + /* tc's associated with this vpe */ + struct list_head tc; + + /* The list of vpe's */ + struct list_head list; + + /* shared symbol address */ + void *shared_ptr; +} vpe_t; + +struct vpecontrol_ { + /* Virtual processing elements */ + struct list_head vpe_list; + + /* Thread contexts */ + struct list_head tc_list; +} vpecontrol; + +static void release_progmem(void *ptr); +static void dump_vpe(vpe_t * v); +extern void save_gp_address(unsigned int secbase, unsigned int rel); + +/* get the vpe associated with this minor */ +struct vpe *get_vpe(int minor) +{ + struct vpe *v; + + list_for_each_entry(v, &vpecontrol.vpe_list, list) { + if (v->minor == minor) + return v; + } + + printk(KERN_DEBUG "VPE: get_vpe minor %d not found\n", minor); + return NULL; +} + +/* get the vpe associated with this minor */ +struct tc *get_tc(int index) +{ + struct tc *t; + + list_for_each_entry(t, &vpecontrol.tc_list, list) { + if (t->index == index) + return t; + } + + printk(KERN_DEBUG "VPE: get_tc index %d not found\n", index); + + return NULL; +} + +struct tc *get_tc_unused(void) +{ + struct tc *t; + + list_for_each_entry(t, &vpecontrol.tc_list, list) { + if (t->state == TC_STATE_UNUSED) + return t; + } + + printk(KERN_DEBUG "VPE: All TC's are in use\n"); + + return NULL; +} + +/* allocate a vpe and associate it with this minor (or index) */ +struct vpe *alloc_vpe(int minor) +{ + struct vpe *v; + + if ((v = kmalloc(sizeof(struct vpe), GFP_KERNEL)) == NULL) { + printk(KERN_WARNING "VPE: alloc_vpe no mem\n"); + return NULL; + } + + memset(v, 0, sizeof(struct vpe)); + + INIT_LIST_HEAD(&v->tc); + list_add_tail(&v->list, &vpecontrol.vpe_list); + + v->minor = minor; + return v; +} + +/* allocate a tc. At startup only tc0 is running, all other can be halted. */ +struct tc *alloc_tc(int index) +{ + struct tc *t; + + if ((t = kmalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) { + printk(KERN_WARNING "VPE: alloc_tc no mem\n"); + return NULL; + } + + memset(t, 0, sizeof(struct tc)); + + INIT_LIST_HEAD(&t->tc); + list_add_tail(&t->list, &vpecontrol.tc_list); + + t->index = index; + + return t; +} + +/* clean up and free everything */ +void release_vpe(struct vpe *v) +{ + list_del(&v->list); + if (v->load_addr) + release_progmem(v); + kfree(v); +} + +void dump_mtregs(void) +{ + unsigned long val; + + val = read_c0_config3(); + printk("config3 0x%lx MT %ld\n", val, + (val & CONFIG3_MT) >> CONFIG3_MT_SHIFT); + + val = read_c0_mvpconf0(); + printk("mvpconf0 0x%lx, PVPE %ld PTC %ld M %ld\n", val, + (val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT, + val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT); + + val = read_c0_mvpcontrol(); + printk("MVPControl 0x%lx, STLB %ld VPC %ld EVP %ld\n", val, + (val & MVPCONTROL_STLB) >> MVPCONTROL_STLB_SHIFT, + (val & MVPCONTROL_VPC) >> MVPCONTROL_VPC_SHIFT, + (val & MVPCONTROL_EVP)); + + val = read_c0_vpeconf0(); + printk("VPEConf0 0x%lx MVP %ld\n", val, + (val & VPECONF0_MVP) >> VPECONF0_MVP_SHIFT); +} + +/* Find some VPE program space */ +static void *alloc_progmem(u32 len) +{ +#ifdef CONFIG_MIPS_VPE_LOADER_TOM + /* this means you must tell linux to use less memory than you physically have */ + return (void *)((max_pfn * PAGE_SIZE) + KSEG0); +#else + // simple grab some mem for now + return kmalloc(len, GFP_KERNEL); +#endif +} + +static void release_progmem(void *ptr) +{ +#ifndef CONFIG_MIPS_VPE_LOADER_TOM + kfree(ptr); +#endif +} + +/* Update size with this section: return offset. */ +static long get_offset(unsigned long *size, Elf_Shdr * sechdr) +{ + long ret; + + ret = ALIGN(*size, sechdr->sh_addralign ? : 1); + *size = ret + sechdr->sh_size; + return ret; +} + +/* Lay out the SHF_ALLOC sections in a way not dissimilar to how ld + might -- code, read-only data, read-write data, small data. Tally + sizes, and place the offsets into sh_entsize fields: high bit means it + belongs in init. */ +static void layout_sections(struct module *mod, const Elf_Ehdr * hdr, + Elf_Shdr * sechdrs, const char *secstrings) +{ + static unsigned long const masks[][2] = { + /* NOTE: all executable code must be the first section + * in this array; otherwise modify the text_size + * finder in the two loops below */ + {SHF_EXECINSTR | SHF_ALLOC, ARCH_SHF_SMALL}, + {SHF_ALLOC, SHF_WRITE | ARCH_SHF_SMALL}, + {SHF_WRITE | SHF_ALLOC, ARCH_SHF_SMALL}, + {ARCH_SHF_SMALL | SHF_ALLOC, 0} + }; + unsigned int m, i; + + for (i = 0; i < hdr->e_shnum; i++) + sechdrs[i].sh_entsize = ~0UL; + + for (m = 0; m < ARRAY_SIZE(masks); ++m) { + for (i = 0; i < hdr->e_shnum; ++i) { + Elf_Shdr *s = &sechdrs[i]; + + // || strncmp(secstrings + s->sh_name, ".init", 5) == 0) + if ((s->sh_flags & masks[m][0]) != masks[m][0] + || (s->sh_flags & masks[m][1]) + || s->sh_entsize != ~0UL) + continue; + s->sh_entsize = get_offset(&mod->core_size, s); + } + + if (m == 0) + mod->core_text_size = mod->core_size; + + } +} + + +/* from module-elf32.c, but subverted a little */ + +struct mips_hi16 { + struct mips_hi16 *next; + Elf32_Addr *addr; + Elf32_Addr value; +}; + +static struct mips_hi16 *mips_hi16_list; +static unsigned int gp_offs, gp_addr; + +static int apply_r_mips_none(struct module *me, uint32_t *location, + Elf32_Addr v) +{ + return 0; +} + +static int apply_r_mips_gprel16(struct module *me, uint32_t *location, + Elf32_Addr v) +{ + int rel; + + if( !(*location & 0xffff) ) { + rel = (int)v - gp_addr; + } + else { + /* .sbss + gp(relative) + offset */ + /* kludge! */ + rel = (int)(short)((int)v + gp_offs + + (int)(short)(*location & 0xffff) - gp_addr); + } + + if( (rel > 32768) || (rel < -32768) ) { + printk(KERN_ERR + "apply_r_mips_gprel16: relative address out of range 0x%x %d\n", + rel, rel); + return -ENOEXEC; + } + + *location = (*location & 0xffff0000) | (rel & 0xffff); + + return 0; +} + +static int apply_r_mips_pc16(struct module *me, uint32_t *location, + Elf32_Addr v) +{ + int rel; + rel = (((unsigned int)v - (unsigned int)location)); + rel >>= 2; // because the offset is in _instructions_ not bytes. + rel -= 1; // and one instruction less due to the branch delay slot. + + if( (rel > 32768) || (rel < -32768) ) { + printk(KERN_ERR + "apply_r_mips_pc16: relative address out of range 0x%x\n", rel); + return -ENOEXEC; + } + + *location = (*location & 0xffff0000) | (rel & 0xffff); + + return 0; +} + +static int apply_r_mips_32(struct module *me, uint32_t *location, + Elf32_Addr v) +{ + *location += v; + + return 0; +} + +static int apply_r_mips_26(struct module *me, uint32_t *location, + Elf32_Addr v) +{ + if (v % 4) { + printk(KERN_ERR "module %s: dangerous relocation mod4\n", me->name); + return -ENOEXEC; + } + +/* Not desperately convinced this is a good check of an overflow condition + anyway. But it gets in the way of handling undefined weak symbols which + we want to set to zero. + if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { + printk(KERN_ERR + "module %s: relocation overflow\n", + me->name); + return -ENOEXEC; + } +*/ + + *location = (*location & ~0x03ffffff) | + ((*location + (v >> 2)) & 0x03ffffff); + return 0; +} + +static int apply_r_mips_hi16(struct module *me, uint32_t *location, + Elf32_Addr v) +{ + struct mips_hi16 *n; + + /* + * We cannot relocate this one now because we don't know the value of + * the carry we need to add. Save the information, and let LO16 do the + * actual relocation. + */ + n = kmalloc(sizeof *n, GFP_KERNEL); + if (!n) + return -ENOMEM; + + n->addr = location; + n->value = v; + n->next = mips_hi16_list; + mips_hi16_list = n; + + return 0; +} + +static int apply_r_mips_lo16(struct module *me, uint32_t *location, + Elf32_Addr v) +{ + unsigned long insnlo = *location; + Elf32_Addr val, vallo; + + /* Sign extend the addend we extract from the lo insn. */ + vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; + + if (mips_hi16_list != NULL) { + struct mips_hi16 *l; + + l = mips_hi16_list; + while (l != NULL) { + struct mips_hi16 *next; + unsigned long insn; + + /* + * The value for the HI16 had best be the same. + */ + if (v != l->value) { + printk("%d != %d\n", v, l->value); + goto out_danger; + } + + + /* + * Do the HI16 relocation. Note that we actually don't + * need to know anything about the LO16 itself, except + * where to find the low 16 bits of the addend needed + * by the LO16. + */ + insn = *l->addr; + val = ((insn & 0xffff) << 16) + vallo; + val += v; + + /* + * Account for the sign extension that will happen in + * the low bits. + */ + val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff; + + insn = (insn & ~0xffff) | val; + *l->addr = insn; + + next = l->next; + kfree(l); + l = next; + } + + mips_hi16_list = NULL; + } + + /* + * Ok, we're done with the HI16 relocs. Now deal with the LO16. + */ + val = v + vallo; + insnlo = (insnlo & ~0xffff) | (val & 0xffff); + *location = insnlo; + + return 0; + +out_danger: + printk(KERN_ERR "module %s: dangerous " "relocation\n", me->name); + + return -ENOEXEC; +} + +static int (*reloc_handlers[]) (struct module *me, uint32_t *location, + Elf32_Addr v) = { + [R_MIPS_NONE] = apply_r_mips_none, + [R_MIPS_32] = apply_r_mips_32, + [R_MIPS_26] = apply_r_mips_26, + [R_MIPS_HI16] = apply_r_mips_hi16, + [R_MIPS_LO16] = apply_r_mips_lo16, + [R_MIPS_GPREL16] = apply_r_mips_gprel16, + [R_MIPS_PC16] = apply_r_mips_pc16 +}; + + +int apply_relocations(Elf32_Shdr *sechdrs, + const char *strtab, + unsigned int symindex, + unsigned int relsec, + struct module *me) +{ + Elf32_Rel *rel = (void *) sechdrs[relsec].sh_addr; + Elf32_Sym *sym; + uint32_t *location; + unsigned int i; + Elf32_Addr v; + int res; + + for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { + Elf32_Word r_info = rel[i].r_info; + + /* This is where to make the change */ + location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr + + rel[i].r_offset; + /* This is the symbol it is referring to */ + sym = (Elf32_Sym *)sechdrs[symindex].sh_addr + + ELF32_R_SYM(r_info); + + if (!sym->st_value) { + printk(KERN_DEBUG "%s: undefined weak symbol %s\n", + me->name, strtab + sym->st_name); + /* just print the warning, dont barf */ + } + + v = sym->st_value; + + res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v); + if( res ) { + printk(KERN_DEBUG + "relocation error 0x%x sym refer <%s> value 0x%x " + "type 0x%x r_info 0x%x\n", + (unsigned int)location, strtab + sym->st_name, v, + r_info, ELF32_R_TYPE(r_info)); + } + + if (res) + return res; + } + + return 0; +} + +void save_gp_address(unsigned int secbase, unsigned int rel) +{ + gp_addr = secbase + rel; + gp_offs = gp_addr - (secbase & 0xffff0000); +} +/* end module-elf32.c */ + + + +/* Change all symbols so that sh_value encodes the pointer directly. */ +static int simplify_symbols(Elf_Shdr * sechdrs, + unsigned int symindex, + const char *strtab, + const char *secstrings, + unsigned int nsecs, struct module *mod) +{ + Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr; + unsigned long secbase, bssbase = 0; + unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); + int ret = 0, size; + + /* find the .bss section for COMMON symbols */ + for (i = 0; i < nsecs; i++) { + if (strncmp(secstrings + sechdrs[i].sh_name, ".bss", 4) == 0) + bssbase = sechdrs[i].sh_addr; + } + + for (i = 1; i < n; i++) { + switch (sym[i].st_shndx) { + case SHN_COMMON: + /* Allocate space for the symbol in the .bss section. st_value is currently size. + We want it to have the address of the symbol. */ + + size = sym[i].st_value; + sym[i].st_value = bssbase; + + bssbase += size; + break; + + case SHN_ABS: + /* Don't need to do anything */ + break; + + case SHN_UNDEF: + /* ret = -ENOENT; */ + break; + + case SHN_MIPS_SCOMMON: + + printk(KERN_DEBUG + "simplify_symbols: ignoring SHN_MIPS_SCOMMON symbol <%s> st_shndx %d\n", + strtab + sym[i].st_name, sym[i].st_shndx); + + // .sbss section + break; + + default: + secbase = sechdrs[sym[i].st_shndx].sh_addr; + + if (strncmp(strtab + sym[i].st_name, "_gp", 3) == 0) { + save_gp_address(secbase, sym[i].st_value); + } + + sym[i].st_value += secbase; + break; + } + + } + + return ret; +} + +#ifdef DEBUG_ELFLOADER +static void dump_elfsymbols(Elf_Shdr * sechdrs, unsigned int symindex, + const char *strtab, struct module *mod) +{ + Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr; + unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); + + printk(KERN_DEBUG "dump_elfsymbols: n %d\n", n); + for (i = 1; i < n; i++) { + printk(KERN_DEBUG " i %d name <%s> 0x%x\n", i, + strtab + sym[i].st_name, sym[i].st_value); + } +} +#endif + +static void dump_tc(struct tc *t) +{ + printk(KERN_WARNING "VPE: TC index %d TCStatus 0x%lx halt 0x%lx\n", + t->index, read_tc_c0_tcstatus(), read_tc_c0_tchalt()); + printk(KERN_WARNING "VPE: tcrestart 0x%lx\n", read_tc_c0_tcrestart()); +} + +static void dump_tclist(void) +{ + struct tc *t; + + list_for_each_entry(t, &vpecontrol.tc_list, list) { + dump_tc(t); + } +} + +/* We are prepared so configure and start the VPE... */ +int vpe_run(vpe_t * v) +{ + unsigned long val; + struct tc *t; + + /* check we are the Master VPE */ + val = read_c0_vpeconf0(); + if (!(val & VPECONF0_MVP)) { + printk(KERN_WARNING + "VPE: only Master VPE's are allowed to configure MT\n"); + return -1; + } + + /* disable MT (using dvpe) */ + dvpe(); + + /* Put MVPE's into 'configuration state' */ + set_c0_mvpcontrol(MVPCONTROL_VPC); + + if (!list_empty(&v->tc)) { + if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) { + printk(KERN_WARNING "VPE: TC %d is already in use.\n", + t->index); + return -ENOEXEC; + } + } else { + printk(KERN_WARNING "VPE: No TC's associated with VPE %d\n", + v->minor); + return -ENOEXEC; + } + + settc(t->index); + + val = read_vpe_c0_vpeconf0(); + + /* should check it is halted, and not activated */ + if ((read_tc_c0_tcstatus() & TCSTATUS_A) || !(read_tc_c0_tchalt() & TCHALT_H)) { + printk(KERN_WARNING "VPE: TC %d is already doing something!\n", + t->index); + + dump_tclist(); + return -ENOEXEC; + } + + /* Write the address we want it to start running from in the TCPC register. */ + write_tc_c0_tcrestart((unsigned long)v->__start); + + /* write the sivc_info address to tccontext */ + write_tc_c0_tccontext((unsigned long)0); + + /* Set up the XTC bit in vpeconf0 to point at our tc */ + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (t->index << VPECONF0_XTC_SHIFT)); + + /* mark the TC as activated, not interrupt exempt and not dynamically allocatable */ + val = read_tc_c0_tcstatus(); + val = (val & ~(TCSTATUS_DA | TCSTATUS_IXMT)) | TCSTATUS_A; + write_tc_c0_tcstatus(val); + + write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H); + + /* set up VPE1 */ + write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); // no multiple TC's + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); // enable this VPE + + /* + * The sde-kit passes 'memsize' to __start in $a3, so set something + * here... + * Or set $a3 (register 7) to zero and define DFLT_STACK_SIZE and + * DFLT_HEAP_SIZE when you compile your program + */ + + mttgpr(7, 0); + + /* set config to be the same as vpe0, particularly kseg0 coherency alg */ + write_vpe_c0_config(read_c0_config()); + + /* clear out any left overs from a previous program */ + write_vpe_c0_cause(0); + + /* take system out of configuration state */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); + + /* clear interrupts enabled IE, ERL, EXL, and KSU from c0 status */ + write_vpe_c0_status(read_vpe_c0_status() & ~(ST0_ERL | ST0_KSU | ST0_IE | ST0_EXL)); + + /* set it running */ + evpe(EVPE_ENABLE); + + return 0; +} + +static unsigned long find_vpe_symbols(vpe_t * v, Elf_Shdr * sechdrs, + unsigned int symindex, const char *strtab, + struct module *mod) +{ + Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr; + unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); + + for (i = 1; i < n; i++) { + if (strcmp(strtab + sym[i].st_name, "__start") == 0) { + v->__start = sym[i].st_value; + } + + if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) { + v->shared_ptr = (void *)sym[i].st_value; + } + } + + return 0; +} + +/* Allocates a VPE with some program code space(the load address), copies the contents + of the program (p)buffer performing relocatations/etc, free's it when finished. +*/ +int vpe_elfload(vpe_t * v) +{ + Elf_Ehdr *hdr; + Elf_Shdr *sechdrs; + long err = 0; + char *secstrings, *strtab = NULL; + unsigned int len, i, symindex = 0, strindex = 0; + + struct module mod; // so we can re-use the relocations code + + memset(&mod, 0, sizeof(struct module)); + strcpy(mod.name, "VPE dummy prog module"); + + hdr = (Elf_Ehdr *) v->pbuffer; + len = v->plen; + + /* Sanity checks against insmoding binaries or wrong arch, + weird elf version */ + if (memcmp(hdr->e_ident, ELFMAG, 4) != 0 + || hdr->e_type != ET_REL || !elf_check_arch(hdr) + || hdr->e_shentsize != sizeof(*sechdrs)) { + printk(KERN_WARNING + "VPE program, wrong arch or weird elf version\n"); + + return -ENOEXEC; + } + + if (len < hdr->e_shoff + hdr->e_shnum * sizeof(Elf_Shdr)) { + printk(KERN_ERR "VPE program length %u truncated\n", len); + return -ENOEXEC; + } + + /* Convenience variables */ + sechdrs = (void *)hdr + hdr->e_shoff; + secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; + sechdrs[0].sh_addr = 0; + + /* And these should exist, but gcc whinges if we don't init them */ + symindex = strindex = 0; + + for (i = 1; i < hdr->e_shnum; i++) { + + if (sechdrs[i].sh_type != SHT_NOBITS + && len < sechdrs[i].sh_offset + sechdrs[i].sh_size) { + printk(KERN_ERR "VPE program length %u truncated\n", + len); + return -ENOEXEC; + } + + /* Mark all sections sh_addr with their address in the + temporary image. */ + sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset; + + /* Internal symbols and strings. */ + if (sechdrs[i].sh_type == SHT_SYMTAB) { + symindex = i; + strindex = sechdrs[i].sh_link; + strtab = (char *)hdr + sechdrs[strindex].sh_offset; + } + } + + layout_sections(&mod, hdr, sechdrs, secstrings); + + v->load_addr = alloc_progmem(mod.core_size); + memset(v->load_addr, 0, mod.core_size); + + printk("VPE elf_loader: loading to %p\n", v->load_addr); + + for (i = 0; i < hdr->e_shnum; i++) { + void *dest; + + if (!(sechdrs[i].sh_flags & SHF_ALLOC)) + continue; + + dest = v->load_addr + sechdrs[i].sh_entsize; + + if (sechdrs[i].sh_type != SHT_NOBITS) + memcpy(dest, (void *)sechdrs[i].sh_addr, + sechdrs[i].sh_size); + /* Update sh_addr to point to copy in image. */ + sechdrs[i].sh_addr = (unsigned long)dest; + } + + /* Fix up syms, so that st_value is a pointer to location. */ + err = + simplify_symbols(sechdrs, symindex, strtab, secstrings, + hdr->e_shnum, &mod); + if (err < 0) { + printk(KERN_WARNING "VPE: unable to simplify symbols\n"); + goto cleanup; + } + + /* Now do relocations. */ + for (i = 1; i < hdr->e_shnum; i++) { + const char *strtab = (char *)sechdrs[strindex].sh_addr; + unsigned int info = sechdrs[i].sh_info; + + /* Not a valid relocation section? */ + if (info >= hdr->e_shnum) + continue; + + /* Don't bother with non-allocated sections */ + if (!(sechdrs[info].sh_flags & SHF_ALLOC)) + continue; + + if (sechdrs[i].sh_type == SHT_REL) + err = + apply_relocations(sechdrs, strtab, symindex, i, &mod); + else if (sechdrs[i].sh_type == SHT_RELA) + err = apply_relocate_add(sechdrs, strtab, symindex, i, + &mod); + if (err < 0) { + printk(KERN_WARNING + "vpe_elfload: error in relocations err %ld\n", + err); + goto cleanup; + } + } + + /* make sure it's physically written out */ + flush_icache_range((unsigned long)v->load_addr, + (unsigned long)v->load_addr + v->len); + + if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) { + + printk(KERN_WARNING + "VPE: program doesn't contain __start or vpe_shared symbols\n"); + err = -ENOEXEC; + } + + printk(" elf loaded\n"); + +cleanup: + return err; +} + +static void dump_vpe(vpe_t * v) +{ + struct tc *t; + + printk(KERN_DEBUG "VPEControl 0x%lx\n", read_vpe_c0_vpecontrol()); + printk(KERN_DEBUG "VPEConf0 0x%lx\n", read_vpe_c0_vpeconf0()); + + list_for_each_entry(t, &vpecontrol.tc_list, list) { + dump_tc(t); + } +} + +/* checks for VPE is unused and gets ready to load program */ +static int vpe_open(struct inode *inode, struct file *filp) +{ + int minor; + vpe_t *v; + + /* assume only 1 device at the mo. */ + if ((minor = MINOR(inode->i_rdev)) != 1) { + printk(KERN_WARNING "VPE: only vpe1 is supported\n"); + return -ENODEV; + } + + if ((v = get_vpe(minor)) == NULL) { + printk(KERN_WARNING "VPE: unable to get vpe\n"); + return -ENODEV; + } + + if (v->state != VPE_STATE_UNUSED) { + unsigned long tmp; + struct tc *t; + + printk(KERN_WARNING "VPE: device %d already in use\n", minor); + + dvpe(); + dump_vpe(v); + + printk(KERN_WARNING "VPE: re-initialising %d\n", minor); + + release_progmem(v->load_addr); + + t = get_tc(minor); + settc(minor); + tmp = read_tc_c0_tcstatus(); + + /* mark not allocated and not dynamically allocatable */ + tmp &= ~(TCSTATUS_A | TCSTATUS_DA); + tmp |= TCSTATUS_IXMT; /* interrupt exempt */ + write_tc_c0_tcstatus(tmp); + + write_tc_c0_tchalt(TCHALT_H); + + } + + // allocate it so when we get write ops we know it's expected. + v->state = VPE_STATE_INUSE; + + /* this of-course trashes what was there before... */ + v->pbuffer = vmalloc(P_SIZE); + v->plen = P_SIZE; + v->load_addr = NULL; + v->len = 0; + + return 0; +} + +static int vpe_release(struct inode *inode, struct file *filp) +{ + int minor, ret = 0; + vpe_t *v; + Elf_Ehdr *hdr; + + minor = MINOR(inode->i_rdev); + if ((v = get_vpe(minor)) == NULL) + return -ENODEV; + + // simple case of fire and forget, so tell the VPE to run... + + hdr = (Elf_Ehdr *) v->pbuffer; + if (memcmp(hdr->e_ident, ELFMAG, 4) == 0) { + if (vpe_elfload(v) >= 0) + vpe_run(v); + else { + printk(KERN_WARNING "VPE: ELF load failed.\n"); + ret = -ENOEXEC; + } + } else { + printk(KERN_WARNING "VPE: only elf files are supported\n"); + ret = -ENOEXEC; + } + + // cleanup any temp buffers + if (v->pbuffer) + vfree(v->pbuffer); + v->plen = 0; + return ret; +} + +static ssize_t vpe_write(struct file *file, const char __user * buffer, + size_t count, loff_t * ppos) +{ + int minor; + size_t ret = count; + vpe_t *v; + + minor = MINOR(file->f_dentry->d_inode->i_rdev); + if ((v = get_vpe(minor)) == NULL) + return -ENODEV; + + if (v->pbuffer == NULL) { + printk(KERN_ERR "vpe_write: no pbuffer\n"); + return -ENOMEM; + } + + if ((count + v->len) > v->plen) { + printk(KERN_WARNING + "VPE Loader: elf size too big. Perhaps strip uneeded symbols\n"); + return -ENOMEM; + } + + count -= copy_from_user(v->pbuffer + v->len, buffer, count); + if (!count) { + printk("vpe_write: copy_to_user failed\n"); + return -EFAULT; + } + + v->len += count; + return ret; +} + +static struct file_operations vpe_fops = { + .owner = THIS_MODULE, + .open = vpe_open, + .release = vpe_release, + .write = vpe_write +}; + +/* module wrapper entry points */ +/* give me a vpe */ +vpe_handle vpe_alloc(void) +{ + int i; + struct vpe *v; + + /* find a vpe */ + for (i = 1; i < MAX_VPES; i++) { + if ((v = get_vpe(i)) != NULL) { + v->state = VPE_STATE_INUSE; + return v; + } + } + return NULL; +} + +EXPORT_SYMBOL(vpe_alloc); + +/* start running from here */ +int vpe_start(vpe_handle vpe, unsigned long start) +{ + struct vpe *v = vpe; + + v->__start = start; + return vpe_run(v); +} + +EXPORT_SYMBOL(vpe_start); + +/* halt it for now */ +int vpe_stop(vpe_handle vpe) +{ + struct vpe *v = vpe; + struct tc *t; + unsigned int evpe_flags; + + evpe_flags = dvpe(); + + if ((t = list_entry(v->tc.next, struct tc, tc)) != NULL) { + + settc(t->index); + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA); + } + + evpe(evpe_flags); + + return 0; +} + +EXPORT_SYMBOL(vpe_stop); + +/* I've done with it thank you */ +int vpe_free(vpe_handle vpe) +{ + struct vpe *v = vpe; + struct tc *t; + unsigned int evpe_flags; + + if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) { + return -ENOEXEC; + } + + evpe_flags = dvpe(); + + /* Put MVPE's into 'configuration state' */ + set_c0_mvpcontrol(MVPCONTROL_VPC); + + settc(t->index); + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA); + + /* mark the TC unallocated and halt'ed */ + write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A); + write_tc_c0_tchalt(TCHALT_H); + + v->state = VPE_STATE_UNUSED; + + clear_c0_mvpcontrol(MVPCONTROL_VPC); + evpe(evpe_flags); + + return 0; +} + +EXPORT_SYMBOL(vpe_free); + +void *vpe_get_shared(int index) +{ + struct vpe *v; + + if ((v = get_vpe(index)) == NULL) { + printk(KERN_WARNING "vpe: invalid vpe index %d\n", index); + return NULL; + } + + return v->shared_ptr; +} + +EXPORT_SYMBOL(vpe_get_shared); + +static int __init vpe_module_init(void) +{ + struct vpe *v = NULL; + struct tc *t; + unsigned long val; + int i; + + if (!cpu_has_mipsmt) { + printk("VPE loader: not a MIPS MT capable processor\n"); + return -ENODEV; + } + + if ((major = register_chrdev(VPE_MAJOR, module_name, &vpe_fops) < 0)) { + printk("VPE loader: unable to register character device\n"); + return -EBUSY; + } + + if (major == 0) + major = VPE_MAJOR; + + dmt(); + dvpe(); + + /* Put MVPE's into 'configuration state' */ + set_c0_mvpcontrol(MVPCONTROL_VPC); + + /* dump_mtregs(); */ + + INIT_LIST_HEAD(&vpecontrol.vpe_list); + INIT_LIST_HEAD(&vpecontrol.tc_list); + + val = read_c0_mvpconf0(); + for (i = 0; i < ((val & MVPCONF0_PTC) + 1); i++) { + t = alloc_tc(i); + + /* VPE's */ + if (i < ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1) { + settc(i); + + if ((v = alloc_vpe(i)) == NULL) { + printk(KERN_WARNING "VPE: unable to allocate VPE\n"); + return -ENODEV; + } + + list_add(&t->tc, &v->tc); /* add the tc to the list of this vpe's tc's. */ + + /* deactivate all but vpe0 */ + if (i != 0) { + unsigned long tmp = read_vpe_c0_vpeconf0(); + + tmp &= ~VPECONF0_VPA; + + /* master VPE */ + tmp |= VPECONF0_MVP; + write_vpe_c0_vpeconf0(tmp); + } + + /* disable multi-threading with TC's */ + write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); + + if (i != 0) { + write_vpe_c0_status((read_c0_status() & + ~(ST0_IM | ST0_IE | ST0_KSU)) + | ST0_CU0); + + /* set config to be the same as vpe0, particularly kseg0 coherency alg */ + write_vpe_c0_config(read_c0_config()); + } + + } + + /* TC's */ + t->pvpe = v; /* set the parent vpe */ + + if (i != 0) { + unsigned long tmp; + + /* tc 0 will of course be running.... */ + if (i == 0) + t->state = TC_STATE_RUNNING; + + settc(i); + + /* bind a TC to each VPE, May as well put all excess TC's + on the last VPE */ + if (i >= (((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1)) + write_tc_c0_tcbind(read_tc_c0_tcbind() | + ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)); + else + write_tc_c0_tcbind(read_tc_c0_tcbind() | i); + + tmp = read_tc_c0_tcstatus(); + + /* mark not allocated and not dynamically allocatable */ + tmp &= ~(TCSTATUS_A | TCSTATUS_DA); + tmp |= TCSTATUS_IXMT; /* interrupt exempt */ + write_tc_c0_tcstatus(tmp); + + write_tc_c0_tchalt(TCHALT_H); + } + } + + /* release config state */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); + + return 0; +} + +static void __exit vpe_module_exit(void) +{ + struct vpe *v, *n; + + list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) { + if (v->state != VPE_STATE_UNUSED) { + release_vpe(v); + } + } + + unregister_chrdev(major, module_name); +} + +module_init(vpe_module_init); +module_exit(vpe_module_exit); +MODULE_DESCRIPTION("MIPS VPE Loader"); +MODULE_AUTHOR("Elizabeth Clarke, MIPS Technologies, Inc"); +MODULE_LICENSE("GPL"); diff --git a/arch/mips/lasat/Kconfig b/arch/mips/lasat/Kconfig new file mode 100644 index 000000000000..1d2ee8a9be13 --- /dev/null +++ b/arch/mips/lasat/Kconfig @@ -0,0 +1,15 @@ +config PICVUE + tristate "PICVUE LCD display driver" + depends on LASAT + +config PICVUE_PROC + tristate "PICVUE LCD display driver /proc interface" + depends on PICVUE + +config DS1603 + bool "DS1603 RTC driver" + depends on LASAT + +config LASAT_SYSCTL + bool "LASAT sysctl interface" + depends on LASAT diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index c90da1639440..852a41901a5e 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c @@ -71,14 +71,13 @@ static void end_lasat_irq(unsigned int irq) } static struct hw_interrupt_type lasat_irq_type = { - "Lasat", - startup_lasat_irq, - shutdown_lasat_irq, - enable_lasat_irq, - disable_lasat_irq, - mask_and_ack_lasat_irq, - end_lasat_irq, - NULL + .typename = "Lasat", + .startup = startup_lasat_irq, + .shutdown = shutdown_lasat_irq, + .enable = enable_lasat_irq, + .disable = disable_lasat_irq, + .ack = mask_and_ack_lasat_irq, + .end = end_lasat_irq, }; static inline int ls1bit32(unsigned int x) diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c index f2604fab9a99..dcd819d57dae 100644 --- a/arch/mips/lasat/setup.c +++ b/arch/mips/lasat/setup.c @@ -155,7 +155,7 @@ void __init serial_init(void) } #endif -static int __init lasat_setup(void) +void __init plat_setup(void) { int i; lasat_misc = &lasat_misc_info[mips_machtype]; @@ -185,8 +185,4 @@ static int __init lasat_setup(void) change_c0_status(ST0_BEV,0); prom_printf("Lasat specific initialization complete\n"); - - return 0; } - -early_initcall(lasat_setup); diff --git a/arch/mips/lib-32/dump_tlb.c b/arch/mips/lib-32/dump_tlb.c index 019ac8f005d7..46519f4331eb 100644 --- a/arch/mips/lib-32/dump_tlb.c +++ b/arch/mips/lib-32/dump_tlb.c @@ -20,16 +20,25 @@ static inline const char *msk2str(unsigned int mask) { switch (mask) { - case PM_4K: return "4kb"; - case PM_16K: return "16kb"; - case PM_64K: return "64kb"; - case PM_256K: return "256kb"; + case PM_4K: + return "4kb"; + case PM_16K: + return "16kb"; + case PM_64K: + return "64kb"; + case PM_256K: + return "256kb"; #ifndef CONFIG_CPU_VR41XX - case PM_1M: return "1Mb"; - case PM_4M: return "4Mb"; - case PM_16M: return "16Mb"; - case PM_64M: return "64Mb"; - case PM_256M: return "256Mb"; + case PM_1M: + return "1Mb"; + case PM_4M: + return "4Mb"; + case PM_16M: + return "16Mb"; + case PM_64M: + return "64Mb"; + case PM_256M: + return "256Mb"; #endif } @@ -47,7 +56,7 @@ void dump_tlb(int first, int last) unsigned int pagemask, c0, c1, asid; unsigned long long entrylo0, entrylo1; unsigned long entryhi; - int i; + int i; asid = read_c0_entryhi() & 0xff; @@ -58,7 +67,7 @@ void dump_tlb(int first, int last) tlb_read(); BARRIER(); pagemask = read_c0_pagemask(); - entryhi = read_c0_entryhi(); + entryhi = read_c0_entryhi(); entrylo0 = read_c0_entrylo0(); entrylo1 = read_c0_entrylo1(); @@ -78,13 +87,11 @@ void dump_tlb(int first, int last) printk("\t\t\t[pa=%08Lx c=%d d=%d v=%d g=%Ld]\n", (entrylo0 << 6) & PAGE_MASK, c0, (entrylo0 & 4) ? 1 : 0, - (entrylo0 & 2) ? 1 : 0, - (entrylo0 & 1)); + (entrylo0 & 2) ? 1 : 0, (entrylo0 & 1)); printk("\t\t\t[pa=%08Lx c=%d d=%d v=%d g=%Ld]\n", (entrylo1 << 6) & PAGE_MASK, c1, (entrylo1 & 4) ? 1 : 0, - (entrylo1 & 2) ? 1 : 0, - (entrylo1 & 1)); + (entrylo1 & 2) ? 1 : 0, (entrylo1 & 1)); printk("\n"); } } @@ -99,7 +106,7 @@ void dump_tlb_all(void) void dump_tlb_wired(void) { - int wired; + int wired; wired = read_c0_wired(); printk("Wired: %d", wired); @@ -138,9 +145,10 @@ void dump_tlb_nonwired(void) void dump_list_process(struct task_struct *t, void *address) { - pgd_t *page_dir, *pgd; - pmd_t *pmd; - pte_t *pte, page; + pgd_t *page_dir, *pgd; + pud_t *pud; + pmd_t *pmd; + pte_t *pte, page; unsigned long addr, val; addr = (unsigned long) address; @@ -152,21 +160,27 @@ void dump_list_process(struct task_struct *t, void *address) if (addr > KSEG0) page_dir = pgd_offset_k(0); - else + else if (t->mm) { page_dir = pgd_offset(t->mm, 0); - printk("page_dir == %08x\n", (unsigned int) page_dir); + printk("page_dir == %08x\n", (unsigned int) page_dir); + } else + printk("Current thread has no mm\n"); if (addr > KSEG0) pgd = pgd_offset_k(addr); - else + else if (t->mm) { pgd = pgd_offset(t->mm, addr); - printk("pgd == %08x, ", (unsigned int) pgd); + printk("pgd == %08x, ", (unsigned int) pgd); + pud = pud_offset(pgd, addr); + printk("pud == %08x, ", (unsigned int) pud); - pmd = pmd_offset(pgd, addr); - printk("pmd == %08x, ", (unsigned int) pmd); + pmd = pmd_offset(pud, addr); + printk("pmd == %08x, ", (unsigned int) pmd); - pte = pte_offset(pmd, addr); - printk("pte == %08x, ", (unsigned int) pte); + pte = pte_offset(pmd, addr); + printk("pte == %08x, ", (unsigned int) pte); + } else + printk("Current thread has no mm\n"); page = *pte; #ifdef CONFIG_64BIT_PHYS_ADDR @@ -176,14 +190,22 @@ void dump_list_process(struct task_struct *t, void *address) #endif val = pte_val(page); - if (val & _PAGE_PRESENT) printk("present "); - if (val & _PAGE_READ) printk("read "); - if (val & _PAGE_WRITE) printk("write "); - if (val & _PAGE_ACCESSED) printk("accessed "); - if (val & _PAGE_MODIFIED) printk("modified "); - if (val & _PAGE_R4KBUG) printk("r4kbug "); - if (val & _PAGE_GLOBAL) printk("global "); - if (val & _PAGE_VALID) printk("valid "); + if (val & _PAGE_PRESENT) + printk("present "); + if (val & _PAGE_READ) + printk("read "); + if (val & _PAGE_WRITE) + printk("write "); + if (val & _PAGE_ACCESSED) + printk("accessed "); + if (val & _PAGE_MODIFIED) + printk("modified "); + if (val & _PAGE_R4KBUG) + printk("r4kbug "); + if (val & _PAGE_GLOBAL) + printk("global "); + if (val & _PAGE_VALID) + printk("valid "); printk("\n"); } @@ -194,14 +216,16 @@ void dump_list_current(void *address) unsigned int vtop(void *address) { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; + pgd_t *pgd; + pud_t *pud; + pmd_t *pmd; + pte_t *pte; unsigned int addr, paddr; addr = (unsigned long) address; pgd = pgd_offset(current->mm, addr); - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + pmd = pmd_offset(pud, addr); pte = pte_offset(pmd, addr); paddr = (KSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK; paddr |= (addr & ~PAGE_MASK); @@ -214,9 +238,9 @@ void dump16(unsigned long *p) int i; for (i = 0; i < 8; i++) { - printk("*%08lx == %08lx, ", (unsigned long)p, *p); + printk("*%08lx == %08lx, ", (unsigned long) p, *p); p++; - printk("*%08lx == %08lx\n", (unsigned long)p, *p); + printk("*%08lx == %08lx\n", (unsigned long) p, *p); p++; } } diff --git a/arch/mips/lib-32/r3k_dump_tlb.c b/arch/mips/lib-32/r3k_dump_tlb.c index a878224004e5..4f2cb74f0766 100644 --- a/arch/mips/lib-32/r3k_dump_tlb.c +++ b/arch/mips/lib-32/r3k_dump_tlb.c @@ -105,6 +105,7 @@ void dump_tlb_nonwired(void) void dump_list_process(struct task_struct *t, void *address) { pgd_t *page_dir, *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte, page; unsigned int addr; @@ -121,7 +122,10 @@ void dump_list_process(struct task_struct *t, void *address) pgd = pgd_offset(t->mm, addr); printk("pgd == %08x, ", (unsigned int) pgd); - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + printk("pud == %08x, ", (unsigned int) pud); + + pmd = pmd_offset(pud, addr); printk("pmd == %08x, ", (unsigned int) pmd); pte = pte_offset(pmd, addr); @@ -149,13 +153,15 @@ void dump_list_current(void *address) unsigned int vtop(void *address) { pgd_t *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte; unsigned int addr, paddr; addr = (unsigned long) address; pgd = pgd_offset(current->mm, addr); - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + pmd = pmd_offset(pud, addr); pte = pte_offset(pmd, addr); paddr = (KSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK; paddr |= (addr & ~PAGE_MASK); diff --git a/arch/mips/lib-64/dump_tlb.c b/arch/mips/lib-64/dump_tlb.c index 42f88e055b4c..11a5f015f040 100644 --- a/arch/mips/lib-64/dump_tlb.c +++ b/arch/mips/lib-64/dump_tlb.c @@ -140,6 +140,7 @@ void dump_tlb_nonwired(void) void dump_list_process(struct task_struct *t, void *address) { pgd_t *page_dir, *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte, page; unsigned long addr, val; @@ -155,7 +156,10 @@ void dump_list_process(struct task_struct *t, void *address) pgd = pgd_offset(t->mm, addr); printk("pgd == %016lx\n", (unsigned long) pgd); - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + printk("pud == %016lx\n", (unsigned long) pud); + + pmd = pmd_offset(pud, addr); printk("pmd == %016lx\n", (unsigned long) pmd); pte = pte_offset(pmd, addr); @@ -184,13 +188,15 @@ void dump_list_current(void *address) unsigned int vtop(void *address) { pgd_t *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte; unsigned int addr, paddr; addr = (unsigned long) address; pgd = pgd_offset(current->mm, addr); - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + pmd = pmd_offset(pud, addr); pte = pte_offset(pmd, addr); paddr = (CKSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK; paddr |= (addr & ~PAGE_MASK); diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 037303412909..cf12caf80774 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -2,8 +2,8 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial_copy.o memcpy.o promlib.o \ - strlen_user.o strncpy_user.o strnlen_user.o +lib-y += csum_partial_copy.o memcpy.o promlib.o strlen_user.o strncpy_user.o \ + strnlen_user.o uncached.o obj-y += iomap.o diff --git a/arch/mips/lib/csum_partial_copy.c b/arch/mips/lib/csum_partial_copy.c index ffed0a6a1c16..6e9f366f961d 100644 --- a/arch/mips/lib/csum_partial_copy.c +++ b/arch/mips/lib/csum_partial_copy.c @@ -16,8 +16,8 @@ /* * copy while checksumming, otherwise like csum_partial */ -unsigned int csum_partial_copy_nocheck(const unsigned char *src, unsigned char *dst, - int len, unsigned int sum) +unsigned int csum_partial_copy_nocheck(const unsigned char *src, + unsigned char *dst, int len, unsigned int sum) { /* * It's 2:30 am and I don't feel like doing it real ... @@ -33,8 +33,8 @@ unsigned int csum_partial_copy_nocheck(const unsigned char *src, unsigned char * * Copy from userspace and compute checksum. If we catch an exception * then zero the rest of the buffer. */ -unsigned int csum_partial_copy_from_user (const unsigned char *src, unsigned char *dst, - int len, unsigned int sum, int *err_ptr) +unsigned int csum_partial_copy_from_user (const unsigned char __user *src, + unsigned char *dst, int len, unsigned int sum, int *err_ptr) { int missing; diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S index a78865f76547..7f9aafa4d80e 100644 --- a/arch/mips/lib/memcpy.S +++ b/arch/mips/lib/memcpy.S @@ -13,6 +13,21 @@ * Mnemonic names for arguments to memcpy/__copy_user */ #include <linux/config.h> + +/* + * Hack to resolve longstanding prefetch issue + * + * Prefetching may be fatal on some systems if we're prefetching beyond the + * end of memory on some systems. It's also a seriously bad idea on non + * dma-coherent systems. + */ +#if !defined(CONFIG_DMA_COHERENT) || !defined(CONFIG_DMA_IP27) +#undef CONFIG_CPU_HAS_PREFETCH +#endif +#ifdef CONFIG_MIPS_MALTA +#undef CONFIG_CPU_HAS_PREFETCH +#endif + #include <asm/asm.h> #include <asm/asm-offsets.h> #include <asm/regdef.h> diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c new file mode 100644 index 000000000000..98ce89f8068b --- /dev/null +++ b/arch/mips/lib/uncached.c @@ -0,0 +1,76 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005 Thiemo Seufer + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * Author: Maciej W. Rozycki <macro@mips.com> + */ + +#include <linux/init.h> + +#include <asm/addrspace.h> +#include <asm/bug.h> + +#ifndef CKSEG2 +#define CKSEG2 CKSSEG +#endif +#ifndef TO_PHYS_MASK +#define TO_PHYS_MASK -1 +#endif + +/* + * FUNC is executed in one of the uncached segments, depending on its + * original address as follows: + * + * 1. If the original address is in CKSEG0 or CKSEG1, then the uncached + * segment used is CKSEG1. + * 2. If the original address is in XKPHYS, then the uncached segment + * used is XKPHYS(2). + * 3. Otherwise it's a bug. + * + * The same remapping is done with the stack pointer. Stack handling + * works because we don't handle stack arguments or more complex return + * values, so we can avoid sharing the same stack area between a cached + * and the uncached mode. + */ +unsigned long __init run_uncached(void *func) +{ + register long sp __asm__("$sp"); + register long ret __asm__("$2"); + long lfunc = (long)func, ufunc; + long usp; + + if (sp >= (long)CKSEG0 && sp < (long)CKSEG2) + usp = CKSEG1ADDR(sp); + else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0LL, 0) && + (long long)sp < (long long)PHYS_TO_XKPHYS(8LL, 0)) + usp = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED, + XKPHYS_TO_PHYS((long long)sp)); + else { + BUG(); + usp = sp; + } + if (lfunc >= (long)CKSEG0 && lfunc < (long)CKSEG2) + ufunc = CKSEG1ADDR(lfunc); + else if ((long long)lfunc >= (long long)PHYS_TO_XKPHYS(0LL, 0) && + (long long)lfunc < (long long)PHYS_TO_XKPHYS(8LL, 0)) + ufunc = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED, + XKPHYS_TO_PHYS((long long)lfunc)); + else { + BUG(); + ufunc = lfunc; + } + + __asm__ __volatile__ ( + " move $16, $sp\n" + " move $sp, %1\n" + " jalr %2\n" + " move $sp, $16" + : "=r" (ret) + : "r" (usp), "r" (ufunc) + : "$16", "$31"); + + return ret; +} diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 99c550632d44..aa5818a0d884 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -70,7 +70,7 @@ static int fpux_emu(struct pt_regs *, /* Further private data for which no space exists in mips_fpu_soft_struct */ -struct mips_fpu_emulator_private fpuemuprivate; +struct mips_fpu_emulator_stats fpuemustats; /* Control registers */ @@ -79,7 +79,17 @@ struct mips_fpu_emulator_private fpuemuprivate; /* Convert Mips rounding mode (0..3) to IEEE library modes. */ static const unsigned char ieee_rm[4] = { - IEEE754_RN, IEEE754_RZ, IEEE754_RU, IEEE754_RD + [FPU_CSR_RN] = IEEE754_RN, + [FPU_CSR_RZ] = IEEE754_RZ, + [FPU_CSR_RU] = IEEE754_RU, + [FPU_CSR_RD] = IEEE754_RD, +}; +/* Convert IEEE library modes to Mips rounding mode (0..3). */ +static const unsigned char mips_rm[4] = { + [IEEE754_RN] = FPU_CSR_RN, + [IEEE754_RZ] = FPU_CSR_RZ, + [IEEE754_RD] = FPU_CSR_RD, + [IEEE754_RU] = FPU_CSR_RU, }; #if __mips >= 4 @@ -196,11 +206,11 @@ static int isBranchInstr(mips_instruction * i) static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) { mips_instruction ir; - vaddr_t emulpc, contpc; + void * emulpc, *contpc; unsigned int cond; - if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) { - fpuemuprivate.stats.errors++; + if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) { + fpuemustats.errors++; return SIGBUS; } @@ -221,41 +231,39 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) * Linux MIPS branch emulator operates on context, updating the * cp0_epc. */ - emulpc = REG_TO_VA(xcp->cp0_epc + 4); /* Snapshot emulation target */ + emulpc = (void *) (xcp->cp0_epc + 4); /* Snapshot emulation target */ if (__compute_return_epc(xcp)) { #ifdef CP1DBG printk("failed to emulate branch at %p\n", - REG_TO_VA(xcp->cp0_epc)); + (void *) (xcp->cp0_epc)); #endif return SIGILL; } - if (get_user(ir, (mips_instruction *) emulpc)) { - fpuemuprivate.stats.errors++; + if (get_user(ir, (mips_instruction __user *) emulpc)) { + fpuemustats.errors++; return SIGBUS; } /* __compute_return_epc() will have updated cp0_epc */ - contpc = REG_TO_VA xcp->cp0_epc; + contpc = (void *) xcp->cp0_epc; /* In order not to confuse ptrace() et al, tweak context */ - xcp->cp0_epc = VA_TO_REG emulpc - 4; - } - else { - emulpc = REG_TO_VA xcp->cp0_epc; - contpc = REG_TO_VA(xcp->cp0_epc + 4); + xcp->cp0_epc = (unsigned long) emulpc - 4; + } else { + emulpc = (void *) xcp->cp0_epc; + contpc = (void *) (xcp->cp0_epc + 4); } emul: - fpuemuprivate.stats.emulated++; + fpuemustats.emulated++; switch (MIPSInst_OPCODE(ir)) { -#ifndef SINGLE_ONLY_FPU case ldc1_op:{ - u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + + u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + MIPSInst_SIMM(ir)); u64 val; - fpuemuprivate.stats.loads++; + fpuemustats.loads++; if (get_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } DITOREG(val, MIPSInst_RT(ir)); @@ -263,55 +271,42 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) } case sdc1_op:{ - u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + + u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + MIPSInst_SIMM(ir)); u64 val; - fpuemuprivate.stats.stores++; + fpuemustats.stores++; DIFROMREG(val, MIPSInst_RT(ir)); if (put_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } break; } -#endif case lwc1_op:{ - u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + + u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + MIPSInst_SIMM(ir)); u32 val; - fpuemuprivate.stats.loads++; + fpuemustats.loads++; if (get_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } -#ifdef SINGLE_ONLY_FPU - if (MIPSInst_RT(ir) & 1) { - /* illegal register in single-float mode */ - return SIGILL; - } -#endif SITOREG(val, MIPSInst_RT(ir)); break; } case swc1_op:{ - u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + + u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + MIPSInst_SIMM(ir)); u32 val; - fpuemuprivate.stats.stores++; -#ifdef SINGLE_ONLY_FPU - if (MIPSInst_RT(ir) & 1) { - /* illegal register in single-float mode */ - return SIGILL; - } -#endif + fpuemustats.stores++; SIFROMREG(val, MIPSInst_RT(ir)); if (put_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } break; @@ -320,7 +315,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) case cop1_op: switch (MIPSInst_RS(ir)) { -#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) +#if defined(__mips64) case dmfc_op: /* copregister fs -> gpr[rt] */ if (MIPSInst_RT(ir) != 0) { @@ -337,12 +332,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) case mfc_op: /* copregister rd -> gpr[rt] */ -#ifdef SINGLE_ONLY_FPU - if (MIPSInst_RD(ir) & 1) { - /* illegal register in single-float mode */ - return SIGILL; - } -#endif if (MIPSInst_RT(ir) != 0) { SIFROMREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); @@ -351,12 +340,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) case mtc_op: /* copregister rd <- rt */ -#ifdef SINGLE_ONLY_FPU - if (MIPSInst_RD(ir) & 1) { - /* illegal register in single-float mode */ - return SIGILL; - } -#endif SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); break; @@ -369,9 +352,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) } if (MIPSInst_RD(ir) == FPCREG_CSR) { value = ctx->fcr31; + value = (value & ~0x3) | mips_rm[value & 0x3]; #ifdef CSRTRACE printk("%p gpr[%d]<-csr=%08x\n", - REG_TO_VA(xcp->cp0_epc), + (void *) (xcp->cp0_epc), MIPSInst_RT(ir), value); #endif } @@ -398,14 +382,13 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) if (MIPSInst_RD(ir) == FPCREG_CSR) { #ifdef CSRTRACE printk("%p gpr[%d]->csr=%08x\n", - REG_TO_VA(xcp->cp0_epc), + (void *) (xcp->cp0_epc), MIPSInst_RT(ir), value); #endif - ctx->fcr31 = value; - /* copy new rounding mode and - flush bit to ieee library state! */ - ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0; - ieee754_csr.rm = ieee_rm[value & 0x3]; + value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03); + ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03); + /* convert to ieee library modes */ + ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3]; } if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { return SIGFPE; @@ -445,20 +428,20 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) * instruction */ xcp->cp0_epc += 4; - contpc = REG_TO_VA + contpc = (void *) (xcp->cp0_epc + (MIPSInst_SIMM(ir) << 2)); - if (get_user(ir, (mips_instruction *) - REG_TO_VA xcp->cp0_epc)) { - fpuemuprivate.stats.errors++; + if (get_user(ir, + (mips_instruction __user *) xcp->cp0_epc)) { + fpuemustats.errors++; return SIGBUS; } switch (MIPSInst_OPCODE(ir)) { case lwc1_op: case swc1_op: -#if (__mips >= 2 || __mips64) && !defined(SINGLE_ONLY_FPU) +#if (__mips >= 2 || defined(__mips64)) case ldc1_op: case sdc1_op: #endif @@ -480,7 +463,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) * Single step the non-cp1 * instruction in the dslot */ - return mips_dsemul(xcp, ir, VA_TO_REG contpc); + return mips_dsemul(xcp, ir, (unsigned long) contpc); } else { /* branch not taken */ @@ -539,8 +522,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) } /* we did it !! */ - xcp->cp0_epc = VA_TO_REG(contpc); + xcp->cp0_epc = (unsigned long) contpc; xcp->cp0_cause &= ~CAUSEF_BD; + return 0; } @@ -570,7 +554,7 @@ static const unsigned char cmptab[8] = { static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \ ieee754##p t) \ { \ - struct ieee754_csr ieee754_csr_save; \ + struct _ieee754_csr ieee754_csr_save; \ s = f1 (s, t); \ ieee754_csr_save = ieee754_csr; \ s = f2 (s, r); \ @@ -616,54 +600,38 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, { unsigned rcsr = 0; /* resulting csr */ - fpuemuprivate.stats.cp1xops++; + fpuemustats.cp1xops++; switch (MIPSInst_FMA_FFMT(ir)) { case s_fmt:{ /* 0 */ ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp); ieee754sp fd, fr, fs, ft; - u32 *va; + u32 __user *va; u32 val; switch (MIPSInst_FUNC(ir)) { case lwxc1_op: - va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + + va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemuprivate.stats.loads++; + fpuemustats.loads++; if (get_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } -#ifdef SINGLE_ONLY_FPU - if (MIPSInst_FD(ir) & 1) { - /* illegal register in single-float - * mode - */ - return SIGILL; - } -#endif SITOREG(val, MIPSInst_FD(ir)); break; case swxc1_op: - va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + + va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemuprivate.stats.stores++; -#ifdef SINGLE_ONLY_FPU - if (MIPSInst_FS(ir) & 1) { - /* illegal register in single-float - * mode - */ - return SIGILL; - } -#endif + fpuemustats.stores++; SIFROMREG(val, MIPSInst_FS(ir)); if (put_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } break; @@ -699,8 +667,6 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; - if (ieee754_csr.nod) - ctx->fcr31 |= 0x1000000; if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { /*printk ("SIGFPE: fpu csr = %08x\n", ctx->fcr31); */ @@ -715,34 +681,33 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, break; } -#ifndef SINGLE_ONLY_FPU case d_fmt:{ /* 1 */ ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp); ieee754dp fd, fr, fs, ft; - u64 *va; + u64 __user *va; u64 val; switch (MIPSInst_FUNC(ir)) { case ldxc1_op: - va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + + va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemuprivate.stats.loads++; + fpuemustats.loads++; if (get_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } DITOREG(val, MIPSInst_FD(ir)); break; case sdxc1_op: - va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + + va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemuprivate.stats.stores++; + fpuemustats.stores++; DIFROMREG(val, MIPSInst_FS(ir)); if (put_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } break; @@ -773,7 +738,6 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, } break; } -#endif case 0x7: /* 7 */ if (MIPSInst_FUNC(ir) != pfetch_op) { @@ -810,7 +774,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, #endif } rv; /* resulting value */ - fpuemuprivate.stats.cp1ops++; + fpuemustats.cp1ops++; switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { case s_fmt:{ /* 0 */ union { @@ -834,7 +798,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, goto scopbop; /* unary ops */ -#if __mips >= 2 || __mips64 +#if __mips >= 2 || defined(__mips64) case fsqrt_op: handler.u = ieee754sp_sqrt; goto scopuop; @@ -913,9 +877,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, case fcvts_op: return SIGILL; /* not defined */ case fcvtd_op:{ -#ifdef SINGLE_ONLY_FPU - return SIGILL; /* not defined */ -#else ieee754sp fs; SPFROMREG(fs, MIPSInst_FS(ir)); @@ -923,7 +884,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, rfmt = d_fmt; goto copcsr; } -#endif case fcvtw_op:{ ieee754sp fs; @@ -933,7 +893,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, goto copcsr; } -#if __mips >= 2 || __mips64 +#if __mips >= 2 || defined(__mips64) case fround_op: case ftrunc_op: case fceil_op: @@ -950,7 +910,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, } #endif /* __mips >= 2 */ -#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) +#if defined(__mips64) case fcvtl_op:{ ieee754sp fs; @@ -974,7 +934,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, rfmt = l_fmt; goto copcsr; } -#endif /* __mips64 && !fpu(single) */ +#endif /* defined(__mips64) */ default: if (MIPSInst_FUNC(ir) >= fcmp_op) { @@ -1001,7 +961,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, break; } -#ifndef SINGLE_ONLY_FPU case d_fmt:{ union { ieee754dp(*b) (ieee754dp, ieee754dp); @@ -1024,7 +983,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, goto dcopbop; /* unary ops */ -#if __mips >= 2 || __mips64 +#if __mips >= 2 || defined(__mips64) case fsqrt_op: handler.u = ieee754dp_sqrt; goto dcopuop; @@ -1108,7 +1067,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, goto copcsr; } -#if __mips >= 2 || __mips64 +#if __mips >= 2 || defined(__mips64) case fround_op: case ftrunc_op: case fceil_op: @@ -1125,7 +1084,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, } #endif -#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) +#if defined(__mips64) case fcvtl_op:{ ieee754dp fs; @@ -1149,7 +1108,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, rfmt = l_fmt; goto copcsr; } -#endif /* __mips >= 3 && !fpu(single) */ +#endif /* __mips >= 3 */ default: if (MIPSInst_FUNC(ir) >= fcmp_op) { @@ -1177,7 +1136,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, } break; } -#endif /* ifndef SINGLE_ONLY_FPU */ case w_fmt:{ ieee754sp fs; @@ -1189,21 +1147,19 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, rv.s = ieee754sp_fint(fs.bits); rfmt = s_fmt; goto copcsr; -#ifndef SINGLE_ONLY_FPU case fcvtd_op: /* convert word to double precision real */ SPFROMREG(fs, MIPSInst_FS(ir)); rv.d = ieee754dp_fint(fs.bits); rfmt = d_fmt; goto copcsr; -#endif default: return SIGILL; } break; } -#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) +#if defined(__mips64) case l_fmt:{ switch (MIPSInst_FUNC(ir)) { case fcvts_op: @@ -1256,18 +1212,16 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, ctx->fcr31 &= ~cond; break; } -#ifndef SINGLE_ONLY_FPU case d_fmt: DPTOREG(rv.d, MIPSInst_FD(ir)); break; -#endif case s_fmt: SPTOREG(rv.s, MIPSInst_FD(ir)); break; case w_fmt: SITOREG(rv.w, MIPSInst_FD(ir)); break; -#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) +#if defined(__mips64) case l_fmt: DITOREG(rv.l, MIPSInst_FD(ir)); break; @@ -1279,10 +1233,10 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, return 0; } -int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, +int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) { - gpreg_t oldepc, prevepc; + unsigned long oldepc, prevepc; mips_instruction insn; int sig = 0; @@ -1290,19 +1244,24 @@ int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, do { prevepc = xcp->cp0_epc; - if (get_user(insn, (mips_instruction *) xcp->cp0_epc)) { - fpuemuprivate.stats.errors++; + if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) { + fpuemustats.errors++; return SIGBUS; } if (insn == 0) xcp->cp0_epc += 4; /* skip nops */ else { - /* Update ieee754_csr. Only relevant if we have a - h/w FPU */ - ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0; - ieee754_csr.rm = ieee_rm[ctx->fcr31 & 0x3]; - ieee754_csr.cx = (ctx->fcr31 >> 12) & 0x1f; + /* + * The 'ieee754_csr' is an alias of + * ctx->fcr31. No need to copy ctx->fcr31 to + * ieee754_csr. But ieee754_csr.rm is ieee + * library modes. (not mips rounding mode) + */ + /* convert to ieee library modes */ + ieee754_csr.rm = ieee_rm[ieee754_csr.rm]; sig = cop1Emulate(xcp, ctx); + /* revert to mips rounding mode */ + ieee754_csr.rm = mips_rm[ieee754_csr.rm]; } if (cpu_has_fpu) diff --git a/arch/mips/math-emu/dp_sqrt.c b/arch/mips/math-emu/dp_sqrt.c index c35e871ae975..032328c49888 100644 --- a/arch/mips/math-emu/dp_sqrt.c +++ b/arch/mips/math-emu/dp_sqrt.c @@ -37,7 +37,7 @@ static const unsigned table[] = { ieee754dp ieee754dp_sqrt(ieee754dp x) { - struct ieee754_csr oldcsr; + struct _ieee754_csr oldcsr; ieee754dp y, z, t; unsigned scalx, yh; COMPXDP; diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index aa989c2246da..8079f3d1eca0 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -28,9 +28,6 @@ #endif #define __mips 4 -extern struct mips_fpu_emulator_private fpuemuprivate; - - /* * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when * we have to emulate the instruction in a COP1 branch delay slot. Do @@ -52,10 +49,10 @@ struct emuframe { mips_instruction emul; mips_instruction badinst; mips_instruction cookie; - gpreg_t epc; + unsigned long epc; }; -int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc) +int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) { extern asmlinkage void handle_dsemulret(void); mips_instruction *dsemul_insns; @@ -91,7 +88,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc) */ /* Ensure that the two instructions are in the same cache line */ - dsemul_insns = (mips_instruction *) REG_TO_VA ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); + dsemul_insns = (mips_instruction *) ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); fr = (struct emuframe *) dsemul_insns; /* Verify that the stack pointer is not competely insane */ @@ -104,11 +101,11 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc) err |= __put_user(cpc, &fr->epc); if (unlikely(err)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } - regs->cp0_epc = VA_TO_REG & fr->emul; + regs->cp0_epc = (unsigned long) &fr->emul; flush_cache_sigtramp((unsigned long)&fr->badinst); @@ -118,7 +115,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc) int do_dsemulret(struct pt_regs *xcp) { struct emuframe *fr; - gpreg_t epc; + unsigned long epc; u32 insn, cookie; int err = 0; @@ -141,7 +138,7 @@ int do_dsemulret(struct pt_regs *xcp) err |= __get_user(cookie, &fr->cookie); if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return 0; } diff --git a/arch/mips/math-emu/dsemul.h b/arch/mips/math-emu/dsemul.h index dbd85f95268d..091f0e76730f 100644 --- a/arch/mips/math-emu/dsemul.h +++ b/arch/mips/math-emu/dsemul.h @@ -1,11 +1,5 @@ -typedef long gpreg_t; -typedef void *vaddr_t; - -#define REG_TO_VA (vaddr_t) -#define VA_TO_REG (gpreg_t) - -int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc); -int do_dsemulret(struct pt_regs *xcp); +extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc); +extern int do_dsemulret(struct pt_regs *xcp); /* Instruction which will always cause an address error */ #define AdELOAD 0x8c000001 /* lw $0,1($0) */ diff --git a/arch/mips/math-emu/ieee754.c b/arch/mips/math-emu/ieee754.c index f0a364adbf34..a93c45dbdefd 100644 --- a/arch/mips/math-emu/ieee754.c +++ b/arch/mips/math-emu/ieee754.c @@ -31,6 +31,8 @@ #include "ieee754int.h" +#include "ieee754sp.h" +#include "ieee754dp.h" #define DP_EBIAS 1023 #define DP_EMIN (-1022) @@ -40,20 +42,6 @@ #define SP_EMIN (-126) #define SP_EMAX 127 -/* indexed by class */ -const char *const ieee754_cname[] = { - "Normal", - "Zero", - "Denormal", - "Infinity", - "QNaN", - "SNaN", -}; - -/* the control status register -*/ -struct ieee754_csr ieee754_csr; - /* special constants */ diff --git a/arch/mips/math-emu/ieee754.h b/arch/mips/math-emu/ieee754.h index b8772f46972d..171f177c0f88 100644 --- a/arch/mips/math-emu/ieee754.h +++ b/arch/mips/math-emu/ieee754.h @@ -1,13 +1,8 @@ -/* single and double precision fp ops - * missing extended precision. -*/ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. * http://www.algor.co.uk * - * ######################################################################## - * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. @@ -21,20 +16,18 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * ######################################################################## - */ - -/************************************************************************** * Nov 7, 2000 * Modification to allow integration with Linux kernel * * Kevin D. Kissell, kevink@mips.com and Carsten Langgard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - *************************************************************************/ + */ +#ifndef __ARCH_MIPS_MATH_EMU_IEEE754_H +#define __ARCH_MIPS_MATH_EMU_IEEE754_H -#ifdef __KERNEL__ -/* Going from Algorithmics to Linux native environment, add this */ +#include <asm/byteorder.h> #include <linux/types.h> +#include <linux/sched.h> /* * Not very pretty, but the Linux kernel's normal va_list definition @@ -44,18 +37,7 @@ #include <stdarg.h> #endif -#else - -/* Note that __KERNEL__ is taken to mean Linux kernel */ - -#if #system(OpenBSD) -#include <machine/types.h> -#endif -#include <machine/endian.h> - -#endif /* __KERNEL__ */ - -#if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__) +#ifdef __LITTLE_ENDIAN struct ieee754dp_konst { unsigned mantlo:32; unsigned manthi:20; @@ -86,13 +68,14 @@ typedef union _ieee754sp { } ieee754sp; #endif -#if (defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN) || defined(__MIPSEB__) +#ifdef __BIG_ENDIAN struct ieee754dp_konst { unsigned sign:1; unsigned bexp:11; unsigned manthi:20; unsigned mantlo:32; }; + typedef union _ieee754dp { struct ieee754dp_konst oparts; struct { @@ -222,7 +205,6 @@ ieee754dp ieee754dp_sqrt(ieee754dp x); #define IEEE754_CLASS_INF 0x03 #define IEEE754_CLASS_SNAN 0x04 #define IEEE754_CLASS_QNAN 0x05 -extern const char *const ieee754_cname[]; /* exception numbers */ #define IEEE754_INEXACT 0x01 @@ -251,93 +233,109 @@ extern const char *const ieee754_cname[]; /* "normal" comparisons */ -static __inline int ieee754sp_eq(ieee754sp x, ieee754sp y) +static inline int ieee754sp_eq(ieee754sp x, ieee754sp y) { return ieee754sp_cmp(x, y, IEEE754_CEQ, 0); } -static __inline int ieee754sp_ne(ieee754sp x, ieee754sp y) +static inline int ieee754sp_ne(ieee754sp x, ieee754sp y) { return ieee754sp_cmp(x, y, IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 0); } -static __inline int ieee754sp_lt(ieee754sp x, ieee754sp y) +static inline int ieee754sp_lt(ieee754sp x, ieee754sp y) { return ieee754sp_cmp(x, y, IEEE754_CLT, 0); } -static __inline int ieee754sp_le(ieee754sp x, ieee754sp y) +static inline int ieee754sp_le(ieee754sp x, ieee754sp y) { return ieee754sp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ, 0); } -static __inline int ieee754sp_gt(ieee754sp x, ieee754sp y) +static inline int ieee754sp_gt(ieee754sp x, ieee754sp y) { return ieee754sp_cmp(x, y, IEEE754_CGT, 0); } -static __inline int ieee754sp_ge(ieee754sp x, ieee754sp y) +static inline int ieee754sp_ge(ieee754sp x, ieee754sp y) { return ieee754sp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ, 0); } -static __inline int ieee754dp_eq(ieee754dp x, ieee754dp y) +static inline int ieee754dp_eq(ieee754dp x, ieee754dp y) { return ieee754dp_cmp(x, y, IEEE754_CEQ, 0); } -static __inline int ieee754dp_ne(ieee754dp x, ieee754dp y) +static inline int ieee754dp_ne(ieee754dp x, ieee754dp y) { return ieee754dp_cmp(x, y, IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 0); } -static __inline int ieee754dp_lt(ieee754dp x, ieee754dp y) +static inline int ieee754dp_lt(ieee754dp x, ieee754dp y) { return ieee754dp_cmp(x, y, IEEE754_CLT, 0); } -static __inline int ieee754dp_le(ieee754dp x, ieee754dp y) +static inline int ieee754dp_le(ieee754dp x, ieee754dp y) { return ieee754dp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ, 0); } -static __inline int ieee754dp_gt(ieee754dp x, ieee754dp y) +static inline int ieee754dp_gt(ieee754dp x, ieee754dp y) { return ieee754dp_cmp(x, y, IEEE754_CGT, 0); } -static __inline int ieee754dp_ge(ieee754dp x, ieee754dp y) +static inline int ieee754dp_ge(ieee754dp x, ieee754dp y) { return ieee754dp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ, 0); } -/* like strtod -*/ +/* + * Like strtod + */ ieee754dp ieee754dp_fstr(const char *s, char **endp); char *ieee754dp_tstr(ieee754dp x, int prec, int fmt, int af); -/* the control status register -*/ -struct ieee754_csr { - unsigned pad:13; +/* + * The control status register + */ +struct _ieee754_csr { +#ifdef __BIG_ENDIAN + unsigned pad0:7; unsigned nod:1; /* set 1 for no denormalised numbers */ - unsigned cx:5; /* exceptions this operation */ + unsigned c:1; /* condition */ + unsigned pad1:5; + unsigned cx:6; /* exceptions this operation */ unsigned mx:5; /* exception enable mask */ unsigned sx:5; /* exceptions total */ unsigned rm:2; /* current rounding mode */ +#endif +#ifdef __LITTLE_ENDIAN + unsigned rm:2; /* current rounding mode */ + unsigned sx:5; /* exceptions total */ + unsigned mx:5; /* exception enable mask */ + unsigned cx:6; /* exceptions this operation */ + unsigned pad1:5; + unsigned c:1; /* condition */ + unsigned nod:1; /* set 1 for no denormalised numbers */ + unsigned pad0:7; +#endif }; -extern struct ieee754_csr ieee754_csr; +#define ieee754_csr (*(struct _ieee754_csr *)(¤t->thread.fpu.soft.fcr31)) -static __inline unsigned ieee754_getrm(void) +static inline unsigned ieee754_getrm(void) { return (ieee754_csr.rm); } -static __inline unsigned ieee754_setrm(unsigned rm) +static inline unsigned ieee754_setrm(unsigned rm) { return (ieee754_csr.rm = rm); } @@ -345,14 +343,14 @@ static __inline unsigned ieee754_setrm(unsigned rm) /* * get current exceptions */ -static __inline unsigned ieee754_getcx(void) +static inline unsigned ieee754_getcx(void) { return (ieee754_csr.cx); } /* test for current exception condition */ -static __inline int ieee754_cxtest(unsigned n) +static inline int ieee754_cxtest(unsigned n) { return (ieee754_csr.cx & n); } @@ -360,21 +358,21 @@ static __inline int ieee754_cxtest(unsigned n) /* * get sticky exceptions */ -static __inline unsigned ieee754_getsx(void) +static inline unsigned ieee754_getsx(void) { return (ieee754_csr.sx); } /* clear sticky conditions */ -static __inline unsigned ieee754_clrsx(void) +static inline unsigned ieee754_clrsx(void) { return (ieee754_csr.sx = 0); } /* test for sticky exception condition */ -static __inline int ieee754_sxtest(unsigned n) +static inline int ieee754_sxtest(unsigned n) { return (ieee754_csr.sx & n); } @@ -406,52 +404,34 @@ extern const struct ieee754sp_konst __ieee754sp_spcvals[]; #define ieee754dp_spcvals ((const ieee754dp *)__ieee754dp_spcvals) #define ieee754sp_spcvals ((const ieee754sp *)__ieee754sp_spcvals) -/* return infinity with given sign -*/ -#define ieee754dp_inf(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)]) -#define ieee754dp_zero(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PZERO+(sn)]) -#define ieee754dp_one(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PONE+(sn)]) -#define ieee754dp_ten(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PTEN+(sn)]) -#define ieee754dp_indef() \ - (ieee754dp_spcvals[IEEE754_SPCVAL_INDEF]) -#define ieee754dp_max(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PMAX+(sn)]) -#define ieee754dp_min(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PMIN+(sn)]) -#define ieee754dp_mind(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PMIND+(sn)]) -#define ieee754dp_1e31() \ - (ieee754dp_spcvals[IEEE754_SPCVAL_P1E31]) -#define ieee754dp_1e63() \ - (ieee754dp_spcvals[IEEE754_SPCVAL_P1E63]) - -#define ieee754sp_inf(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)]) -#define ieee754sp_zero(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PZERO+(sn)]) -#define ieee754sp_one(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PONE+(sn)]) -#define ieee754sp_ten(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PTEN+(sn)]) -#define ieee754sp_indef() \ - (ieee754sp_spcvals[IEEE754_SPCVAL_INDEF]) -#define ieee754sp_max(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PMAX+(sn)]) -#define ieee754sp_min(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PMIN+(sn)]) -#define ieee754sp_mind(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PMIND+(sn)]) -#define ieee754sp_1e31() \ - (ieee754sp_spcvals[IEEE754_SPCVAL_P1E31]) -#define ieee754sp_1e63() \ - (ieee754sp_spcvals[IEEE754_SPCVAL_P1E63]) - -/* indefinite integer value -*/ +/* + * Return infinity with given sign + */ +#define ieee754dp_inf(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)]) +#define ieee754dp_zero(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PZERO+(sn)]) +#define ieee754dp_one(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PONE+(sn)]) +#define ieee754dp_ten(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PTEN+(sn)]) +#define ieee754dp_indef() (ieee754dp_spcvals[IEEE754_SPCVAL_INDEF]) +#define ieee754dp_max(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PMAX+(sn)]) +#define ieee754dp_min(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PMIN+(sn)]) +#define ieee754dp_mind(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PMIND+(sn)]) +#define ieee754dp_1e31() (ieee754dp_spcvals[IEEE754_SPCVAL_P1E31]) +#define ieee754dp_1e63() (ieee754dp_spcvals[IEEE754_SPCVAL_P1E63]) + +#define ieee754sp_inf(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)]) +#define ieee754sp_zero(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PZERO+(sn)]) +#define ieee754sp_one(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PONE+(sn)]) +#define ieee754sp_ten(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PTEN+(sn)]) +#define ieee754sp_indef() (ieee754sp_spcvals[IEEE754_SPCVAL_INDEF]) +#define ieee754sp_max(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PMAX+(sn)]) +#define ieee754sp_min(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PMIN+(sn)]) +#define ieee754sp_mind(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PMIND+(sn)]) +#define ieee754sp_1e31() (ieee754sp_spcvals[IEEE754_SPCVAL_P1E31]) +#define ieee754sp_1e63() (ieee754sp_spcvals[IEEE754_SPCVAL_P1E63]) + +/* + * Indefinite integer value + */ #define ieee754si_indef() INT_MAX #ifdef LONG_LONG_MAX #define ieee754di_indef() LONG_LONG_MAX @@ -487,3 +467,5 @@ extern void ieee754_xcpt(struct ieee754xctx *xcp); /* compat */ #define ieee754dp_fix(x) ieee754dp_tint(x) #define ieee754sp_fix(x) ieee754sp_tint(x) + +#endif /* __ARCH_MIPS_MATH_EMU_IEEE754_H */ diff --git a/arch/mips/math-emu/kernel_linkage.c b/arch/mips/math-emu/kernel_linkage.c index 4002f0cf79f3..d187ab71c2ff 100644 --- a/arch/mips/math-emu/kernel_linkage.c +++ b/arch/mips/math-emu/kernel_linkage.c @@ -27,8 +27,6 @@ #include <asm/fpu_emulator.h> -extern struct mips_fpu_emulator_private fpuemuprivate; - #define SIGNALLING_NAN 0x7ff800007ff80000LL void fpu_emulator_init_fpu(void) @@ -65,7 +63,6 @@ int fpu_emulator_save_context(struct sigcontext *sc) &sc->sc_fpregs[i]); } err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); - err |= __put_user(fpuemuprivate.eir, &sc->sc_fpc_eir); return err; } @@ -81,7 +78,6 @@ int fpu_emulator_restore_context(struct sigcontext *sc) &sc->sc_fpregs[i]); } err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); - err |= __get_user(fpuemuprivate.eir, &sc->sc_fpc_eir); return err; } @@ -102,7 +98,6 @@ int fpu_emulator_save_context32(struct sigcontext32 *sc) &sc->sc_fpregs[i]); } err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); - err |= __put_user(fpuemuprivate.eir, &sc->sc_fpc_eir); return err; } @@ -118,7 +113,6 @@ int fpu_emulator_restore_context32(struct sigcontext32 *sc) &sc->sc_fpregs[i]); } err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); - err |= __get_user(fpuemuprivate.eir, &sc->sc_fpc_eir); return err; } diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c index 19d4b0792460..bc0ebc69bfb3 100644 --- a/arch/mips/mips-boards/atlas/atlas_int.c +++ b/arch/mips/mips-boards/atlas/atlas_int.c @@ -76,14 +76,13 @@ static void end_atlas_irq(unsigned int irq) } static struct hw_interrupt_type atlas_irq_type = { - "Atlas", - startup_atlas_irq, - shutdown_atlas_irq, - enable_atlas_irq, - disable_atlas_irq, - mask_and_ack_atlas_irq, - end_atlas_irq, - NULL + .typename = "Atlas", + .startup = startup_atlas_irq, + .shutdown = shutdown_atlas_irq, + .enable = enable_atlas_irq, + .disable = disable_atlas_irq, + .ack = mask_and_ack_atlas_irq, + .end = end_atlas_irq, }; static inline int ls1bit32(unsigned int x) diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c index 0a1dd9bbc02e..625843b30bed 100644 --- a/arch/mips/mips-boards/atlas/atlas_setup.c +++ b/arch/mips/mips-boards/atlas/atlas_setup.c @@ -50,8 +50,10 @@ const char *get_system_type(void) return "MIPS Atlas"; } -static int __init atlas_setup(void) +void __init plat_setup(void) { + mips_pcibios_init(); + ioport_resource.end = 0x7fffffff; serial_init (); @@ -64,12 +66,8 @@ static int __init atlas_setup(void) board_time_init = mips_time_init; board_timer_setup = mips_timer_setup; rtc_get_time = mips_rtc_get_time; - - return 0; } -early_initcall(atlas_setup); - static void __init serial_init(void) { #ifdef CONFIG_SERIAL_8250 diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index 311155d1d3ed..eab5a705e989 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -1,6 +1,8 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard <carstenl@mips.com> + * Maciej W. Rozycki <macro@mips.com> * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -22,18 +24,19 @@ #include <linux/string.h> #include <linux/kernel.h> -#include <asm/io.h> #include <asm/bootinfo.h> +#include <asm/gt64120.h> +#include <asm/io.h> +#include <asm/system.h> +#include <asm/cacheflush.h> +#include <asm/traps.h> + #include <asm/mips-boards/prom.h> #include <asm/mips-boards/generic.h> -#ifdef CONFIG_MIPS_GT64120 -#include <asm/gt64120.h> -#endif -#include <asm/mips-boards/msc01_pci.h> #include <asm/mips-boards/bonito64.h> -#ifdef CONFIG_MIPS_MALTA +#include <asm/mips-boards/msc01_pci.h> + #include <asm/mips-boards/malta.h> -#endif #ifdef CONFIG_KGDB extern int rs_kgdb_hook(int, int); @@ -223,8 +226,34 @@ void __init kgdb_config (void) } #endif +void __init mips_nmi_setup (void) +{ + void *base; + extern char except_vec_nmi; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa80) : + (void *)(CAC_BASE + 0x380); + memcpy(base, &except_vec_nmi, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + +void __init mips_ejtag_setup (void) +{ + void *base; + extern char except_vec_ejtag_debug; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa00) : + (void *)(CAC_BASE + 0x300); + memcpy(base, &except_vec_ejtag_debug, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + void __init prom_init(void) { + u32 start, map, mask, data; + prom_argc = fw_arg0; _prom_argv = (int *) fw_arg1; _prom_envp = (int *) fw_arg2; @@ -266,12 +295,15 @@ void __init prom_init(void) #else GT_WRITE(GT_PCI0_CMD_OFS, 0); #endif + /* Fix up PCI I/O mapping if necessary (for Atlas). */ + start = GT_READ(GT_PCI0IOLD_OFS); + map = GT_READ(GT_PCI0IOREMAP_OFS); + if ((start & map) != 0) { + map &= ~start; + GT_WRITE(GT_PCI0IOREMAP_OFS, map); + } -#ifdef CONFIG_MIPS_MALTA set_io_port_base(MALTA_GT_PORT_BASE); -#else - set_io_port_base((unsigned long)ioremap(0, 0x20000000)); -#endif break; case MIPS_REVISION_CORID_CORE_EMUL_BON: @@ -300,18 +332,21 @@ void __init prom_init(void) BONITO_BONGENCFG_BYTESWAP; #endif -#ifdef CONFIG_MIPS_MALTA set_io_port_base(MALTA_BONITO_PORT_BASE); -#else - set_io_port_base((unsigned long)ioremap(0, 0x20000000)); -#endif break; case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_EMUL_MSC: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); + mb(); + MSC_READ(MSC01_PCI_CFG, data); + MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); + wmb(); + + /* Fix up lane swapping. */ #ifdef CONFIG_CPU_LITTLE_ENDIAN MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); #else @@ -320,12 +355,23 @@ void __init prom_init(void) MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); #endif + /* Fix up target memory mapping. */ + MSC_READ(MSC01_PCI_BAR0, mask); + MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); + + /* Don't handle target retries indefinitely. */ + if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == + MSC01_PCI_CFG_MAXRTRY_MSK) + data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << + MSC01_PCI_CFG_MAXRTRY_SHF)) | + ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << + MSC01_PCI_CFG_MAXRTRY_SHF); + + wmb(); + MSC_WRITE(MSC01_PCI_CFG, data); + mb(); -#ifdef CONFIG_MIPS_MALTA set_io_port_base(MALTA_MSC_PORT_BASE); -#else - set_io_port_base((unsigned long)ioremap(0, 0x20000000)); -#endif break; default: @@ -334,6 +380,9 @@ void __init prom_init(void) while(1); /* We die here... */ } #endif + board_nmi_handler_setup = mips_nmi_setup; + board_ejtag_handler_setup = mips_ejtag_setup; + prom_printf("\nLINUX started...\n"); prom_init_cmdline(); prom_meminit(); diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c index 5ae2b43e4c2e..2c8afd77a20b 100644 --- a/arch/mips/mips-boards/generic/memory.c +++ b/arch/mips/mips-boards/generic/memory.c @@ -22,6 +22,7 @@ #include <linux/init.h> #include <linux/mm.h> #include <linux/bootmem.h> +#include <linux/string.h> #include <asm/bootinfo.h> #include <asm/page.h> @@ -55,18 +56,30 @@ struct prom_pmemblock * __init prom_getmdesc(void) { char *memsize_str; unsigned int memsize; + char cmdline[CL_SIZE], *ptr; - memsize_str = prom_getenv("memsize"); - if (!memsize_str) { - prom_printf("memsize not set in boot prom, set to default (32Mb)\n"); - memsize = 0x02000000; - } else { + /* Check the command line first for a memsize directive */ + strcpy(cmdline, arcs_cmdline); + ptr = strstr(cmdline, "memsize="); + if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) + ptr = strstr(ptr, " memsize="); + + if (ptr) { + memsize = memparse(ptr + 8, &ptr); + } + else { + /* otherwise look in the environment */ + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + prom_printf("memsize not set in boot prom, set to default (32Mb)\n"); + memsize = 0x02000000; + } else { #ifdef DEBUG - prom_printf("prom_memsize = %s\n", memsize_str); + prom_printf("prom_memsize = %s\n", memsize_str); #endif - memsize = simple_strtol(memsize_str, NULL, 0); + memsize = simple_strtol(memsize_str, NULL, 0); + } } - memset(mdesc, 0, sizeof(mdesc)); mdesc[0].type = yamon_dontuse; diff --git a/arch/mips/mips-boards/generic/mipsIRQ.S b/arch/mips/mips-boards/generic/mipsIRQ.S index 131f49bccb20..a397ecb872d6 100644 --- a/arch/mips/mips-boards/generic/mipsIRQ.S +++ b/arch/mips/mips-boards/generic/mipsIRQ.S @@ -29,6 +29,20 @@ #include <asm/regdef.h> #include <asm/stackframe.h> +#ifdef CONFIG_MIPS_ATLAS +#include <asm/mips-boards/atlasint.h> +#define CASCADE_IRQ MIPSCPU_INT_ATLAS +#define CASCADE_DISPATCH atlas_hw0_irqdispatch +#endif +#ifdef CONFIG_MIPS_MALTA +#include <asm/mips-boards/maltaint.h> +#define CASCADE_IRQ MIPSCPU_INT_I8259A +#define CASCADE_DISPATCH malta_hw0_irqdispatch +#endif +#ifdef CONFIG_MIPS_SEAD +#include <asm/mips-boards/seadint.h> +#endif + /* A lot of complication here is taken away because: * * 1) We handle one interrupt and return, sitting in a loop and moving across @@ -80,74 +94,62 @@ mfc0 s0, CP0_CAUSE # get irq bits mfc0 s1, CP0_STATUS # get irq mask + andi s0, ST0_IM # CAUSE.CE may be non-zero! and s0, s1 - /* First we check for r4k counter/timer IRQ. */ - andi a0, s0, CAUSEF_IP7 - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) + .set mips32 + clz a0, s0 + .set mips0 + negu a0 + addu a0, 31-CAUSEB_IP + bltz a0, spurious +#else + beqz s0, spurious + li a0, 7 - /* Wheee, a timer interrupt. */ - move a0, sp - jal mips_timer_interrupt - nop + and t0, s0, 0xf000 + sltiu t0, t0, 1 + sll t0, 2 + subu a0, t0 + sll s0, t0 - j ret_from_irq - nop + and t0, s0, 0xc000 + sltiu t0, t0, 1 + sll t0, 1 + subu a0, t0 + sll s0, t0 -1: -#if defined(CONFIG_MIPS_SEAD) - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt -#else - beq a0, zero, 1f # delay slot, check hw3 interrupt - andi a0, s0, CAUSEF_IP5 + and t0, s0, 0x8000 + sltiu t0, t0, 1 + # sll t0, 0 + subu a0, t0 + # sll s0, t0 #endif - /* Wheee, combined hardware level zero interrupt. */ -#if defined(CONFIG_MIPS_ATLAS) - jal atlas_hw0_irqdispatch -#elif defined(CONFIG_MIPS_MALTA) - jal malta_hw0_irqdispatch -#elif defined(CONFIG_MIPS_SEAD) - jal sead_hw0_irqdispatch -#else -#error "MIPS board not supported\n" -#endif - move a0, sp # delay slot +#ifdef CASCADE_IRQ + li a1, CASCADE_IRQ + bne a0, a1, 1f + addu a0, MIPSCPU_INT_BASE - j ret_from_irq - nop # delay slot + jal CASCADE_DISPATCH + move a0, sp -1: -#if defined(CONFIG_MIPS_SEAD) - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP5 # delay slot, check hw3 interrupt - jal sead_hw1_irqdispatch - move a0, sp # delay slot - j ret_from_irq - nop # delay slot -1: -#endif -#if defined(CONFIG_MIPS_MALTA) - beq a0, zero, 1f # check hw3 (coreHI) interrupt - nop - jal corehi_irqdispatch - move a0, sp j ret_from_irq nop 1: +#else + addu a0, MIPSCPU_INT_BASE #endif - /* - * Here by mistake? This is possible, what can happen is that by the - * time we take the exception the IRQ pin goes low, so just leave if - * this is the case. - */ - move a1,s0 - PRINT("Got interrupt: c0_cause = %08x\n") - mfc0 a1, CP0_EPC - PRINT("c0_epc = %08x\n") + + jal do_IRQ + move a1, sp j ret_from_irq nop + + +spurious: + j spurious_interrupt + nop END(mipsIRQ) diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c index 92c34bda02ae..1f6f9df74ab2 100644 --- a/arch/mips/mips-boards/generic/pci.c +++ b/arch/mips/mips-boards/generic/pci.c @@ -1,6 +1,8 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard <carstenl@mips.com> + * Maciej W. Rozycki <macro@mips.com> * * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) * @@ -19,65 +21,46 @@ * * MIPS boards specific PCI support. */ -#include <linux/config.h> #include <linux/types.h> #include <linux/pci.h> #include <linux/kernel.h> #include <linux/init.h> -#include <asm/mips-boards/generic.h> #include <asm/gt64120.h> + +#include <asm/mips-boards/generic.h> #include <asm/mips-boards/bonito64.h> #include <asm/mips-boards/msc01_pci.h> -#ifdef CONFIG_MIPS_MALTA -#include <asm/mips-boards/malta.h> -#endif static struct resource bonito64_mem_resource = { .name = "Bonito PCI MEM", - .start = 0x10000000UL, - .end = 0x1bffffffUL, .flags = IORESOURCE_MEM, }; static struct resource bonito64_io_resource = { - .name = "Bonito IO MEM", - .start = 0x00002000UL, /* avoid conflicts with YAMON allocated I/O addresses */ + .name = "Bonito PCI I/O", + .start = 0x00000000UL, .end = 0x000fffffUL, .flags = IORESOURCE_IO, }; static struct resource gt64120_mem_resource = { - .name = "GT64120 PCI MEM", - .start = 0x10000000UL, - .end = 0x1bdfffffUL, + .name = "GT-64120 PCI MEM", .flags = IORESOURCE_MEM, }; static struct resource gt64120_io_resource = { - .name = "GT64120 IO MEM", -#ifdef CONFIG_MIPS_ATLAS - .start = 0x18000000UL, - .end = 0x181fffffUL, -#endif -#ifdef CONFIG_MIPS_MALTA - .start = 0x00002000UL, - .end = 0x001fffffUL, -#endif + .name = "GT-64120 PCI I/O", .flags = IORESOURCE_IO, }; static struct resource msc_mem_resource = { .name = "MSC PCI MEM", - .start = 0x10000000UL, - .end = 0x1fffffffUL, .flags = IORESOURCE_MEM, }; static struct resource msc_io_resource = { - .name = "MSC IO MEM", - .start = 0x00002000UL, - .end = 0x007fffffUL, + .name = "MSC PCI I/O", .flags = IORESOURCE_IO, }; @@ -89,7 +72,6 @@ static struct pci_controller bonito64_controller = { .pci_ops = &bonito64_pci_ops, .io_resource = &bonito64_io_resource, .mem_resource = &bonito64_mem_resource, - .mem_offset = 0x10000000UL, .io_offset = 0x00000000UL, }; @@ -97,21 +79,18 @@ static struct pci_controller gt64120_controller = { .pci_ops = >64120_pci_ops, .io_resource = >64120_io_resource, .mem_resource = >64120_mem_resource, - .mem_offset = 0x00000000UL, - .io_offset = 0x00000000UL, }; -static struct pci_controller msc_controller = { +static struct pci_controller msc_controller = { .pci_ops = &msc_pci_ops, .io_resource = &msc_io_resource, .mem_resource = &msc_mem_resource, - .mem_offset = 0x10000000UL, - .io_offset = 0x00000000UL, }; -static int __init pcibios_init(void) +void __init mips_pcibios_init(void) { struct pci_controller *controller; + unsigned long start, end, map, start1, end1, map1, map2, map3, mask; switch (mips_revision_corid) { case MIPS_REVISION_CORID_QED_RM5261: @@ -130,34 +109,140 @@ static int __init pcibios_init(void) (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/ ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/ - GT_PCI0_CFGADDR_CONFIGEN_BIT ); + GT_PCI0_CFGADDR_CONFIGEN_BIT); /* Perform the write */ GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE)); + /* Set up resource ranges from the controller's registers. */ + start = GT_READ(GT_PCI0M0LD_OFS); + end = GT_READ(GT_PCI0M0HD_OFS); + map = GT_READ(GT_PCI0M0REMAP_OFS); + end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); + start1 = GT_READ(GT_PCI0M1LD_OFS); + end1 = GT_READ(GT_PCI0M1HD_OFS); + map1 = GT_READ(GT_PCI0M1REMAP_OFS); + end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK); + /* Cannot support multiple windows, use the wider. */ + if (end1 - start1 > end - start) { + start = start1; + end = end1; + map = map1; + } + mask = ~(start ^ end); + /* We don't support remapping with a discontiguous mask. */ + BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && + mask != ~((mask & -mask) - 1)); + gt64120_mem_resource.start = start; + gt64120_mem_resource.end = end; + gt64120_controller.mem_offset = (start & mask) - (map & mask); + /* Addresses are 36-bit, so do shifts in the destinations. */ + gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF; + gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF; + gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; + gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF; + + start = GT_READ(GT_PCI0IOLD_OFS); + end = GT_READ(GT_PCI0IOHD_OFS); + map = GT_READ(GT_PCI0IOREMAP_OFS); + end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); + mask = ~(start ^ end); + /* We don't support remapping with a discontiguous mask. */ + BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && + mask != ~((mask & -mask) - 1)); + gt64120_io_resource.start = map & mask; + gt64120_io_resource.end = (map & mask) | ~mask; + gt64120_controller.io_offset = 0; + /* Addresses are 36-bit, so do shifts in the destinations. */ + gt64120_io_resource.start <<= GT_PCI_DCRM_SHF; + gt64120_io_resource.end <<= GT_PCI_DCRM_SHF; + gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; + controller = >64120_controller; break; case MIPS_REVISION_CORID_BONITO64: case MIPS_REVISION_CORID_CORE_20K: case MIPS_REVISION_CORID_CORE_EMUL_BON: + /* Set up resource ranges from the controller's registers. */ + map = BONITO_PCIMAP; + map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >> + BONITO_PCIMAP_PCIMAP_LO0_SHIFT; + map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >> + BONITO_PCIMAP_PCIMAP_LO1_SHIFT; + map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >> + BONITO_PCIMAP_PCIMAP_LO2_SHIFT; + /* Combine as many adjacent windows as possible. */ + map = map1; + start = BONITO_PCILO0_BASE; + end = 1; + if (map3 == map2 + 1) { + map = map2; + start = BONITO_PCILO1_BASE; + end++; + } + if (map2 == map1 + 1) { + map = map1; + start = BONITO_PCILO0_BASE; + end++; + } + bonito64_mem_resource.start = start; + bonito64_mem_resource.end = start + + BONITO_PCIMAP_WINBASE(end) - 1; + bonito64_controller.mem_offset = start - + BONITO_PCIMAP_WINBASE(map); + controller = &bonito64_controller; break; case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_EMUL_MSC: + /* Set up resource ranges from the controller's registers. */ + MSC_READ(MSC01_PCI_SC2PMBASL, start); + MSC_READ(MSC01_PCI_SC2PMMSKL, mask); + MSC_READ(MSC01_PCI_SC2PMMAPL, map); + msc_mem_resource.start = start & mask; + msc_mem_resource.end = (start & mask) | ~mask; + msc_controller.mem_offset = (start & mask) - (map & mask); + + MSC_READ(MSC01_PCI_SC2PIOBASL, start); + MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); + MSC_READ(MSC01_PCI_SC2PIOMAPL, map); + msc_io_resource.start = map & mask; + msc_io_resource.end = (map & mask) | ~mask; + msc_controller.io_offset = 0; + ioport_resource.end = ~mask; + + /* If ranges overlap I/O takes precedence. */ + start = start & mask; + end = start | ~mask; + if ((start >= msc_mem_resource.start && + start <= msc_mem_resource.end) || + (end >= msc_mem_resource.start && + end <= msc_mem_resource.end)) { + /* Use the larger space. */ + start = max(start, msc_mem_resource.start); + end = min(end, msc_mem_resource.end); + if (start - msc_mem_resource.start >= + msc_mem_resource.end - end) + msc_mem_resource.end = start - 1; + else + msc_mem_resource.start = end + 1; + } + controller = &msc_controller; break; default: - return 1; + return; } + if (controller->io_resource->start < 0x00001000UL) /* FIXME */ + controller->io_resource->start = 0x00001000UL; + + iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ ioport_resource.end = controller->io_resource->end; register_pci_controller (controller); - - return 0; } - -early_initcall(pcibios_init); diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index 16315444dd5a..72a12d931cba 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -31,22 +31,21 @@ #include <asm/mipsregs.h> #include <asm/ptrace.h> +#include <asm/hardirq.h> +#include <asm/irq.h> #include <asm/div64.h> #include <asm/cpu.h> #include <asm/time.h> #include <asm/mc146818-time.h> +#include <asm/msc01_ic.h> #include <asm/mips-boards/generic.h> #include <asm/mips-boards/prom.h> +#include <asm/mips-boards/maltaint.h> +#include <asm/mc146818-time.h> unsigned long cpu_khz; -#if defined(CONFIG_MIPS_SEAD) -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ5) -#else -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) -#endif - #if defined(CONFIG_MIPS_ATLAS) static char display_string[] = " LINUX ON ATLAS "; #endif @@ -59,20 +58,61 @@ static char display_string[] = " LINUX ON SEAD "; static unsigned int display_count = 0; #define MAX_DISPLAY_COUNT (sizeof(display_string) - 8) -#define MIPS_CPU_TIMER_IRQ (NR_IRQS-1) - static unsigned int timer_tick_count=0; +static int mips_cpu_timer_irq; -void mips_timer_interrupt(struct pt_regs *regs) +static inline void scroll_display_message(void) { if ((timer_tick_count++ % HZ) == 0) { mips_display_message(&display_string[display_count++]); if (display_count == MAX_DISPLAY_COUNT) - display_count = 0; + display_count = 0; + } +} + +static void mips_timer_dispatch (struct pt_regs *regs) +{ + do_IRQ (mips_cpu_timer_irq, regs); +} +irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ +#ifdef CONFIG_SMP + int cpu = smp_processor_id(); + + if (cpu == 0) { + /* + * CPU 0 handles the global timer interrupt job and process accounting + * resets count/compare registers to trigger next timer int. + */ + (void) timer_interrupt(irq, dev_id, regs); + scroll_display_message(); + } + else { + /* Everyone else needs to reset the timer int here as + ll_local_timer_interrupt doesn't */ + /* + * FIXME: need to cope with counter underflow. + * More support needs to be added to kernel/time for + * counter/timer interrupts on multiple CPU's + */ + write_c0_compare (read_c0_count() + (mips_hpt_frequency/HZ)); + /* + * other CPUs should do profiling and process accounting + */ + local_timer_interrupt (irq, dev_id, regs); } - ll_timer_interrupt(MIPS_CPU_TIMER_IRQ, regs); + return IRQ_HANDLED; +#else + irqreturn_t r; + + r = timer_interrupt(irq, dev_id, regs); + + scroll_display_message(); + + return r; +#endif } /* @@ -140,10 +180,8 @@ void __init mips_time_init(void) local_irq_save(flags); -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) /* Set Data mode - binary. */ CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); -#endif est_freq = estimate_cpu_frequency (); @@ -157,11 +195,29 @@ void __init mips_time_init(void) void __init mips_timer_setup(struct irqaction *irq) { + if (cpu_has_veic) { + set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); + mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; + } + else { + if (cpu_has_vint) + set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch); + mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR; + } + + /* we are using the cpu counter for timer interrupts */ - irq->handler = no_action; /* we use our own handler */ - setup_irq(MIPS_CPU_TIMER_IRQ, irq); + irq->handler = mips_timer_interrupt; /* we use our own handler */ + setup_irq(mips_cpu_timer_irq, irq); + +#ifdef CONFIG_SMP + /* irq_desc(riptor) is a global resource, when the interrupt overlaps + on seperate cpu's the first one tries to handle the second interrupt. + The effect is that the int remains disabled on the second cpu. + Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ + irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; +#endif /* to generate the first timer interrupt */ write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); - set_c0_status(ALLINTS); } diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c index dd2db35966bc..d06dc5ad6c9e 100644 --- a/arch/mips/mips-boards/malta/malta_int.c +++ b/arch/mips/mips-boards/malta/malta_int.c @@ -30,6 +30,7 @@ #include <linux/random.h> #include <asm/i8259.h> +#include <asm/irq_cpu.h> #include <asm/io.h> #include <asm/mips-boards/malta.h> #include <asm/mips-boards/maltaint.h> @@ -37,8 +38,10 @@ #include <asm/gt64120.h> #include <asm/mips-boards/generic.h> #include <asm/mips-boards/msc01_pci.h> +#include <asm/msc01_ic.h> extern asmlinkage void mipsIRQ(void); +extern void mips_timer_interrupt(void); static DEFINE_SPINLOCK(mips_irq_lock); @@ -54,6 +57,7 @@ static inline int mips_pcibios_iack(void) switch(mips_revision_corid) { case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_EMUL_MSC: MSC_READ(MSC01_PCI_IACK, irq); irq &= 0xff; @@ -91,88 +95,86 @@ static inline int mips_pcibios_iack(void) return irq; } -static inline int get_int(int *irq) +static inline int get_int(void) { unsigned long flags; - + int irq; spin_lock_irqsave(&mips_irq_lock, flags); - *irq = mips_pcibios_iack(); + irq = mips_pcibios_iack(); /* - * IRQ7 is used to detect spurious interrupts. - * The interrupt acknowledge cycle returns IRQ7, if no - * interrupts is requested. - * We can differentiate between this situation and a - * "Normal" IRQ7 by reading the ISR. + * The only way we can decide if an interrupt is spurious + * is by checking the 8259 registers. This needs a spinlock + * on an SMP system, so leave it up to the generic code... */ - if (*irq == 7) - { - outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR, - PIIX4_ICTLR1_OCW3); - if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) { - spin_unlock_irqrestore(&mips_irq_lock, flags); - printk("We got a spurious interrupt from PIIX4.\n"); - atomic_inc(&irq_err_count); - return -1; /* Spurious interrupt. */ - } - } spin_unlock_irqrestore(&mips_irq_lock, flags); - return 0; + return irq; } void malta_hw0_irqdispatch(struct pt_regs *regs) { int irq; - if (get_int(&irq)) - return; /* interrupt has already been cleared */ + irq = get_int(); + if (irq < 0) + return; /* interrupt has already been cleared */ - do_IRQ(irq, regs); + do_IRQ(MALTA_INT_BASE+irq, regs); } void corehi_irqdispatch(struct pt_regs *regs) { - unsigned int data,datahi; - - /* Mask out corehi interrupt. */ - clear_c0_status(IE_IRQ3); + unsigned int intrcause,datalo,datahi; + unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr; printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n" , regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr); + + /* Read all the registers and then print them as there is a + problem with interspersed printk's upsetting the Bonito controller. + Do it for the others too. + */ + switch(mips_revision_corid) { case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: - case MIPS_REVISION_CORID_CORE_EMUL_MSC: + case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_EMUL_MSC: + ll_msc_irq(regs); break; case MIPS_REVISION_CORID_QED_RM5261: case MIPS_REVISION_CORID_CORE_LV: case MIPS_REVISION_CORID_CORE_FPGA: case MIPS_REVISION_CORID_CORE_FPGAR2: - data = GT_READ(GT_INTRCAUSE_OFS); - printk("GT_INTRCAUSE = %08x\n", data); - data = GT_READ(GT_CPUERR_ADDRLO_OFS); + intrcause = GT_READ(GT_INTRCAUSE_OFS); + datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); - printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, data); + printk("GT_INTRCAUSE = %08x\n", intrcause); + printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo); break; case MIPS_REVISION_CORID_BONITO64: case MIPS_REVISION_CORID_CORE_20K: case MIPS_REVISION_CORID_CORE_EMUL_BON: - data = BONITO_INTISR; - printk("BONITO_INTISR = %08x\n", data); - data = BONITO_INTEN; - printk("BONITO_INTEN = %08x\n", data); - data = BONITO_INTPOL; - printk("BONITO_INTPOL = %08x\n", data); - data = BONITO_INTEDGE; - printk("BONITO_INTEDGE = %08x\n", data); - data = BONITO_INTSTEER; - printk("BONITO_INTSTEER = %08x\n", data); - data = BONITO_PCICMD; - printk("BONITO_PCICMD = %08x\n", data); + pcibadaddr = BONITO_PCIBADADDR; + pcimstat = BONITO_PCIMSTAT; + intisr = BONITO_INTISR; + inten = BONITO_INTEN; + intpol = BONITO_INTPOL; + intedge = BONITO_INTEDGE; + intsteer = BONITO_INTSTEER; + pcicmd = BONITO_PCICMD; + printk("BONITO_INTISR = %08x\n", intisr); + printk("BONITO_INTEN = %08x\n", inten); + printk("BONITO_INTPOL = %08x\n", intpol); + printk("BONITO_INTEDGE = %08x\n", intedge); + printk("BONITO_INTSTEER = %08x\n", intsteer); + printk("BONITO_PCICMD = %08x\n", pcicmd); + printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr); + printk("BONITO_PCIMSTAT = %08x\n", pcimstat); break; } @@ -180,8 +182,71 @@ void corehi_irqdispatch(struct pt_regs *regs) die("CoreHi interrupt", regs); } +static struct irqaction i8259irq = { + .handler = no_action, + .name = "XT-PIC cascade" +}; + +static struct irqaction corehi_irqaction = { + .handler = no_action, + .name = "CoreHi" +}; + +msc_irqmap_t __initdata msc_irqmap[] = { + {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, + {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, +}; +int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t); + +msc_irqmap_t __initdata msc_eicirqmap[] = { + {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, + {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} +}; +int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t); + void __init arch_init_irq(void) { set_except_vector(0, mipsIRQ); init_i8259_irqs(); + + if (!cpu_has_veic) + mips_cpu_irq_init (MIPSCPU_INT_BASE); + + switch(mips_revision_corid) { + case MIPS_REVISION_CORID_CORE_MSC: + case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_EMUL_MSC: + if (cpu_has_veic) + init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); + else + init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); + } + + if (cpu_has_veic) { + set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch); + set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch); + setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); + setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); + } + else if (cpu_has_vint) { + set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); + set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch); + + setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); + setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); + } + else { + set_except_vector(0, mipsIRQ); + setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); + setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); + } } diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c index df6db6419ae9..2209e8a9de34 100644 --- a/arch/mips/mips-boards/malta/malta_setup.c +++ b/arch/mips/mips-boards/malta/malta_setup.c @@ -111,10 +111,12 @@ void __init fd_activate(void) } #endif -static int __init malta_setup(void) +void __init plat_setup(void) { unsigned int i; + mips_pcibios_init(); + /* Request I/O space for devices used on the Malta board. */ for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) request_resource(&ioport_resource, standard_io_resources+i); @@ -224,8 +226,4 @@ static int __init malta_setup(void) board_time_init = mips_time_init; board_timer_setup = mips_timer_setup; rtc_get_time = mips_rtc_get_time; - - return 0; } - -early_initcall(malta_setup); diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c index e5109657ed5a..e1dd7e009750 100644 --- a/arch/mips/mips-boards/sead/sead_int.c +++ b/arch/mips/mips-boards/sead/sead_int.c @@ -2,6 +2,7 @@ * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2004 Maciej W. Rozycki * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -21,7 +22,9 @@ */ #include <linux/init.h> #include <linux/irq.h> -#include <linux/interrupt.h> + +#include <asm/irq_cpu.h> +#include <asm/system.h> #include <asm/mips-boards/seadint.h> @@ -39,13 +42,8 @@ asmlinkage void sead_hw1_irqdispatch(struct pt_regs *regs) void __init arch_init_irq(void) { - /* - * Mask out all interrupt - */ - clear_c0_status(0x0000ff00); + mips_cpu_irq_init(0); /* Now safe to set the exception vector. */ set_except_vector(0, mipsIRQ); - - mips_cpu_irq_init(0); } diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c index 29892b88a4fc..de90bec5505e 100644 --- a/arch/mips/mips-boards/sead/sead_setup.c +++ b/arch/mips/mips-boards/sead/sead_setup.c @@ -57,8 +57,6 @@ static void __init sead_setup(void) mips_reboot_setup(); } -early_initcall(sead_setup); - static void __init serial_init(void) { #ifdef CONFIG_SERIAL_8250 diff --git a/arch/mips/mips-boards/sim/Makefile b/arch/mips/mips-boards/sim/Makefile new file mode 100644 index 000000000000..5b977de4ecff --- /dev/null +++ b/arch/mips/mips-boards/sim/Makefile @@ -0,0 +1,20 @@ +# +# Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. +# +# This program is free software; you can distribute it and/or modify it +# under the terms of the GNU General Public License (Version 2) as +# published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. +# + +obj-y := sim_setup.o sim_mem.o sim_time.o sim_printf.o sim_int.o sim_irq.o \ + sim_cmdline.o +obj-$(CONFIG_SMP) += sim_smp.o diff --git a/arch/mips/mips-boards/sim/cmdline.c b/arch/mips/mips-boards/sim/cmdline.c new file mode 100644 index 000000000000..fef9fbd8e710 --- /dev/null +++ b/arch/mips/mips-boards/sim/cmdline.c @@ -0,0 +1,59 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Kernel command line creation using the prom monitor (YAMON) argc/argv. + */ +#include <linux/init.h> +#include <linux/string.h> + +#include <asm/bootinfo.h> + +extern int prom_argc; +extern int *_prom_argv; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension. + */ +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)])) + +char arcs_cmdline[CL_SIZE]; + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + + +void __init prom_init_cmdline(void) +{ + char *cp; + int actr; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while(actr < prom_argc) { + strcpy(cp, prom_argv(actr)); + cp += strlen(prom_argv(actr)); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ + --cp; + *cp = '\0'; +} diff --git a/arch/mips/mips-boards/sim/sim_IRQ.c b/arch/mips/mips-boards/sim/sim_IRQ.c new file mode 100644 index 000000000000..9987a85aabeb --- /dev/null +++ b/arch/mips/mips-boards/sim/sim_IRQ.c @@ -0,0 +1,148 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Interrupt exception dispatch code. + */ +#include <linux/config.h> + +#include <asm/asm.h> +#include <asm/mipsregs.h> +#include <asm/regdef.h> +#include <asm/stackframe.h> + +/* A lot of complication here is taken away because: + * + * 1) We handle one interrupt and return, sitting in a loop and moving across + * all the pending IRQ bits in the cause register is _NOT_ the answer, the + * common case is one pending IRQ so optimize in that direction. + * + * 2) We need not check against bits in the status register IRQ mask, that + * would make this routine slow as hell. + * + * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in + * between like BSD spl() brain-damage. + * + * Furthermore, the IRQs on the MIPS board look basically (barring software + * IRQs which we don't use at all and all external interrupt sources are + * combined together on hardware interrupt 0 (MIPS IRQ 2)) like: + * + * MIPS IRQ Source + * -------- ------ + * 0 Software (ignored) + * 1 Software (ignored) + * 2 Combined hardware interrupt (hw0) + * 3 Hardware (ignored) + * 4 Hardware (ignored) + * 5 Hardware (ignored) + * 6 Hardware (ignored) + * 7 R4k timer (what we use) + * + * Note: On the SEAD board thing are a little bit different. + * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired + * wired to UART1. + * + * We handle the IRQ according to _our_ priority which is: + * + * Highest ---- R4k Timer + * Lowest ---- Combined hardware interrupt + * + * then we just return, if multiple IRQs are pending then we will just take + * another exception, big deal. + */ + + .text + .set noreorder + .set noat + .align 5 + NESTED(mipsIRQ, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + + mfc0 s0, CP0_CAUSE # get irq bits + mfc0 s1, CP0_STATUS # get irq mask + and s0, s1 + + /* First we check for r4k counter/timer IRQ. */ + andi a0, s0, CAUSEF_IP7 + beq a0, zero, 1f + andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt + + /* Wheee, a timer interrupt. */ + move a0, sp + jal mips_timer_interrupt + nop + + j ret_from_irq + nop + +1: +#if defined(CONFIG_MIPS_SEAD) + beq a0, zero, 1f + andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt +#else + beq a0, zero, 1f # delay slot, check hw3 interrupt + andi a0, s0, CAUSEF_IP5 +#endif + + /* Wheee, combined hardware level zero interrupt. */ +#if defined(CONFIG_MIPS_ATLAS) + jal atlas_hw0_irqdispatch +#elif defined(CONFIG_MIPS_MALTA) + jal malta_hw0_irqdispatch +#elif defined(CONFIG_MIPS_SEAD) + jal sead_hw0_irqdispatch +#else +#error "MIPS board not supported\n" +#endif + move a0, sp # delay slot + + j ret_from_irq + nop # delay slot + +1: +#if defined(CONFIG_MIPS_SEAD) + beq a0, zero, 1f + andi a0, s0, CAUSEF_IP5 # delay slot, check hw3 interrupt + jal sead_hw1_irqdispatch + move a0, sp # delay slot + j ret_from_irq + nop # delay slot +1: +#endif +#if defined(CONFIG_MIPS_MALTA) + beq a0, zero, 1f # check hw3 (coreHI) interrupt + nop + jal corehi_irqdispatch + move a0, sp + j ret_from_irq + nop +1: +#endif + /* + * Here by mistake? This is possible, what can happen is that by the + * time we take the exception the IRQ pin goes low, so just leave if + * this is the case. + */ + move a1,s0 + PRINT("Got interrupt: c0_cause = %08x\n") + mfc0 a1, CP0_EPC + PRINT("c0_epc = %08x\n") + + j ret_from_irq + nop + END(mipsIRQ) diff --git a/arch/mips/mips-boards/sim/sim_cmdline.c b/arch/mips/mips-boards/sim/sim_cmdline.c new file mode 100644 index 000000000000..9df37c6fca36 --- /dev/null +++ b/arch/mips/mips-boards/sim/sim_cmdline.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include <linux/init.h> +#include <linux/string.h> +#include <asm/bootinfo.h> + +extern char arcs_cmdline[]; + +char * __init prom_getcmdline(void) +{ + return arcs_cmdline; +} + + +void __init prom_init_cmdline(void) +{ + /* nothing to do */ +} diff --git a/arch/mips/mips-boards/sim/sim_int.c b/arch/mips/mips-boards/sim/sim_int.c new file mode 100644 index 000000000000..a4d0a2c05031 --- /dev/null +++ b/arch/mips/mips-boards/sim/sim_int.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/interrupt.h> +#include <linux/kernel_stat.h> +#include <asm/mips-boards/simint.h> + + +extern void mips_cpu_irq_init(int); + +extern asmlinkage void simIRQ(void); + +asmlinkage void sim_hw0_irqdispatch(struct pt_regs *regs) +{ + do_IRQ(2, regs); +} + +void __init arch_init_irq(void) +{ + /* Now safe to set the exception vector. */ + set_except_vector(0, simIRQ); + + mips_cpu_irq_init(MIPSCPU_INT_BASE); +} diff --git a/arch/mips/mips-boards/sim/sim_irq.S b/arch/mips/mips-boards/sim/sim_irq.S new file mode 100644 index 000000000000..835f0387fcd4 --- /dev/null +++ b/arch/mips/mips-boards/sim/sim_irq.S @@ -0,0 +1,99 @@ +/* + * Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Interrupt exception dispatch code. + * + */ +#include <linux/config.h> + +#include <asm/asm.h> +#include <asm/mipsregs.h> +#include <asm/regdef.h> +#include <asm/stackframe.h> + +#include <asm/mips-boards/simint.h> + + + .text + .set noreorder + .set noat + .align 5 + NESTED(simIRQ, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + + mfc0 s0, CP0_CAUSE # get irq bits + mfc0 s1, CP0_STATUS # get irq mask + andi s0, ST0_IM # CAUSE.CE may be non-zero! + and s0, s1 + +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) + .set mips32 + clz a0, s0 + .set mips0 + negu a0 + addu a0, 31-CAUSEB_IP + bltz a0, spurious +#else + beqz s0, spurious + li a0, 7 + + and t0, s0, 0xf000 + sltiu t0, t0, 1 + sll t0, 2 + subu a0, t0 + sll s0, t0 + + and t0, s0, 0xc000 + sltiu t0, t0, 1 + sll t0, 1 + subu a0, t0 + sll s0, t0 + + and t0, s0, 0x8000 + sltiu t0, t0, 1 + # sll t0, 0 + subu a0, t0 + # sll s0, t0 +#endif + +#ifdef CASCADE_IRQ + li a1, CASCADE_IRQ + bne a0, a1, 1f + addu a0, MIPSCPU_INT_BASE + + jal CASCADE_DISPATCH + move a0, sp + + j ret_from_irq + nop +1: +#else + addu a0, MIPSCPU_INT_BASE +#endif + + jal do_IRQ + move a1, sp + + j ret_from_irq + nop + + +spurious: + j spurious_interrupt + nop + END(simIRQ) diff --git a/arch/mips/mips-boards/sim/sim_mem.c b/arch/mips/mips-boards/sim/sim_mem.c new file mode 100644 index 000000000000..0dbd7435bb2a --- /dev/null +++ b/arch/mips/mips-boards/sim/sim_mem.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/bootmem.h> + +#include <asm/bootinfo.h> +#include <asm/page.h> + +#include <asm/mips-boards/prom.h> + +/*#define DEBUG*/ + +enum simmem_memtypes { + simmem_reserved = 0, + simmem_free, +}; +struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; + +#ifdef DEBUG +static char *mtypes[3] = { + "SIM reserved memory", + "SIM free memory", +}; +#endif + +/* References to section boundaries */ +extern char _end; + +#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK) + + +struct prom_pmemblock * __init prom_getmdesc(void) +{ + unsigned int memsize; + + memsize = 0x02000000; + prom_printf("Setting default memory size 0x%08x\n", memsize); + + memset(mdesc, 0, sizeof(mdesc)); + + mdesc[0].type = simmem_reserved; + mdesc[0].base = 0x00000000; + mdesc[0].size = 0x00001000; + + mdesc[1].type = simmem_free; + mdesc[1].base = 0x00001000; + mdesc[1].size = 0x000ff000; + + mdesc[2].type = simmem_reserved; + mdesc[2].base = 0x00100000; + mdesc[2].size = CPHYSADDR(PFN_ALIGN(&_end)) - mdesc[2].base; + + mdesc[3].type = simmem_free; + mdesc[3].base = CPHYSADDR(PFN_ALIGN(&_end)); + mdesc[3].size = memsize - mdesc[3].base; + + return &mdesc[0]; +} + +static int __init prom_memtype_classify (unsigned int type) +{ + switch (type) { + case simmem_free: + return BOOT_MEM_RAM; + case simmem_reserved: + default: + return BOOT_MEM_RESERVED; + } +} + +void __init prom_meminit(void) +{ + struct prom_pmemblock *p; + + p = prom_getmdesc(); + + while (p->size) { + long type; + unsigned long base, size; + + type = prom_memtype_classify (p->type); + base = p->base; + size = p->size; + + add_memory_region(base, size, type); + p++; + } +} + +unsigned long __init prom_free_prom_memory(void) +{ + int i; + unsigned long freed = 0; + unsigned long addr; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) + continue; + + addr = boot_mem_map.map[i].addr; + while (addr < boot_mem_map.map[i].addr + + boot_mem_map.map[i].size) { + ClearPageReserved(virt_to_page(__va(addr))); + set_page_count(virt_to_page(__va(addr)), 1); + free_page((unsigned long)__va(addr)); + addr += PAGE_SIZE; + freed += PAGE_SIZE; + } + } + printk("Freeing prom memory: %ldkb freed\n", freed >> 10); + + return freed; +} diff --git a/arch/mips/mips-boards/sim/sim_printf.c b/arch/mips/mips-boards/sim/sim_printf.c new file mode 100644 index 000000000000..3ee5a0b501a6 --- /dev/null +++ b/arch/mips/mips-boards/sim/sim_printf.c @@ -0,0 +1,74 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Putting things on the screen/serial line using YAMONs facilities. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/serial_reg.h> +#include <linux/spinlock.h> +#include <asm/io.h> +#include <asm/system.h> + +static inline unsigned int serial_in(int offset) +{ + return inb(0x3f8 + offset); +} + +static inline void serial_out(int offset, int value) +{ + outb(value, 0x3f8 + offset); +} + +int putPromChar(char c) +{ + while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) + ; + + serial_out(UART_TX, c); + + return 1; +} + +char getPromChar(void) +{ + while (!(serial_in(UART_LSR) & 1)) + ; + + return serial_in(UART_RX); +} + +void prom_printf(char *fmt, ...) +{ + va_list args; + int l; + char *p, *buf_end; + char buf[1024]; + + va_start(args, fmt); + l = vsprintf(buf, fmt, args); /* hopefully i < sizeof(buf) */ + va_end(args); + + buf_end = buf + l; + + for (p = buf; p < buf_end; p++) { + /* Crude cr/nl handling is better than none */ + if (*p == '\n') + putPromChar('\r'); + putPromChar(*p); + } +} diff --git a/arch/mips/mips-boards/sim/sim_setup.c b/arch/mips/mips-boards/sim/sim_setup.c new file mode 100644 index 000000000000..485d5a58d9cf --- /dev/null +++ b/arch/mips/mips-boards/sim/sim_setup.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#include <linux/config.h> +#include <linux/init.h> +#include <linux/string.h> +#include <linux/kernel.h> +#include <linux/ioport.h> +#include <linux/tty.h> +#include <linux/serial.h> +#include <linux/serial_core.h> + +#include <asm/cpu.h> +#include <asm/bootinfo.h> +#include <asm/irq.h> +#include <asm/mips-boards/generic.h> +#include <asm/mips-boards/prom.h> +#include <asm/serial.h> +#include <asm/io.h> +#include <asm/time.h> +#include <asm/mips-boards/sim.h> +#include <asm/mips-boards/simint.h> + + +extern void sim_time_init(void); +extern void sim_timer_setup(struct irqaction *irq); +static void __init serial_init(void); +unsigned int _isbonito = 0; + +extern void __init sanitize_tlb_entries(void); + + +const char *get_system_type(void) +{ + return "MIPSsim"; +} + +void __init plat_setup(void) +{ + set_io_port_base(0xbfd00000); + + serial_init(); + + board_time_init = sim_time_init; + board_timer_setup = sim_timer_setup; + prom_printf("Linux started...\n"); + +#ifdef CONFIG_MT_SMP + sanitize_tlb_entries(); +#endif +} + +void prom_init(void) +{ + set_io_port_base(0xbfd00000); + + prom_printf("\nLINUX started...\n"); + prom_init_cmdline(); + prom_meminit(); +} + + +static void __init serial_init(void) +{ +#ifdef CONFIG_SERIAL_8250 + struct uart_port s; + + memset(&s, 0, sizeof(s)); + + s.iobase = 0x3f8; + + /* hardware int 4 - the serial int, is CPU int 6 + but poll for now */ + s.irq = 0; + s.uartclk = BASE_BAUD * 16; + s.flags = ASYNC_BOOT_AUTOCONF | UPF_SKIP_TEST; + s.iotype = SERIAL_IO_PORT | ASYNC_SKIP_TEST; + s.regshift = 0; + s.timeout = 4; + + if (early_serial_setup(&s) != 0) { + prom_printf(KERN_ERR "Serial setup failed!\n"); + } + +#endif +} diff --git a/arch/mips/mips-boards/sim/sim_smp.c b/arch/mips/mips-boards/sim/sim_smp.c new file mode 100644 index 000000000000..19824359f5de --- /dev/null +++ b/arch/mips/mips-boards/sim/sim_smp.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +/* + * Simulator Platform-specific hooks for SMP operation + */ +#include <linux/config.h> +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/cpumask.h> +#include <linux/interrupt.h> +#include <asm/atomic.h> +#include <asm/cpu.h> +#include <asm/processor.h> +#include <asm/system.h> +#include <asm/hardirq.h> +#include <asm/mmu_context.h> +#include <asm/smp.h> +#ifdef CONFIG_MIPS_MT_SMTC +#include <asm/smtc_ipi.h> +#endif /* CONFIG_MIPS_MT_SMTC */ + +/* VPE/SMP Prototype implements platform interfaces directly */ +#if !defined(CONFIG_MIPS_MT_SMP) + +/* + * Cause the specified action to be performed on a targeted "CPU" + */ + +void core_send_ipi(int cpu, unsigned int action) +{ +#ifdef CONFIG_MIPS_MT_SMTC + void smtc_send_ipi(int, int, unsigned int); + + smtc_send_ipi(cpu, LINUX_SMP_IPI, action); +#endif /* CONFIG_MIPS_MT_SMTC */ +/* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ + +} + +/* + * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map + */ + +void __init prom_build_cpu_map(void) +{ +#ifdef CONFIG_MIPS_MT_SMTC + extern int mipsmt_build_cpu_map(int startslot); + int nextslot; + + cpus_clear(phys_cpu_present_map); + + /* Register the boot CPU */ + + smp_prepare_boot_cpu(); + + /* + * As of November, 2004, MIPSsim only simulates one core + * at a time. However, that core may be a MIPS MT core + * with multiple virtual processors and thread contexts. + */ + + if (read_c0_config3() & (1<<2)) { + nextslot = mipsmt_build_cpu_map(1); + } +#endif /* CONFIG_MIPS_MT_SMTC */ +} + +/* + * Platform "CPU" startup hook + */ + +void prom_boot_secondary(int cpu, struct task_struct *idle) +{ +#ifdef CONFIG_MIPS_MT_SMTC + extern void smtc_boot_secondary(int cpu, struct task_struct *t); + + smtc_boot_secondary(cpu, idle); +#endif /* CONFIG_MIPS_MT_SMTC */ +} + +/* + * Post-config but pre-boot cleanup entry point + */ + +void prom_init_secondary(void) +{ +#ifdef CONFIG_MIPS_MT_SMTC + void smtc_init_secondary(void); + + smtc_init_secondary(); +#endif /* CONFIG_MIPS_MT_SMTC */ +} + +/* + * Platform SMP pre-initialization + */ + +void prom_prepare_cpus(unsigned int max_cpus) +{ +#ifdef CONFIG_MIPS_MT_SMTC + void mipsmt_prepare_cpus(int c); + /* + * As noted above, we can assume a single CPU for now + * but it may be multithreaded. + */ + + if (read_c0_config3() & (1<<2)) { + mipsmt_prepare_cpus(max_cpus); + } +#endif /* CONFIG_MIPS_MT_SMTC */ +} + +/* + * SMP initialization finalization entry point + */ + +void prom_smp_finish(void) +{ +#ifdef CONFIG_MIPS_MT_SMTC + void smtc_smp_finish(void); + + smtc_smp_finish(); +#endif /* CONFIG_MIPS_MT_SMTC */ +} + +/* + * Hook for after all CPUs are online + */ + +void prom_cpus_done(void) +{ +#ifdef CONFIG_MIPS_MT_SMTC + +#endif /* CONFIG_MIPS_MT_SMTC */ +} +#endif /* CONFIG_MIPS32R2_MT_SMP */ diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mips-boards/sim/sim_time.c new file mode 100644 index 000000000000..18b968c696d1 --- /dev/null +++ b/arch/mips/mips-boards/sim/sim_time.c @@ -0,0 +1,215 @@ +#include <linux/types.h> +#include <linux/config.h> +#include <linux/init.h> +#include <linux/kernel_stat.h> +#include <linux/sched.h> +#include <linux/spinlock.h> + +#include <asm/mipsregs.h> +#include <asm/ptrace.h> +#include <asm/hardirq.h> +#include <asm/div64.h> +#include <asm/cpu.h> +#include <asm/time.h> + +#include <linux/interrupt.h> +#include <linux/mc146818rtc.h> +#include <linux/timex.h> +#include <asm/mipsregs.h> +#include <asm/ptrace.h> +#include <asm/hardirq.h> +#include <asm/irq.h> +#include <asm/div64.h> +#include <asm/cpu.h> +#include <asm/time.h> +#include <asm/mc146818-time.h> +#include <asm/msc01_ic.h> + +#include <asm/mips-boards/generic.h> +#include <asm/mips-boards/prom.h> +#include <asm/mips-boards/simint.h> +#include <asm/mc146818-time.h> +#include <asm/smp.h> + + +unsigned long cpu_khz; + +extern asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs); + +irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ +#ifdef CONFIG_SMP + int cpu = smp_processor_id(); + + /* + * CPU 0 handles the global timer interrupt job + * resets count/compare registers to trigger next timer int. + */ +#ifndef CONFIG_MIPS_MT_SMTC + if (cpu == 0) { + timer_interrupt(irq, dev_id, regs); + } + else { + /* Everyone else needs to reset the timer int here as + ll_local_timer_interrupt doesn't */ + /* + * FIXME: need to cope with counter underflow. + * More support needs to be added to kernel/time for + * counter/timer interrupts on multiple CPU's + */ + write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ)); + } +#else /* SMTC */ + /* + * In SMTC system, one Count/Compare set exists per VPE. + * Which TC within a VPE gets the interrupt is essentially + * random - we only know that it shouldn't be one with + * IXMT set. Whichever TC gets the interrupt needs to + * send special interprocessor interrupts to the other + * TCs to make sure that they schedule, etc. + * + * That code is specific to the SMTC kernel, not to + * the simulation platform, so it's invoked from + * the general MIPS timer_interrupt routine. + * + * We have a problem in that the interrupt vector code + * had to turn off the timer IM bit to avoid redundant + * entries, but we may never get to mips_cpu_irq_end + * to turn it back on again if the scheduler gets + * involved. So we clear the pending timer here, + * and re-enable the mask... + */ + + int vpflags = dvpe(); + write_c0_compare (read_c0_count() - 1); + clear_c0_cause(0x100 << MIPSCPU_INT_CPUCTR); + set_c0_status(0x100 << MIPSCPU_INT_CPUCTR); + irq_enable_hazard(); + evpe(vpflags); + + if(cpu_data[cpu].vpe_id == 0) timer_interrupt(irq, dev_id, regs); + else write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ)); + smtc_timer_broadcast(cpu_data[cpu].vpe_id); + +#endif /* CONFIG_MIPS_MT_SMTC */ + + /* + * every CPU should do profiling and process accounting + */ + local_timer_interrupt (irq, dev_id, regs); + return IRQ_HANDLED; +#else + return timer_interrupt (irq, dev_id, regs); +#endif +} + + + +/* + * Estimate CPU frequency. Sets mips_counter_frequency as a side-effect + */ +static unsigned int __init estimate_cpu_frequency(void) +{ + unsigned int prid = read_c0_prid() & 0xffff00; + unsigned int count; + +#if 1 + /* + * hardwire the board frequency to 12MHz. + */ + + if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || + (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) + count = 12000000; + else + count = 6000000; +#else + unsigned int flags; + + local_irq_save(flags); + + /* Start counter exactly on falling edge of update flag */ + while (CMOS_READ(RTC_REG_A) & RTC_UIP); + while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); + + /* Start r4k counter. */ + write_c0_count(0); + + /* Read counter exactly on falling edge of update flag */ + while (CMOS_READ(RTC_REG_A) & RTC_UIP); + while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); + + count = read_c0_count(); + + /* restore interrupts */ + local_irq_restore(flags); +#endif + + mips_hpt_frequency = count; + + if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && + (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) + count *= 2; + + count += 5000; /* round */ + count -= count%10000; + + return count; +} + +void __init sim_time_init(void) +{ + unsigned int est_freq, flags; + + local_irq_save(flags); + + + /* Set Data mode - binary. */ + CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); + + + est_freq = estimate_cpu_frequency (); + + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, + (est_freq%1000000)*100/1000000); + + cpu_khz = est_freq / 1000; + + local_irq_restore(flags); +} + +static int mips_cpu_timer_irq; + +static void mips_timer_dispatch (struct pt_regs *regs) +{ + do_IRQ (mips_cpu_timer_irq, regs); +} + + +void __init sim_timer_setup(struct irqaction *irq) +{ + if (cpu_has_veic) { + set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); + mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; + } + else { + if (cpu_has_vint) + set_vi_handler(MIPSCPU_INT_CPUCTR, mips_timer_dispatch); + mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR; + } + + /* we are using the cpu counter for timer interrupts */ + irq->handler = sim_timer_interrupt; + setup_irq(mips_cpu_timer_irq, irq); + +#ifdef CONFIG_SMP + /* irq_desc(riptor) is a global resource, when the interrupt overlaps + on seperate cpu's the first one tries to handle the second interrupt. + The effect is that the int remains disabled on the second cpu. + Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ + irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; +#endif + + /* to generate the first timer interrupt */ + write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ)); +} diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index b56a0abdc3d4..b0178da019f0 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -22,7 +22,7 @@ obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r8k.o obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_SB1) += c-sb1.o cerr-sb1.o cex-sb1.o pg-sb1.o \ - tlb-sb1.o + tlb-r4k.o obj-$(CONFIG_CPU_TX39XX) += c-tx39.o pg-r4k.o tlb-r3k.o obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c index c659f99eb39a..27f4fa25e8c9 100644 --- a/arch/mips/mm/c-r3k.c +++ b/arch/mips/mm/c-r3k.c @@ -221,12 +221,14 @@ static inline unsigned long get_phys_page (unsigned long addr, struct mm_struct *mm) { pgd_t *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte; unsigned long physpage; pgd = pgd_offset(mm, addr); - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + pmd = pmd_offset(pud, addr); pte = pte_offset(pmd, addr); if ((physpage = pte_val(*pte)) & _PAGE_VALID) @@ -317,7 +319,7 @@ static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size) r3k_flush_dcache_range(start, start + size); } -void __init ld_mmu_r23000(void) +void __init r3k_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 5ea84bc98c6a..38223b44d962 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -16,6 +16,7 @@ #include <asm/bcache.h> #include <asm/bootinfo.h> +#include <asm/cache.h> #include <asm/cacheops.h> #include <asm/cpu.h> #include <asm/cpu-features.h> @@ -26,8 +27,14 @@ #include <asm/system.h> #include <asm/mmu_context.h> #include <asm/war.h> +#include <asm/cacheflush.h> /* for run_uncached() */ -static unsigned long icache_size, dcache_size, scache_size; +/* + * Must die. + */ +static unsigned long icache_size __read_mostly; +static unsigned long dcache_size __read_mostly; +static unsigned long scache_size __read_mostly; /* * Dummy cache handling routines for machines without boardcaches @@ -43,8 +50,8 @@ static struct bcache_ops no_sc_ops = { struct bcache_ops *bcops = &no_sc_ops; -#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010) -#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x2020) +#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) +#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) #define R4600_HIT_CACHEOP_WAR_IMPL \ do { \ @@ -190,12 +197,12 @@ static inline void r4k_blast_icache_page_indexed_setup(void) if (ic_lsize == 16) r4k_blast_icache_page_indexed = blast_icache16_page_indexed; else if (ic_lsize == 32) { - if (TX49XX_ICACHE_INDEX_INV_WAR) - r4k_blast_icache_page_indexed = - tx49_blast_icache32_page_indexed; - else if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) + if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) r4k_blast_icache_page_indexed = blast_icache32_r4600_v1_page_indexed; + else if (TX49XX_ICACHE_INDEX_INV_WAR) + r4k_blast_icache_page_indexed = + tx49_blast_icache32_page_indexed; else r4k_blast_icache_page_indexed = blast_icache32_page_indexed; @@ -361,24 +368,33 @@ static void r4k_flush_cache_mm(struct mm_struct *mm) struct flush_cache_page_args { struct vm_area_struct *vma; - unsigned long page; + unsigned long addr; }; static inline void local_r4k_flush_cache_page(void *args) { struct flush_cache_page_args *fcp_args = args; struct vm_area_struct *vma = fcp_args->vma; - unsigned long page = fcp_args->page; + unsigned long addr = fcp_args->addr; int exec = vma->vm_flags & VM_EXEC; struct mm_struct *mm = vma->vm_mm; pgd_t *pgdp; + pud_t *pudp; pmd_t *pmdp; pte_t *ptep; - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); + /* + * If ownes no valid ASID yet, cannot possibly have gotten + * this page into the cache. + */ + if (cpu_context(smp_processor_id(), mm) == 0) + return; + + addr &= PAGE_MASK; + pgdp = pgd_offset(mm, addr); + pudp = pud_offset(pgdp, addr); + pmdp = pmd_offset(pudp, addr); + ptep = pte_offset(pmdp, addr); /* * If the page isn't marked valid, the page cannot possibly be @@ -395,12 +411,12 @@ static inline void local_r4k_flush_cache_page(void *args) */ if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) { if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { - r4k_blast_dcache_page(page); + r4k_blast_dcache_page(addr); if (exec && !cpu_icache_snoops_remote_store) - r4k_blast_scache_page(page); + r4k_blast_scache_page(addr); } if (exec) - r4k_blast_icache_page(page); + r4k_blast_icache_page(addr); return; } @@ -409,36 +425,30 @@ static inline void local_r4k_flush_cache_page(void *args) * Do indexed flush, too much work to get the (possible) TLB refills * to work correctly. */ - page = INDEX_BASE + (page & (dcache_size - 1)); + addr = INDEX_BASE + (addr & (dcache_size - 1)); if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { - r4k_blast_dcache_page_indexed(page); + r4k_blast_dcache_page_indexed(addr); if (exec && !cpu_icache_snoops_remote_store) - r4k_blast_scache_page_indexed(page); + r4k_blast_scache_page_indexed(addr); } if (exec) { if (cpu_has_vtag_icache) { int cpu = smp_processor_id(); - if (cpu_context(cpu, vma->vm_mm) != 0) - drop_mmu_context(vma->vm_mm, cpu); + if (cpu_context(cpu, mm) != 0) + drop_mmu_context(mm, cpu); } else - r4k_blast_icache_page_indexed(page); + r4k_blast_icache_page_indexed(addr); } } -static void r4k_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn) +static void r4k_flush_cache_page(struct vm_area_struct *vma, + unsigned long addr, unsigned long pfn) { struct flush_cache_page_args args; - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (cpu_context(smp_processor_id(), vma->vm_mm) == 0) - return; - args.vma = vma; - args.page = page; + args.addr = addr; on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1); } @@ -454,16 +464,16 @@ static void r4k_flush_data_cache_page(unsigned long addr) } struct flush_icache_range_args { - unsigned long start; - unsigned long end; + unsigned long __user start; + unsigned long __user end; }; static inline void local_r4k_flush_icache_range(void *args) { struct flush_icache_range_args *fir_args = args; - unsigned long dc_lsize = current_cpu_data.dcache.linesz; - unsigned long ic_lsize = current_cpu_data.icache.linesz; - unsigned long sc_lsize = current_cpu_data.scache.linesz; + unsigned long dc_lsize = cpu_dcache_line_size(); + unsigned long ic_lsize = cpu_icache_line_size(); + unsigned long sc_lsize = cpu_scache_line_size(); unsigned long start = fir_args->start; unsigned long end = fir_args->end; unsigned long addr, aend; @@ -472,6 +482,7 @@ static inline void local_r4k_flush_icache_range(void *args) if (end - start > dcache_size) { r4k_blast_dcache(); } else { + R4600_HIT_CACHEOP_WAR_IMPL; addr = start & ~(dc_lsize - 1); aend = (end - 1) & ~(dc_lsize - 1); @@ -492,7 +503,7 @@ static inline void local_r4k_flush_icache_range(void *args) aend = (end - 1) & ~(sc_lsize - 1); while (1) { - /* Hit_Writeback_Inv_D */ + /* Hit_Writeback_Inv_SD */ protected_writeback_scache_line(addr); if (addr == aend) break; @@ -517,7 +528,8 @@ static inline void local_r4k_flush_icache_range(void *args) } } -static void r4k_flush_icache_range(unsigned long start, unsigned long end) +static void r4k_flush_icache_range(unsigned long __user start, + unsigned long __user end) { struct flush_icache_range_args args; @@ -525,6 +537,7 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end) args.end = end; on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1); + instruction_hazard(); } /* @@ -613,7 +626,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) BUG_ON(size == 0); if (cpu_has_subset_pcaches) { - unsigned long sc_lsize = current_cpu_data.scache.linesz; + unsigned long sc_lsize = cpu_scache_line_size(); if (size >= scache_size) { r4k_blast_scache(); @@ -639,7 +652,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) if (size >= dcache_size) { r4k_blast_dcache(); } else { - unsigned long dc_lsize = current_cpu_data.dcache.linesz; + unsigned long dc_lsize = cpu_dcache_line_size(); R4600_HIT_CACHEOP_WAR_IMPL; a = addr & ~(dc_lsize - 1); @@ -663,7 +676,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) BUG_ON(size == 0); if (cpu_has_subset_pcaches) { - unsigned long sc_lsize = current_cpu_data.scache.linesz; + unsigned long sc_lsize = cpu_scache_line_size(); if (size >= scache_size) { r4k_blast_scache(); @@ -684,7 +697,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) if (size >= dcache_size) { r4k_blast_dcache(); } else { - unsigned long dc_lsize = current_cpu_data.dcache.linesz; + unsigned long dc_lsize = cpu_dcache_line_size(); R4600_HIT_CACHEOP_WAR_IMPL; a = addr & ~(dc_lsize - 1); @@ -708,9 +721,9 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) */ static void local_r4k_flush_cache_sigtramp(void * arg) { - unsigned long ic_lsize = current_cpu_data.icache.linesz; - unsigned long dc_lsize = current_cpu_data.dcache.linesz; - unsigned long sc_lsize = current_cpu_data.scache.linesz; + unsigned long ic_lsize = cpu_icache_line_size(); + unsigned long dc_lsize = cpu_dcache_line_size(); + unsigned long sc_lsize = cpu_scache_line_size(); unsigned long addr = (unsigned long) arg; R4600_HIT_CACHEOP_WAR_IMPL; @@ -762,6 +775,7 @@ static inline void rm7k_erratum31(void) for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { __asm__ __volatile__ ( + ".set push\n\t" ".set noreorder\n\t" ".set mips3\n\t" "cache\t%1, 0(%0)\n\t" @@ -776,8 +790,7 @@ static inline void rm7k_erratum31(void) "cache\t%1, 0x1000(%0)\n\t" "cache\t%1, 0x2000(%0)\n\t" "cache\t%1, 0x3000(%0)\n\t" - ".set\tmips0\n\t" - ".set\treorder\n\t" + ".set pop\n" : : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); } @@ -1011,9 +1024,19 @@ static void __init probe_pcache(void) * normally they'd suffer from aliases but magic in the hardware deals * with that for us so we don't need to take care ourselves. */ - if (c->cputype != CPU_R10000 && c->cputype != CPU_R12000) - if (c->dcache.waysize > PAGE_SIZE) - c->dcache.flags |= MIPS_CACHE_ALIASES; + switch (c->cputype) { + case CPU_20KC: + case CPU_25KF: + case CPU_R10000: + case CPU_R12000: + case CPU_SB1: + break; + case CPU_24K: + if (!(read_c0_config7() & (1 << 16))) + default: + if (c->dcache.waysize > PAGE_SIZE) + c->dcache.flags |= MIPS_CACHE_ALIASES; + } switch (c->cputype) { case CPU_20KC: @@ -1024,7 +1047,11 @@ static void __init probe_pcache(void) c->icache.flags |= MIPS_CACHE_VTAG; break; + case CPU_AU1000: case CPU_AU1500: + case CPU_AU1100: + case CPU_AU1550: + case CPU_AU1200: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; } @@ -1102,7 +1129,6 @@ static int __init probe_scache(void) return 1; } -typedef int (*probe_func_t)(unsigned long); extern int r5k_sc_init(void); extern int rm7k_sc_init(void); @@ -1110,7 +1136,6 @@ static void __init setup_scache(void) { struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int config = read_c0_config(); - probe_func_t probe_scache_kseg1; int sc_present = 0; /* @@ -1123,8 +1148,7 @@ static void __init setup_scache(void) case CPU_R4000MC: case CPU_R4400SC: case CPU_R4400MC: - probe_scache_kseg1 = (probe_func_t) (CKSEG1ADDR(&probe_scache)); - sc_present = probe_scache_kseg1(config); + sc_present = run_uncached(probe_scache); if (sc_present) c->options |= MIPS_CPU_CACHE_CDEX_S; break; @@ -1198,7 +1222,7 @@ static inline void coherency_setup(void) } } -void __init ld_mmu_r4xx0(void) +void __init r4k_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); @@ -1206,15 +1230,11 @@ void __init ld_mmu_r4xx0(void) struct cpuinfo_mips *c = ¤t_cpu_data; /* Default cache error handler for R4000 and R5000 family */ - memcpy((void *)(CAC_BASE + 0x100), &except_vec2_generic, 0x80); - memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80); + set_uncached_handler (0x100, &except_vec2_generic, 0x80); probe_pcache(); setup_scache(); - if (c->dcache.sets * c->dcache.ways > PAGE_SIZE) - c->dcache.flags |= MIPS_CACHE_ALIASES; - r4k_blast_dcache_page_setup(); r4k_blast_dcache_page_indexed_setup(); r4k_blast_dcache_setup(); @@ -1252,9 +1272,8 @@ void __init ld_mmu_r4xx0(void) _dma_cache_inv = r4k_dma_cache_inv; #endif - __flush_cache_all(); - coherency_setup(); - build_clear_page(); build_copy_page(); + local_r4k___flush_cache_all(NULL); + coherency_setup(); } diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c index 502f68c664b2..2f08b535f20e 100644 --- a/arch/mips/mm/c-sb1.c +++ b/arch/mips/mm/c-sb1.c @@ -235,7 +235,7 @@ static inline void __sb1_flush_icache_range(unsigned long start, /* * Invalidate all caches on this CPU */ -static void local_sb1___flush_cache_all(void) +static void __attribute_used__ local_sb1___flush_cache_all(void) { __sb1_writeback_inv_dcache_all(); __sb1_flush_icache_all(); @@ -492,19 +492,17 @@ static __init void probe_cache_sizes(void) } /* - * This is called from loadmmu.c. We have to set up all the + * This is called from cache.c. We have to set up all the * memory management function pointers, as well as initialize * the caches and tlbs */ -void ld_mmu_sb1(void) +void sb1_cache_init(void) { extern char except_vec2_sb1; extern char handle_vec2_sb1; /* Special cache error handler for SB1 */ - memcpy((void *)(CAC_BASE + 0x100), &except_vec2_sb1, 0x80); - memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_sb1, 0x80); - memcpy((void *)CKSEG1ADDR(&handle_vec2_sb1), &handle_vec2_sb1, 0x80); + set_uncached_handler (0x100, &except_vec2_sb1, 0x80); probe_cache_sizes(); diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index ff5afab64b2f..0a97a9434eba 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -167,15 +167,16 @@ static void tx39_flush_cache_mm(struct mm_struct *mm) static void tx39_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - struct mm_struct *mm = vma->vm_mm; + int exec; - if (!cpu_has_dc_aliases) + if (!(cpu_context(smp_processor_id(), vma->vm_mm))) return; - if (cpu_context(smp_processor_id(), mm) != 0) { + exec = vma->vm_flags & VM_EXEC; + if (cpu_has_dc_aliases || exec) tx39_blast_dcache(); + if (exec) tx39_blast_icache(); - } } static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn) @@ -183,6 +184,7 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page int exec = vma->vm_flags & VM_EXEC; struct mm_struct *mm = vma->vm_mm; pgd_t *pgdp; + pud_t *pudp; pmd_t *pmdp; pte_t *ptep; @@ -195,7 +197,8 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page page &= PAGE_MASK; pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); + pudp = pud_offset(pgdp, page); + pmdp = pmd_offset(pudp, page); ptep = pte_offset(pmdp, page); /* @@ -407,7 +410,7 @@ static __init void tx39_probe_cache(void) } } -void __init ld_mmu_tx39(void) +void __init tx39_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); @@ -490,4 +493,5 @@ void __init ld_mmu_tx39(void) build_clear_page(); build_copy_page(); + tx39h_flush_icache_all(); } diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 1d95cdb77bed..314701a66b13 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -23,8 +23,10 @@ void (*__flush_cache_all)(void); void (*flush_cache_mm)(struct mm_struct *mm); void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, unsigned long end); -void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); -void (*flush_icache_range)(unsigned long start, unsigned long end); +void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, + unsigned long pfn); +void (*flush_icache_range)(unsigned long __user start, + unsigned long __user end); void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); /* MIPS specific cache operations */ @@ -32,6 +34,8 @@ void (*flush_cache_sigtramp)(unsigned long addr); void (*flush_data_cache_page)(unsigned long addr); void (*flush_icache_all)(void); +EXPORT_SYMBOL(flush_data_cache_page); + #ifdef CONFIG_DMA_NONCOHERENT /* DMA cache operations. */ @@ -49,10 +53,12 @@ EXPORT_SYMBOL(_dma_cache_inv); * We could optimize the case where the cache argument is not BCACHE but * that seems very atypical use ... */ -asmlinkage int sys_cacheflush(unsigned long addr, unsigned long int bytes, - unsigned int cache) +asmlinkage int sys_cacheflush(unsigned long __user addr, + unsigned long bytes, unsigned int cache) { - if (!access_ok(VERIFY_WRITE, (void *) addr, bytes)) + if (bytes == 0) + return 0; + if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes)) return -EFAULT; flush_icache_range(addr, addr + bytes); @@ -100,58 +106,48 @@ void __update_cache(struct vm_area_struct *vma, unsigned long address, } } -extern void ld_mmu_r23000(void); -extern void ld_mmu_r4xx0(void); -extern void ld_mmu_tx39(void); -extern void ld_mmu_r6000(void); -extern void ld_mmu_tfp(void); -extern void ld_mmu_andes(void); -extern void ld_mmu_sb1(void); +#define __weak __attribute__((weak)) + +static char cache_panic[] __initdata = "Yeee, unsupported cache architecture."; void __init cpu_cache_init(void) { - if (cpu_has_4ktlb) { -#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \ - defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \ - defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \ - defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32) || \ - defined(CONFIG_CPU_MIPS64) || defined(CONFIG_CPU_TX49XX) || \ - defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000) - ld_mmu_r4xx0(); -#endif - } else switch (current_cpu_data.cputype) { -#ifdef CONFIG_CPU_R3000 - case CPU_R2000: - case CPU_R3000: - case CPU_R3000A: - case CPU_R3081E: - ld_mmu_r23000(); - break; -#endif -#ifdef CONFIG_CPU_TX39XX - case CPU_TX3912: - case CPU_TX3922: - case CPU_TX3927: - ld_mmu_tx39(); - break; -#endif -#ifdef CONFIG_CPU_R10000 - case CPU_R10000: - case CPU_R12000: - ld_mmu_r4xx0(); - break; -#endif -#ifdef CONFIG_CPU_SB1 - case CPU_SB1: - ld_mmu_sb1(); - break; -#endif - - case CPU_R8000: - panic("R8000 is unsupported"); - break; - - default: - panic("Yeee, unsupported cache architecture."); + if (cpu_has_3k_cache) { + extern void __weak r3k_cache_init(void); + + r3k_cache_init(); + return; + } + if (cpu_has_6k_cache) { + extern void __weak r6k_cache_init(void); + + r6k_cache_init(); + return; + } + if (cpu_has_4k_cache) { + extern void __weak r4k_cache_init(void); + + r4k_cache_init(); + return; } + if (cpu_has_8k_cache) { + extern void __weak r8k_cache_init(void); + + r8k_cache_init(); + return; + } + if (cpu_has_tx39_cache) { + extern void __weak tx39_cache_init(void); + + tx39_cache_init(); + return; + } + if (cpu_has_sb1_cache) { + extern void __weak sb1_cache_init(void); + + sb1_cache_init(); + return; + } + + panic(cache_panic); } diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c index 7166ffe63502..1cf3c6006ccd 100644 --- a/arch/mips/mm/cerr-sb1.c +++ b/arch/mips/mm/cerr-sb1.c @@ -19,13 +19,19 @@ #include <linux/sched.h> #include <asm/mipsregs.h> #include <asm/sibyte/sb1250.h> +#include <asm/sibyte/sb1250_regs.h> -#ifndef CONFIG_SIBYTE_BUS_WATCHER +#if !defined(CONFIG_SIBYTE_BUS_WATCHER) || defined(CONFIG_SIBYTE_BW_TRACE) #include <asm/io.h> -#include <asm/sibyte/sb1250_regs.h> #include <asm/sibyte/sb1250_scd.h> #endif +/* + * We'd like to dump the L2_ECC_TAG register on errors, but errata make + * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.) + */ +#undef DUMP_L2_ECC_TAG_ON_ERROR + /* SB1 definitions */ /* XXX should come from config1 XXX */ @@ -139,12 +145,18 @@ static inline void breakout_cerrd(unsigned int val) static void check_bus_watcher(void) { uint32_t status, l2_err, memio_err; +#ifdef DUMP_L2_ECC_TAG_ON_ERROR + uint64_t l2_tag; +#endif /* Destructive read, clears register and interrupt */ status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); /* Bit 31 is always on, but there's no #define for that */ if (status & ~(1UL << 31)) { l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); +#ifdef DUMP_L2_ECC_TAG_ON_ERROR + l2_tag = in64(IO_SPACE_BASE | A_L2_ECC_TAG); +#endif memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); prom_printf("\nLast recorded signature:\n"); @@ -153,6 +165,9 @@ static void check_bus_watcher(void) (int)(G_SCD_BERR_TID(status) >> 6), (int)G_SCD_BERR_RID(status), (int)G_SCD_BERR_DCODE(status)); +#ifdef DUMP_L2_ECC_TAG_ON_ERROR + prom_printf("Last L2 tag w/ bad ECC: %016llx\n", l2_tag); +#endif } else { prom_printf("Bus watcher indicates no error\n"); } @@ -166,6 +181,16 @@ asmlinkage void sb1_cache_error(void) uint64_t cerr_dpa; uint32_t errctl, cerr_i, cerr_d, dpalo, dpahi, eepc, res; +#ifdef CONFIG_SIBYTE_BW_TRACE + /* Freeze the trace buffer now */ +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) + csr_out32(M_BCM1480_SCD_TRACE_CFG_FREEZE, IO_SPACE_BASE | A_SCD_TRACE_CFG); +#else + csr_out32(M_SCD_TRACE_CFG_FREEZE, IO_SPACE_BASE | A_SCD_TRACE_CFG); +#endif + prom_printf("Trace buffer frozen\n"); +#endif + prom_printf("Cache error exception on CPU %x:\n", (read_c0_prid() >> 25) & 0x7); @@ -229,11 +254,19 @@ asmlinkage void sb1_cache_error(void) check_bus_watcher(); - while (1); /* - * This tends to make things get really ugly; let's just stall instead. - * panic("Can't handle the cache error!"); + * Calling panic() when a fatal cache error occurs scrambles the + * state of the system (and the cache), making it difficult to + * investigate after the fact. However, if you just stall the CPU, + * the other CPU may keep on running, which is typically very + * undesirable. */ +#ifdef CONFIG_SB1_CERR_STALL + while (1) + ; +#else + panic("unhandled cache error"); +#endif } @@ -434,7 +467,8 @@ static struct dc_state dc_states[] = { }; #define DC_TAG_VALID(state) \ - (((state) == 0xf) || ((state) == 0x13) || ((state) == 0x19) || ((state == 0x16)) || ((state) == 0x1c)) + (((state) == 0x0) || ((state) == 0xf) || ((state) == 0x13) || \ + ((state) == 0x19) || ((state) == 0x16) || ((state) == 0x1c)) static char *dc_state_str(unsigned char state) { @@ -505,6 +539,7 @@ static uint32_t extract_dc(unsigned short addr, int data) uint64_t datalo; uint32_t datalohi, datalolo, datahi; int offset; + char bad_ecc = 0; for (offset = 0; offset < 4; offset++) { /* Index-load-data-D */ @@ -525,8 +560,7 @@ static uint32_t extract_dc(unsigned short addr, int data) ecc = dc_ecc(datalo); if (ecc != datahi) { int bits = 0; - prom_printf(" ** bad ECC (%02x %02x) ->", - datahi, ecc); + bad_ecc |= 1 << (3-offset); ecc ^= datahi; while (ecc) { if (ecc & 1) bits++; @@ -537,6 +571,10 @@ static uint32_t extract_dc(unsigned short addr, int data) prom_printf(" %02X-%016llX", datahi, datalo); } prom_printf("\n"); + if (bad_ecc) + prom_printf(" dwords w/ bad ECC: %d %d %d %d\n", + !!(bad_ecc & 8), !!(bad_ecc & 4), + !!(bad_ecc & 2), !!(bad_ecc & 1)); } } return res; diff --git a/arch/mips/mm/cex-sb1.S b/arch/mips/mm/cex-sb1.S index 2c3a23aa88c3..0e71580774ff 100644 --- a/arch/mips/mm/cex-sb1.S +++ b/arch/mips/mm/cex-sb1.S @@ -64,6 +64,10 @@ LEAF(except_vec2_sb1) sd k0,0x170($0) sd k1,0x178($0) +#if CONFIG_SB1_CEX_ALWAYS_FATAL + j handle_vec2_sb1 + nop +#else /* * M_ERRCTL_RECOVERABLE is bit 31, which makes it easy to tell * if we can fast-path out of here for a h/w-recovered error. @@ -134,6 +138,7 @@ unrecoverable: /* Unrecoverable Icache or Dcache error; log it and/or fail */ j handle_vec2_sb1 nop +#endif END(except_vec2_sb1) diff --git a/arch/mips/mm/dma-coherent.c b/arch/mips/mm/dma-coherent.c index a617f8c327e8..f6b3c722230c 100644 --- a/arch/mips/mm/dma-coherent.c +++ b/arch/mips/mm/dma-coherent.c @@ -9,10 +9,10 @@ */ #include <linux/config.h> #include <linux/types.h> +#include <linux/dma-mapping.h> #include <linux/mm.h> #include <linux/module.h> #include <linux/string.h> -#include <linux/pci.h> #include <asm/cache.h> #include <asm/io.h> diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c index 4ce02028a292..cd4ea8474f89 100644 --- a/arch/mips/mm/dma-noncoherent.c +++ b/arch/mips/mm/dma-noncoherent.c @@ -105,22 +105,7 @@ dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, { unsigned long addr = (unsigned long) ptr; - switch (direction) { - case DMA_TO_DEVICE: - dma_cache_wback(addr, size); - break; - - case DMA_FROM_DEVICE: - dma_cache_inv(addr, size); - break; - - case DMA_BIDIRECTIONAL: - dma_cache_wback_inv(addr, size); - break; - - default: - BUG(); - } + __dma_sync(addr, size, direction); return virt_to_phys(ptr); } @@ -133,22 +118,7 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, unsigned long addr; addr = dma_addr + PAGE_OFFSET; - switch (direction) { - case DMA_TO_DEVICE: - //dma_cache_wback(addr, size); - break; - - case DMA_FROM_DEVICE: - //dma_cache_inv(addr, size); - break; - - case DMA_BIDIRECTIONAL: - //dma_cache_wback_inv(addr, size); - break; - - default: - BUG(); - } + //__dma_sync(addr, size, direction); } EXPORT_SYMBOL(dma_unmap_single); @@ -164,10 +134,11 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, unsigned long addr; addr = (unsigned long) page_address(sg->page); - if (addr) + if (addr) { __dma_sync(addr + sg->offset, sg->length, direction); - sg->dma_address = (dma_addr_t) - (page_to_phys(sg->page) + sg->offset); + sg->dma_address = (dma_addr_t)page_to_phys(sg->page) + + sg->offset; + } } return nents; @@ -218,9 +189,8 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, for (i = 0; i < nhwentries; i++, sg++) { addr = (unsigned long) page_address(sg->page); - if (!addr) - continue; - dma_cache_wback_inv(addr + sg->offset, sg->length); + if (addr) + __dma_sync(addr + sg->offset, sg->length, direction); } } diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index ec8077c74e9c..2d9624fd10ec 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -25,6 +25,7 @@ #include <asm/system.h> #include <asm/uaccess.h> #include <asm/ptrace.h> +#include <asm/highmem.h> /* For VMALLOC_END */ /* * This routine handles page faults. It determines the address, @@ -57,7 +58,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write, * only copy the information from the master page table, * nothing more. */ - if (unlikely(address >= VMALLOC_START)) + if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END)) goto vmalloc_fault; /* @@ -140,7 +141,7 @@ bad_area_nosemaphore: info.si_signo = SIGSEGV; info.si_errno = 0; /* info.si_code has been set above */ - info.si_addr = (void *) address; + info.si_addr = (void __user *) address; force_sig_info(SIGSEGV, &info, tsk); return; } @@ -196,7 +197,7 @@ do_sigbus: info.si_signo = SIGBUS; info.si_errno = 0; info.si_code = BUS_ADRERR; - info.si_addr = (void *) address; + info.si_addr = (void __user *) address; force_sig_info(SIGBUS, &info, tsk); return; @@ -212,6 +213,7 @@ vmalloc_fault: */ int offset = __pgd_offset(address); pgd_t *pgd, *pgd_k; + pud_t *pud, *pud_k; pmd_t *pmd, *pmd_k; pte_t *pte_k; @@ -222,8 +224,13 @@ vmalloc_fault: goto no_context; set_pgd(pgd, *pgd_k); - pmd = pmd_offset(pgd, address); - pmd_k = pmd_offset(pgd_k, address); + pud = pud_offset(pgd, address); + pud_k = pud_offset(pgd_k, address); + if (!pud_present(*pud_k)) + goto no_context; + + pmd = pmd_offset(pud, address); + pmd_k = pmd_offset(pud_k, address); if (!pmd_present(*pmd_k)) goto no_context; set_pmd(pmd, *pmd_k); diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c index dd5e2e31885b..1f7b37b38f5c 100644 --- a/arch/mips/mm/highmem.c +++ b/arch/mips/mm/highmem.c @@ -83,6 +83,25 @@ void __kunmap_atomic(void *kvaddr, enum km_type type) preempt_check_resched(); } +/* + * This is the same as kmap_atomic() but can map memory that doesn't + * have a struct page associated with it. + */ +void *kmap_atomic_pfn(unsigned long pfn, enum km_type type) +{ + enum fixed_addresses idx; + unsigned long vaddr; + + inc_preempt_count(); + + idx = type + KM_TYPE_NR*smp_processor_id(); + vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); + set_pte(kmap_pte-idx, pfn_pte(pfn, kmap_prot)); + flush_tlb_one(vaddr); + + return (void*) vaddr; +} + struct page *__kmap_atomic_to_page(void *ptr) { unsigned long idx, vaddr = (unsigned long)ptr; diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index dc6830b10fab..f75ab748e8cd 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -83,7 +83,7 @@ pte_t *kmap_pte; pgprot_t kmap_prot; #define kmap_get_fixmap_pte(vaddr) \ - pte_offset_kernel(pmd_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)) + pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) static void __init kmap_init(void) { @@ -96,36 +96,42 @@ static void __init kmap_init(void) kmap_prot = PAGE_KERNEL; } -#ifdef CONFIG_64BIT -static void __init fixrange_init(unsigned long start, unsigned long end, +#ifdef CONFIG_32BIT +void __init fixrange_init(unsigned long start, unsigned long end, pgd_t *pgd_base) { pgd_t *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte; - int i, j; + int i, j, k; unsigned long vaddr; vaddr = start; i = __pgd_offset(vaddr); - j = __pmd_offset(vaddr); + j = __pud_offset(vaddr); + k = __pmd_offset(vaddr); pgd = pgd_base + i; for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) { - pmd = (pmd_t *)pgd; - for (; (j < PTRS_PER_PMD) && (vaddr != end); pmd++, j++) { - if (pmd_none(*pmd)) { - pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); - set_pmd(pmd, __pmd(pte)); - if (pte != pte_offset_kernel(pmd, 0)) - BUG(); + pud = (pud_t *)pgd; + for ( ; (j < PTRS_PER_PUD) && (vaddr != end); pud++, j++) { + pmd = (pmd_t *)pud; + for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) { + if (pmd_none(*pmd)) { + pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); + set_pmd(pmd, __pmd(pte)); + if (pte != pte_offset_kernel(pmd, 0)) + BUG(); + } + vaddr += PMD_SIZE; } - vaddr += PMD_SIZE; + k = 0; } j = 0; } } -#endif /* CONFIG_64BIT */ +#endif /* CONFIG_32BIT */ #endif /* CONFIG_HIGHMEM */ #ifndef CONFIG_NEED_MULTIPLE_NODES diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c index adf352273f63..9c44ca70befa 100644 --- a/arch/mips/mm/ioremap.c +++ b/arch/mips/mm/ioremap.c @@ -79,9 +79,14 @@ static int remap_area_pages(unsigned long address, phys_t phys_addr, BUG(); spin_lock(&init_mm.page_table_lock); do { + pud_t *pud; pmd_t *pmd; - pmd = pmd_alloc(&init_mm, dir, address); + error = -ENOMEM; + pud = pud_alloc(&init_mm, dir, address); + if (!pud) + break; + pmd = pmd_alloc(&init_mm, pud, address); if (!pmd) break; if (remap_area_pmd(pmd, address, end - address, @@ -97,15 +102,6 @@ static int remap_area_pages(unsigned long address, phys_t phys_addr, } /* - * Allow physical addresses to be fixed up to help 36 bit peripherals. - */ -phys_t __attribute__ ((weak)) -fixup_bigphys_addr(phys_t phys_addr, phys_t size) -{ - return phys_addr; -} - -/* * Generic mapping function (not visible outside): */ @@ -121,7 +117,7 @@ fixup_bigphys_addr(phys_t phys_addr, phys_t size) #define IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL)) -void * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags) +void __iomem * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags) { struct vm_struct * area; unsigned long offset; @@ -141,7 +137,7 @@ void * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags) */ if (IS_LOW512(phys_addr) && IS_LOW512(last_addr) && flags == _CACHE_UNCACHED) - return (void *) KSEG1ADDR(phys_addr); + return (void __iomem *) CKSEG1ADDR(phys_addr); /* * Don't allow anybody to remap normal RAM that we're using.. @@ -177,10 +173,10 @@ void * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags) return NULL; } - return (void *) (offset + (char *)addr); + return (void __iomem *) (offset + (char *)addr); } -#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == KSEG1) +#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) void __iounmap(volatile void __iomem *addr) { @@ -190,10 +186,8 @@ void __iounmap(volatile void __iomem *addr) return; p = remove_vm_area((void *) (PAGE_MASK & (unsigned long __force) addr)); - if (!p) { + if (!p) printk(KERN_ERR "iounmap: bad address %p\n", addr); - return; - } kfree(p); } diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c index 9f8b16541577..f51e180072e3 100644 --- a/arch/mips/mm/pg-r4k.c +++ b/arch/mips/mm/pg-r4k.c @@ -25,7 +25,10 @@ #include <asm/cpu.h> #include <asm/war.h> -#define half_scache_line_size() (cpu_scache_line_size() >> 1) +#define half_scache_line_size() (cpu_scache_line_size() >> 1) +#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) +#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) + /* * Maximum sizes: @@ -198,15 +201,15 @@ static inline void build_cdex_p(void) if (store_offset & (cpu_dcache_line_size() - 1)) return; - if (R4600_V1_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2010)) { + if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) { build_nop(); build_nop(); build_nop(); build_nop(); } - if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020)) - build_insn_word(0x8c200000); /* lw $zero, ($at) */ + if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) + build_insn_word(0x3c01a000); /* lui $at, 0xa000 */ mi.c_format.opcode = cache_op; mi.c_format.rs = 4; /* $a0 */ @@ -361,7 +364,7 @@ void __init build_clear_page(void) build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_clear : 0)); - if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020)) + if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) build_insn_word(0x3c01a000); /* lui $at, 0xa000 */ dest = label(); @@ -404,9 +407,6 @@ dest = label(); build_jr_ra(); - flush_icache_range((unsigned long)&clear_page_array, - (unsigned long) epc); - BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array)); } @@ -420,7 +420,7 @@ void __init build_copy_page(void) build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_copy : 0)); - if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020)) + if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) build_insn_word(0x3c01a000); /* lui $at, 0xa000 */ dest = label(); @@ -482,8 +482,5 @@ dest = label(); build_jr_ra(); - flush_icache_range((unsigned long)©_page_array, - (unsigned long) epc); - BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array)); } diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c index 1b6df7133c1e..148c65b9cd8b 100644 --- a/arch/mips/mm/pg-sb1.c +++ b/arch/mips/mm/pg-sb1.c @@ -60,7 +60,8 @@ static inline void clear_page_cpu(void *page) " .set noreorder \n" #ifdef CONFIG_CPU_HAS_PREFETCH " daddiu %0, %0, 128 \n" - " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%0) \n" /* Prefetch the first 4 lines */ + " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%0) \n" + /* Prefetch the first 4 lines */ " pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%0) \n" " pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%0) \n" " pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%0) \n" @@ -106,7 +107,8 @@ static inline void copy_page_cpu(void *to, void *from) #ifdef CONFIG_CPU_HAS_PREFETCH " daddiu %0, %0, 128 \n" " daddiu %1, %1, 128 \n" - " pref " SB1_PREF_LOAD_STREAMED_HINT ", -128(%0)\n" /* Prefetch the first 4 lines */ + " pref " SB1_PREF_LOAD_STREAMED_HINT ", -128(%0)\n" + /* Prefetch the first 4 lines */ " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%1)\n" " pref " SB1_PREF_LOAD_STREAMED_HINT ", -96(%0)\n" " pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%1)\n" @@ -207,66 +209,73 @@ typedef struct dmadscr_s { u64 pad_b; } dmadscr_t; -static dmadscr_t page_descr[NR_CPUS] __attribute__((aligned(SMP_CACHE_BYTES))); +static dmadscr_t page_descr[DM_NUM_CHANNELS] + __attribute__((aligned(SMP_CACHE_BYTES))); void sb1_dma_init(void) { - int cpu = smp_processor_id(); - u64 base_val = CPHYSADDR(&page_descr[cpu]) | V_DM_DSCR_BASE_RINGSZ(1); + int i; - bus_writeq(base_val, - (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); - bus_writeq(base_val | M_DM_DSCR_BASE_RESET, - (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); - bus_writeq(base_val | M_DM_DSCR_BASE_ENABL, - (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); + for (i = 0; i < DM_NUM_CHANNELS; i++) { + const u64 base_val = CPHYSADDR(&page_descr[i]) | + V_DM_DSCR_BASE_RINGSZ(1); + volatile void *base_reg = + IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE)); + + __raw_writeq(base_val, base_reg); + __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg); + __raw_writeq(base_val | M_DM_DSCR_BASE_ENABL, base_reg); + } } void clear_page(void *page) { - int cpu = smp_processor_id(); + u64 to_phys = CPHYSADDR(page); + unsigned int cpu = smp_processor_id(); - /* if the page is above Kseg0, use old way */ + /* if the page is not in KSEG0, use old way */ if ((long)KSEGX(page) != (long)CKSEG0) return clear_page_cpu(page); - page_descr[cpu].dscr_a = CPHYSADDR(page) | M_DM_DSCRA_ZERO_MEM | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; + page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM | + M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); - bus_writeq(1, (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); + __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); /* * Don't really want to do it this way, but there's no * reliable way to delay completion detection. */ - while (!(bus_readq((void *)(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) & - M_DM_DSCR_BASE_INTERRUPT)))) + while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) + & M_DM_DSCR_BASE_INTERRUPT)) ; - bus_readq((void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); + __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); } void copy_page(void *to, void *from) { - unsigned long from_phys = CPHYSADDR(from); - unsigned long to_phys = CPHYSADDR(to); - int cpu = smp_processor_id(); + u64 from_phys = CPHYSADDR(from); + u64 to_phys = CPHYSADDR(to); + unsigned int cpu = smp_processor_id(); - /* if either page is above Kseg0, use old way */ + /* if any page is not in KSEG0, use old way */ if ((long)KSEGX(to) != (long)CKSEG0 || (long)KSEGX(from) != (long)CKSEG0) return copy_page_cpu(to, from); - page_descr[cpu].dscr_a = CPHYSADDR(to_phys) | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; - page_descr[cpu].dscr_b = CPHYSADDR(from_phys) | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); - bus_writeq(1, (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); + page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST | + M_DM_DSCRA_INTERRUPT; + page_descr[cpu].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); + __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); /* * Don't really want to do it this way, but there's no * reliable way to delay completion detection. */ - while (!(bus_readq((void *)(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) & - M_DM_DSCR_BASE_INTERRUPT)))) + while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) + & M_DM_DSCR_BASE_INTERRUPT)) ; - bus_readq((void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); + __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); } #else /* !CONFIG_SIBYTE_DMA_PAGEOPS */ diff --git a/arch/mips/mm/pgtable-32.c b/arch/mips/mm/pgtable-32.c index 4f07f81e8500..4a3c4919e314 100644 --- a/arch/mips/mm/pgtable-32.c +++ b/arch/mips/mm/pgtable-32.c @@ -10,6 +10,7 @@ #include <linux/mm.h> #include <linux/bootmem.h> #include <linux/highmem.h> +#include <asm/fixmap.h> #include <asm/pgtable.h> void pgd_init(unsigned long page) @@ -29,42 +30,12 @@ void pgd_init(unsigned long page) } } -#ifdef CONFIG_HIGHMEM -static void __init fixrange_init (unsigned long start, unsigned long end, - pgd_t *pgd_base) -{ - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - int i, j; - unsigned long vaddr; - - vaddr = start; - i = __pgd_offset(vaddr); - j = __pmd_offset(vaddr); - pgd = pgd_base + i; - - for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) { - pmd = (pmd_t *)pgd; - for (; (j < PTRS_PER_PMD) && (vaddr != end); pmd++, j++) { - if (pmd_none(*pmd)) { - pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); - set_pmd(pmd, __pmd((unsigned long)pte)); - if (pte != pte_offset_kernel(pmd, 0)) - BUG(); - } - vaddr += PMD_SIZE; - } - j = 0; - } -} -#endif - void __init pagetable_init(void) { #ifdef CONFIG_HIGHMEM unsigned long vaddr; pgd_t *pgd, *pgd_base; + pud_t *pud; pmd_t *pmd; pte_t *pte; #endif @@ -90,7 +61,8 @@ void __init pagetable_init(void) fixrange_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base); pgd = swapper_pg_dir + __pgd_offset(vaddr); - pmd = pmd_offset(pgd, vaddr); + pud = pud_offset(pgd, vaddr); + pmd = pmd_offset(pud, vaddr); pte = pte_offset_kernel(pmd, vaddr); pkmap_page_table = pte; #endif diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c index 4e92f931aaba..9e8ff8badb19 100644 --- a/arch/mips/mm/sc-rm7k.c +++ b/arch/mips/mm/sc-rm7k.c @@ -15,6 +15,7 @@ #include <asm/cacheops.h> #include <asm/mipsregs.h> #include <asm/processor.h> +#include <asm/cacheflush.h> /* for run_uncached() */ /* Primary cache parameters. */ #define sc_lsize 32 @@ -96,25 +97,13 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size) } /* - * This function is executed in the uncached segment CKSEG1. - * It must not touch the stack, because the stack pointer still points - * into CKSEG0. - * - * Three options: - * - Write it in assembly and guarantee that we don't use the stack. - * - Disable caching for CKSEG0 before calling it. - * - Pray that GCC doesn't randomly start using the stack. - * - * This being Linux, we obviously take the least sane of those options - - * following DaveM's lead in c-r4k.c - * - * It seems we get our kicks from relying on unguaranteed behaviour in GCC + * This function is executed in uncached address space. */ static __init void __rm7k_sc_enable(void) { int i; - set_c0_config(1 << 3); /* CONF_SE */ + set_c0_config(RM7K_CONF_SE); write_c0_taglo(0); write_c0_taghi(0); @@ -127,24 +116,22 @@ static __init void __rm7k_sc_enable(void) ".set mips0\n\t" ".set reorder" : - : "r" (KSEG0ADDR(i)), "i" (Index_Store_Tag_SD)); + : "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD)); } } static __init void rm7k_sc_enable(void) { - void (*func)(void) = (void *) KSEG1ADDR(&__rm7k_sc_enable); - - if (read_c0_config() & 0x08) /* CONF_SE */ + if (read_c0_config() & RM7K_CONF_SE) return; - printk(KERN_INFO "Enabling secondary cache..."); - func(); + printk(KERN_INFO "Enabling secondary cache...\n"); + run_uncached(__rm7k_sc_enable); } static void rm7k_sc_disable(void) { - clear_c0_config(1<<3); /* CONF_SE */ + clear_c0_config(RM7K_CONF_SE); } struct bcache_ops rm7k_sc_ops = { @@ -158,19 +145,19 @@ void __init rm7k_sc_init(void) { unsigned int config = read_c0_config(); - if ((config >> 31) & 1) /* Bit 31 set -> no S-Cache */ + if ((config & RM7K_CONF_SC)) return; printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n", (scache_size >> 10), sc_lsize); - if (!((config >> 3) & 1)) /* CONF_SE */ + if (!(config & RM7K_CONF_SE)) rm7k_sc_enable(); /* * While we're at it let's deal with the tertiary cache. */ - if (!((config >> 17) & 1)) { + if (!(config & RM7K_CONF_TC)) { /* * We can't enable the L3 cache yet. There may be board-specific @@ -183,9 +170,9 @@ void __init rm7k_sc_init(void) * to probe it. */ printk(KERN_INFO "Tertiary cache present, %s enabled\n", - config&(1<<12) ? "already" : "not (yet)"); + (config & RM7K_CONF_TE) ? "already" : "not (yet)"); - if ((config >> 12) & 1) + if ((config & RM7K_CONF_TE)) rm7k_tcache_enabled = 1; } diff --git a/arch/mips/mm/tlb-andes.c b/arch/mips/mm/tlb-andes.c index 167e08e9661a..3f422a849c41 100644 --- a/arch/mips/mm/tlb-andes.c +++ b/arch/mips/mm/tlb-andes.c @@ -195,6 +195,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) { unsigned long flags; pgd_t *pgdp; + pud_t *pudp; pmd_t *pmdp; pte_t *ptep; int idx, pid; @@ -220,7 +221,8 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) write_c0_entryhi(address | (pid)); pgdp = pgd_offset(vma->vm_mm, address); tlb_probe(); - pmdp = pmd_offset(pgdp, address); + pudp = pud_offset(pgdp, address); + pmdp = pmd_offset(pudp, address); idx = read_c0_index(); ptep = pte_offset_map(pmdp, address); write_c0_entrylo0(pte_val(*ptep++) >> 6); diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 59d38bc05b69..8297970f0bb1 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -21,6 +21,12 @@ extern void build_tlb_refill_handler(void); +/* + * Make sure all entries differ. If they're not different + * MIPS32 will take revenge ... + */ +#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) + /* CP0 hazard avoidance. */ #define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ "nop; nop; nop; nop; nop; nop;\n\t" \ @@ -42,11 +48,8 @@ void local_flush_tlb_all(void) /* Blast 'em all away. */ while (entry < current_cpu_data.tlbsize) { - /* - * Make sure all entries differ. If they're not different - * MIPS32 will take revenge ... - */ - write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1))); + /* Make sure all entries differ. */ + write_c0_entryhi(UNIQUE_ENTRYHI(entry)); write_c0_index(entry); mtc0_tlbw_hazard(); tlb_write_indexed(); @@ -57,12 +60,21 @@ void local_flush_tlb_all(void) local_irq_restore(flags); } +/* All entries common to a mm share an asid. To effectively flush + these entries, we just bump the asid. */ void local_flush_tlb_mm(struct mm_struct *mm) { - int cpu = smp_processor_id(); + int cpu; + + preempt_disable(); - if (cpu_context(cpu, mm) != 0) - drop_mmu_context(mm,cpu); + cpu = smp_processor_id(); + + if (cpu_context(cpu, mm) != 0) { + drop_mmu_context(mm, cpu); + } + + preempt_enable(); } void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, @@ -75,9 +87,9 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long flags; int size; - local_irq_save(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; size = (size + 1) >> 1; + local_irq_save(flags); if (size <= current_cpu_data.tlbsize/2) { int oldpid = read_c0_entryhi(); int newpid = cpu_asid(cpu, mm); @@ -99,8 +111,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, if (idx < 0) continue; /* Make sure all entries differ. */ - write_c0_entryhi(CKSEG0 + - (idx << (PAGE_SHIFT + 1))); + write_c0_entryhi(UNIQUE_ENTRYHI(idx)); mtc0_tlbw_hazard(); tlb_write_indexed(); } @@ -118,9 +129,9 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) unsigned long flags; int size; - local_irq_save(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; size = (size + 1) >> 1; + local_irq_save(flags); if (size <= current_cpu_data.tlbsize / 2) { int pid = read_c0_entryhi(); @@ -142,7 +153,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) if (idx < 0) continue; /* Make sure all entries differ. */ - write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1))); + write_c0_entryhi(UNIQUE_ENTRYHI(idx)); mtc0_tlbw_hazard(); tlb_write_indexed(); } @@ -176,7 +187,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) if (idx < 0) goto finish; /* Make sure all entries differ. */ - write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1))); + write_c0_entryhi(UNIQUE_ENTRYHI(idx)); mtc0_tlbw_hazard(); tlb_write_indexed(); tlbw_use_hazard(); @@ -197,8 +208,8 @@ void local_flush_tlb_one(unsigned long page) int oldpid, idx; local_irq_save(flags); - page &= (PAGE_MASK << 1); oldpid = read_c0_entryhi(); + page &= (PAGE_MASK << 1); write_c0_entryhi(page); mtc0_tlbw_hazard(); tlb_probe(); @@ -208,7 +219,7 @@ void local_flush_tlb_one(unsigned long page) write_c0_entrylo1(0); if (idx >= 0) { /* Make sure all entries differ. */ - write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1))); + write_c0_entryhi(UNIQUE_ENTRYHI(idx)); mtc0_tlbw_hazard(); tlb_write_indexed(); tlbw_use_hazard(); @@ -227,6 +238,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) { unsigned long flags; pgd_t *pgdp; + pud_t *pudp; pmd_t *pmdp; pte_t *ptep; int idx, pid; @@ -237,35 +249,34 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) if (current->active_mm != vma->vm_mm) return; - pid = read_c0_entryhi() & ASID_MASK; - local_irq_save(flags); + + pid = read_c0_entryhi() & ASID_MASK; address &= (PAGE_MASK << 1); write_c0_entryhi(address | pid); pgdp = pgd_offset(vma->vm_mm, address); mtc0_tlbw_hazard(); tlb_probe(); BARRIER; - pmdp = pmd_offset(pgdp, address); + pudp = pud_offset(pgdp, address); + pmdp = pmd_offset(pudp, address); idx = read_c0_index(); ptep = pte_offset_map(pmdp, address); - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) - write_c0_entrylo0(ptep->pte_high); - ptep++; - write_c0_entrylo1(ptep->pte_high); +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) + write_c0_entrylo0(ptep->pte_high); + ptep++; + write_c0_entrylo1(ptep->pte_high); #else - write_c0_entrylo0(pte_val(*ptep++) >> 6); - write_c0_entrylo1(pte_val(*ptep) >> 6); + write_c0_entrylo0(pte_val(*ptep++) >> 6); + write_c0_entrylo1(pte_val(*ptep) >> 6); #endif - write_c0_entryhi(address | pid); mtc0_tlbw_hazard(); if (idx < 0) tlb_write_random(); else tlb_write_indexed(); tlbw_use_hazard(); - write_c0_entryhi(pid); local_irq_restore(flags); } @@ -357,7 +368,8 @@ __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, old_pagemask = read_c0_pagemask(); wired = read_c0_wired(); if (--temp_tlb_entry < wired) { - printk(KERN_WARNING "No TLB space left for add_temporary_entry\n"); + printk(KERN_WARNING + "No TLB space left for add_temporary_entry\n"); ret = -ENOSPC; goto out; } @@ -388,7 +400,7 @@ static void __init probe_tlb(unsigned long config) * is not supported, we assume R4k style. Cpu probing already figured * out the number of tlb entries. */ - if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY) + if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY) return; reg = read_c0_config1(); diff --git a/arch/mips/mm/tlb-sb1.c b/arch/mips/mm/tlb-sb1.c deleted file mode 100644 index 6256cafcf3a2..000000000000 --- a/arch/mips/mm/tlb-sb1.c +++ /dev/null @@ -1,376 +0,0 @@ -/* - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#include <linux/init.h> -#include <asm/mmu_context.h> -#include <asm/bootinfo.h> -#include <asm/cpu.h> - -extern void build_tlb_refill_handler(void); - -#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) - -/* Dump the current entry* and pagemask registers */ -static inline void dump_cur_tlb_regs(void) -{ - unsigned int entryhihi, entryhilo, entrylo0hi, entrylo0lo, entrylo1hi; - unsigned int entrylo1lo, pagemask; - - __asm__ __volatile__ ( - ".set push \n" - ".set noreorder \n" - ".set mips64 \n" - ".set noat \n" - " tlbr \n" - " dmfc0 $1, $10 \n" - " dsrl32 %0, $1, 0 \n" - " sll %1, $1, 0 \n" - " dmfc0 $1, $2 \n" - " dsrl32 %2, $1, 0 \n" - " sll %3, $1, 0 \n" - " dmfc0 $1, $3 \n" - " dsrl32 %4, $1, 0 \n" - " sll %5, $1, 0 \n" - " mfc0 %6, $5 \n" - ".set pop \n" - : "=r" (entryhihi), "=r" (entryhilo), - "=r" (entrylo0hi), "=r" (entrylo0lo), - "=r" (entrylo1hi), "=r" (entrylo1lo), - "=r" (pagemask)); - - printk("%08X%08X %08X%08X %08X%08X %08X", - entryhihi, entryhilo, - entrylo0hi, entrylo0lo, - entrylo1hi, entrylo1lo, - pagemask); -} - -void sb1_dump_tlb(void) -{ - unsigned long old_ctx; - unsigned long flags; - int entry; - local_irq_save(flags); - old_ctx = read_c0_entryhi(); - printk("Current TLB registers state:\n" - " EntryHi EntryLo0 EntryLo1 PageMask Index\n" - "--------------------------------------------------------------------\n"); - dump_cur_tlb_regs(); - printk(" %08X\n", read_c0_index()); - printk("\n\nFull TLB Dump:\n" - "Idx EntryHi EntryLo0 EntryLo1 PageMask\n" - "--------------------------------------------------------------\n"); - for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { - write_c0_index(entry); - printk("\n%02i ", entry); - dump_cur_tlb_regs(); - } - printk("\n"); - write_c0_entryhi(old_ctx); - local_irq_restore(flags); -} - -void local_flush_tlb_all(void) -{ - unsigned long flags; - unsigned long old_ctx; - int entry; - - local_irq_save(flags); - /* Save old context and create impossible VPN2 value */ - old_ctx = read_c0_entryhi() & ASID_MASK; - write_c0_entrylo0(0); - write_c0_entrylo1(0); - - entry = read_c0_wired(); - while (entry < current_cpu_data.tlbsize) { - write_c0_entryhi(UNIQUE_ENTRYHI(entry)); - write_c0_index(entry); - tlb_write_indexed(); - entry++; - } - write_c0_entryhi(old_ctx); - local_irq_restore(flags); -} - - -/* - * Use a bogus region of memory (starting at 0) to sanitize the TLB's. - * Use increments of the maximum page size (16MB), and check for duplicate - * entries before doing a given write. Then, when we're safe from collisions - * with the firmware, go back and give all the entries invalid addresses with - * the normal flush routine. Wired entries will be killed as well! - */ -static void __init sb1_sanitize_tlb(void) -{ - int entry; - long addr = 0; - - long inc = 1<<24; /* 16MB */ - /* Save old context and create impossible VPN2 value */ - write_c0_entrylo0(0); - write_c0_entrylo1(0); - for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { - do { - addr += inc; - write_c0_entryhi(addr); - tlb_probe(); - } while ((int)(read_c0_index()) >= 0); - write_c0_index(entry); - tlb_write_indexed(); - } - /* Now that we know we're safe from collisions, we can safely flush - the TLB with the "normal" routine. */ - local_flush_tlb_all(); -} - -void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - int cpu; - - local_irq_save(flags); - cpu = smp_processor_id(); - if (cpu_context(cpu, mm) != 0) { - int size; - size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; - size = (size + 1) >> 1; - if (size <= (current_cpu_data.tlbsize/2)) { - int oldpid = read_c0_entryhi() & ASID_MASK; - int newpid = cpu_asid(cpu, mm); - - start &= (PAGE_MASK << 1); - end += ((PAGE_SIZE << 1) - 1); - end &= (PAGE_MASK << 1); - while (start < end) { - int idx; - - write_c0_entryhi(start | newpid); - start += (PAGE_SIZE << 1); - tlb_probe(); - idx = read_c0_index(); - write_c0_entrylo0(0); - write_c0_entrylo1(0); - write_c0_entryhi(UNIQUE_ENTRYHI(idx)); - if (idx < 0) - continue; - tlb_write_indexed(); - } - write_c0_entryhi(oldpid); - } else { - drop_mmu_context(mm, cpu); - } - } - local_irq_restore(flags); -} - -void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) -{ - unsigned long flags; - int size; - - size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; - size = (size + 1) >> 1; - - local_irq_save(flags); - if (size <= (current_cpu_data.tlbsize/2)) { - int pid = read_c0_entryhi(); - - start &= (PAGE_MASK << 1); - end += ((PAGE_SIZE << 1) - 1); - end &= (PAGE_MASK << 1); - - while (start < end) { - int idx; - - write_c0_entryhi(start); - start += (PAGE_SIZE << 1); - tlb_probe(); - idx = read_c0_index(); - write_c0_entrylo0(0); - write_c0_entrylo1(0); - write_c0_entryhi(UNIQUE_ENTRYHI(idx)); - if (idx < 0) - continue; - tlb_write_indexed(); - } - write_c0_entryhi(pid); - } else { - local_flush_tlb_all(); - } - local_irq_restore(flags); -} - -void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) -{ - unsigned long flags; - int cpu = smp_processor_id(); - - local_irq_save(flags); - if (cpu_context(cpu, vma->vm_mm) != 0) { - int oldpid, newpid, idx; - newpid = cpu_asid(cpu, vma->vm_mm); - page &= (PAGE_MASK << 1); - oldpid = read_c0_entryhi() & ASID_MASK; - write_c0_entryhi(page | newpid); - tlb_probe(); - idx = read_c0_index(); - write_c0_entrylo0(0); - write_c0_entrylo1(0); - if (idx < 0) - goto finish; - /* Make sure all entries differ. */ - write_c0_entryhi(UNIQUE_ENTRYHI(idx)); - tlb_write_indexed(); - finish: - write_c0_entryhi(oldpid); - } - local_irq_restore(flags); -} - -/* - * Remove one kernel space TLB entry. This entry is assumed to be marked - * global so we don't do the ASID thing. - */ -void local_flush_tlb_one(unsigned long page) -{ - unsigned long flags; - int oldpid, idx; - - page &= (PAGE_MASK << 1); - oldpid = read_c0_entryhi() & ASID_MASK; - - local_irq_save(flags); - write_c0_entryhi(page); - tlb_probe(); - idx = read_c0_index(); - if (idx >= 0) { - /* Make sure all entries differ. */ - write_c0_entryhi(UNIQUE_ENTRYHI(idx)); - write_c0_entrylo0(0); - write_c0_entrylo1(0); - tlb_write_indexed(); - } - - write_c0_entryhi(oldpid); - local_irq_restore(flags); -} - -/* All entries common to a mm share an asid. To effectively flush - these entries, we just bump the asid. */ -void local_flush_tlb_mm(struct mm_struct *mm) -{ - int cpu; - - preempt_disable(); - - cpu = smp_processor_id(); - - if (cpu_context(cpu, mm) != 0) { - drop_mmu_context(mm, cpu); - } - - preempt_enable(); -} - -/* Stolen from mips32 routines */ - -void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) -{ - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - int idx, pid; - - /* - * Handle debugger faulting in for debugee. - */ - if (current->active_mm != vma->vm_mm) - return; - - local_irq_save(flags); - - pid = read_c0_entryhi() & ASID_MASK; - address &= (PAGE_MASK << 1); - write_c0_entryhi(address | (pid)); - pgdp = pgd_offset(vma->vm_mm, address); - tlb_probe(); - pmdp = pmd_offset(pgdp, address); - idx = read_c0_index(); - ptep = pte_offset_map(pmdp, address); - write_c0_entrylo0(pte_val(*ptep++) >> 6); - write_c0_entrylo1(pte_val(*ptep) >> 6); - if (idx < 0) { - tlb_write_random(); - } else { - tlb_write_indexed(); - } - local_irq_restore(flags); -} - -void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask) -{ - unsigned long flags; - unsigned long wired; - unsigned long old_pagemask; - unsigned long old_ctx; - - local_irq_save(flags); - old_ctx = read_c0_entryhi() & 0xff; - old_pagemask = read_c0_pagemask(); - wired = read_c0_wired(); - write_c0_wired(wired + 1); - write_c0_index(wired); - - write_c0_pagemask(pagemask); - write_c0_entryhi(entryhi); - write_c0_entrylo0(entrylo0); - write_c0_entrylo1(entrylo1); - tlb_write_indexed(); - - write_c0_entryhi(old_ctx); - write_c0_pagemask(old_pagemask); - - local_flush_tlb_all(); - local_irq_restore(flags); -} - -/* - * This is called from loadmmu.c. We have to set up all the - * memory management function pointers, as well as initialize - * the caches and tlbs - */ -void tlb_init(void) -{ - write_c0_pagemask(PM_DEFAULT_MASK); - write_c0_wired(0); - - /* - * We don't know what state the firmware left the TLB's in, so this is - * the ultra-conservative way to flush the TLB's and avoid machine - * check exceptions due to duplicate TLB entries - */ - sb1_sanitize_tlb(); - - build_tlb_refill_handler(); -} diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 6569be3983c7..0f9485806bac 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -6,6 +6,7 @@ * Synthesize TLB refill handlers at runtime. * * Copyright (C) 2004,2005 by Thiemo Seufer + * Copyright (C) 2005 Maciej W. Rozycki */ #include <stdarg.h> @@ -91,7 +92,7 @@ enum opcode { insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, - insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, + insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, @@ -134,7 +135,6 @@ static __initdata struct insn insn_table[] = { { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, - { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE }, { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, { insn_j, M(j_op,0,0,0,0,0), JIMM }, @@ -366,7 +366,6 @@ I_u2u1u3(_dsll); I_u2u1u3(_dsll32); I_u2u1u3(_dsra); I_u2u1u3(_dsrl); -I_u2u1u3(_dsrl32); I_u3u1u2(_dsubu); I_0(_eret); I_u1(_j); @@ -412,7 +411,6 @@ enum label_id { label_nopage_tlbm, label_smp_pgtable_change, label_r3000_write_probe_fail, - label_r3000_write_probe_ok }; struct label { @@ -445,7 +443,6 @@ L_LA(_nopage_tlbs) L_LA(_nopage_tlbm) L_LA(_smp_pgtable_change) L_LA(_r3000_write_probe_fail) -L_LA(_r3000_write_probe_ok) /* convenience macros for instructions */ #ifdef CONFIG_64BIT @@ -490,7 +487,7 @@ L_LA(_r3000_write_probe_ok) static __init int __attribute__((unused)) in_compat_space_p(long addr) { /* Is this address in 32bit compat space? */ - return (((addr) & 0xffffffff00000000) == 0xffffffff00000000); + return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); } static __init int __attribute__((unused)) rel_highest(long val) @@ -734,7 +731,7 @@ static void __init build_r3000_tlb_refill_handler(void) if (p > tlb_handler + 32) panic("TLB refill handler space exceeded"); - printk("Synthesized TLB handler (%u instructions).\n", + printk("Synthesized TLB refill handler (%u instructions).\n", (unsigned int)(p - tlb_handler)); #ifdef DEBUG_TLB { @@ -746,7 +743,6 @@ static void __init build_r3000_tlb_refill_handler(void) #endif memcpy((void *)CAC_BASE, tlb_handler, 0x80); - flush_icache_range(CAC_BASE, CAC_BASE + 0x80); } /* @@ -783,6 +779,8 @@ static __initdata u32 final_handler[64]; static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p) { switch (current_cpu_data.cputype) { + /* Found by experiment: R4600 v2.0 needs this, too. */ + case CPU_R4600: case CPU_R5000: case CPU_R5000A: case CPU_NEVADA: @@ -834,12 +832,20 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, case CPU_R4700: case CPU_R5000: case CPU_R5000A: + i_nop(p); + tlbw(p); + i_nop(p); + break; + + case CPU_R4300: case CPU_5KC: case CPU_TX49XX: case CPU_AU1000: case CPU_AU1100: case CPU_AU1500: case CPU_AU1550: + case CPU_AU1200: + case CPU_PR4450: i_nop(p); tlbw(p); break; @@ -848,6 +854,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, case CPU_R12000: case CPU_4KC: case CPU_SB1: + case CPU_SB1A: case CPU_4KSC: case CPU_20KC: case CPU_25KF: @@ -875,6 +882,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, case CPU_4KEC: case CPU_24K: + case CPU_34K: i_ehb(p); tlbw(p); break; @@ -911,6 +919,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, case CPU_VR4131: case CPU_VR4133: + case CPU_R5432: i_nop(p); i_nop(p); tlbw(p); @@ -942,34 +951,29 @@ build_get_pmde64(u32 **p, struct label **l, struct reloc **r, /* No i_nop needed here, since the next insn doesn't touch TMP. */ #ifdef CONFIG_SMP +# ifdef CONFIG_BUILD_ELF64 /* - * 64 bit SMP has the lower part of &pgd_current[smp_processor_id()] + * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 * stored in CONTEXT. */ - if (in_compat_space_p(pgdc)) { - i_dmfc0(p, ptr, C0_CONTEXT); - i_dsra(p, ptr, ptr, 23); - i_ld(p, ptr, 0, ptr); - } else { -#ifdef CONFIG_BUILD_ELF64 - i_dmfc0(p, ptr, C0_CONTEXT); - i_dsrl(p, ptr, ptr, 23); - i_dsll(p, ptr, ptr, 3); - i_LA_mostly(p, tmp, pgdc); - i_daddu(p, ptr, ptr, tmp); - i_dmfc0(p, tmp, C0_BADVADDR); - i_ld(p, ptr, rel_lo(pgdc), ptr); -#else - i_dmfc0(p, ptr, C0_CONTEXT); - i_lui(p, tmp, rel_highest(pgdc)); - i_dsll(p, ptr, ptr, 9); - i_daddiu(p, tmp, tmp, rel_higher(pgdc)); - i_dsrl32(p, ptr, ptr, 0); - i_and(p, ptr, ptr, tmp); - i_dmfc0(p, tmp, C0_BADVADDR); - i_ld(p, ptr, 0, ptr); -#endif - } + i_dmfc0(p, ptr, C0_CONTEXT); + i_dsrl(p, ptr, ptr, 23); + i_LA_mostly(p, tmp, pgdc); + i_daddu(p, ptr, ptr, tmp); + i_dmfc0(p, tmp, C0_BADVADDR); + i_ld(p, ptr, rel_lo(pgdc), ptr); +# else + /* + * 64 bit SMP running in compat space has the lower part of + * &pgd_current[smp_processor_id()] stored in CONTEXT. + */ + if (!in_compat_space_p(pgdc)) + panic("Invalid page directory address!"); + + i_dmfc0(p, ptr, C0_CONTEXT); + i_dsra(p, ptr, ptr, 23); + i_ld(p, ptr, 0, ptr); +# endif #else i_LA_mostly(p, ptr, pgdc); i_ld(p, ptr, rel_lo(pgdc), ptr); @@ -1026,7 +1030,6 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) i_mfc0(p, ptr, C0_CONTEXT); i_LA_mostly(p, tmp, pgdc); i_srl(p, ptr, ptr, 23); - i_sll(p, ptr, ptr, 2); i_addu(p, ptr, tmp, ptr); #else i_LA_mostly(p, ptr, pgdc); @@ -1245,13 +1248,19 @@ static void __init build_r4000_tlb_refill_handler(void) { int i; - for (i = 0; i < 64; i++) - printk("%08x\n", final_handler[i]); + f = final_handler; +#ifdef CONFIG_64BIT + if (final_len > 32) + final_len = 64; + else + f = final_handler + 32; +#endif /* CONFIG_64BIT */ + for (i = 0; i < final_len; i++) + printk("%08x\n", f[i]); } #endif memcpy((void *)CAC_BASE, final_handler, 0x100); - flush_icache_range(CAC_BASE, CAC_BASE + 0x100); } /* @@ -1277,37 +1286,41 @@ u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE]; u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE]; static void __init -iPTE_LW(u32 **p, struct label **l, unsigned int pte, int offset, - unsigned int ptr) +iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr) { #ifdef CONFIG_SMP # ifdef CONFIG_64BIT_PHYS_ADDR if (cpu_has_64bits) - i_lld(p, pte, offset, ptr); + i_lld(p, pte, 0, ptr); else # endif - i_LL(p, pte, offset, ptr); + i_LL(p, pte, 0, ptr); #else # ifdef CONFIG_64BIT_PHYS_ADDR if (cpu_has_64bits) - i_ld(p, pte, offset, ptr); + i_ld(p, pte, 0, ptr); else # endif - i_LW(p, pte, offset, ptr); + i_LW(p, pte, 0, ptr); #endif } static void __init -iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, int offset, - unsigned int ptr) +iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr, + unsigned int mode) { +#ifdef CONFIG_64BIT_PHYS_ADDR + unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); +#endif + + i_ori(p, pte, pte, mode); #ifdef CONFIG_SMP # ifdef CONFIG_64BIT_PHYS_ADDR if (cpu_has_64bits) - i_scd(p, pte, offset, ptr); + i_scd(p, pte, 0, ptr); else # endif - i_SC(p, pte, offset, ptr); + i_SC(p, pte, 0, ptr); if (r10000_llsc_war()) il_beqzl(p, r, pte, label_smp_pgtable_change); @@ -1318,7 +1331,7 @@ iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, int offset, if (!cpu_has_64bits) { /* no i_nop needed */ i_ll(p, pte, sizeof(pte_t) / 2, ptr); - i_ori(p, pte, pte, _PAGE_VALID); + i_ori(p, pte, pte, hwmode); i_sc(p, pte, sizeof(pte_t) / 2, ptr); il_beqz(p, r, pte, label_smp_pgtable_change); /* no i_nop needed */ @@ -1331,15 +1344,15 @@ iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, int offset, #else # ifdef CONFIG_64BIT_PHYS_ADDR if (cpu_has_64bits) - i_sd(p, pte, offset, ptr); + i_sd(p, pte, 0, ptr); else # endif - i_SW(p, pte, offset, ptr); + i_SW(p, pte, 0, ptr); # ifdef CONFIG_64BIT_PHYS_ADDR if (!cpu_has_64bits) { i_lw(p, pte, sizeof(pte_t) / 2, ptr); - i_ori(p, pte, pte, _PAGE_VALID); + i_ori(p, pte, pte, hwmode); i_sw(p, pte, sizeof(pte_t) / 2, ptr); i_lw(p, pte, 0, ptr); } @@ -1359,7 +1372,7 @@ build_pte_present(u32 **p, struct label **l, struct reloc **r, i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); il_bnez(p, r, pte, lid); - iPTE_LW(p, l, pte, 0, ptr); + iPTE_LW(p, l, pte, ptr); } /* Make PTE valid, store result in PTR. */ @@ -1367,8 +1380,9 @@ static void __init build_make_valid(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr) { - i_ori(p, pte, pte, _PAGE_VALID | _PAGE_ACCESSED); - iPTE_SW(p, r, pte, 0, ptr); + unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; + + iPTE_SW(p, r, pte, ptr, mode); } /* @@ -1382,7 +1396,7 @@ build_pte_writable(u32 **p, struct label **l, struct reloc **r, i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); il_bnez(p, r, pte, lid); - iPTE_LW(p, l, pte, 0, ptr); + iPTE_LW(p, l, pte, ptr); } /* Make PTE writable, update software status bits as well, then store @@ -1392,9 +1406,10 @@ static void __init build_make_write(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr) { - i_ori(p, pte, pte, - _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); - iPTE_SW(p, r, pte, 0, ptr); + unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID + | _PAGE_DIRTY); + + iPTE_SW(p, r, pte, ptr, mode); } /* @@ -1407,41 +1422,48 @@ build_pte_modifiable(u32 **p, struct label **l, struct reloc **r, { i_andi(p, pte, pte, _PAGE_WRITE); il_beqz(p, r, pte, lid); - iPTE_LW(p, l, pte, 0, ptr); + iPTE_LW(p, l, pte, ptr); } /* * R3000 style TLB load/store/modify handlers. */ -/* This places the pte in the page table at PTR into ENTRYLO0. */ +/* + * This places the pte into ENTRYLO0 and writes it with tlbwi. + * Then it returns. + */ static void __init -build_r3000_pte_reload(u32 **p, unsigned int ptr) +build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) { - i_lw(p, ptr, 0, ptr); - i_nop(p); /* load delay */ - i_mtc0(p, ptr, C0_ENTRYLO0); - i_nop(p); /* cp0 delay */ + i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ + i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ + i_tlbwi(p); + i_jr(p, tmp); + i_rfe(p); /* branch delay */ } /* - * The index register may have the probe fail bit set, - * because we would trap on access kseg2, i.e. without refill. + * This places the pte into ENTRYLO0 and writes it with tlbwi + * or tlbwr as appropriate. This is because the index register + * may have the probe fail bit set as a result of a trap on a + * kseg2 access, i.e. without refill. Then it returns. */ static void __init -build_r3000_tlb_write(u32 **p, struct label **l, struct reloc **r, - unsigned int tmp) +build_r3000_tlb_reload_write(u32 **p, struct label **l, struct reloc **r, + unsigned int pte, unsigned int tmp) { i_mfc0(p, tmp, C0_INDEX); - i_nop(p); /* cp0 delay */ - il_bltz(p, r, tmp, label_r3000_write_probe_fail); - i_nop(p); /* branch delay */ - i_tlbwi(p); - il_b(p, r, label_r3000_write_probe_ok); - i_nop(p); /* branch delay */ + i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ + il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ + i_mfc0(p, tmp, C0_EPC); /* branch delay */ + i_tlbwi(p); /* cp0 delay */ + i_jr(p, tmp); + i_rfe(p); /* branch delay */ l_r3000_write_probe_fail(l, *p); - i_tlbwr(p); - l_r3000_write_probe_ok(l, *p); + i_tlbwr(p); /* cp0 delay */ + i_jr(p, tmp); + i_rfe(p); /* branch delay */ } static void __init @@ -1461,17 +1483,7 @@ build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, i_andi(p, pte, pte, 0xffc); /* load delay */ i_addu(p, ptr, ptr, pte); i_lw(p, pte, 0, ptr); - i_nop(p); /* load delay */ - i_tlbp(p); -} - -static void __init -build_r3000_tlbchange_handler_tail(u32 **p, unsigned int tmp) -{ - i_mfc0(p, tmp, C0_EPC); - i_nop(p); /* cp0 delay */ - i_jr(p, tmp); - i_rfe(p); /* branch delay */ + i_tlbp(p); /* load delay */ } static void __init build_r3000_tlb_load_handler(void) @@ -1486,10 +1498,9 @@ static void __init build_r3000_tlb_load_handler(void) build_r3000_tlbchange_handler_head(&p, K0, K1); build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); + i_nop(&p); /* load delay */ build_make_valid(&p, &r, K0, K1); - build_r3000_pte_reload(&p, K1); - build_r3000_tlb_write(&p, &l, &r, K0); - build_r3000_tlbchange_handler_tail(&p, K0); + build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); l_nopage_tlbl(&l, p); i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); @@ -1506,13 +1517,10 @@ static void __init build_r3000_tlb_load_handler(void) { int i; - for (i = 0; i < FASTPATH_SIZE; i++) + for (i = 0; i < (p - handle_tlbl); i++) printk("%08x\n", handle_tlbl[i]); } #endif - - flush_icache_range((unsigned long)handle_tlbl, - (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32)); } static void __init build_r3000_tlb_store_handler(void) @@ -1527,10 +1535,9 @@ static void __init build_r3000_tlb_store_handler(void) build_r3000_tlbchange_handler_head(&p, K0, K1); build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); + i_nop(&p); /* load delay */ build_make_write(&p, &r, K0, K1); - build_r3000_pte_reload(&p, K1); - build_r3000_tlb_write(&p, &l, &r, K0); - build_r3000_tlbchange_handler_tail(&p, K0); + build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); l_nopage_tlbs(&l, p); i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); @@ -1547,13 +1554,10 @@ static void __init build_r3000_tlb_store_handler(void) { int i; - for (i = 0; i < FASTPATH_SIZE; i++) + for (i = 0; i < (p - handle_tlbs); i++) printk("%08x\n", handle_tlbs[i]); } #endif - - flush_icache_range((unsigned long)handle_tlbs, - (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32)); } static void __init build_r3000_tlb_modify_handler(void) @@ -1568,10 +1572,9 @@ static void __init build_r3000_tlb_modify_handler(void) build_r3000_tlbchange_handler_head(&p, K0, K1); build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); + i_nop(&p); /* load delay */ build_make_write(&p, &r, K0, K1); - build_r3000_pte_reload(&p, K1); - i_tlbwi(&p); - build_r3000_tlbchange_handler_tail(&p, K0); + build_r3000_pte_reload_tlbwi(&p, K0, K1); l_nopage_tlbm(&l, p); i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); @@ -1588,13 +1591,10 @@ static void __init build_r3000_tlb_modify_handler(void) { int i; - for (i = 0; i < FASTPATH_SIZE; i++) + for (i = 0; i < (p - handle_tlbm); i++) printk("%08x\n", handle_tlbm[i]); } #endif - - flush_icache_range((unsigned long)handle_tlbm, - (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32)); } /* @@ -1620,7 +1620,7 @@ build_r4000_tlbchange_handler_head(u32 **p, struct label **l, #ifdef CONFIG_SMP l_smp_pgtable_change(l, *p); # endif - iPTE_LW(p, l, pte, 0, ptr); /* get even pte */ + iPTE_LW(p, l, pte, ptr); /* get even pte */ build_tlb_probe_entry(p); } @@ -1680,13 +1680,10 @@ static void __init build_r4000_tlb_load_handler(void) { int i; - for (i = 0; i < FASTPATH_SIZE; i++) + for (i = 0; i < (p - handle_tlbl); i++) printk("%08x\n", handle_tlbl[i]); } #endif - - flush_icache_range((unsigned long)handle_tlbl, - (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32)); } static void __init build_r4000_tlb_store_handler(void) @@ -1719,13 +1716,10 @@ static void __init build_r4000_tlb_store_handler(void) { int i; - for (i = 0; i < FASTPATH_SIZE; i++) + for (i = 0; i < (p - handle_tlbs); i++) printk("%08x\n", handle_tlbs[i]); } #endif - - flush_icache_range((unsigned long)handle_tlbs, - (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32)); } static void __init build_r4000_tlb_modify_handler(void) @@ -1759,13 +1753,10 @@ static void __init build_r4000_tlb_modify_handler(void) { int i; - for (i = 0; i < FASTPATH_SIZE; i++) + for (i = 0; i < (p - handle_tlbm); i++) printk("%08x\n", handle_tlbm[i]); } #endif - - flush_icache_range((unsigned long)handle_tlbm, - (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32)); } void __init build_tlb_refill_handler(void) @@ -1813,3 +1804,13 @@ void __init build_tlb_refill_handler(void) } } } + +void __init flush_tlb_handlers(void) +{ + flush_icache_range((unsigned long)handle_tlbl, + (unsigned long)handle_tlbl + sizeof(handle_tlbl)); + flush_icache_range((unsigned long)handle_tlbs, + (unsigned long)handle_tlbs + sizeof(handle_tlbs)); + flush_icache_range((unsigned long)handle_tlbm, + (unsigned long)handle_tlbm + sizeof(handle_tlbm)); +} diff --git a/arch/mips/momentum/Kconfig b/arch/mips/momentum/Kconfig new file mode 100644 index 000000000000..70a61cf7174d --- /dev/null +++ b/arch/mips/momentum/Kconfig @@ -0,0 +1,6 @@ +config JAGUAR_DMALOW + bool "Low DMA Mode" + depends on MOMENCO_JAGUAR_ATX + help + Select to Y if jump JP5 is set on your board, N otherwise. Normally + the jumper is set, so if you feel unsafe, just say Y. diff --git a/arch/mips/momentum/jaguar_atx/prom.c b/arch/mips/momentum/jaguar_atx/prom.c index 14ae2e713585..aae7a802767a 100644 --- a/arch/mips/momentum/jaguar_atx/prom.c +++ b/arch/mips/momentum/jaguar_atx/prom.c @@ -236,8 +236,9 @@ void __init prom_init(void) #endif } -void __init prom_free_prom_memory(void) +unsigned long __init prom_free_prom_memory(void) { + return 0; } void __init prom_fixup_mem_map(unsigned long start, unsigned long end) diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c index 90288cf2b1e0..768bf4406452 100644 --- a/arch/mips/momentum/jaguar_atx/setup.c +++ b/arch/mips/momentum/jaguar_atx/setup.c @@ -351,7 +351,7 @@ static __init int __init ja_pci_init(void) arch_initcall(ja_pci_init); -static int __init momenco_jaguar_atx_setup(void) +void __init plat_setup(void) { unsigned int tmpword; @@ -467,8 +467,4 @@ static int __init momenco_jaguar_atx_setup(void) } #endif - - return 0; } - -early_initcall(momenco_jaguar_atx_setup); diff --git a/arch/mips/momentum/ocelot_3/prom.c b/arch/mips/momentum/ocelot_3/prom.c index c4fa9c525faa..9803daa2a792 100644 --- a/arch/mips/momentum/ocelot_3/prom.c +++ b/arch/mips/momentum/ocelot_3/prom.c @@ -239,8 +239,9 @@ void __init prom_init(void) #endif } -void __init prom_free_prom_memory(void) +unsigned long __init prom_free_prom_memory(void) { + return 0; } void __init prom_fixup_mem_map(unsigned long start, unsigned long end) diff --git a/arch/mips/momentum/ocelot_3/setup.c b/arch/mips/momentum/ocelot_3/setup.c index ce2efcbab7aa..a7803e08f9db 100644 --- a/arch/mips/momentum/ocelot_3/setup.c +++ b/arch/mips/momentum/ocelot_3/setup.c @@ -307,7 +307,7 @@ static __init int __init ja_pci_init(void) arch_initcall(ja_pci_init); -static int __init momenco_ocelot_3_setup(void) +void __init plat_setup(void) { unsigned int tmpword; @@ -391,8 +391,4 @@ static int __init momenco_ocelot_3_setup(void) /* Support for 128 MB memory */ add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM); - - return 0; } - -early_initcall(momenco_ocelot_3_setup); diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c index dea48b3ad687..bd885785e2f9 100644 --- a/arch/mips/momentum/ocelot_c/cpci-irq.c +++ b/arch/mips/momentum/ocelot_c/cpci-irq.c @@ -129,14 +129,13 @@ void ll_cpci_irq(struct pt_regs *regs) #define shutdown_cpci_irq disable_cpci_irq struct hw_interrupt_type cpci_irq_type = { - "CPCI/FPGA", - startup_cpci_irq, - shutdown_cpci_irq, - enable_cpci_irq, - disable_cpci_irq, - mask_and_ack_cpci_irq, - end_cpci_irq, - NULL + .typename = "CPCI/FPGA", + .startup = startup_cpci_irq, + .shutdown = shutdown_cpci_irq, + .enable = enable_cpci_irq, + .disable = disable_cpci_irq, + .ack = mask_and_ack_cpci_irq, + .end = end_cpci_irq, }; void cpci_irq_init(void) diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c index 844ddd06349b..ce70fc96f160 100644 --- a/arch/mips/momentum/ocelot_c/setup.c +++ b/arch/mips/momentum/ocelot_c/setup.c @@ -222,7 +222,7 @@ void momenco_time_init(void) rtc_set_time = m48t37y_set_time; } -static void __init momenco_ocelot_c_setup(void) +void __init plat_setup(void) { unsigned int tmpword; @@ -340,8 +340,6 @@ static void __init momenco_ocelot_c_setup(void) } } -early_initcall(momenco_ocelot_c_setup); - #ifndef CONFIG_64BIT /* This needs to be one of the first initcalls, because no I/O port access can work before this */ diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c index ebe1507b17df..755bde5146be 100644 --- a/arch/mips/momentum/ocelot_c/uart-irq.c +++ b/arch/mips/momentum/ocelot_c/uart-irq.c @@ -122,14 +122,13 @@ void ll_uart_irq(struct pt_regs *regs) #define shutdown_uart_irq disable_uart_irq struct hw_interrupt_type uart_irq_type = { - "UART/FPGA", - startup_uart_irq, - shutdown_uart_irq, - enable_uart_irq, - disable_uart_irq, - mask_and_ack_uart_irq, - end_uart_irq, - NULL + .typename = "UART/FPGA", + .startup = startup_uart_irq, + .shutdown = shutdown_uart_irq, + .enable = enable_uart_irq, + .disable = disable_uart_irq, + .ack = mask_and_ack_uart_irq, + .end = end_uart_irq, }; void uart_irq_init(void) diff --git a/arch/mips/momentum/ocelot_g/setup.c b/arch/mips/momentum/ocelot_g/setup.c index 38a78ab8c830..6336751391c3 100644 --- a/arch/mips/momentum/ocelot_g/setup.c +++ b/arch/mips/momentum/ocelot_g/setup.c @@ -160,7 +160,7 @@ static void __init setup_l3cache(unsigned long size) printk("Done\n"); } -static int __init momenco_ocelot_g_setup(void) +void __init plat_setup(void) { void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache); unsigned int tmpword; @@ -240,12 +240,8 @@ static int __init momenco_ocelot_g_setup(void) /* FIXME: Fix up the DiskOnChip mapping */ MV_WRITE(0x468, 0xfef73); - - return 0; } -early_initcall(momenco_ocelot_g_setup); - /* This needs to be one of the first initcalls, because no I/O port access can work before this */ diff --git a/arch/mips/oprofile/Kconfig b/arch/mips/oprofile/Kconfig index 19d37730b664..55feaf798596 100644 --- a/arch/mips/oprofile/Kconfig +++ b/arch/mips/oprofile/Kconfig @@ -11,7 +11,7 @@ config PROFILING config OPROFILE tristate "OProfile system profiling (EXPERIMENTAL)" - depends on PROFILING + depends on PROFILING && EXPERIMENTAL help OProfile is a profiling system capable of profiling the whole system, include the kernel, kernel modules, libraries, diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index ab65ce3d471a..dd2cc42f1b6d 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -3,7 +3,8 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2004 by Ralf Baechle + * Copyright (C) 2004, 2005 Ralf Baechle + * Copyright (C) 2005 MIPS Technologies, Inc. */ #include <linux/errno.h> #include <linux/init.h> @@ -45,10 +46,10 @@ static int op_mips_create_files(struct super_block * sb, struct dentry * root) oprofilefs_create_ulong(sb, dir, "enabled", &ctr[i].enabled); oprofilefs_create_ulong(sb, dir, "event", &ctr[i].event); oprofilefs_create_ulong(sb, dir, "count", &ctr[i].count); - /* Dummies. */ oprofilefs_create_ulong(sb, dir, "kernel", &ctr[i].kernel); oprofilefs_create_ulong(sb, dir, "user", &ctr[i].user); oprofilefs_create_ulong(sb, dir, "exl", &ctr[i].exl); + /* Dummy. */ oprofilefs_create_ulong(sb, dir, "unit_mask", &ctr[i].unit_mask); } @@ -68,9 +69,10 @@ static void op_mips_stop(void) on_each_cpu(model->cpu_stop, NULL, 0, 1); } -void __init oprofile_arch_init(struct oprofile_operations *ops) +int __init oprofile_arch_init(struct oprofile_operations *ops) { struct op_mips_model *lmodel = NULL; + int res; switch (current_cpu_data.cputype) { case CPU_24K: @@ -83,21 +85,25 @@ void __init oprofile_arch_init(struct oprofile_operations *ops) }; if (!lmodel) - return; + return -ENODEV; - if (lmodel->init()) - return; + res = lmodel->init(); + if (res) + return res; model = lmodel; - ops->create_files = op_mips_create_files; - ops->setup = op_mips_setup; - ops->start = op_mips_start; - ops->stop = op_mips_stop; - ops->cpu_type = lmodel->cpu_type; + ops->create_files = op_mips_create_files; + ops->setup = op_mips_setup; + //ops->shutdown = op_mips_shutdown; + ops->start = op_mips_start; + ops->stop = op_mips_stop; + ops->cpu_type = lmodel->cpu_type; printk(KERN_INFO "oprofile: using %s performance monitoring.\n", lmodel->cpu_type); + + return 0; } void oprofile_arch_exit(void) diff --git a/arch/mips/oprofile/op_impl.h b/arch/mips/oprofile/op_impl.h index 9f5cdff041be..f0121557047d 100644 --- a/arch/mips/oprofile/op_impl.h +++ b/arch/mips/oprofile/op_impl.h @@ -10,6 +10,11 @@ #ifndef OP_IMPL_H #define OP_IMPL_H 1 +struct pt_regs; + +extern void null_perf_irq(struct pt_regs *regs); +extern void (*perf_irq)(struct pt_regs *regs); + /* Per-counter configuration as set via oprofilefs. */ struct op_counter_config { unsigned long enabled; diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c new file mode 100644 index 000000000000..d36b64dfcb2f --- /dev/null +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -0,0 +1,215 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004, 2005 by Ralf Baechle + * Copyright (C) 2005 by MIPS Technologies, Inc. + */ +#include <linux/oprofile.h> +#include <linux/interrupt.h> +#include <linux/smp.h> + +#include "op_impl.h" + +#define M_PERFCTL_EXL (1UL << 0) +#define M_PERFCTL_KERNEL (1UL << 1) +#define M_PERFCTL_SUPERVISOR (1UL << 2) +#define M_PERFCTL_USER (1UL << 3) +#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) +#define M_PERFCTL_EVENT(event) ((event) << 5) +#define M_PERFCTL_WIDE (1UL << 30) +#define M_PERFCTL_MORE (1UL << 31) + +#define M_COUNTER_OVERFLOW (1UL << 31) + +struct op_mips_model op_model_mipsxx; + +static struct mipsxx_register_config { + unsigned int control[4]; + unsigned int counter[4]; +} reg; + +/* Compute all of the registers in preparation for enabling profiling. */ + +static void mipsxx_reg_setup(struct op_counter_config *ctr) +{ + unsigned int counters = op_model_mipsxx.num_counters; + int i; + + /* Compute the performance counter control word. */ + /* For now count kernel and user mode */ + for (i = 0; i < counters; i++) { + reg.control[i] = 0; + reg.counter[i] = 0; + + if (!ctr[i].enabled) + continue; + + reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) | + M_PERFCTL_INTERRUPT_ENABLE; + if (ctr[i].kernel) + reg.control[i] |= M_PERFCTL_KERNEL; + if (ctr[i].user) + reg.control[i] |= M_PERFCTL_USER; + if (ctr[i].exl) + reg.control[i] |= M_PERFCTL_EXL; + reg.counter[i] = 0x80000000 - ctr[i].count; + } +} + +/* Program all of the registers in preparation for enabling profiling. */ + +static void mipsxx_cpu_setup (void *args) +{ + unsigned int counters = op_model_mipsxx.num_counters; + + switch (counters) { + case 4: + write_c0_perfctrl3(0); + write_c0_perfcntr3(reg.counter[3]); + case 3: + write_c0_perfctrl2(0); + write_c0_perfcntr2(reg.counter[2]); + case 2: + write_c0_perfctrl1(0); + write_c0_perfcntr1(reg.counter[1]); + case 1: + write_c0_perfctrl0(0); + write_c0_perfcntr0(reg.counter[0]); + } +} + +/* Start all counters on current CPU */ +static void mipsxx_cpu_start(void *args) +{ + unsigned int counters = op_model_mipsxx.num_counters; + + switch (counters) { + case 4: + write_c0_perfctrl3(reg.control[3]); + case 3: + write_c0_perfctrl2(reg.control[2]); + case 2: + write_c0_perfctrl1(reg.control[1]); + case 1: + write_c0_perfctrl0(reg.control[0]); + } +} + +/* Stop all counters on current CPU */ +static void mipsxx_cpu_stop(void *args) +{ + unsigned int counters = op_model_mipsxx.num_counters; + + switch (counters) { + case 4: + write_c0_perfctrl3(0); + case 3: + write_c0_perfctrl2(0); + case 2: + write_c0_perfctrl1(0); + case 1: + write_c0_perfctrl0(0); + } +} + +static void mipsxx_perfcount_handler(struct pt_regs *regs) +{ + unsigned int counters = op_model_mipsxx.num_counters; + unsigned int control; + unsigned int counter; + + switch (counters) { +#define HANDLE_COUNTER(n) \ + case n + 1: \ + control = read_c0_perfctrl ## n(); \ + counter = read_c0_perfcntr ## n(); \ + if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \ + (counter & M_COUNTER_OVERFLOW)) { \ + oprofile_add_sample(regs, n); \ + write_c0_perfcntr ## n(reg.counter[n]); \ + } + HANDLE_COUNTER(3) + HANDLE_COUNTER(2) + HANDLE_COUNTER(1) + HANDLE_COUNTER(0) + } +} + +#define M_CONFIG1_PC (1 << 4) + +static inline int n_counters(void) +{ + if (!(read_c0_config1() & M_CONFIG1_PC)) + return 0; + if (!(read_c0_perfctrl0() & M_PERFCTL_MORE)) + return 1; + if (!(read_c0_perfctrl1() & M_PERFCTL_MORE)) + return 2; + if (!(read_c0_perfctrl2() & M_PERFCTL_MORE)) + return 3; + + return 4; +} + +static inline void reset_counters(int counters) +{ + switch (counters) { + case 4: + write_c0_perfctrl3(0); + write_c0_perfcntr3(0); + case 3: + write_c0_perfctrl2(0); + write_c0_perfcntr2(0); + case 2: + write_c0_perfctrl1(0); + write_c0_perfcntr1(0); + case 1: + write_c0_perfctrl0(0); + write_c0_perfcntr0(0); + } +} + +static int __init mipsxx_init(void) +{ + int counters; + + counters = n_counters(); + if (counters == 0) + return -ENODEV; + + reset_counters(counters); + + op_model_mipsxx.num_counters = counters; + switch (current_cpu_data.cputype) { + case CPU_24K: + op_model_mipsxx.cpu_type = "mips/24K"; + break; + + default: + printk(KERN_ERR "Profiling unsupported for this CPU\n"); + + return -ENODEV; + } + + perf_irq = mipsxx_perfcount_handler; + + return 0; +} + +static void mipsxx_exit(void) +{ + reset_counters(op_model_mipsxx.num_counters); + + perf_irq = null_perf_irq; +} + +struct op_mips_model op_model_mipsxx = { + .reg_setup = mipsxx_reg_setup, + .cpu_setup = mipsxx_cpu_setup, + .init = mipsxx_init, + .exit = mipsxx_exit, + .cpu_start = mipsxx_cpu_start, + .cpu_stop = mipsxx_cpu_stop, +}; diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c index bee47793cb1a..9b75e41c78ef 100644 --- a/arch/mips/oprofile/op_model_rm9000.c +++ b/arch/mips/oprofile/op_model_rm9000.c @@ -5,6 +5,7 @@ * * Copyright (C) 2004 by Ralf Baechle */ +#include <linux/init.h> #include <linux/oprofile.h> #include <linux/interrupt.h> #include <linux/smp.h> @@ -114,7 +115,7 @@ static irqreturn_t rm9000_perfcount_handler(int irq, void * dev_id, return IRQ_HANDLED; } -static int rm9000_init(void) +static int __init rm9000_init(void) { return request_irq(rm9000_perfcount_irq, rm9000_perfcount_handler, 0, "Perfcounter", NULL); diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 83d81c9cdc2b..7b7468304022 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_MIPS_ITE8172) += fixup-ite8172g.o obj-$(CONFIG_MIPS_IVR) += fixup-ivr.o obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o +obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o @@ -45,11 +46,13 @@ obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \ obj-$(CONFIG_SGI_IP27) += pci-ip27.o obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o +obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o +obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o diff --git a/arch/mips/pci/fixup-atlas.c b/arch/mips/pci/fixup-atlas.c index 2406835833d6..87920b245931 100644 --- a/arch/mips/pci/fixup-atlas.c +++ b/arch/mips/pci/fixup-atlas.c @@ -1,14 +1,37 @@ +/* + * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * Author: Maciej W. Rozycki <macro@mips.com> + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ #include <linux/config.h> #include <linux/init.h> #include <linux/pci.h> + #include <asm/mips-boards/atlasint.h> -#define INTD ATLASINT_INTD -#define INTC ATLASINT_INTC -#define INTB ATLASINT_INTB +#define PCIA ATLASINT_PCIA +#define PCIB ATLASINT_PCIB +#define PCIC ATLASINT_PCIC +#define PCID ATLASINT_PCID #define INTA ATLASINT_INTA -#define SCSI ATLASINT_SCSI +#define INTB ATLASINT_INTB #define ETH ATLASINT_ETH +#define INTC ATLASINT_INTC +#define SCSI ATLASINT_SCSI +#define INTD ATLASINT_INTD static char irq_tab[][5] __initdata = { /* INTA INTB INTC INTD */ @@ -27,13 +50,13 @@ static char irq_tab[][5] __initdata = { {0, 0, 0, 0, 0 }, /* 12: Unused */ {0, 0, 0, 0, 0 }, /* 13: Unused */ {0, 0, 0, 0, 0 }, /* 14: Unused */ - {0, 0, 0, 0, 0 }, /* 15: Unused */ + {0, PCIA, PCIB, PCIC, PCID }, /* 15: cPCI (behind 21150) */ {0, SCSI, 0, 0, 0 }, /* 16: SYM53C810A SCSI */ {0, 0, 0, 0, 0 }, /* 17: Core */ - {0, INTA, INTB, INTC, INTD }, /* 18: PCI Slot 1 */ - {0, ETH, 0, 0, 0 }, /* 19: SAA9730 Ethernet */ - {0, 0, 0, 0, 0 }, /* 20: PCI Slot 3 */ - {0, 0, 0, 0, 0 } /* 21: PCI Slot 4 */ + {0, INTA, INTB, INTC, INTD }, /* 18: PCI Slot */ + {0, ETH, 0, 0, 0 }, /* 19: SAA9730 Eth. et al. */ + {0, 0, 0, 0, 0 }, /* 20: Unused */ + {0, 0, 0, 0, 0 } /* 21: Unused */ }; int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c index 39fe2b16fcec..c2f8304fe55b 100644 --- a/arch/mips/pci/fixup-au1000.c +++ b/arch/mips/pci/fixup-au1000.c @@ -26,7 +26,6 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include <linux/config.h> #include <linux/types.h> #include <linux/pci.h> #include <linux/kernel.h> @@ -34,82 +33,7 @@ #include <asm/mach-au1x00/au1000.h> -/* - * Shortcut - */ -#ifdef CONFIG_SOC_AU1500 -#define INTA AU1000_PCI_INTA -#define INTB AU1000_PCI_INTB -#define INTC AU1000_PCI_INTC -#define INTD AU1000_PCI_INTD -#endif - -#ifdef CONFIG_SOC_AU1550 -#define INTA AU1550_PCI_INTA -#define INTB AU1550_PCI_INTB -#define INTC AU1550_PCI_INTC -#define INTD AU1550_PCI_INTD -#endif - -#define INTX 0xFF /* not valid */ - -#ifdef CONFIG_MIPS_DB1500 -static char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT371 */ - [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */ -}; -#endif - -#ifdef CONFIG_MIPS_BOSPORUS -static char irq_tab_alchemy[][5] __initdata = { - [11] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 11 - miniPCI */ - [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - SN1741 */ - [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */ -}; -#endif - -#ifdef CONFIG_MIPS_MIRAGE -static char irq_tab_alchemy[][5] __initdata = { - [11] = { -1, INTD, INTX, INTX, INTX}, /* IDSEL 11 - SMI VGX */ - [12] = { -1, INTX, INTX, INTC, INTX}, /* IDSEL 12 - PNX1300 */ - [13] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 13 - miniPCI */ -}; -#endif - -#ifdef CONFIG_MIPS_DB1550 -static char irq_tab_alchemy[][5] __initdata = { - [11] = { -1, INTC, INTX, INTX, INTX}, /* IDSEL 11 - on-board HPT371 */ - [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */ - [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */ -}; -#endif - -#ifdef CONFIG_MIPS_PB1500 -static char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT370 */ - [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */ -}; -#endif - -#ifdef CONFIG_MIPS_PB1550 -static char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */ - [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */ -}; -#endif - -#ifdef CONFIG_MIPS_MTX1 -static char irq_tab_alchemy[][5] __initdata = { - [0] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 00 - AdapterA-Slot0 (top) */ - [1] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 01 - AdapterA-Slot1 (bottom) */ - [2] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 02 - AdapterB-Slot0 (top) */ - [3] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 03 - AdapterB-Slot1 (bottom) */ - [4] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 04 - AdapterC-Slot0 (top) */ - [5] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 05 - AdapterC-Slot1 (bottom) */ - [6] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 06 - AdapterD-Slot0 (top) */ - [7] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 07 - AdapterD-Slot1 (bottom) */ -}; -#endif +extern char irq_tab_alchemy[][5]; int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index 57e1ca2116bb..909292f50d06 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c @@ -21,6 +21,20 @@ extern int cobalt_board_id; +static void qube_raq_galileo_early_fixup(struct pci_dev *dev) +{ + if (dev->devfn == PCI_DEVFN(0, 0) && + (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) { + + dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff); + + printk(KERN_INFO "Galileo: fixed bridge class\n"); + } +} + +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, + qube_raq_galileo_early_fixup); + static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) { unsigned short cfgword; @@ -48,6 +62,9 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev) { unsigned short galileo_id; + if (dev->devfn != PCI_DEVFN(0, 0)) + return; + /* Fix PCI latency-timer and cache-line-size values in Galileo * host bridge. */ @@ -55,6 +72,13 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); /* + * The code described by the comment below has been removed + * as it causes bus mastering by the Ethernet controllers + * to break under any kind of network load. We always set + * the retry timeouts to their maximum. + * + * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x-- + * * On all machines prior to Q2, we had the STOP line disconnected * from Galileo to VIA on PCI. The new Galileo does not function * correctly unless we have it connected. @@ -64,21 +88,43 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev) */ pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id); galileo_id &= 0xff; /* mask off class info */ + + printk(KERN_INFO "Galileo: revision %u\n", galileo_id); + +#if 0 if (galileo_id >= 0x10) { /* New Galileo, assumes PCI stop line to VIA is connected. */ GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS); - } else if (galileo_id == 0x1 || galileo_id == 0x2) { + } else if (galileo_id == 0x1 || galileo_id == 0x2) +#endif + { signed int timeo; /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ timeo = GALILEO_INL(GT_PCI0_TOR_OFS); /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ - GALILEO_OUTL(0xffff, GT_PCI0_TOR_OFS); + GALILEO_OUTL( + (0xff << 16) | /* retry count */ + (0xff << 8) | /* timeout 1 */ + 0xff, /* timeout 0 */ + GT_PCI0_TOR_OFS); + + /* enable PCI retry exceeded interrupt */ + GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); } } -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GALILEO, PCI_ANY_ID, +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, qube_raq_galileo_fixup); +static char irq_tab_qube1[] __initdata = { + [COBALT_PCICONF_CPU] = 0, + [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ, + [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, + [COBALT_PCICONF_VIA] = 0, + [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, + [COBALT_PCICONF_ETH1] = 0 +}; + static char irq_tab_cobalt[] __initdata = { [COBALT_PCICONF_CPU] = 0, [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, @@ -99,6 +145,9 @@ static char irq_tab_raq2[] __initdata = { int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { + if (cobalt_board_id < COBALT_BRD_ID_QUBE2) + return irq_tab_qube1[slot]; + if (cobalt_board_id == COBALT_BRD_ID_RAQ2) return irq_tab_raq2[slot]; diff --git a/arch/mips/pci/fixup-pnx8550.c b/arch/mips/pci/fixup-pnx8550.c new file mode 100644 index 000000000000..4256b3b30b77 --- /dev/null +++ b/arch/mips/pci/fixup-pnx8550.c @@ -0,0 +1,57 @@ +/* + * Philips PNX8550 pci fixups. + * + * Copyright 2005 Embedded Alley Solutions, Inc + * source@embeddealley.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/init.h> + +#include <asm/mach-pnx8550/pci.h> +#include <asm/mach-pnx8550/int.h> + + +#undef DEBUG +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +extern char irq_tab_jbs[][5]; + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ + /* no need to fixup IO resources */ +} + +void __init pcibios_fixup(void) +{ + /* nothing to do here */ +} + +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + return irq_tab_jbs[slot][pin]; +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c new file mode 100644 index 000000000000..f455520ada88 --- /dev/null +++ b/arch/mips/pci/fixup-tx4938.c @@ -0,0 +1,92 @@ +/* + * Toshiba rbtx4938 pci routines + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/init.h> + +#include <asm/tx4938/rbtx4938.h> + +extern struct pci_controller tx4938_pci_controller[]; + +int pci_get_irq(struct pci_dev *dev, int pin) +{ + int irq = pin; + u8 slot = PCI_SLOT(dev->devfn); + struct pci_controller *controller = (struct pci_controller *)dev->sysdata; + + if (controller == &tx4938_pci_controller[1]) { + /* TX4938 PCIC1 */ + switch (slot) { + case TX4938_PCIC_IDSEL_AD_TO_SLOT(31): + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL) + return RBTX4938_IRQ_IRC + TX4938_IR_ETH0; + break; + case TX4938_PCIC_IDSEL_AD_TO_SLOT(30): + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL) + return RBTX4938_IRQ_IRC + TX4938_IR_ETH1; + break; + } + return 0; + } + + /* IRQ rotation */ + irq--; /* 0-3 */ + if (dev->bus->parent == NULL && + (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) { + /* PCI CardSlot (IDSEL=A23) */ + /* PCIA => PCIA (IDSEL=A23) */ + irq = (irq + 0 + slot) % 4; + } else { + /* PCI Backplane */ + irq = (irq + 33 - slot) % 4; + } + irq++; /* 1-4 */ + + switch (irq) { + case 1: + irq = RBTX4938_IRQ_IOC_PCIA; + break; + case 2: + irq = RBTX4938_IRQ_IOC_PCIB; + break; + case 3: + irq = RBTX4938_IRQ_IOC_PCIC; + break; + case 4: + irq = RBTX4938_IRQ_IOC_PCID; + break; + } + return irq; +} + +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + unsigned char irq = 0; + + irq = pci_get_irq(dev, pin); + + printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n", + dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn), irq); + + return irq; +} + +/* + * Do platform specific device initialization at pci_enable_device() time + */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c index c1c91ca0f9c2..be1420126c42 100644 --- a/arch/mips/pci/ops-au1000.c +++ b/arch/mips/pci/ops-au1000.c @@ -50,11 +50,6 @@ int (*board_pci_idsel)(unsigned int devsel, int assert); -/* CP0 hazard avoidance. */ -#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ - "nop; nop; nop; nop;\t" \ - ".set reorder\n\t") - void mod_wired_entry(int entry, unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask) @@ -66,16 +61,12 @@ void mod_wired_entry(int entry, unsigned long entrylo0, old_ctx = read_c0_entryhi() & 0xff; old_pagemask = read_c0_pagemask(); write_c0_index(entry); - BARRIER; write_c0_pagemask(pagemask); write_c0_entryhi(entryhi); write_c0_entrylo0(entrylo0); write_c0_entrylo1(entrylo1); - BARRIER; tlb_write_indexed(); - BARRIER; write_c0_entryhi(old_ctx); - BARRIER; write_c0_pagemask(old_pagemask); } @@ -128,9 +119,8 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, last_entryLo0 = last_entryLo1 = 0xffffffff; } - /* Since the Au1xxx doesn't do the idsel timing exactly to spec, - * many board vendors implement their own off-chip idsel, so call - * it now. If it doesn't succeed, may as well bail out at this point. + /* Allow board vendors to implement their own off-chip idsel. + * If it doesn't succeed, may as well bail out at this point. */ if (board_pci_idsel) { if (board_pci_idsel(device, 1) == 0) { diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c index 4b4e086a7eb1..dc35270b65a2 100644 --- a/arch/mips/pci/ops-bonito64.c +++ b/arch/mips/pci/ops-bonito64.c @@ -1,6 +1,8 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard <carstenl@mips.com> + * Maciej W. Rozycki <macro@mips.com> * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -17,7 +19,6 @@ * * MIPS boards specific PCI support. */ -#include <linux/config.h> #include <linux/types.h> #include <linux/pci.h> #include <linux/kernel.h> @@ -57,13 +58,6 @@ static int bonito64_pcibios_config_access(unsigned char access_type, return -1; } -#ifdef CONFIG_MIPS_BOARDS_GEN - if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) { - /* MIPS Core boards have Bonito connected as device 17 */ - return -1; - } -#endif - /* Clear cause register bits */ BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR | BONITO_PCICMD_MTABORT_CLR); diff --git a/arch/mips/pci/ops-gt64111.c b/arch/mips/pci/ops-gt64111.c index c5b0fc184c2a..c1807934768d 100644 --- a/arch/mips/pci/ops-gt64111.c +++ b/arch/mips/pci/ops-gt64111.c @@ -18,15 +18,15 @@ #include <asm/cobalt/cobalt.h> /* - * Accessing device 31 hangs the GT64120. Not sure if this will also hang - * the GT64111, let's be paranoid for now. + * Device 31 on the GT64111 is used to generate PCI special + * cycles, so we shouldn't expected to find a device there ... */ static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn) { - if (bus->number == 0 && devfn == PCI_DEVFN(31, 0)) - return -1; + if (bus->number == 0 && PCI_SLOT(devfn) < 31) + return 0; - return 0; + return -1; } static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn, diff --git a/arch/mips/pci/ops-gt64120.c b/arch/mips/pci/ops-gt64120.c index 7b99dfa33dfc..6335844d607a 100644 --- a/arch/mips/pci/ops-gt64120.c +++ b/arch/mips/pci/ops-gt64120.c @@ -1,6 +1,8 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard <carstenl@mips.com> + * Maciej W. Rozycki <macro@mips.com> * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -43,10 +45,6 @@ static int gt64120_pcibios_config_access(unsigned char access_type, unsigned char busnum = bus->number; u32 intr; - if ((busnum == 0) && (PCI_SLOT(devfn) == 0)) - /* Galileo itself is devfn 0, don't move it around */ - return -1; - if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0))) return -1; /* Because of a bug in the galileo (for slot 31). */ diff --git a/arch/mips/pci/ops-msc.c b/arch/mips/pci/ops-msc.c index 7bc099643a9d..5d9fbb0f4670 100644 --- a/arch/mips/pci/ops-msc.c +++ b/arch/mips/pci/ops-msc.c @@ -21,7 +21,6 @@ * MIPS boards specific PCI support. * */ -#include <linux/config.h> #include <linux/types.h> #include <linux/pci.h> #include <linux/kernel.h> @@ -49,34 +48,17 @@ static int msc_pcibios_config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, int where, u32 * data) { unsigned char busnum = bus->number; - unsigned char type; u32 intr; -#ifdef CONFIG_MIPS_BOARDS_GEN - if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) { - /* MIPS Core boards have SOCit connected as device 17 */ - return -1; - } -#endif - /* Clear status register bits. */ MSC_WRITE(MSC01_PCI_INTSTAT, (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)); - /* Setup address */ - if (busnum == 0) - type = 0; /* Type 0 */ - else - type = 1; /* Type 1 */ - MSC_WRITE(MSC01_PCI_CFGADDR, ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) | - (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) - | (PCI_FUNC(devfn) << - MSC01_PCI_CFGADDR_FNUM_SHF) | ((where / - 4) << - MSC01_PCI_CFGADDR_RNUM_SHF) - | (type))); + (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) | + (PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) | + ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF))); /* Perform access */ if (access_type == PCI_ACCESS_WRITE) @@ -86,15 +68,12 @@ static int msc_pcibios_config_access(unsigned char access_type, /* Detect Master/Target abort */ MSC_READ(MSC01_PCI_INTSTAT, intr); - if (intr & (MSC01_PCI_INTCFG_MA_BIT | - MSC01_PCI_INTCFG_TA_BIT)) { + if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) { /* Error occurred */ /* Clear bits */ - MSC_READ(MSC01_PCI_INTSTAT, intr); MSC_WRITE(MSC01_PCI_INTSTAT, - (MSC01_PCI_INTCFG_MA_BIT | - MSC01_PCI_INTCFG_TA_BIT)); + (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)); return -1; } diff --git a/arch/mips/pci/ops-nile4.c b/arch/mips/pci/ops-nile4.c index a7169928b351..a8d38dc8c504 100644 --- a/arch/mips/pci/ops-nile4.c +++ b/arch/mips/pci/ops-nile4.c @@ -15,7 +15,7 @@ volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE; -static spinlock_t nile4_pci_lock; +static DEFINE_SPINLOCK(nile4_pci_lock); static int nile4_pcibios_config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, int where, u32 * val) diff --git a/arch/mips/pci/ops-pnx8550.c b/arch/mips/pci/ops-pnx8550.c new file mode 100644 index 000000000000..454b65cc3354 --- /dev/null +++ b/arch/mips/pci/ops-pnx8550.c @@ -0,0 +1,284 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * + * 2.6 port, Embedded Alley Solutions, Inc + * + * Based on: + * Author: source@mvista.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/vmalloc.h> +#include <linux/delay.h> + +#include <asm/mach-pnx8550/pci.h> +#include <asm/mach-pnx8550/glb.h> +#include <asm/debug.h> + + +static inline void clear_status(void) +{ + unsigned long pci_stat; + + pci_stat = inl(PCI_BASE | PCI_GPPM_STATUS); + outl(pci_stat, PCI_BASE | PCI_GPPM_ICLR); +} + +static inline unsigned int +calc_cfg_addr(struct pci_bus *bus, unsigned int devfn, int where) +{ + unsigned int addr; + + addr = ((bus->number > 0) ? (((bus->number & 0xff) << PCI_CFG_BUS_SHIFT) | 1) : 0); + addr |= ((devfn & 0xff) << PCI_CFG_FUNC_SHIFT) | (where & 0xfc); + + return addr; +} + +static int +config_access(unsigned int pci_cmd, struct pci_bus *bus, unsigned int devfn, int where, unsigned int pci_mode, unsigned int *val) +{ + unsigned int flags; + unsigned long loops = 0; + unsigned long ioaddr = calc_cfg_addr(bus, devfn, where); + + local_irq_save(flags); + /*Clear pending interrupt status */ + if (inl(PCI_BASE | PCI_GPPM_STATUS)) { + clear_status(); + while (!(inl(PCI_BASE | PCI_GPPM_STATUS) == 0)) ; + } + + outl(ioaddr, PCI_BASE | PCI_GPPM_ADDR); + + if ((pci_cmd == PCI_CMD_IOW) || (pci_cmd == PCI_CMD_CONFIG_WRITE)) + outl(*val, PCI_BASE | PCI_GPPM_WDAT); + + outl(INIT_PCI_CYCLE | pci_cmd | (pci_mode & PCI_BYTE_ENABLE_MASK), + PCI_BASE | PCI_GPPM_CTRL); + + loops = + ((loops_per_jiffy * + PCI_IO_JIFFIES_TIMEOUT) >> (PCI_IO_JIFFIES_SHIFT)); + while (1) { + if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_DONE) { + if ((pci_cmd == PCI_CMD_IOR) || + (pci_cmd == PCI_CMD_CONFIG_READ)) + *val = inl(PCI_BASE | PCI_GPPM_RDAT); + clear_status(); + local_irq_restore(flags); + return PCIBIOS_SUCCESSFUL; + } else if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_R_MABORT) { + break; + } + + loops--; + if (loops == 0) { + printk("%s : Arbiter Locked.\n", __FUNCTION__); + } + } + + clear_status(); + if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_IOW)) { + printk("%s timeout (GPPM_CTRL=%X) ioaddr %lX pci_cmd %X\n", + __FUNCTION__, inl(PCI_BASE | PCI_GPPM_CTRL), ioaddr, + pci_cmd); + } + + if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_CONFIG_READ)) + *val = 0xffffffff; + local_irq_restore(flags); + return PCIBIOS_DEVICE_NOT_FOUND; +} + +/* + * We can't address 8 and 16 bit words directly. Instead we have to + * read/write a 32bit word and mask/modify the data we actually want. + */ +static int +read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val) +{ + unsigned int data = 0; + int err; + + if (bus == 0) + return -1; + + err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data); + switch (where & 0x03) { + case 0: + *val = (unsigned char)(data & 0x000000ff); + break; + case 1: + *val = (unsigned char)((data & 0x0000ff00) >> 8); + break; + case 2: + *val = (unsigned char)((data & 0x00ff0000) >> 16); + break; + case 3: + *val = (unsigned char)((data & 0xff000000) >> 24); + break; + } + + return err; +} + +static int +read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val) +{ + unsigned int data = 0; + int err; + + if (bus == 0) + return -1; + + if (where & 0x01) + return PCIBIOS_BAD_REGISTER_NUMBER; + + err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(3 << (where & 3)), &data); + switch (where & 0x02) { + case 0: + *val = (unsigned short)(data & 0x0000ffff); + break; + case 2: + *val = (unsigned short)((data & 0xffff0000) >> 16); + break; + } + + return err; +} + +static int +read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val) +{ + int err; + if (bus == 0) + return -1; + + if (where & 0x03) + return PCIBIOS_BAD_REGISTER_NUMBER; + + err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, 0, val); + + return err; +} + +static int +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val) +{ + unsigned int data = (unsigned int)val; + int err; + + if (bus == 0) + return -1; + + switch (where & 0x03) { + case 1: + data = (data << 8); + break; + case 2: + data = (data << 16); + break; + case 3: + data = (data << 24); + break; + default: + break; + } + + err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data); + + return err; +} + +static int +write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val) +{ + unsigned int data = (unsigned int)val; + int err; + + if (bus == 0) + return -1; + + if (where & 0x01) + return PCIBIOS_BAD_REGISTER_NUMBER; + + switch (where & 0x02) { + case 2: + data = (data << 16); + break; + default: + break; + } + err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, ~(3 << (where & 3)), &data); + + return err; +} + +static int +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val) +{ + int err; + if (bus == 0) + return -1; + + if (where & 0x03) + return PCIBIOS_BAD_REGISTER_NUMBER; + + err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, 0, &val); + + return err; +} + +static int config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val) +{ + switch (size) { + case 1: { + u8 _val; + int rc = read_config_byte(bus, devfn, where, &_val); + *val = _val; + return rc; + } + case 2: { + u16 _val; + int rc = read_config_word(bus, devfn, where, &_val); + *val = _val; + return rc; + } + default: + return read_config_dword(bus, devfn, where, val); + } +} + +static int config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) +{ + switch (size) { + case 1: + return write_config_byte(bus, devfn, where, (u8) val); + case 2: + return write_config_word(bus, devfn, where, (u16) val); + default: + return write_config_dword(bus, devfn, where, val); + } +} + +struct pci_ops pnx8550_pci_ops = { + config_read, + config_write +}; diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c new file mode 100644 index 000000000000..4c0dcfce5297 --- /dev/null +++ b/arch/mips/pci/ops-tx4938.c @@ -0,0 +1,198 @@ +/* + * Define the pci_ops for the Toshiba rbtx4938 + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/init.h> + +#include <asm/addrspace.h> +#include <asm/tx4938/rbtx4938.h> + +/* initialize in setup */ +struct resource pci_io_resource = { + .name = "pci IO space", + .start = 0, + .end = 0, + .flags = IORESOURCE_IO +}; + +/* initialize in setup */ +struct resource pci_mem_resource = { + .name = "pci memory space", + .start = 0, + .end = 0, + .flags = IORESOURCE_MEM +}; + +struct resource tx4938_pcic1_pci_io_resource = { + .name = "PCI1 IO", + .start = 0, + .end = 0, + .flags = IORESOURCE_IO +}; +struct resource tx4938_pcic1_pci_mem_resource = { + .name = "PCI1 mem", + .start = 0, + .end = 0, + .flags = IORESOURCE_MEM +}; + +static int mkaddr(int bus, int dev_fn, int where, int *flagsp) +{ + if (bus > 0) { + /* Type 1 configuration */ + tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | + ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1; + } else { + if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0)) + return -1; + + /* Type 0 configuration */ + tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | + ((dev_fn & 0xff) << 0x08) | (where & 0xfc); + } + /* clear M_ABORT and Disable M_ABORT Int. */ + tx4938_pcicptr->pcistatus = + (tx4938_pcicptr->pcistatus & 0x0000ffff) | + (PCI_STATUS_REC_MASTER_ABORT << 16); + tx4938_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT; + + return 0; +} + +static int check_abort(int flags) +{ + int code = PCIBIOS_SUCCESSFUL; + /* wait write cycle completion before checking error status */ + while (tx4938_pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB) + ; + if (tx4938_pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { + tx4938_pcicptr->pcistatus = + (tx4938_pcicptr-> + pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT + << 16); + tx4938_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; + code = PCIBIOS_DEVICE_NOT_FOUND; + } + return code; +} + +static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) +{ + int flags, retval, dev, busno, func; + + dev = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + + /* check if the bus is top-level */ + if (bus->parent != NULL) + busno = bus->number; + else { + busno = 0; + } + + if (mkaddr(busno, devfn, where, &flags)) + return -1; + + switch (size) { + case 1: + *val = *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | +#ifdef __BIG_ENDIAN + ((where & 3) ^ 3)); +#else + (where & 3)); +#endif + break; + case 2: + *val = *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | +#ifdef __BIG_ENDIAN + ((where & 3) ^ 2)); +#else + (where & 3)); +#endif + break; + case 4: + *val = tx4938_pcicptr->g2pcfgdata; + break; + } + + retval = check_abort(flags); + if (retval == PCIBIOS_DEVICE_NOT_FOUND) + *val = 0xffffffff; + + return retval; +} + +static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 val) +{ + int flags, dev, busno, func; + + busno = bus->number; + dev = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + + /* check if the bus is top-level */ + if (bus->parent != NULL) { + busno = bus->number; + } else { + busno = 0; + } + + if (mkaddr(busno, devfn, where, &flags)) + return -1; + + switch (size) { + case 1: + *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | +#ifdef __BIG_ENDIAN + ((where & 3) ^ 3)) = val; +#else + (where & 3)) = val; +#endif + break; + case 2: + *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | +#ifdef __BIG_ENDIAN + ((where & 0x3) ^ 0x2)) = val; +#else + (where & 3)) = val; +#endif + break; + case 4: + tx4938_pcicptr->g2pcfgdata = val; + break; + } + + return check_abort(flags); +} + +struct pci_ops tx4938_pci_ops = { + tx4938_pcibios_read_config, + tx4938_pcibios_write_config +}; + +struct pci_controller tx4938_pci_controller[] = { + /* h/w only supports devices 0x00 to 0x14 */ + { + .pci_ops = &tx4938_pci_ops, + .io_resource = &pci_io_resource, + .mem_resource = &pci_mem_resource, + }, + /* h/w only supports devices 0x00 to 0x14 */ + { + .pci_ops = &tx4938_pci_ops, + .io_resource = &tx4938_pcic1_pci_io_resource, + .mem_resource = &tx4938_pcic1_pci_mem_resource, + } +}; diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c new file mode 100644 index 000000000000..f194b4e4f86a --- /dev/null +++ b/arch/mips/pci/pci-bcm1480.c @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2001,2002,2005 Broadcom Corporation + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * BCM1x80/1x55-specific PCI support + * + * This module provides the glue between Linux's PCI subsystem + * and the hardware. We basically provide glue for accessing + * configuration space, and set up the translation for I/O + * space accesses. + * + * To access configuration space, we use ioremap. In the 32-bit + * kernel, this consumes either 4 or 8 page table pages, and 16MB of + * kernel mapped memory. Hopefully neither of these should be a huge + * problem. + * + * XXX: AT THIS TIME, ONLY the NATIVE PCI-X INTERFACE IS SUPPORTED. + */ +#include <linux/config.h> +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/console.h> +#include <linux/tty.h> + +#include <asm/sibyte/bcm1480_regs.h> +#include <asm/sibyte/bcm1480_scd.h> +#include <asm/sibyte/board.h> +#include <asm/io.h> + +/* + * Macros for calculating offsets into config space given a device + * structure or dev/fun/reg + */ +#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where)) +#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) + +static void *cfg_space; + +#define PCI_BUS_ENABLED 1 +#define PCI_DEVICE_MODE 2 + +static int bcm1480_bus_status = 0; + +#define PCI_BRIDGE_DEVICE 0 + +/* + * Read/write 32-bit values in config space. + */ +static inline u32 READCFG32(u32 addr) +{ + return *(u32 *)(cfg_space + (addr&~3)); +} + +static inline void WRITECFG32(u32 addr, u32 data) +{ + *(u32 *)(cfg_space + (addr & ~3)) = data; +} + +int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + return dev->irq; +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +/* + * Some checks before doing config cycles: + * In PCI Device Mode, hide everything on bus 0 except the LDT host + * bridge. Otherwise, access is controlled by bridge MasterEn bits. + */ +static int bcm1480_pci_can_access(struct pci_bus *bus, int devfn) +{ + u32 devno; + + if (!(bcm1480_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE))) + return 0; + + if (bus->number == 0) { + devno = PCI_SLOT(devfn); + if (bcm1480_bus_status & PCI_DEVICE_MODE) + return 0; + else + return 1; + } else + return 1; +} + +/* + * Read/write access functions for various sizes of values + * in config space. Return all 1's for disallowed accesses + * for a kludgy but adequate simulation of master aborts. + */ + +static int bcm1480_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) +{ + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (bcm1480_pci_can_access(bus, devfn)) + data = READCFG32(CFGADDR(bus, devfn, where)); + else + data = 0xFFFFFFFF; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + +static int bcm1480_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 cfgaddr = CFGADDR(bus, devfn, where); + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (!bcm1480_pci_can_access(bus, devfn)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + data = READCFG32(cfgaddr); + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else + data = val; + + WRITECFG32(cfgaddr, data); + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops bcm1480_pci_ops = { + bcm1480_pcibios_read, + bcm1480_pcibios_write, +}; + +static struct resource bcm1480_mem_resource = { + .name = "BCM1480 PCI MEM", + .start = 0x30000000UL, + .end = 0x3fffffffUL, + .flags = IORESOURCE_MEM, +}; + +static struct resource bcm1480_io_resource = { + .name = "BCM1480 PCI I/O", + .start = 0x2c000000UL, + .end = 0x2dffffffUL, + .flags = IORESOURCE_IO, +}; + +struct pci_controller bcm1480_controller = { + .pci_ops = &bcm1480_pci_ops, + .mem_resource = &bcm1480_mem_resource, + .io_resource = &bcm1480_io_resource, +}; + + +static int __init bcm1480_pcibios_init(void) +{ + uint32_t cmdreg; + uint64_t reg; + extern int pci_probe_only; + + /* CFE will assign PCI resources */ + pci_probe_only = 1; + + /* Avoid ISA compat ranges. */ + PCIBIOS_MIN_IO = 0x00008000UL; + PCIBIOS_MIN_MEM = 0x01000000UL; + + /* Set I/O resource limits. - unlimited for now to accomodate HT */ + ioport_resource.end = 0xffffffffUL; + iomem_resource.end = 0xffffffffUL; + + cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 16*1024*1024); + + /* + * See if the PCI bus has been configured by the firmware. + */ + reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG)); + if (!(reg & M_BCM1480_SYS_PCI_HOST)) { + bcm1480_bus_status |= PCI_DEVICE_MODE; + } else { + cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), + PCI_COMMAND)); + if (!(cmdreg & PCI_COMMAND_MASTER)) { + printk + ("PCI: Skipping PCI probe. Bus is not initialized.\n"); + iounmap(cfg_space); + return 1; /* XXX */ + } + bcm1480_bus_status |= PCI_BUS_ENABLED; + } + + /* turn on ExpMemEn */ + cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40)); + printk("PCIFeatureCtrl = %x\n", cmdreg); + WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40), + cmdreg | 0x10); + cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40)); + printk("PCIFeatureCtrl = %x\n", cmdreg); + + /* + * Establish mappings in KSEG2 (kernel virtual) to PCI I/O + * space. Use "match bytes" policy to make everything look + * little-endian. So, you need to also set + * CONFIG_SWAP_IO_SPACE, but this is the combination that + * works correctly with most of Linux's drivers. + * XXX ehs: Should this happen in PCI Device mode? + */ + + set_io_port_base((unsigned long) + ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536)); + isa_slot_offset = (unsigned long) + ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024); + + register_pci_controller(&bcm1480_controller); + +#ifdef CONFIG_VGA_CONSOLE + take_over_console(&vga_con,0,MAX_NR_CONSOLES-1,1); +#endif + return 0; +} + +arch_initcall(bcm1480_pcibios_init); diff --git a/arch/mips/pci/pci-bcm1480ht.c b/arch/mips/pci/pci-bcm1480ht.c new file mode 100644 index 000000000000..aca4a2e7a1c6 --- /dev/null +++ b/arch/mips/pci/pci-bcm1480ht.c @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2001,2002,2005 Broadcom Corporation + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * BCM1480/1455-specific HT support (looking like PCI) + * + * This module provides the glue between Linux's PCI subsystem + * and the hardware. We basically provide glue for accessing + * configuration space, and set up the translation for I/O + * space accesses. + * + * To access configuration space, we use ioremap. In the 32-bit + * kernel, this consumes either 4 or 8 page table pages, and 16MB of + * kernel mapped memory. Hopefully neither of these should be a huge + * problem. + * + */ +#include <linux/config.h> +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/console.h> +#include <linux/tty.h> + +#include <asm/sibyte/bcm1480_regs.h> +#include <asm/sibyte/bcm1480_scd.h> +#include <asm/sibyte/board.h> +#include <asm/io.h> + +/* + * Macros for calculating offsets into config space given a device + * structure or dev/fun/reg + */ +#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where)) +#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) + +static void *ht_cfg_space; + +#define PCI_BUS_ENABLED 1 +#define PCI_DEVICE_MODE 2 + +static int bcm1480ht_bus_status = 0; + +#define PCI_BRIDGE_DEVICE 0 +#define HT_BRIDGE_DEVICE 1 + +/* + * HT's level-sensitive interrupts require EOI, which is generated + * through a 4MB memory-mapped region + */ +unsigned long ht_eoi_space; + +/* + * Read/write 32-bit values in config space. + */ +static inline u32 READCFG32(u32 addr) +{ + return *(u32 *)(ht_cfg_space + (addr&~3)); +} + +static inline void WRITECFG32(u32 addr, u32 data) +{ + *(u32 *)(ht_cfg_space + (addr & ~3)) = data; +} + +/* + * Some checks before doing config cycles: + * In PCI Device Mode, hide everything on bus 0 except the LDT host + * bridge. Otherwise, access is controlled by bridge MasterEn bits. + */ +static int bcm1480ht_can_access(struct pci_bus *bus, int devfn) +{ + u32 devno; + + if (!(bcm1480ht_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE))) + return 0; + + if (bus->number == 0) { + devno = PCI_SLOT(devfn); + if (bcm1480ht_bus_status & PCI_DEVICE_MODE) + return 0; + } + return 1; +} + +/* + * Read/write access functions for various sizes of values + * in config space. Return all 1's for disallowed accesses + * for a kludgy but adequate simulation of master aborts. + */ + +static int bcm1480ht_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) +{ + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (bcm1480ht_can_access(bus, devfn)) + data = READCFG32(CFGADDR(bus, devfn, where)); + else + data = 0xFFFFFFFF; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + +static int bcm1480ht_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 cfgaddr = CFGADDR(bus, devfn, where); + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (!bcm1480ht_can_access(bus, devfn)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + data = READCFG32(cfgaddr); + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else + data = val; + + WRITECFG32(cfgaddr, data); + + return PCIBIOS_SUCCESSFUL; +} + +static int bcm1480ht_pcibios_get_busno(void) +{ + return 0; +} + +struct pci_ops bcm1480ht_pci_ops = { + .read = bcm1480ht_pcibios_read, + .write = bcm1480ht_pcibios_write, +}; + +static struct resource bcm1480ht_mem_resource = { + .name = "BCM1480 HT MEM", + .start = 0x40000000UL, + .end = 0x5fffffffUL, + .flags = IORESOURCE_MEM, +}; + +static struct resource bcm1480ht_io_resource = { + .name = "BCM1480 HT I/O", + .start = 0x00000000UL, + .end = 0x01ffffffUL, + .flags = IORESOURCE_IO, +}; + +struct pci_controller bcm1480ht_controller = { + .pci_ops = &bcm1480ht_pci_ops, + .mem_resource = &bcm1480ht_mem_resource, + .io_resource = &bcm1480ht_io_resource, + .index = 1, + .get_busno = bcm1480ht_pcibios_get_busno, +}; + +static int __init bcm1480ht_pcibios_init(void) +{ + uint32_t cmdreg; + + ht_cfg_space = ioremap(A_BCM1480_PHYS_HT_CFG_MATCH_BITS, 16*1024*1024); + + /* + * See if the PCI bus has been configured by the firmware. + */ + cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), + PCI_COMMAND)); + if (!(cmdreg & PCI_COMMAND_MASTER)) { + printk("HT: Skipping HT probe. Bus is not initialized.\n"); + iounmap(ht_cfg_space); + return 1; /* XXX */ + } + bcm1480ht_bus_status |= PCI_BUS_ENABLED; + + ht_eoi_space = (unsigned long) + ioremap(A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES, + 4 * 1024 * 1024); + + register_pci_controller(&bcm1480ht_controller); + + return 0; +} + +arch_initcall(bcm1480ht_pcibios_init); diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index 068e0e508e15..efc96ce99eeb 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -485,5 +485,12 @@ static void __init pci_fixup_ioc3(struct pci_dev *d) pci_disable_swapping(d); } +int pcibus_to_node(struct pci_bus *bus) +{ + struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); + + return bc->nasid; +} + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, pci_fixup_ioc3); diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c index 000dc6af6cd3..180af89bcb1e 100644 --- a/arch/mips/pci/pci-ip32.c +++ b/arch/mips/pci/pci-ip32.c @@ -136,7 +136,9 @@ static int __init mace_init(void) BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0, "MACE PCI error", NULL)); - ioport_resource.end = mace_pci_io_resource.end; + iomem_resource = mace_pci_mem_resource; + ioport_resource = mace_pci_io_resource; + register_pci_controller(&mace_pci_controller); return 0; diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c index ae3cc4b254b5..88fb191ad2eb 100644 --- a/arch/mips/pci/pci-lasat.c +++ b/arch/mips/pci/pci-lasat.c @@ -7,12 +7,8 @@ */ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/interrupt.h> #include <linux/pci.h> #include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/pci.h> -#include <linux/delay.h> #include <asm/bootinfo.h> extern struct pci_ops nile4_pci_ops; @@ -20,14 +16,14 @@ extern struct pci_ops gt64120_pci_ops; static struct resource lasat_pci_mem_resource = { .name = "LASAT PCI MEM", .start = 0x18000000, - .end = 0x19FFFFFF, + .end = 0x19ffffff, .flags = IORESOURCE_MEM, }; static struct resource lasat_pci_io_resource = { .name = "LASAT PCI IO", .start = 0x1a000000, - .end = 0x1bFFFFFF, + .end = 0x1bffffff, .flags = IORESOURCE_IO, }; @@ -38,23 +34,25 @@ static struct pci_controller lasat_pci_controller = { static int __init lasat_pci_setup(void) { - printk("PCI: starting\n"); + printk("PCI: starting\n"); - switch (mips_machtype) { - case MACH_LASAT_100: + switch (mips_machtype) { + case MACH_LASAT_100: lasat_pci_controller.pci_ops = >64120_pci_ops; break; - case MACH_LASAT_200: + case MACH_LASAT_200: lasat_pci_controller.pci_ops = &nile4_pci_ops; break; - default: + default: panic("pcibios_init: mips_machtype incorrect"); } register_pci_controller(&lasat_pci_controller); - return 0; + + return 0; } -early_initcall(lasat_pci_setup); + +arch_initcall(lasat_pci_setup); #define LASATINT_ETH1 0 #define LASATINT_ETH0 1 @@ -68,24 +66,22 @@ early_initcall(lasat_pci_setup); int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - switch (slot) { - case 1: - return LASATINT_PCIA; /* Expansion Module 0 */ - case 2: - return LASATINT_PCIB; /* Expansion Module 1 */ - case 3: - return LASATINT_PCIC; /* Expansion Module 2 */ - case 4: - return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */ - case 5: - return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */ - case 6: - return LASATINT_HDC; /* IDE controller */ - default: - return 0xff; /* Illegal */ - } + switch (slot) { + case 1: + case 2: + case 3: + return LASATINT_PCIA + (((slot-1) + (pin-1)) % 4); + case 4: + return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */ + case 5: + return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */ + case 6: + return LASATINT_HDC; /* IDE controller */ + default: + return 0xff; /* Illegal */ + } - return -1; + return -1; } /* Do platform specific device initialization at pci_enable_device() time */ diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index a8d499b0a36f..21402ffd7c98 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -127,15 +127,20 @@ static int __init pcibios_init(void) if (!hose->iommu) PCI_DMA_BUS_IS_PHYS = 1; + if (hose->get_busno && pci_probe_only) + next_busno = (*hose->get_busno)(); + bus = pci_scan_bus(next_busno, hose->pci_ops, hose); hose->bus = bus; hose->need_domain_info = need_domain_info; - next_busno = bus->subordinate + 1; - /* Don't allow 8-bit bus number overflow inside the hose - - reserve some space for bridges. */ - if (next_busno > 224) { - next_busno = 0; - need_domain_info = 1; + if (bus) { + next_busno = bus->subordinate + 1; + /* Don't allow 8-bit bus number overflow inside the hose - + reserve some space for bridges. */ + if (next_busno > 224) { + next_busno = 0; + need_domain_info = 1; + } } continue; @@ -164,7 +169,7 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask) pci_read_config_word(dev, PCI_COMMAND, &cmd); old_cmd = cmd; - for(idx=0; idx<6; idx++) { + for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { /* Only set up the requested stuff */ if (!(mask & (1<<idx))) continue; diff --git a/arch/mips/philips/pnx8550/common/Kconfig b/arch/mips/philips/pnx8550/common/Kconfig new file mode 100644 index 000000000000..072572d173cc --- /dev/null +++ b/arch/mips/philips/pnx8550/common/Kconfig @@ -0,0 +1 @@ +# Place holder diff --git a/arch/mips/philips/pnx8550/common/Makefile b/arch/mips/philips/pnx8550/common/Makefile new file mode 100644 index 000000000000..6e38f3bc443c --- /dev/null +++ b/arch/mips/philips/pnx8550/common/Makefile @@ -0,0 +1,27 @@ +# +# Per Hallsmark, per.hallsmark@mvista.com +# +# ######################################################################## +# +# This program is free software; you can distribute it and/or modify it +# under the terms of the GNU General Public License (Version 2) as +# published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. +# +# ####################################################################### +# +# Makefile for the PNX8550 specific kernel interface routines +# under Linux. +# + +obj-y := setup.o prom.o mipsIRQ.o int.o reset.o time.o proc.o platform.o +obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_KGDB) += gdb_hook.o diff --git a/arch/mips/philips/pnx8550/common/gdb_hook.c b/arch/mips/philips/pnx8550/common/gdb_hook.c new file mode 100644 index 000000000000..ad4624f6d9bc --- /dev/null +++ b/arch/mips/philips/pnx8550/common/gdb_hook.c @@ -0,0 +1,109 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * This is the interface to the remote debugger stub. + * + */ +#include <linux/types.h> +#include <linux/serial.h> +#include <linux/serialP.h> +#include <linux/serial_reg.h> +#include <linux/serial_ip3106.h> + +#include <asm/serial.h> +#include <asm/io.h> + +#include <uart.h> + +static struct serial_state rs_table[IP3106_NR_PORTS] = { +}; +static struct async_struct kdb_port_info = {0}; + +void rs_kgdb_hook(int tty_no) +{ + struct serial_state *ser = &rs_table[tty_no]; + + kdb_port_info.state = ser; + kdb_port_info.magic = SERIAL_MAGIC; + kdb_port_info.port = tty_no; + kdb_port_info.flags = ser->flags; + + /* + * Clear all interrupts + */ + /* Clear all the transmitter FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_TX_RST; + /* Clear all the receiver FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_RX_RST; + /* Clear all interrupts */ + ip3106_iclr(UART_BASE, tty_no) = IP3106_UART_INT_ALLRX | + IP3106_UART_INT_ALLTX; + + /* + * Now, initialize the UART + */ + ip3106_lcr(UART_BASE, tty_no) = IP3106_UART_LCR_8BIT; + ip3106_baud(UART_BASE, tty_no) = 5; // 38400 Baud +} + +int putDebugChar(char c) +{ + /* Wait until FIFO not full */ + while (((ip3106_fifo(UART_BASE, kdb_port_info.port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16) + ; + /* Send one char */ + ip3106_fifo(UART_BASE, kdb_port_info.port) = c; + + return 1; +} + +char getDebugChar(void) +{ + char ch; + + /* Wait until there is a char in the FIFO */ + while (!((ip3106_fifo(UART_BASE, kdb_port_info.port) & + IP3106_UART_FIFO_RXFIFO) >> 8)) + ; + /* Read one char */ + ch = ip3106_fifo(UART_BASE, kdb_port_info.port) & + IP3106_UART_FIFO_RBRTHR; + /* Advance the RX FIFO read pointer */ + ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_NEXT; + return (ch); +} + +void rs_disable_debug_interrupts(void) +{ + ip3106_ien(UART_BASE, kdb_port_info.port) = 0; /* Disable all interrupts */ +} + +void rs_enable_debug_interrupts(void) +{ + /* Clear all the transmitter FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_TX_RST; + /* Clear all the receiver FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_RST; + /* Clear all interrupts */ + ip3106_iclr(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX | + IP3106_UART_INT_ALLTX; + ip3106_ien(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX; /* Enable RX interrupts */ +} diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c new file mode 100644 index 000000000000..546144988bf5 --- /dev/null +++ b/arch/mips/philips/pnx8550/common/int.c @@ -0,0 +1,293 @@ +/* + * + * Copyright (C) 2005 Embedded Alley Solutions, Inc + * Ported to 2.6. + * + * Per Hallsmark, per.hallsmark@mvista.com + * Copyright (C) 2000, 2001 MIPS Technologies, Inc. + * Copyright (C) 2001 Ralf Baechle + * + * Cleaned up and bug fixing: Pete Popov, ppopov@embeddedalley.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include <linux/config.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/interrupt.h> +#include <linux/kernel_stat.h> +#include <linux/random.h> +#include <linux/module.h> + +#include <asm/io.h> +#include <asm/gdb-stub.h> +#include <int.h> +#include <uart.h> + +extern asmlinkage void cp0_irqdispatch(void); + +static DEFINE_SPINLOCK(irq_lock); + +/* default prio for interrupts */ +/* first one is a no-no so therefore always prio 0 (disabled) */ +static char gic_prio[PNX8550_INT_GIC_TOTINT] = { + 0, 1, 1, 1, 1, 15, 1, 1, 1, 1, // 0 - 9 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 10 - 19 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 20 - 29 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 30 - 39 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 40 - 49 + 1, 1, 1, 1, 1, 1, 1, 1, 2, 1, // 50 - 59 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 60 - 69 + 1 // 70 +}; + +void hw0_irqdispatch(int irq, struct pt_regs *regs) +{ + /* find out which interrupt */ + irq = PNX8550_GIC_VECTOR_0 >> 3; + + if (irq == 0) { + printk("hw0_irqdispatch: irq 0, spurious interrupt?\n"); + return; + } + do_IRQ(PNX8550_INT_GIC_MIN + irq, regs); +} + + +void timer_irqdispatch(int irq, struct pt_regs *regs) +{ + irq = (0x01c0 & read_c0_config7()) >> 6; + + if (irq == 0) { + printk("timer_irqdispatch: irq 0, spurious interrupt?\n"); + return; + } + + if (irq & 0x1) { + do_IRQ(PNX8550_INT_TIMER1, regs); + } + if (irq & 0x2) { + do_IRQ(PNX8550_INT_TIMER2, regs); + } + if (irq & 0x4) { + do_IRQ(PNX8550_INT_TIMER3, regs); + } +} + +static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask) +{ + unsigned long status = read_c0_status(); + + status &= ~((clr_mask & 0xFF) << 8); + status |= (set_mask & 0xFF) << 8; + + write_c0_status(status); +} + +static inline void mask_gic_int(unsigned int irq_nr) +{ + /* interrupt disabled, bit 26(WE_ENABLE)=1 and bit 16(enable)=0 */ + PNX8550_GIC_REQ(irq_nr) = 1<<28; /* set priority to 0 */ +} + +static inline void unmask_gic_int(unsigned int irq_nr) +{ + /* set prio mask to lower four bits and enable interrupt */ + PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr]; +} + +static inline void mask_irq(unsigned int irq_nr) +{ + if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { + modify_cp0_intmask(1 << irq_nr, 0); + } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && + (irq_nr <= PNX8550_INT_GIC_MAX)) { + mask_gic_int(irq_nr - PNX8550_INT_GIC_MIN); + } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) && + (irq_nr <= PNX8550_INT_TIMER_MAX)) { + modify_cp0_intmask(1 << 7, 0); + } else { + printk("mask_irq: irq %d doesn't exist!\n", irq_nr); + } +} + +static inline void unmask_irq(unsigned int irq_nr) +{ + if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { + modify_cp0_intmask(0, 1 << irq_nr); + } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && + (irq_nr <= PNX8550_INT_GIC_MAX)) { + unmask_gic_int(irq_nr - PNX8550_INT_GIC_MIN); + } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) && + (irq_nr <= PNX8550_INT_TIMER_MAX)) { + modify_cp0_intmask(0, 1 << 7); + } else { + printk("mask_irq: irq %d doesn't exist!\n", irq_nr); + } +} + +#define pnx8550_disable pnx8550_ack +static void pnx8550_ack(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&irq_lock, flags); + mask_irq(irq); + spin_unlock_irqrestore(&irq_lock, flags); +} + +#define pnx8550_enable pnx8550_unmask +static void pnx8550_unmask(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&irq_lock, flags); + unmask_irq(irq); + spin_unlock_irqrestore(&irq_lock, flags); +} + +static unsigned int startup_irq(unsigned int irq_nr) +{ + pnx8550_unmask(irq_nr); + return 0; +} + +static void shutdown_irq(unsigned int irq_nr) +{ + pnx8550_ack(irq_nr); + return; +} + +int pnx8550_set_gic_priority(int irq, int priority) +{ + int gic_irq = irq-PNX8550_INT_GIC_MIN; + int prev_priority = PNX8550_GIC_REQ(gic_irq) & 0xf; + + gic_prio[gic_irq] = priority; + PNX8550_GIC_REQ(gic_irq) |= (0x10000000 | gic_prio[gic_irq]); + + return prev_priority; +} + +static inline void mask_and_ack_level_irq(unsigned int irq) +{ + pnx8550_disable(irq); + return; +} + +static void end_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { + pnx8550_enable(irq); + } +} + +static struct hw_interrupt_type level_irq_type = { + .typename = "PNX Level IRQ", + .startup = startup_irq, + .shutdown = shutdown_irq, + .enable = pnx8550_enable, + .disable = pnx8550_disable, + .ack = mask_and_ack_level_irq, + .end = end_irq, +}; + +static struct irqaction gic_action = { + .handler = no_action, + .flags = SA_INTERRUPT, + .name = "GIC", +}; + +static struct irqaction timer_action = { + .handler = no_action, + .flags = SA_INTERRUPT, + .name = "Timer", +}; + +void __init arch_init_irq(void) +{ + int i; + int configPR; + + /* init of cp0 interrupts */ + set_except_vector(0, cp0_irqdispatch); + + for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { + irq_desc[i].handler = &level_irq_type; + pnx8550_ack(i); /* mask the irq just in case */ + } + + /* init of GIC/IPC interrupts */ + /* should be done before cp0 since cp0 init enables the GIC int */ + for (i = PNX8550_INT_GIC_MIN; i <= PNX8550_INT_GIC_MAX; i++) { + int gic_int_line = i - PNX8550_INT_GIC_MIN; + if (gic_int_line == 0 ) + continue; // don't fiddle with int 0 + /* + * enable change of TARGET, ENABLE and ACTIVE_LOW bits + * set TARGET 0 to route through hw0 interrupt + * set ACTIVE_LOW 0 active high (correct?) + * + * We really should setup an interrupt description table + * to do this nicely. + * Note, PCI INTA is active low on the bus, but inverted + * in the GIC, so to us it's active high. + */ +#ifdef CONFIG_PNX8550_V2PCI + if (gic_int_line == (PNX8550_INT_GPIO0 - PNX8550_INT_GIC_MIN)) { + /* PCI INT through gpio 8, which is setup in + * pnx8550_setup.c and routed to GPIO + * Interrupt Level 0 (GPIO Connection 58). + * Set it active low. */ + + PNX8550_GIC_REQ(gic_int_line) = 0x1E020000; + } else +#endif + { + PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000; + } + + /* mask/priority is still 0 so we will not get any + * interrupts until it is unmasked */ + + irq_desc[i].handler = &level_irq_type; + } + + /* Priority level 0 */ + PNX8550_GIC_PRIMASK_0 = PNX8550_GIC_PRIMASK_1 = 0; + + /* Set int vector table address */ + PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; + + irq_desc[MIPS_CPU_GIC_IRQ].handler = &level_irq_type; + setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); + + /* init of Timer interrupts */ + for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) { + irq_desc[i].handler = &level_irq_type; + } + + /* Stop Timer 1-3 */ + configPR = read_c0_config7(); + configPR |= 0x00000038; + write_c0_config7(configPR); + + irq_desc[MIPS_CPU_TIMER_IRQ].handler = &level_irq_type; + setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); +} + +EXPORT_SYMBOL(pnx8550_set_gic_priority); diff --git a/arch/mips/philips/pnx8550/common/mipsIRQ.S b/arch/mips/philips/pnx8550/common/mipsIRQ.S new file mode 100644 index 000000000000..338bffda3fab --- /dev/null +++ b/arch/mips/philips/pnx8550/common/mipsIRQ.S @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2002 Philips, Inc. All rights. + * Copyright (c) 2002 Red Hat, Inc. All rights. + * + * This software may be freely redistributed under the terms of the + * GNU General Public License. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Based upon arch/mips/galileo-boards/ev64240/int-handler.S + * + */ +#include <asm/asm.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/regdef.h> +#include <asm/stackframe.h> + +/* + * cp0_irqdispatch + * + * Code to handle in-core interrupt exception. + */ + + .align 5 + .set reorder + .set noat + NESTED(cp0_irqdispatch, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + mfc0 t0,CP0_CAUSE + mfc0 t2,CP0_STATUS + + and t0,t2 + + andi t1,t0,STATUSF_IP2 /* int0 hardware line */ + bnez t1,ll_hw0_irq + nop + + andi t1,t0,STATUSF_IP7 /* int5 hardware line */ + bnez t1,ll_timer_irq + nop + + /* wrong alarm or masked ... */ + + j spurious_interrupt + nop + END(cp0_irqdispatch) + + .align 5 + .set reorder +ll_hw0_irq: + li a0,2 + move a1,sp + jal hw0_irqdispatch + nop + j ret_from_irq + nop + + .align 5 + .set reorder +ll_timer_irq: + mfc0 t3,CP0_CONFIG,7 + andi t4,t3,0x01c0 + beqz t4,ll_timer_out + nop + li a0,7 + move a1,sp + jal timer_irqdispatch + nop + +ll_timer_out: j ret_from_irq + nop diff --git a/arch/mips/philips/pnx8550/common/pci.c b/arch/mips/philips/pnx8550/common/pci.c new file mode 100644 index 000000000000..baa6905f649f --- /dev/null +++ b/arch/mips/philips/pnx8550/common/pci.c @@ -0,0 +1,133 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * + * Author: source@mvista.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/init.h> + +#include <pci.h> +#include <glb.h> +#include <nand.h> + +static struct resource pci_io_resource = { + "pci IO space", + (u32)(PNX8550_PCIIO + 0x1000), /* reserve regacy I/O space */ + (u32)(PNX8550_PCIIO + PNX8550_PCIIO_SIZE), + IORESOURCE_IO +}; + +static struct resource pci_mem_resource = { + "pci memory space", + (u32)(PNX8550_PCIMEM), + (u32)(PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1), + IORESOURCE_MEM +}; + +extern struct pci_ops pnx8550_pci_ops; + +static struct pci_controller pnx8550_controller = { + .pci_ops = &pnx8550_pci_ops, + .io_resource = &pci_io_resource, + .mem_resource = &pci_mem_resource, +}; + +/* Return the total size of DRAM-memory, (RANK0 + RANK1) */ +static inline unsigned long get_system_mem_size(void) +{ + /* Read IP2031_RANK0_ADDR_LO */ + unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010); + /* Read IP2031_RANK1_ADDR_HI */ + unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018); + + return dram_r1_hi - dram_r0_lo + 1; +} + +static int __init pnx8550_pci_setup(void) +{ + int pci_mem_code; + int mem_size = get_system_mem_size() >> 20; + + /* Clear the Global 2 Register, PCI Inta Output Enable Registers + Bit 1:Enable DAC Powerdown + -> 0:DACs are enabled and are working normally + 1:DACs are powerdown + Bit 0:Enable of PCI inta output + -> 0 = Disable PCI inta output + 1 = Enable PCI inta output + */ + PNX8550_GLB2_ENAB_INTA_O = 0; + + /* Calc the PCI mem size code */ + if (mem_size >= 128) + pci_mem_code = SIZE_128M; + else if (mem_size >= 64) + pci_mem_code = SIZE_64M; + else if (mem_size >= 32) + pci_mem_code = SIZE_32M; + else + pci_mem_code = SIZE_16M; + + /* Set PCI_XIO registers */ + outl(pci_mem_resource.start, PCI_BASE | PCI_BASE1_LO); + outl(pci_mem_resource.end + 1, PCI_BASE | PCI_BASE1_HI); + outl(pci_io_resource.start, PCI_BASE | PCI_BASE2_LO); + outl(pci_io_resource.end, PCI_BASE | PCI_BASE2_HI); + + /* Send memory transaction via PCI_BASE2 */ + outl(0x00000001, PCI_BASE | PCI_IO); + + /* Unlock the setup register */ + outl(0xca, PCI_BASE | PCI_UNLOCKREG); + + /* + * BAR0 of PNX8550 (pci base 10) must be zero in order for ide + * to work, and in order for bus_to_baddr to work without any + * hacks. + */ + outl(0x00000000, PCI_BASE | PCI_BASE10); + + /* + *These two bars are set by default or the boot code. + * However, it's safer to set them here so we're not boot + * code dependent. + */ + outl(0x1be00000, PCI_BASE | PCI_BASE14); /* PNX MMIO */ + outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18); /* XIO */ + + outl(PCI_EN_TA | + PCI_EN_PCI2MMI | + PCI_EN_XIO | + PCI_SETUP_BASE18_SIZE(SIZE_32M) | + PCI_SETUP_BASE18_EN | + PCI_SETUP_BASE14_EN | + PCI_SETUP_BASE10_PREF | + PCI_SETUP_BASE10_SIZE(pci_mem_code) | + PCI_SETUP_CFGMANAGE_EN | + PCI_SETUP_PCIARB_EN, + PCI_BASE | + PCI_SETUP); /* PCI_SETUP */ + outl(0x00000000, PCI_BASE | PCI_CTRL); /* PCI_CONTROL */ + + register_pci_controller(&pnx8550_controller); + + return 0; +} + +arch_initcall(pnx8550_pci_setup); diff --git a/arch/mips/philips/pnx8550/common/platform.c b/arch/mips/philips/pnx8550/common/platform.c new file mode 100644 index 000000000000..8aa9bd65b45e --- /dev/null +++ b/arch/mips/philips/pnx8550/common/platform.c @@ -0,0 +1,135 @@ +/* + * Platform device support for Philips PNX8550 SoCs + * + * Copyright 2005, Embedded Alley Solutions, Inc + * + * Based on arch/mips/au1000/common/platform.c + * Platform device support for Au1x00 SoCs. + * + * Copyright 2004, Matt Porter <mporter@kernel.crashing.org> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/resource.h> +#include <linux/serial.h> +#include <linux/serial_ip3106.h> + +#include <int.h> +#include <usb.h> +#include <uart.h> + +extern struct uart_ops ip3106_pops; + +static struct resource pnx8550_usb_ohci_resources[] = { + [0] = { + .start = PNX8550_USB_OHCI_OP_BASE, + .end = PNX8550_USB_OHCI_OP_BASE + + PNX8550_USB_OHCI_OP_LEN, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX8550_INT_USB, + .end = PNX8550_INT_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource pnx8550_uart_resources[] = { + [0] = { + .start = PNX8550_UART_PORT0, + .end = PNX8550_UART_PORT0 + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX8550_UART_INT(0), + .end = PNX8550_UART_INT(0), + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = PNX8550_UART_PORT1, + .end = PNX8550_UART_PORT1 + 0xfff, + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = PNX8550_UART_INT(1), + .end = PNX8550_UART_INT(1), + .flags = IORESOURCE_IRQ, + }, +}; + +struct ip3106_port ip3106_ports[] = { + [0] = { + .port = { + .type = PORT_IP3106, + .iotype = SERIAL_IO_MEM, + .membase = (void __iomem *)PNX8550_UART_PORT0, + .mapbase = PNX8550_UART_PORT0, + .irq = PNX8550_UART_INT(0), + .uartclk = 3692300, + .fifosize = 16, + .ops = &ip3106_pops, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 0, + }, + }, + [1] = { + .port = { + .type = PORT_IP3106, + .iotype = SERIAL_IO_MEM, + .membase = (void __iomem *)PNX8550_UART_PORT1, + .mapbase = PNX8550_UART_PORT1, + .irq = PNX8550_UART_INT(1), + .uartclk = 3692300, + .fifosize = 16, + .ops = &ip3106_pops, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 1, + }, + }, +}; + +/* The dmamask must be set for OHCI to work */ +static u64 ohci_dmamask = ~(u32)0; + +static u64 uart_dmamask = ~(u32)0; + +static struct platform_device pnx8550_usb_ohci_device = { + .name = "pnx8550-ohci", + .id = -1, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(pnx8550_usb_ohci_resources), + .resource = pnx8550_usb_ohci_resources, +}; + +static struct platform_device pnx8550_uart_device = { + .name = "ip3106-uart", + .id = -1, + .dev = { + .dma_mask = &uart_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = ip3106_ports, + }, + .num_resources = ARRAY_SIZE(pnx8550_uart_resources), + .resource = pnx8550_uart_resources, +}; + +static struct platform_device *pnx8550_platform_devices[] __initdata = { + &pnx8550_usb_ohci_device, + &pnx8550_uart_device, +}; + +int pnx8550_platform_init(void) +{ + return platform_add_devices(pnx8550_platform_devices, + ARRAY_SIZE(pnx8550_platform_devices)); +} + +arch_initcall(pnx8550_platform_init); diff --git a/arch/mips/philips/pnx8550/common/proc.c b/arch/mips/philips/pnx8550/common/proc.c new file mode 100644 index 000000000000..72a016767e09 --- /dev/null +++ b/arch/mips/philips/pnx8550/common/proc.c @@ -0,0 +1,113 @@ +/* + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include <linux/init.h> +#include <linux/proc_fs.h> +#include <linux/irq.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/interrupt.h> +#include <linux/kernel_stat.h> +#include <linux/random.h> + +#include <asm/io.h> +#include <asm/gdb-stub.h> +#include <int.h> +#include <uart.h> + + +static int pnx8550_timers_read (char* page, char** start, off_t offset, int count, int* eof, void* data) +{ + int len = 0; + int configPR = read_c0_config7(); + + if (offset==0) { + len += sprintf(&page[len],"Timer: count, compare, tc, status\n"); + len += sprintf(&page[len]," 1: %11i, %8i, %1i, %s\n", + read_c0_count(), read_c0_compare(), + (configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on"); + len += sprintf(&page[len]," 2: %11i, %8i, %1i, %s\n", + read_c0_count2(), read_c0_compare2(), + (configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on"); + len += sprintf(&page[len]," 3: %11i, %8i, %1i, %s\n", + read_c0_count3(), read_c0_compare3(), + (configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on"); + } + + return len; +} + +static int pnx8550_registers_read (char* page, char** start, off_t offset, int count, int* eof, void* data) +{ + int len = 0; + + if (offset==0) { + len += sprintf(&page[len],"config1: %#10.8x\n",read_c0_config1()); + len += sprintf(&page[len],"config2: %#10.8x\n",read_c0_config2()); + len += sprintf(&page[len],"config3: %#10.8x\n",read_c0_config3()); + len += sprintf(&page[len],"configPR: %#10.8x\n",read_c0_config7()); + len += sprintf(&page[len],"status: %#10.8x\n",read_c0_status()); + len += sprintf(&page[len],"cause: %#10.8x\n",read_c0_cause()); + len += sprintf(&page[len],"count: %#10.8x\n",read_c0_count()); + len += sprintf(&page[len],"count_2: %#10.8x\n",read_c0_count2()); + len += sprintf(&page[len],"count_3: %#10.8x\n",read_c0_count3()); + len += sprintf(&page[len],"compare: %#10.8x\n",read_c0_compare()); + len += sprintf(&page[len],"compare_2: %#10.8x\n",read_c0_compare2()); + len += sprintf(&page[len],"compare_3: %#10.8x\n",read_c0_compare3()); + } + + return len; +} + +static struct proc_dir_entry* pnx8550_dir = NULL; +static struct proc_dir_entry* pnx8550_timers = NULL; +static struct proc_dir_entry* pnx8550_registers = NULL; + +static int pnx8550_proc_init( void ) +{ + + // Create /proc/pnx8550 + pnx8550_dir = create_proc_entry("pnx8550", S_IFDIR|S_IRUGO, NULL); + if (pnx8550_dir){ + pnx8550_dir->nlink = 1; + } + else { + printk(KERN_ERR "Can't create pnx8550 proc dir\n"); + return -1; + } + + // Create /proc/pnx8550/timers + pnx8550_timers = create_proc_entry("timers", S_IFREG|S_IRUGO, pnx8550_dir ); + if (pnx8550_timers){ + pnx8550_timers->nlink = 1; + pnx8550_timers->read_proc = pnx8550_timers_read; + } + else { + printk(KERN_ERR "Can't create pnx8550 timers proc file\n"); + } + + // Create /proc/pnx8550/registers + pnx8550_registers = create_proc_entry("registers", S_IFREG|S_IRUGO, pnx8550_dir ); + if (pnx8550_registers){ + pnx8550_registers->nlink = 1; + pnx8550_registers->read_proc = pnx8550_registers_read; + } + else { + printk(KERN_ERR "Can't create pnx8550 registers proc file\n"); + } + + return 0; +} + +__initcall(pnx8550_proc_init); diff --git a/arch/mips/philips/pnx8550/common/prom.c b/arch/mips/philips/pnx8550/common/prom.c new file mode 100644 index 000000000000..70aac9759412 --- /dev/null +++ b/arch/mips/philips/pnx8550/common/prom.c @@ -0,0 +1,138 @@ +/* + * + * Per Hallsmark, per.hallsmark@mvista.com + * + * Based on jmr3927/common/prom.c + * + * 2004 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/string.h> +#include <linux/serial_ip3106.h> + +#include <asm/bootinfo.h> +#include <uart.h> + +/* #define DEBUG_CMDLINE */ + +extern int prom_argc; +extern char **prom_argv, **prom_envp; + +typedef struct +{ + char *name; +/* char *val; */ +}t_env_var; + + +char * prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +void prom_init_cmdline(void) +{ + char *cp; + int actr; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while(actr < prom_argc) { + strcpy(cp, prom_argv[actr]); + cp += strlen(prom_argv[actr]); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ + --cp; + *cp = '\0'; +} + +char *prom_getenv(char *envname) +{ + /* + * Return a pointer to the given environment variable. + * Environment variables are stored in the form of "memsize=64". + */ + + t_env_var *env = (t_env_var *)prom_envp; + int i; + + i = strlen(envname); + + while(env->name) { + if(strncmp(envname, env->name, i) == 0) { + return(env->name + strlen(envname) + 1); + } + env++; + } + return(NULL); +} + +inline unsigned char str2hexnum(unsigned char c) +{ + if(c >= '0' && c <= '9') + return c - '0'; + if(c >= 'a' && c <= 'f') + return c - 'a' + 10; + if(c >= 'A' && c <= 'F') + return c - 'A' + 10; + return 0; /* foo */ +} + +inline void str2eaddr(unsigned char *ea, unsigned char *str) +{ + int i; + + for(i = 0; i < 6; i++) { + unsigned char num; + + if((*str == '.') || (*str == ':')) + str++; + num = str2hexnum(*str++) << 4; + num |= (str2hexnum(*str++)); + ea[i] = num; + } +} + +int get_ethernet_addr(char *ethernet_addr) +{ + char *ethaddr_str; + + ethaddr_str = prom_getenv("ethaddr"); + if (!ethaddr_str) { + printk("ethaddr not set in boot prom\n"); + return -1; + } + str2eaddr(ethernet_addr, ethaddr_str); + return 0; +} + +unsigned long __init prom_free_prom_memory(void) +{ + return 0; +} + +extern int pnx8550_console_port; + +/* used by prom_printf */ +void prom_putchar(char c) +{ + if (pnx8550_console_port != -1) { + /* Wait until FIFO not full */ + while( ((ip3106_fifo(UART_BASE, pnx8550_console_port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16) + ; + /* Send one char */ + ip3106_fifo(UART_BASE, pnx8550_console_port) = c; + } +} + +EXPORT_SYMBOL(prom_getcmdline); +EXPORT_SYMBOL(get_ethernet_addr); +EXPORT_SYMBOL(str2eaddr); diff --git a/arch/mips/philips/pnx8550/common/reset.c b/arch/mips/philips/pnx8550/common/reset.c new file mode 100644 index 000000000000..7b2cbc5b2c7c --- /dev/null +++ b/arch/mips/philips/pnx8550/common/reset.c @@ -0,0 +1,49 @@ +/*. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Reset the PNX8550 board. + * + */ +#include <linux/slab.h> +#include <asm/reboot.h> +#include <glb.h> + +void pnx8550_machine_restart(char *command) +{ + char head[] = "************* Machine restart *************"; + char foot[] = "*******************************************"; + + printk("\n\n"); + printk("%s\n", head); + if (command != NULL) + printk("* %s\n", command); + printk("%s\n", foot); + + PNX8550_RST_CTL = PNX8550_RST_DO_SW_RST; +} + +void pnx8550_machine_halt(void) +{ + printk("*** Machine halt. (Not implemented) ***\n"); +} + +void pnx8550_machine_power_off(void) +{ + printk("*** Machine power off. (Not implemented) ***\n"); +} diff --git a/arch/mips/philips/pnx8550/common/setup.c b/arch/mips/philips/pnx8550/common/setup.c new file mode 100644 index 000000000000..ee6bf72094f6 --- /dev/null +++ b/arch/mips/philips/pnx8550/common/setup.c @@ -0,0 +1,149 @@ +/* + * + * 2.6 port, Embedded Alley Solutions, Inc + * + * Based on Per Hallsmark, per.hallsmark@mvista.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include <linux/config.h> +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/ioport.h> +#include <linux/mm.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/serial_ip3106.h> + +#include <asm/cpu.h> +#include <asm/bootinfo.h> +#include <asm/irq.h> +#include <asm/mipsregs.h> +#include <asm/reboot.h> +#include <asm/pgtable.h> +#include <asm/time.h> + +#include <glb.h> +#include <int.h> +#include <pci.h> +#include <uart.h> +#include <nand.h> + +extern void prom_printf(char *fmt, ...); + +extern void __init board_setup(void); +extern void pnx8550_machine_restart(char *); +extern void pnx8550_machine_halt(void); +extern void pnx8550_machine_power_off(void); +extern struct resource ioport_resource; +extern struct resource iomem_resource; +extern void (*board_time_init)(void); +extern void pnx8550_time_init(void); +extern void (*board_timer_setup)(struct irqaction *irq); +extern void pnx8550_timer_setup(struct irqaction *irq); +extern void rs_kgdb_hook(int tty_no); +extern void prom_printf(char *fmt, ...); +extern char *prom_getcmdline(void); + +struct resource standard_io_resources[] = { + {"dma1", 0x00, 0x1f, IORESOURCE_BUSY}, + {"timer", 0x40, 0x5f, IORESOURCE_BUSY}, + {"dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, + {"dma2", 0xc0, 0xdf, IORESOURCE_BUSY}, +}; + +#define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource)) + +extern struct resource pci_io_resource; +extern struct resource pci_mem_resource; + +/* Return the total size of DRAM-memory, (RANK0 + RANK1) */ +unsigned long get_system_mem_size(void) +{ + /* Read IP2031_RANK0_ADDR_LO */ + unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010); + /* Read IP2031_RANK1_ADDR_HI */ + unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018); + + return dram_r1_hi - dram_r0_lo + 1; +} + +int pnx8550_console_port = -1; + +void __init plat_setup(void) +{ + int i; + char* argptr; + + board_setup(); /* board specific setup */ + + _machine_restart = pnx8550_machine_restart; + _machine_halt = pnx8550_machine_halt; + _machine_power_off = pnx8550_machine_power_off; + + board_time_init = pnx8550_time_init; + board_timer_setup = pnx8550_timer_setup; + + /* Clear the Global 2 Register, PCI Inta Output Enable Registers + Bit 1:Enable DAC Powerdown + -> 0:DACs are enabled and are working normally + 1:DACs are powerdown + Bit 0:Enable of PCI inta output + -> 0 = Disable PCI inta output + 1 = Enable PCI inta output + */ + PNX8550_GLB2_ENAB_INTA_O = 0; + + /* IO/MEM resources. */ + set_io_port_base(KSEG1); + ioport_resource.start = 0; + ioport_resource.end = ~0; + iomem_resource.start = 0; + iomem_resource.end = ~0; + + /* Request I/O space for devices on this board */ + for (i = 0; i < STANDARD_IO_RESOURCES; i++) + request_resource(&ioport_resource, standard_io_resources + i); + + /* Place the Mode Control bit for GPIO pin 16 in primary function */ + /* Pin 16 is used by UART1, UA1_TX */ + outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) | + (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT), + PNX8550_GPIO_MC1); + + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "console=ttyS")) != NULL) { + argptr += strlen("console=ttyS"); + pnx8550_console_port = *argptr == '0' ? 0 : 1; + + /* We must initialize the UART (console) before prom_printf */ + /* Set LCR to 8-bit and BAUD to 38400 (no 5) */ + ip3106_lcr(UART_BASE, pnx8550_console_port) = + IP3106_UART_LCR_8BIT; + ip3106_baud(UART_BASE, pnx8550_console_port) = 5; + } + +#ifdef CONFIG_KGDB + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { + int line; + argptr += strlen("kgdb=ttyS"); + line = *argptr == '0' ? 0 : 1; + rs_kgdb_hook(line); + prom_printf("KGDB: Using ttyS%i for session, " + "please connect your debugger\n", line ? 1 : 0); + } +#endif + return; +} diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c new file mode 100644 index 000000000000..70664ea96b92 --- /dev/null +++ b/arch/mips/philips/pnx8550/common/time.c @@ -0,0 +1,105 @@ +/* + * Copyright 2001, 2002, 2003 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * Common time service routines for MIPS machines. See + * Documents/MIPS/README.txt. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/param.h> +#include <linux/time.h> +#include <linux/timer.h> +#include <linux/smp.h> +#include <linux/kernel_stat.h> +#include <linux/spinlock.h> +#include <linux/interrupt.h> +#include <linux/module.h> + +#include <asm/bootinfo.h> +#include <asm/cpu.h> +#include <asm/time.h> +#include <asm/hardirq.h> +#include <asm/div64.h> +#include <asm/debug.h> + +#include <int.h> +#include <cm.h> + +extern unsigned int mips_hpt_frequency; + +/* + * pnx8550_time_init() - it does the following things: + * + * 1) board_time_init() - + * a) (optional) set up RTC routines, + * b) (optional) calibrate and set the mips_hpt_frequency + * (only needed if you intended to use fixed_rate_gettimeoffset + * or use cpu counter as timer interrupt source) + */ + +void pnx8550_time_init(void) +{ + unsigned int n; + unsigned int m; + unsigned int p; + unsigned int pow2p; + + /* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */ + /* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1: FIXME) */ + + n = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_N_MASK) >> 16; + m = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_M_MASK) >> 8; + p = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_P_MASK) >> 2; + pow2p = (1 << p); + + db_assert(m != 0 && pow2p != 0); + + /* + * Compute the frequency as in the PNX8550 User Manual 1.0, p.186 + * (a.k.a. 8-10). Divide by HZ for a timer offset that results in + * HZ timer interrupts per second. + */ + mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p)); +} + +/* + * pnx8550_timer_setup() - it does the following things: + * + * 5) board_timer_setup() - + * a) (optional) over-write any choices made above by time_init(). + * b) machine specific code should setup the timer irqaction. + * c) enable the timer interrupt + */ + +void __init pnx8550_timer_setup(struct irqaction *irq) +{ + int configPR; + + setup_irq(PNX8550_INT_TIMER1, irq); + + /* Start timer1 */ + configPR = read_c0_config7(); + configPR &= ~0x00000008; + write_c0_config7(configPR); + + /* Timer 2 stop */ + configPR = read_c0_config7(); + configPR |= 0x00000010; + write_c0_config7(configPR); + + write_c0_count2(0); + write_c0_compare2(0xffffffff); + + /* Timer 3 stop */ + configPR = read_c0_config7(); + configPR |= 0x00000020; + write_c0_config7(configPR); +} diff --git a/arch/mips/philips/pnx8550/jbs/Makefile b/arch/mips/philips/pnx8550/jbs/Makefile new file mode 100644 index 000000000000..e8228dbca8f6 --- /dev/null +++ b/arch/mips/philips/pnx8550/jbs/Makefile @@ -0,0 +1,4 @@ + +# Makefile for the Philips JBS Board. + +lib-y := init.o board_setup.o irqmap.o diff --git a/arch/mips/philips/pnx8550/jbs/board_setup.c b/arch/mips/philips/pnx8550/jbs/board_setup.c new file mode 100644 index 000000000000..f92826e0096d --- /dev/null +++ b/arch/mips/philips/pnx8550/jbs/board_setup.c @@ -0,0 +1,65 @@ +/* + * JBS Specific board startup routines. + * + * Copyright 2005, Embedded Alley Solutions, Inc + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/ioport.h> +#include <linux/mm.h> +#include <linux/console.h> +#include <linux/mc146818rtc.h> +#include <linux/delay.h> + +#include <asm/cpu.h> +#include <asm/bootinfo.h> +#include <asm/irq.h> +#include <asm/mipsregs.h> +#include <asm/reboot.h> +#include <asm/pgtable.h> + +#include <glb.h> + +/* CP0 hazard avoidance. */ +#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ + "nop; nop; nop; nop; nop; nop;\n\t" \ + ".set reorder\n\t") + +void __init board_setup(void) +{ + unsigned long config0, configpr; + + config0 = read_c0_config(); + + /* clear all three cache coherency fields */ + config0 &= ~(0x7 | (7<<25) | (7<<28)); + config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | + (CONF_CM_DEFAULT<<28)); + write_c0_config(config0); + BARRIER; + + configpr = read_c0_config7(); + configpr |= (1<<19); /* enable tlb */ + write_c0_config7(configpr); + BARRIER; +} diff --git a/arch/mips/philips/pnx8550/jbs/init.c b/arch/mips/philips/pnx8550/jbs/init.c new file mode 100644 index 000000000000..85f449174bc3 --- /dev/null +++ b/arch/mips/philips/pnx8550/jbs/init.c @@ -0,0 +1,57 @@ +/* + * + * Copyright 2005 Embedded Alley Solutions, Inc + * source@embeddedalley.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/bootmem.h> +#include <asm/addrspace.h> +#include <asm/bootinfo.h> +#include <linux/string.h> +#include <linux/kernel.h> + +int prom_argc; +char **prom_argv, **prom_envp; +extern void __init prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "Philips PNX8550/JBS"; +} + +void __init prom_init(void) +{ + + unsigned long memsize; + + mips_machgroup = MACH_GROUP_PHILIPS; + mips_machtype = MACH_PHILIPS_JBS; + + //memsize = 0x02800000; /* Trimedia uses memory above */ + memsize = 0x08000000; /* Trimedia uses memory above */ + add_memory_region(0, memsize, BOOT_MEM_RAM); +} diff --git a/arch/mips/philips/pnx8550/jbs/irqmap.c b/arch/mips/philips/pnx8550/jbs/irqmap.c new file mode 100644 index 000000000000..f78e0423dc98 --- /dev/null +++ b/arch/mips/philips/pnx8550/jbs/irqmap.c @@ -0,0 +1,36 @@ +/* + * Philips JBS board irqmap. + * + * Copyright 2005 Embedded Alley Solutions, Inc + * source@embeddealley.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/init.h> +#include <int.h> + +char irq_tab_jbs[][5] __initdata = { + [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [17] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, +}; + diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig new file mode 100644 index 000000000000..24d514c9dff9 --- /dev/null +++ b/arch/mips/pmc-sierra/Kconfig @@ -0,0 +1,3 @@ +config HYPERTRANSPORT + bool "Hypertransport Support for PMC-Sierra Yosemite" + depends on PMC_YOSEMITE diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h index c19f01a32045..a31288335fba 100644 --- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h +++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h @@ -34,7 +34,6 @@ #include <linux/pci.h> #include <linux/kernel.h> #include <linux/slab.h> -#include <linux/version.h> #include <asm/pci.h> #include <asm/io.h> #include <linux/init.h> diff --git a/arch/mips/pmc-sierra/yosemite/ht-irq.c b/arch/mips/pmc-sierra/yosemite/ht-irq.c index d22c9ffe4914..5aec4057314e 100644 --- a/arch/mips/pmc-sierra/yosemite/ht-irq.c +++ b/arch/mips/pmc-sierra/yosemite/ht-irq.c @@ -26,7 +26,6 @@ #include <linux/types.h> #include <linux/pci.h> #include <linux/kernel.h> -#include <linux/version.h> #include <linux/init.h> #include <asm/pci.h> diff --git a/arch/mips/pmc-sierra/yosemite/ht.c b/arch/mips/pmc-sierra/yosemite/ht.c index dad228d3a220..54b65a80abf5 100644 --- a/arch/mips/pmc-sierra/yosemite/ht.c +++ b/arch/mips/pmc-sierra/yosemite/ht.c @@ -28,7 +28,6 @@ #include <linux/pci.h> #include <linux/kernel.h> #include <linux/slab.h> -#include <linux/version.h> #include <asm/pci.h> #include <asm/io.h> diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c index 1fb3e697948d..555bfacf7647 100644 --- a/arch/mips/pmc-sierra/yosemite/prom.c +++ b/arch/mips/pmc-sierra/yosemite/prom.c @@ -132,8 +132,9 @@ void __init prom_init(void) prom_grab_secondary(); } -void __init prom_free_prom_memory(void) +unsigned long __init prom_free_prom_memory(void) { + return 0; } void __init prom_fixup_mem_map(unsigned long start, unsigned long end) diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c index 7225bbf20ce4..bdc2ab55bed6 100644 --- a/arch/mips/pmc-sierra/yosemite/setup.c +++ b/arch/mips/pmc-sierra/yosemite/setup.c @@ -212,7 +212,7 @@ static void __init py_late_time_init(void) py_rtc_setup(); } -static int __init pmc_yosemite_setup(void) +void __init plat_setup(void) { board_time_init = yosemite_time_init; late_time_init = py_late_time_init; @@ -228,8 +228,4 @@ static int __init pmc_yosemite_setup(void) OCD_WRITE(RM9000x2_OCD_HTBAR0, HYPERTRANSPORT_BAR0_ADDR); OCD_WRITE(RM9000x2_OCD_HTMASK0, HYPERTRANSPORT_SIZE0); #endif - - return 0; } - -early_initcall(pmc_yosemite_setup); diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c index 1d3b0734c78c..0527170d6adb 100644 --- a/arch/mips/pmc-sierra/yosemite/smp.c +++ b/arch/mips/pmc-sierra/yosemite/smp.c @@ -9,7 +9,7 @@ extern void (*mips_hpt_init)(unsigned int); #define LAUNCHSTACK_SIZE 256 -static spinlock_t launch_lock __initdata; +static __initdata DEFINE_SPINLOCK(launch_lock); static unsigned long secondary_sp __initdata; static unsigned long secondary_gp __initdata; diff --git a/arch/mips/qemu/q-setup.c b/arch/mips/qemu/q-setup.c index 1a80eee8cd35..022eb1af6db1 100644 --- a/arch/mips/qemu/q-setup.c +++ b/arch/mips/qemu/q-setup.c @@ -4,6 +4,11 @@ #define QEMU_PORT_BASE 0xb4000000 +const char *get_system_type(void) +{ + return "Qemu"; +} + static void __init qemu_timer_setup(struct irqaction *irq) { /* set the clock to 100 Hz */ diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c index fa0e719c5bd1..b19820110aa3 100644 --- a/arch/mips/sgi-ip22/ip22-eisa.c +++ b/arch/mips/sgi-ip22/ip22-eisa.c @@ -29,6 +29,7 @@ #include <linux/sched.h> #include <linux/interrupt.h> #include <linux/delay.h> +#include <asm/io.h> #include <asm/irq.h> #include <asm/mipsregs.h> #include <asm/addrspace.h> @@ -37,42 +38,29 @@ #include <asm/sgi/mc.h> #include <asm/sgi/ip22.h> -#define EISA_MAX_SLOTS 4 +/* I2 has four EISA slots. */ +#define IP22_EISA_MAX_SLOTS 4 #define EISA_MAX_IRQ 16 -#define EISA_TO_PHYS(x) (0x00080000 | (x)) -#define EISA_TO_KSEG1(x) ((void *) KSEG1ADDR(EISA_TO_PHYS((x)))) - -#define EIU_MODE_REG 0x0009ffc0 -#define EIU_STAT_REG 0x0009ffc4 -#define EIU_PREMPT_REG 0x0009ffc8 -#define EIU_QUIET_REG 0x0009ffcc -#define EIU_INTRPT_ACK 0x00090004 - -#define EISA_DMA1_STATUS 8 -#define EISA_INT1_CTRL 0x20 -#define EISA_INT1_MASK 0x21 -#define EISA_INT2_CTRL 0xA0 -#define EISA_INT2_MASK 0xA1 -#define EISA_DMA2_STATUS 0xD0 -#define EISA_DMA2_WRITE_SINGLE 0xD4 -#define EISA_EXT_NMI_RESET_CTRL 0x461 -#define EISA_INT1_EDGE_LEVEL 0x4D0 -#define EISA_INT2_EDGE_LEVEL 0x4D1 -#define EISA_VENDOR_ID_OFFSET 0xC80 - -#define EIU_WRITE_32(x,y) { *((u32 *) KSEG1ADDR(x)) = (u32) (y); mb(); } -#define EIU_READ_8(x) *((u8 *) KSEG1ADDR(x)) -#define EISA_WRITE_8(x,y) { *((u8 *) EISA_TO_KSEG1(x)) = (u8) (y); mb(); } -#define EISA_READ_8(x) *((u8 *) EISA_TO_KSEG1(x)) - -static char *decode_eisa_sig(u8 * sig) +#define EIU_MODE_REG 0x0001ffc0 +#define EIU_STAT_REG 0x0001ffc4 +#define EIU_PREMPT_REG 0x0001ffc8 +#define EIU_QUIET_REG 0x0001ffcc +#define EIU_INTRPT_ACK 0x00010004 + +static char __init *decode_eisa_sig(unsigned long addr) { - static char sig_str[8]; - u16 rev; + static char sig_str[EISA_SIG_LEN]; + u8 sig[4]; + u16 rev; + int i; + + for (i = 0; i < 4; i++) { + sig[i] = inb (addr + i); - if (sig[0] & 0x80) - return NULL; + if (!i && (sig[0] & 0x80)) + return NULL; + } sig_str[0] = ((sig[0] >> 2) & 0x1f) + ('A' - 1); sig_str[1] = (((sig[0] & 3) << 3) | (sig[1] >> 5)) + ('A' - 1); @@ -83,23 +71,26 @@ static char *decode_eisa_sig(u8 * sig) return sig_str; } -static void ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs) +static irqreturn_t ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs) { u8 eisa_irq; u8 dma1, dma2; - eisa_irq = EIU_READ_8(EIU_INTRPT_ACK); - dma1 = EISA_READ_8(EISA_DMA1_STATUS); - dma2 = EISA_READ_8(EISA_DMA2_STATUS); - - if (eisa_irq >= EISA_MAX_IRQ) { - /* Oops, Bad Stuff Happened... */ - printk(KERN_ERR "eisa_irq %d out of bound\n", eisa_irq); + eisa_irq = inb(EIU_INTRPT_ACK); + dma1 = inb(EISA_DMA1_STATUS); + dma2 = inb(EISA_DMA2_STATUS); - EISA_WRITE_8(EISA_INT2_CTRL, 0x20); - EISA_WRITE_8(EISA_INT1_CTRL, 0x20); - } else + if (eisa_irq < EISA_MAX_IRQ) { do_IRQ(eisa_irq, regs); + return IRQ_HANDLED; + } + + /* Oops, Bad Stuff Happened... */ + printk(KERN_ERR "eisa_irq %d out of bound\n", eisa_irq); + + outb(0x20, EISA_INT2_CTRL); + outb(0x20, EISA_INT1_CTRL); + return IRQ_NONE; } static void enable_eisa1_irq(unsigned int irq) @@ -109,9 +100,9 @@ static void enable_eisa1_irq(unsigned int irq) local_irq_save(flags); - mask = EISA_READ_8(EISA_INT1_MASK); + mask = inb(EISA_INT1_MASK); mask &= ~((u8) (1 << irq)); - EISA_WRITE_8(EISA_INT1_MASK, mask); + outb(mask, EISA_INT1_MASK); local_irq_restore(flags); } @@ -122,9 +113,9 @@ static unsigned int startup_eisa1_irq(unsigned int irq) /* Only use edge interrupts for EISA */ - edge = EISA_READ_8(EISA_INT1_EDGE_LEVEL); + edge = inb(EISA_INT1_EDGE_LEVEL); edge &= ~((u8) (1 << irq)); - EISA_WRITE_8(EISA_INT1_EDGE_LEVEL, edge); + outb(edge, EISA_INT1_EDGE_LEVEL); enable_eisa1_irq(irq); return 0; @@ -134,9 +125,9 @@ static void disable_eisa1_irq(unsigned int irq) { u8 mask; - mask = EISA_READ_8(EISA_INT1_MASK); + mask = inb(EISA_INT1_MASK); mask |= ((u8) (1 << irq)); - EISA_WRITE_8(EISA_INT1_MASK, mask); + outb(mask, EISA_INT1_MASK); } #define shutdown_eisa1_irq disable_eisa1_irq @@ -145,7 +136,7 @@ static void mask_and_ack_eisa1_irq(unsigned int irq) { disable_eisa1_irq(irq); - EISA_WRITE_8(EISA_INT1_CTRL, 0x20); + outb(0x20, EISA_INT1_CTRL); } static void end_eisa1_irq(unsigned int irq) @@ -171,9 +162,9 @@ static void enable_eisa2_irq(unsigned int irq) local_irq_save(flags); - mask = EISA_READ_8(EISA_INT2_MASK); + mask = inb(EISA_INT2_MASK); mask &= ~((u8) (1 << (irq - 8))); - EISA_WRITE_8(EISA_INT2_MASK, mask); + outb(mask, EISA_INT2_MASK); local_irq_restore(flags); } @@ -184,9 +175,9 @@ static unsigned int startup_eisa2_irq(unsigned int irq) /* Only use edge interrupts for EISA */ - edge = EISA_READ_8(EISA_INT2_EDGE_LEVEL); + edge = inb(EISA_INT2_EDGE_LEVEL); edge &= ~((u8) (1 << (irq - 8))); - EISA_WRITE_8(EISA_INT2_EDGE_LEVEL, edge); + outb(edge, EISA_INT2_EDGE_LEVEL); enable_eisa2_irq(irq); return 0; @@ -196,9 +187,9 @@ static void disable_eisa2_irq(unsigned int irq) { u8 mask; - mask = EISA_READ_8(EISA_INT2_MASK); + mask = inb(EISA_INT2_MASK); mask |= ((u8) (1 << (irq - 8))); - EISA_WRITE_8(EISA_INT2_MASK, mask); + outb(mask, EISA_INT2_MASK); } #define shutdown_eisa2_irq disable_eisa2_irq @@ -207,8 +198,7 @@ static void mask_and_ack_eisa2_irq(unsigned int irq) { disable_eisa2_irq(irq); - EISA_WRITE_8(EISA_INT2_CTRL, 0x20); - EISA_WRITE_8(EISA_INT1_CTRL, 0x20); + outb(0x20, EISA_INT2_CTRL); } static void end_eisa2_irq(unsigned int irq) @@ -241,7 +231,6 @@ int __init ip22_eisa_init(void) { int i, c; char *str; - u8 *slot_addr; if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) { printk(KERN_INFO "EISA: bus not present.\n"); @@ -249,11 +238,8 @@ int __init ip22_eisa_init(void) } printk(KERN_INFO "EISA: Probing bus...\n"); - for (c = 0, i = 1; i <= EISA_MAX_SLOTS; i++) { - slot_addr = - (u8 *) EISA_TO_KSEG1((0x1000 * i) + - EISA_VENDOR_ID_OFFSET); - if ((str = decode_eisa_sig(slot_addr))) { + for (c = 0, i = 1; i <= IP22_EISA_MAX_SLOTS; i++) { + if ((str = decode_eisa_sig(0x1000 * i + EISA_VENDOR_ID_OFFSET))) { printk(KERN_INFO "EISA: slot %d : %s detected.\n", i, str); c++; @@ -268,25 +254,25 @@ int __init ip22_eisa_init(void) Please wave your favorite dead chicken over the busses */ /* First say hello to the EIU */ - EIU_WRITE_32(EIU_PREMPT_REG, 0x0000FFFF); - EIU_WRITE_32(EIU_QUIET_REG, 1); - EIU_WRITE_32(EIU_MODE_REG, 0x40f3c07F); + outl(0x0000FFFF, EIU_PREMPT_REG); + outl(1, EIU_QUIET_REG); + outl(0x40f3c07F, EIU_MODE_REG); /* Now be nice to the EISA chipset */ - EISA_WRITE_8(EISA_EXT_NMI_RESET_CTRL, 1); - for (i = 0; i < 10000; i++); /* Wait long enough for the dust to settle */ - EISA_WRITE_8(EISA_EXT_NMI_RESET_CTRL, 0); - EISA_WRITE_8(EISA_INT1_CTRL, 0x11); - EISA_WRITE_8(EISA_INT2_CTRL, 0x11); - EISA_WRITE_8(EISA_INT1_MASK, 0); - EISA_WRITE_8(EISA_INT2_MASK, 8); - EISA_WRITE_8(EISA_INT1_MASK, 4); - EISA_WRITE_8(EISA_INT2_MASK, 2); - EISA_WRITE_8(EISA_INT1_MASK, 1); - EISA_WRITE_8(EISA_INT2_MASK, 1); - EISA_WRITE_8(EISA_INT1_MASK, 0xfb); - EISA_WRITE_8(EISA_INT2_MASK, 0xff); - EISA_WRITE_8(EISA_DMA2_WRITE_SINGLE, 0); + outb(1, EISA_EXT_NMI_RESET_CTRL); + udelay(50); /* Wait long enough for the dust to settle */ + outb(0, EISA_EXT_NMI_RESET_CTRL); + outb(0x11, EISA_INT1_CTRL); + outb(0x11, EISA_INT2_CTRL); + outb(0, EISA_INT1_MASK); + outb(8, EISA_INT2_MASK); + outb(4, EISA_INT1_MASK); + outb(2, EISA_INT2_MASK); + outb(1, EISA_INT1_MASK); + outb(1, EISA_INT2_MASK); + outb(0xfb, EISA_INT1_MASK); + outb(0xff, EISA_INT2_MASK); + outb(0, EISA_DMA2_WRITE_SINGLE); for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) { irq_desc[i].status = IRQ_DISABLED; diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c index 0e96a5d67993..5e59b4c8876b 100644 --- a/arch/mips/sgi-ip22/ip22-setup.c +++ b/arch/mips/sgi-ip22/ip22-setup.c @@ -53,7 +53,7 @@ EXPORT_SYMBOL(ip22_do_break); extern void ip22_be_init(void) __init; extern void ip22_time_init(void) __init; -static int __init ip22_setup(void) +void __init plat_setup(void) { char *ctype; @@ -137,8 +137,4 @@ static int __init ip22_setup(void) } } #endif - - return 0; } - -early_initcall(ip22_setup); diff --git a/arch/mips/sgi-ip27/Kconfig b/arch/mips/sgi-ip27/Kconfig new file mode 100644 index 000000000000..7b0bc4437243 --- /dev/null +++ b/arch/mips/sgi-ip27/Kconfig @@ -0,0 +1,54 @@ +#config SGI_SN0_XXL +# bool "IP27 XXL" +# depends on SGI_IP27 +# This options adds support for userspace processes upto 16TB size. +# Normally the limit is just .5TB. + +config SGI_SN0_N_MODE + bool "IP27 N-Mode" + depends on SGI_IP27 + help + The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be + configured in either N-Modes which allows for more nodes or M-Mode + which allows for more memory. Your system is most probably + running in M-Mode, so you should say N here. + +config ARCH_DISCONTIGMEM_ENABLE + bool + default y if SGI_IP27 + help + Say Y to upport efficient handling of discontiguous physical memory, + for architectures which are either NUMA (Non-Uniform Memory Access) + or have huge holes in the physical address space for other reasons. + See <file:Documentation/vm/numa> for more. + +config NUMA + bool "NUMA Support" + depends on SGI_IP27 + help + Say Y to compile the kernel to support NUMA (Non-Uniform Memory + Access). This option is for configuring high-end multiprocessor + server machines. If in doubt, say N. + +config MAPPED_KERNEL + bool "Mapped kernel support" + depends on SGI_IP27 + help + Change the way a Linux kernel is loaded into memory on a MIPS64 + machine. This is required in order to support text replication and + NUMA. If you need to understand it, read the source code. + +config REPLICATE_KTEXT + bool "Kernel text replication support" + depends on SGI_IP27 + help + Say Y here to enable replicating the kernel text across multiple + nodes in a NUMA cluster. This trades memory for speed. + +config REPLICATE_EXHANDLERS + bool "Exception handler replication support" + depends on SGI_IP27 + help + Say Y here to enable replicating the kernel exception handlers + across multiple nodes in a NUMA cluster. This trades memory for + speed. diff --git a/arch/mips/sgi-ip27/ip27-console.c b/arch/mips/sgi-ip27/ip27-console.c index d97f5b5ef844..3e1ac299b804 100644 --- a/arch/mips/sgi-ip27/ip27-console.c +++ b/arch/mips/sgi-ip27/ip27-console.c @@ -30,8 +30,10 @@ static inline struct ioc3_uartregs *console_uart(void) { struct ioc3 *ioc3; + nasid_t nasid; - ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(get_nasid())->memory_base; + nasid = (master_nasid == INVALID_NASID) ? get_nasid() : master_nasid; + ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(nasid)->memory_base; return &ioc3->sregs.uarta; } diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c index 6dcee5c46c74..8651a0e75404 100644 --- a/arch/mips/sgi-ip27/ip27-init.c +++ b/arch/mips/sgi-ip27/ip27-init.c @@ -56,12 +56,12 @@ static void __init per_hub_init(cnodeid_t cnode) { struct hub_data *hub = hub_data(cnode); nasid_t nasid = COMPACT_TO_NASID_NODEID(cnode); + int i; cpu_set(smp_processor_id(), hub->h_cpus); if (test_and_set_bit(cnode, hub_init_mask)) return; - /* * Set CRB timeout at 5ms, (< PI timeout of 10ms) */ @@ -88,6 +88,24 @@ static void __init per_hub_init(cnodeid_t cnode) __flush_cache_all(); } #endif + + /* + * Some interrupts are reserved by hardware or by software convention. + * Mark these as reserved right away so they won't be used accidently + * later. + */ + for (i = 0; i <= BASE_PCI_IRQ; i++) { + __set_bit(i, hub->irq_alloc_mask); + LOCAL_HUB_CLR_INTR(INT_PEND0_BASELVL + i); + } + + __set_bit(IP_PEND0_6_63, hub->irq_alloc_mask); + LOCAL_HUB_S(PI_INT_PEND_MOD, IP_PEND0_6_63); + + for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++) { + __set_bit(i, hub->irq_alloc_mask); + LOCAL_HUB_CLR_INTR(INT_PEND1_BASELVL + i); + } } void __init per_cpu_init(void) @@ -104,30 +122,12 @@ void __init per_cpu_init(void) clear_c0_status(ST0_IM); + per_hub_init(cnode); + for (i = 0; i < LEVELS_PER_SLICE; i++) si->level_to_irq[i] = -1; /* - * Some interrupts are reserved by hardware or by software convention. - * Mark these as reserved right away so they won't be used accidently - * later. - */ - for (i = 0; i <= BASE_PCI_IRQ; i++) { - __set_bit(i, si->irq_alloc_mask); - LOCAL_HUB_S(PI_INT_PEND_MOD, i); - } - - __set_bit(IP_PEND0_6_63, si->irq_alloc_mask); - LOCAL_HUB_S(PI_INT_PEND_MOD, IP_PEND0_6_63); - - for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++) { - __set_bit(i, si->irq_alloc_mask + 1); - LOCAL_HUB_S(PI_INT_PEND_MOD, i); - } - - LOCAL_HUB_L(PI_INT_PEND0); - - /* * We use this so we can find the local hub's data as fast as only * possible. */ @@ -140,8 +140,6 @@ void __init per_cpu_init(void) install_cpu_nmi_handler(cputoslice(cpu)); set_c0_status(SRB_DEV0 | SRB_DEV1); - - per_hub_init(cnode); } /* @@ -198,7 +196,7 @@ extern void ip27_setup_console(void); extern void ip27_time_init(void); extern void ip27_reboot_setup(void); -static int __init ip27_setup(void) +void __init plat_setup(void) { hubreg_t p, e, n_mode; nasid_t nid; @@ -245,8 +243,4 @@ static int __init ip27_setup(void) set_io_port_base(IO_BASE); board_time_init = ip27_time_init; - - return 0; } - -early_initcall(ip27_setup); diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index 61817a18aed2..73e5e52781d8 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -5,6 +5,9 @@ * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 1999 - 2001 Kanoj Sarcar */ + +#undef DEBUG + #include <linux/config.h> #include <linux/init.h> #include <linux/irq.h> @@ -14,11 +17,11 @@ #include <linux/types.h> #include <linux/interrupt.h> #include <linux/ioport.h> -#include <linux/irq.h> #include <linux/timex.h> #include <linux/slab.h> #include <linux/random.h> #include <linux/smp_lock.h> +#include <linux/kernel.h> #include <linux/kernel_stat.h> #include <linux/delay.h> #include <linux/bitops.h> @@ -37,13 +40,6 @@ #include <asm/sn/hub.h> #include <asm/sn/intr.h> -#undef DEBUG_IRQ -#ifdef DEBUG_IRQ -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - /* * Linux has a controller-independent x86 interrupt architecture. * every controller has a 'controller-template', that is used @@ -74,14 +70,15 @@ extern int irq_to_slot[]; static inline int alloc_level(int cpu, int irq) { + struct hub_data *hub = hub_data(cpu_to_node(cpu)); struct slice_data *si = cpu_data[cpu].data; - int level; /* pre-allocated entries */ + int level; - level = find_first_zero_bit(si->irq_alloc_mask, LEVELS_PER_SLICE); + level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE); if (level >= LEVELS_PER_SLICE) panic("Cpu %d flooded with devices\n", cpu); - __set_bit(level, si->irq_alloc_mask); + __set_bit(level, hub->irq_alloc_mask); si->level_to_irq[level] = irq; return level; @@ -216,9 +213,11 @@ static int intr_connect_level(int cpu, int bit) { nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); struct slice_data *si = cpu_data[cpu].data; + unsigned long flags; - __set_bit(bit, si->irq_enable_mask); + set_bit(bit, si->irq_enable_mask); + local_irq_save(flags); if (!cputoslice(cpu)) { REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]); @@ -226,6 +225,7 @@ static int intr_connect_level(int cpu, int bit) REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]); REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]); } + local_irq_restore(flags); return 0; } @@ -235,7 +235,7 @@ static int intr_disconnect_level(int cpu, int bit) nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); struct slice_data *si = cpu_data[cpu].data; - __clear_bit(bit, si->irq_enable_mask); + clear_bit(bit, si->irq_enable_mask); if (!cputoslice(cpu)) { REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); @@ -261,7 +261,7 @@ static unsigned int startup_bridge_irq(unsigned int irq) bc = IRQ_TO_BRIDGE(irq); bridge = bc->base; - DBG("bridge_startup(): irq= 0x%x pin=%d\n", irq, pin); + pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", irq, pin); /* * "map" irq to a swlevel greater than 6 since the first 6 bits * of INT_PEND0 are taken @@ -298,12 +298,13 @@ static unsigned int startup_bridge_irq(unsigned int irq) static void shutdown_bridge_irq(unsigned int irq) { struct bridge_controller *bc = IRQ_TO_BRIDGE(irq); + struct hub_data *hub = hub_data(cpu_to_node(bc->irq_cpu)); bridge_t *bridge = bc->base; struct slice_data *si = cpu_data[bc->irq_cpu].data; int pin, swlevel; cpuid_t cpu; - DBG("bridge_shutdown: irq 0x%x\n", irq); + pr_debug("bridge_shutdown: irq 0x%x\n", irq); pin = SLOT_FROM_PCI_IRQ(irq); /* @@ -313,7 +314,7 @@ static void shutdown_bridge_irq(unsigned int irq) swlevel = find_level(&cpu, irq); intr_disconnect_level(cpu, swlevel); - __clear_bit(swlevel, si->irq_alloc_mask); + __clear_bit(swlevel, hub->irq_alloc_mask); si->level_to_irq[swlevel] = -1; bridge->b_int_enable &= ~(1 << pin); @@ -433,25 +434,24 @@ void install_ipi(void) int slice = LOCAL_HUB_L(PI_CPU_NUM); int cpu = smp_processor_id(); struct slice_data *si = cpu_data[cpu].data; - hubreg_t mask, set; + struct hub_data *hub = hub_data(cpu_to_node(cpu)); + int resched, call; + + resched = CPU_RESCHED_A_IRQ + slice; + __set_bit(resched, hub->irq_alloc_mask); + __set_bit(resched, si->irq_enable_mask); + LOCAL_HUB_CLR_INTR(resched); + + call = CPU_CALL_A_IRQ + slice; + __set_bit(call, hub->irq_alloc_mask); + __set_bit(call, si->irq_enable_mask); + LOCAL_HUB_CLR_INTR(call); if (slice == 0) { - LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ); - LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ); - mask = LOCAL_HUB_L(PI_INT_MASK0_A); /* Slice A */ - set = (1UL << CPU_RESCHED_A_IRQ) | (1UL << CPU_CALL_A_IRQ); - mask |= set; - si->irq_enable_mask[0] |= set; - si->irq_alloc_mask[0] |= set; - LOCAL_HUB_S(PI_INT_MASK0_A, mask); + LOCAL_HUB_S(PI_INT_MASK0_A, si->irq_enable_mask[0]); + LOCAL_HUB_S(PI_INT_MASK1_A, si->irq_enable_mask[1]); } else { - LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ); - LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ); - mask = LOCAL_HUB_L(PI_INT_MASK0_B); /* Slice B */ - set = (1UL << CPU_RESCHED_B_IRQ) | (1UL << CPU_CALL_B_IRQ); - mask |= set; - si->irq_enable_mask[1] |= set; - si->irq_alloc_mask[1] |= set; - LOCAL_HUB_S(PI_INT_MASK0_B, mask); + LOCAL_HUB_S(PI_INT_MASK0_B, si->irq_enable_mask[0]); + LOCAL_HUB_S(PI_INT_MASK1_B, si->irq_enable_mask[1]); } } diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c index 17f768cba94f..3a8291b7d26d 100644 --- a/arch/mips/sgi-ip27/ip27-smp.c +++ b/arch/mips/sgi-ip27/ip27-smp.c @@ -127,37 +127,28 @@ void cpu_node_probe(void) printk("Discovered %d cpus on %d nodes\n", highest + 1, num_online_nodes()); } -static void intr_clear_bits(nasid_t nasid, volatile hubreg_t *pend, - int base_level) +static __init void intr_clear_all(nasid_t nasid) { - volatile hubreg_t bits; int i; - /* Check pending interrupts */ - if ((bits = HUB_L(pend)) != 0) - for (i = 0; i < N_INTPEND_BITS; i++) - if (bits & (1 << i)) - LOCAL_HUB_CLR_INTR(base_level + i); -} - -static void intr_clear_all(nasid_t nasid) -{ REMOTE_HUB_S(nasid, PI_INT_MASK0_A, 0); REMOTE_HUB_S(nasid, PI_INT_MASK0_B, 0); REMOTE_HUB_S(nasid, PI_INT_MASK1_A, 0); REMOTE_HUB_S(nasid, PI_INT_MASK1_B, 0); - intr_clear_bits(nasid, REMOTE_HUB_ADDR(nasid, PI_INT_PEND0), - INT_PEND0_BASELVL); - intr_clear_bits(nasid, REMOTE_HUB_ADDR(nasid, PI_INT_PEND1), - INT_PEND1_BASELVL); + + for (i = 0; i < 128; i++) + REMOTE_HUB_CLR_INTR(nasid, i); } void __init prom_prepare_cpus(unsigned int max_cpus) { cnodeid_t cnode; - for_each_online_node(cnode) + for_each_online_node(cnode) { + if (cnode == 0) + continue; intr_clear_all(COMPACT_TO_NASID_NODEID(cnode)); + } replicate_kernel_text(); diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index fc3a8e90d763..2eb22d692ed9 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -163,14 +163,13 @@ static void end_cpu_irq(unsigned int irq) #define mask_and_ack_cpu_irq disable_cpu_irq static struct hw_interrupt_type ip32_cpu_interrupt = { - "IP32 CPU", - startup_cpu_irq, - shutdown_cpu_irq, - enable_cpu_irq, - disable_cpu_irq, - mask_and_ack_cpu_irq, - end_cpu_irq, - NULL + .typename = "IP32 CPU", + .startup = startup_cpu_irq, + .shutdown = shutdown_cpu_irq, + .enable = enable_cpu_irq, + .disable = disable_cpu_irq, + .ack = mask_and_ack_cpu_irq, + .end = end_cpu_irq, }; /* @@ -234,14 +233,13 @@ static void end_crime_irq(unsigned int irq) #define shutdown_crime_irq disable_crime_irq static struct hw_interrupt_type ip32_crime_interrupt = { - "IP32 CRIME", - startup_crime_irq, - shutdown_crime_irq, - enable_crime_irq, - disable_crime_irq, - mask_and_ack_crime_irq, - end_crime_irq, - NULL + .typename = "IP32 CRIME", + .startup = startup_crime_irq, + .shutdown = shutdown_crime_irq, + .enable = enable_crime_irq, + .disable = disable_crime_irq, + .ack = mask_and_ack_crime_irq, + .end = end_crime_irq, }; /* @@ -294,14 +292,13 @@ static void end_macepci_irq(unsigned int irq) #define mask_and_ack_macepci_irq disable_macepci_irq static struct hw_interrupt_type ip32_macepci_interrupt = { - "IP32 MACE PCI", - startup_macepci_irq, - shutdown_macepci_irq, - enable_macepci_irq, - disable_macepci_irq, - mask_and_ack_macepci_irq, - end_macepci_irq, - NULL + .typename = "IP32 MACE PCI", + .startup = startup_macepci_irq, + .shutdown = shutdown_macepci_irq, + .enable = enable_macepci_irq, + .disable = disable_macepci_irq, + .ack = mask_and_ack_macepci_irq, + .end = end_macepci_irq, }; /* This is used for MACE ISA interrupts. That means bits 4-6 in the @@ -425,14 +422,13 @@ static void end_maceisa_irq(unsigned irq) #define shutdown_maceisa_irq disable_maceisa_irq static struct hw_interrupt_type ip32_maceisa_interrupt = { - "IP32 MACE ISA", - startup_maceisa_irq, - shutdown_maceisa_irq, - enable_maceisa_irq, - disable_maceisa_irq, - mask_and_ack_maceisa_irq, - end_maceisa_irq, - NULL + .typename = "IP32 MACE ISA", + .startup = startup_maceisa_irq, + .shutdown = shutdown_maceisa_irq, + .enable = enable_maceisa_irq, + .disable = disable_maceisa_irq, + .ack = mask_and_ack_maceisa_irq, + .end = end_maceisa_irq, }; /* This is used for regular non-ISA, non-PCI MACE interrupts. That means @@ -476,14 +472,13 @@ static void end_mace_irq(unsigned int irq) #define mask_and_ack_mace_irq disable_mace_irq static struct hw_interrupt_type ip32_mace_interrupt = { - "IP32 MACE", - startup_mace_irq, - shutdown_mace_irq, - enable_mace_irq, - disable_mace_irq, - mask_and_ack_mace_irq, - end_mace_irq, - NULL + .typename = "IP32 MACE", + .startup = startup_mace_irq, + .shutdown = shutdown_mace_irq, + .enable = enable_mace_irq, + .disable = disable_mace_irq, + .ack = mask_and_ack_mace_irq, + .end = end_mace_irq, }; static void ip32_unknown_interrupt(struct pt_regs *regs) diff --git a/arch/mips/sgi-ip32/ip32-memory.c b/arch/mips/sgi-ip32/ip32-memory.c index fc76ca92bab9..d37d40a3cdae 100644 --- a/arch/mips/sgi-ip32/ip32-memory.c +++ b/arch/mips/sgi-ip32/ip32-memory.c @@ -36,8 +36,8 @@ void __init prom_meminit (void) if (base + size > (256 << 20)) base += CRIME_HI_MEM_BASE; - printk("CRIME MC: bank %u base 0x%016lx size %luMB\n", - bank, base, size); + printk("CRIME MC: bank %u base 0x%016lx size %luMiB\n", + bank, base, size >> 20); add_memory_region (base, size, BOOT_MEM_RAM); } } diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c index 8d270be58224..d10a269aeae1 100644 --- a/arch/mips/sgi-ip32/ip32-setup.c +++ b/arch/mips/sgi-ip32/ip32-setup.c @@ -92,7 +92,7 @@ void __init ip32_timer_setup(struct irqaction *irq) setup_irq(IP32_R4K_TIMER_IRQ, irq); } -static int __init ip32_setup(void) +void __init plat_setup(void) { board_be_init = ip32_be_init; @@ -152,8 +152,4 @@ static int __init ip32_setup(void) } } #endif - - return 0; } - -early_initcall(ip32_setup); diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig new file mode 100644 index 000000000000..de46f62ac462 --- /dev/null +++ b/arch/mips/sibyte/Kconfig @@ -0,0 +1,161 @@ +config SIBYTE_SB1250 + bool + select HW_HAS_PCI + select SIBYTE_HAS_LDT + select SIBYTE_SB1xxx_SOC + +config SIBYTE_BCM1120 + bool + select SIBYTE_BCM112X + select SIBYTE_SB1xxx_SOC + +config SIBYTE_BCM1125 + bool + select HW_HAS_PCI + select SIBYTE_BCM112X + select SIBYTE_SB1xxx_SOC + +config SIBYTE_BCM1125H + bool + select HW_HAS_PCI + select SIBYTE_BCM112X + select SIBYTE_HAS_LDT + select SIBYTE_SB1xxx_SOC + +config SIBYTE_BCM112X + bool + select SIBYTE_SB1xxx_SOC + +config SIBYTE_BCM1x80 + bool + select HW_HAS_PCI + select SIBYTE_SB1xxx_SOC + +config SIBYTE_BCM1x55 + bool + select HW_HAS_PCI + select SIBYTE_SB1xxx_SOC + +config SIBYTE_SB1xxx_SOC + bool + depends on EXPERIMENTAL + select DMA_COHERENT + select SIBYTE_CFE + select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + +choice + prompt "SiByte SOC Stepping" + depends on SIBYTE_SB1xxx_SOC + +config CPU_SB1_PASS_1 + bool "1250 Pass1" + depends on SIBYTE_SB1250 + select CPU_HAS_PREFETCH + +config CPU_SB1_PASS_2_1250 + bool "1250 An" + depends on SIBYTE_SB1250 + select CPU_SB1_PASS_2 + help + Also called BCM1250 Pass 2 + +config CPU_SB1_PASS_2_2 + bool "1250 Bn" + depends on SIBYTE_SB1250 + select CPU_HAS_PREFETCH + help + Also called BCM1250 Pass 2.2 + +config CPU_SB1_PASS_4 + bool "1250 Cn" + depends on SIBYTE_SB1250 + select CPU_HAS_PREFETCH + help + Also called BCM1250 Pass 3 + +config CPU_SB1_PASS_2_112x + bool "112x Hybrid" + depends on SIBYTE_BCM112X + select CPU_SB1_PASS_2 + +config CPU_SB1_PASS_3 + bool "112x An" + depends on SIBYTE_BCM112X + select CPU_HAS_PREFETCH + +endchoice + +config CPU_SB1_PASS_2 + bool + +config SIBYTE_HAS_LDT + bool + depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H) + default y + +config SIMULATION + bool "Running under simulation" + depends on SIBYTE_SB1xxx_SOC + help + Build a kernel suitable for running under the GDB simulator. + Primarily adjusts the kernel's notion of time. + +config CONFIG_SB1_CEX_ALWAYS_FATAL + bool "All cache exceptions considered fatal (no recovery attempted)" + depends on SIBYTE_SB1xxx_SOC + +config CONFIG_SB1_CERR_STALL + bool "Stall (rather than panic) on fatal cache error" + depends on SIBYTE_SB1xxx_SOC + +config SIBYTE_CFE + bool "Booting from CFE" + depends on SIBYTE_SB1xxx_SOC + help + Make use of the CFE API for enumerating available memory, + controlling secondary CPUs, and possibly console output. + +config SIBYTE_CFE_CONSOLE + bool "Use firmware console" + depends on SIBYTE_CFE + help + Use the CFE API's console write routines during boot. Other console + options (VT console, sb1250 duart console, etc.) should not be + configured. + +config SIBYTE_STANDALONE + bool + depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE + default y + +config SIBYTE_STANDALONE_RAM_SIZE + int "Memory size (in megabytes)" + depends on SIBYTE_STANDALONE + default "32" + +config SIBYTE_BUS_WATCHER + bool "Support for Bus Watcher statistics" + depends on SIBYTE_SB1xxx_SOC + help + Handle and keep statistics on the bus error interrupts (COR_ECC, + BAD_ECC, IO_BUS). + +config SIBYTE_BW_TRACE + bool "Capture bus trace before bus error" + depends on SIBYTE_BUS_WATCHER + help + Run a continuous bus trace, dumping the raw data as soon as + a ZBbus error is detected. Cannot work if ZBbus profiling + is turned on, and also will interfere with JTAG-based trace + buffer activity. Raw buffer data is dumped to console, and + must be processed off-line. + +config SIBYTE_SB1250_PROF + bool "Support for SB1/SOC profiling - SB1/SCD perf counters" + depends on SIBYTE_SB1xxx_SOC + +config SIBYTE_TBPROF + bool "Support for ZBbus profiling" + depends on SIBYTE_SB1xxx_SOC diff --git a/arch/mips/sibyte/bcm1480/Makefile b/arch/mips/sibyte/bcm1480/Makefile new file mode 100644 index 000000000000..538d5a51ae94 --- /dev/null +++ b/arch/mips/sibyte/bcm1480/Makefile @@ -0,0 +1,5 @@ +obj-y := setup.o irq.o irq_handler.o time.o + +obj-$(CONFIG_SMP) += smp.o + +EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c new file mode 100644 index 000000000000..b2a1ba5d23df --- /dev/null +++ b/arch/mips/sibyte/bcm1480/irq.c @@ -0,0 +1,476 @@ +/* + * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include <linux/config.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/linkage.h> +#include <linux/interrupt.h> +#include <linux/spinlock.h> +#include <linux/mm.h> +#include <linux/slab.h> +#include <linux/kernel_stat.h> + +#include <asm/errno.h> +#include <asm/signal.h> +#include <asm/system.h> +#include <asm/ptrace.h> +#include <asm/io.h> + +#include <asm/sibyte/bcm1480_regs.h> +#include <asm/sibyte/bcm1480_int.h> +#include <asm/sibyte/bcm1480_scd.h> + +#include <asm/sibyte/sb1250_uart.h> +#include <asm/sibyte/sb1250.h> + +/* + * These are the routines that handle all the low level interrupt stuff. + * Actions handled here are: initialization of the interrupt map, requesting of + * interrupt lines by handlers, dispatching if interrupts to handlers, probing + * for interrupt lines + */ + + +#define shutdown_bcm1480_irq disable_bcm1480_irq +static void end_bcm1480_irq(unsigned int irq); +static void enable_bcm1480_irq(unsigned int irq); +static void disable_bcm1480_irq(unsigned int irq); +static unsigned int startup_bcm1480_irq(unsigned int irq); +static void ack_bcm1480_irq(unsigned int irq); +#ifdef CONFIG_SMP +static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask); +#endif + +#ifdef CONFIG_PCI +extern unsigned long ht_eoi_space; +#endif + +#ifdef CONFIG_KGDB +#include <asm/gdb-stub.h> +extern void breakpoint(void); +static int kgdb_irq; +#ifdef CONFIG_GDB_CONSOLE +extern void register_gdb_console(void); +#endif + +/* kgdb is on when configured. Pass "nokgdb" kernel arg to turn it off */ +static int kgdb_flag = 1; +static int __init nokgdb(char *str) +{ + kgdb_flag = 0; + return 1; +} +__setup("nokgdb", nokgdb); + +/* Default to UART1 */ +int kgdb_port = 1; +#ifdef CONFIG_SIBYTE_SB1250_DUART +extern char sb1250_duart_present[]; +#endif +#endif + +static struct hw_interrupt_type bcm1480_irq_type = { + .typename = "BCM1480-IMR", + .startup = startup_bcm1480_irq, + .shutdown = shutdown_bcm1480_irq, + .enable = enable_bcm1480_irq, + .disable = disable_bcm1480_irq, + .ack = ack_bcm1480_irq, + .end = end_bcm1480_irq, +#ifdef CONFIG_SMP + .set_affinity = bcm1480_set_affinity +#endif +}; + +/* Store the CPU id (not the logical number) */ +int bcm1480_irq_owner[BCM1480_NR_IRQS]; + +DEFINE_SPINLOCK(bcm1480_imr_lock); + +void bcm1480_mask_irq(int cpu, int irq) +{ + unsigned long flags; + u64 cur_ints,hl_spacing; + + spin_lock_irqsave(&bcm1480_imr_lock, flags); + hl_spacing = 0; + if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) { + hl_spacing = BCM1480_IMR_HL_SPACING; + irq -= BCM1480_NR_IRQS_HALF; + } + cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); + cur_ints |= (((u64) 1) << irq); + ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); + spin_unlock_irqrestore(&bcm1480_imr_lock, flags); +} + +void bcm1480_unmask_irq(int cpu, int irq) +{ + unsigned long flags; + u64 cur_ints,hl_spacing; + + spin_lock_irqsave(&bcm1480_imr_lock, flags); + hl_spacing = 0; + if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) { + hl_spacing = BCM1480_IMR_HL_SPACING; + irq -= BCM1480_NR_IRQS_HALF; + } + cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); + cur_ints &= ~(((u64) 1) << irq); + ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); + spin_unlock_irqrestore(&bcm1480_imr_lock, flags); +} + +#ifdef CONFIG_SMP +static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask) +{ + int i = 0, old_cpu, cpu, int_on; + u64 cur_ints; + irq_desc_t *desc = irq_desc + irq; + unsigned long flags; + unsigned int irq_dirty; + + i = first_cpu(mask); + if (next_cpu(i, mask) <= NR_CPUS) { + printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq); + return; + } + + /* Convert logical CPU to physical CPU */ + cpu = cpu_logical_map(i); + + /* Protect against other affinity changers and IMR manipulation */ + spin_lock_irqsave(&desc->lock, flags); + spin_lock(&bcm1480_imr_lock); + + /* Swizzle each CPU's IMR (but leave the IP selection alone) */ + old_cpu = bcm1480_irq_owner[irq]; + irq_dirty = irq; + if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) { + irq_dirty -= BCM1480_NR_IRQS_HALF; + } + + int k; + for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */ + cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); + int_on = !(cur_ints & (((u64) 1) << irq_dirty)); + if (int_on) { + /* If it was on, mask it */ + cur_ints |= (((u64) 1) << irq_dirty); + ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); + } + bcm1480_irq_owner[irq] = cpu; + if (int_on) { + /* unmask for the new CPU */ + cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); + cur_ints &= ~(((u64) 1) << irq_dirty); + ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); + } + } + spin_unlock(&bcm1480_imr_lock); + spin_unlock_irqrestore(&desc->lock, flags); +} +#endif + + +/* Defined in arch/mips/sibyte/bcm1480/irq_handler.S */ +extern void bcm1480_irq_handler(void); + +/*****************************************************************************/ + +static unsigned int startup_bcm1480_irq(unsigned int irq) +{ + bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); + + return 0; /* never anything pending */ +} + + +static void disable_bcm1480_irq(unsigned int irq) +{ + bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); +} + +static void enable_bcm1480_irq(unsigned int irq) +{ + bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); +} + + +static void ack_bcm1480_irq(unsigned int irq) +{ + u64 pending; + unsigned int irq_dirty; + + /* + * If the interrupt was an HT interrupt, now is the time to + * clear it. NOTE: we assume the HT bridge was set up to + * deliver the interrupts to all CPUs (which makes affinity + * changing easier for us) + */ + irq_dirty = irq; + if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) { + irq_dirty -= BCM1480_NR_IRQS_HALF; + } + int k; + for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */ + pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq], + R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING)))); + pending &= ((u64)1 << (irq_dirty)); + if (pending) { +#ifdef CONFIG_SMP + int i; + for (i=0; i<NR_CPUS; i++) { + /* + * Clear for all CPUs so an affinity switch + * doesn't find an old status + */ + __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i), + R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); + } +#else + __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); +#endif + + /* + * Generate EOI. For Pass 1 parts, EOI is a nop. For + * Pass 2, the LDT world may be edge-triggered, but + * this EOI shouldn't hurt. If they are + * level-sensitive, the EOI is required. + */ +#ifdef CONFIG_PCI + if (ht_eoi_space) + *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0; +#endif + } + } + bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); +} + + +static void end_bcm1480_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); + } +} + + +void __init init_bcm1480_irqs(void) +{ + int i; + + for (i = 0; i < NR_IRQS; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + if (i < BCM1480_NR_IRQS) { + irq_desc[i].handler = &bcm1480_irq_type; + bcm1480_irq_owner[i] = 0; + } else { + irq_desc[i].handler = &no_irq_type; + } + } +} + + +static irqreturn_t bcm1480_dummy_handler(int irq, void *dev_id, + struct pt_regs *regs) +{ + return IRQ_NONE; +} + +static struct irqaction bcm1480_dummy_action = { + .handler = bcm1480_dummy_handler, + .flags = 0, + .mask = CPU_MASK_NONE, + .name = "bcm1480-private", + .next = NULL, + .dev_id = 0 +}; + +int bcm1480_steal_irq(int irq) +{ + irq_desc_t *desc = irq_desc + irq; + unsigned long flags; + int retval = 0; + + if (irq >= BCM1480_NR_IRQS) + return -EINVAL; + + spin_lock_irqsave(&desc->lock,flags); + /* Don't allow sharing at all for these */ + if (desc->action != NULL) + retval = -EBUSY; + else { + desc->action = &bcm1480_dummy_action; + desc->depth = 0; + } + spin_unlock_irqrestore(&desc->lock,flags); + return 0; +} + +/* + * init_IRQ is called early in the boot sequence from init/main.c. It + * is responsible for setting up the interrupt mapper and installing the + * handler that will be responsible for dispatching interrupts to the + * "right" place. + */ +/* + * For now, map all interrupts to IP[2]. We could save + * some cycles by parceling out system interrupts to different + * IP lines, but keep it simple for bringup. We'll also direct + * all interrupts to a single CPU; we should probably route + * PCI and LDT to one cpu and everything else to the other + * to balance the load a bit. + * + * On the second cpu, everything is set to IP5, which is + * ignored, EXCEPT the mailbox interrupt. That one is + * set to IP[2] so it is handled. This is needed so we + * can do cross-cpu function calls, as requred by SMP + */ + +#define IMR_IP2_VAL K_BCM1480_INT_MAP_I0 +#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 +#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 +#define IMR_IP5_VAL K_BCM1480_INT_MAP_I3 +#define IMR_IP6_VAL K_BCM1480_INT_MAP_I4 + +void __init arch_init_irq(void) +{ + + unsigned int i, cpu; + u64 tmp; + unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | + STATUSF_IP1 | STATUSF_IP0; + + /* Default everything to IP2 */ + /* Start with _high registers which has no bit 0 interrupt source */ + for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */ + for (cpu = 0; cpu < 4; cpu++) { + __raw_writeq(IMR_IP2_VAL, + IOADDR(A_BCM1480_IMR_REGISTER(cpu, + R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3))); + } + } + + /* Now do _low registers */ + for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) { + for (cpu = 0; cpu < 4; cpu++) { + __raw_writeq(IMR_IP2_VAL, + IOADDR(A_BCM1480_IMR_REGISTER(cpu, + R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3))); + } + } + + init_bcm1480_irqs(); + + /* + * Map the high 16 bits of mailbox_0 registers to IP[3], for + * inter-cpu messages + */ + /* Was I1 */ + for (cpu = 0; cpu < 4; cpu++) { + __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + + (K_BCM1480_INT_MBOX_0_0 << 3))); + } + + + /* Clear the mailboxes. The firmware may leave them dirty */ + for (cpu = 0; cpu < 4; cpu++) { + __raw_writeq(0xffffffffffffffffULL, + IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU))); + __raw_writeq(0xffffffffffffffffULL, + IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU))); + } + + + /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */ + tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0)); + for (cpu = 0; cpu < 4; cpu++) { + __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H))); + } + tmp = ~((u64) 0); + for (cpu = 0; cpu < 4; cpu++) { + __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L))); + } + + bcm1480_steal_irq(K_BCM1480_INT_MBOX_0_0); + + /* + * Note that the timer interrupts are also mapped, but this is + * done in bcm1480_time_init(). Also, the profiling driver + * does its own management of IP7. + */ + +#ifdef CONFIG_KGDB + imask |= STATUSF_IP6; +#endif + /* Enable necessary IPs, disable the rest */ + change_c0_status(ST0_IM, imask); + set_except_vector(0, bcm1480_irq_handler); + +#ifdef CONFIG_KGDB + if (kgdb_flag) { + kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port; + +#ifdef CONFIG_SIBYTE_SB1250_DUART + sb1250_duart_present[kgdb_port] = 0; +#endif + /* Setup uart 1 settings, mapper */ + /* QQQ FIXME */ + __raw_writeq(M_DUART_IMR_BRK, IO_SPACE_BASE + A_DUART_IMRREG(kgdb_port)); + + bcm1480_steal_irq(kgdb_irq); + __raw_writeq(IMR_IP6_VAL, + IO_SPACE_BASE + A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + + (kgdb_irq<<3)); + bcm1480_unmask_irq(0, kgdb_irq); + +#ifdef CONFIG_GDB_CONSOLE + register_gdb_console(); +#endif + prom_printf("Waiting for GDB on UART port %d\n", kgdb_port); + set_debug_traps(); + breakpoint(); + } +#endif +} + +#ifdef CONFIG_KGDB + +#include <linux/delay.h> + +#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) +#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) + +void bcm1480_kgdb_interrupt(struct pt_regs *regs) +{ + /* + * Clear break-change status (allow some time for the remote + * host to stop the break, since we would see another + * interrupt on the end-of-break too) + */ + kstat.irqs[smp_processor_id()][kgdb_irq]++; + mdelay(500); + duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT | + M_DUART_RX_EN | M_DUART_TX_EN); + set_async_breakpoint(®s->cp0_epc); +} + +#endif /* CONFIG_KGDB */ diff --git a/arch/mips/sibyte/bcm1480/irq_handler.S b/arch/mips/sibyte/bcm1480/irq_handler.S new file mode 100644 index 000000000000..408db88d050f --- /dev/null +++ b/arch/mips/sibyte/bcm1480/irq_handler.S @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * bcm1480_irq_handler() is the routine that is actually called when an + * interrupt occurs. It is installed as the exception vector handler in + * init_IRQ() in arch/mips/sibyte/bcm1480/irq.c + * + * In the handle we figure out which interrupts need handling, and use that + * to call the dispatcher, which will take care of actually calling + * registered handlers + * + * Note that we take care of all raised interrupts in one go at the handler. + * This is more BSDish than the Indy code, and also, IMHO, more sane. + */ +#include <linux/config.h> + +#include <asm/addrspace.h> +#include <asm/asm.h> +#include <asm/mipsregs.h> +#include <asm/regdef.h> +#include <asm/stackframe.h> +#include <asm/sibyte/sb1250_defs.h> +#include <asm/sibyte/bcm1480_regs.h> +#include <asm/sibyte/bcm1480_int.h> + +/* + * What a pain. We have to be really careful saving the upper 32 bits of any + * register across function calls if we don't want them trashed--since were + * running in -o32, the calling routing never saves the full 64 bits of a + * register across a function call. Being the interrupt handler, we're + * guaranteed that interrupts are disabled during this code so we don't have + * to worry about random interrupts blasting the high 32 bits. + */ + + .text + .set push + .set noreorder + .set noat + .set mips64 + #.set mips4 + .align 5 + NESTED(bcm1480_irq_handler, PT_SIZE, sp) + SAVE_ALL + CLI + +#ifdef CONFIG_SIBYTE_BCM1480_PROF + /* Set compare to count to silence count/compare timer interrupts */ + mfc0 t1, CP0_COUNT + mtc0 t1, CP0_COMPARE /* pause to clear IP[7] bit of cause ? */ +#endif + /* Read cause */ + mfc0 s0, CP0_CAUSE + +#ifdef CONFIG_SIBYTE_BCM1480_PROF + /* Cpu performance counter interrupt is routed to IP[7] */ + andi t1, s0, CAUSEF_IP7 + beqz t1, 0f + srl t1, s0, (CAUSEB_BD-2) /* Shift BD bit to bit 2 */ + and t1, t1, 0x4 /* mask to get just BD bit */ +#ifdef CONFIG_MIPS64 + dmfc0 a0, CP0_EPC + daddu a0, a0, t1 /* a0 = EPC + (BD ? 4 : 0) */ +#else + mfc0 a0, CP0_EPC + addu a0, a0, t1 /* a0 = EPC + (BD ? 4 : 0) */ +#endif + jal sbprof_cpu_intr + nop + j ret_from_irq + nop +0: +#endif + + /* Timer interrupt is routed to IP[4] */ + andi t1, s0, CAUSEF_IP4 + beqz t1, 1f + nop + jal bcm1480_timer_interrupt + move a0, sp /* Pass the registers along */ + j ret_from_irq + nop /* delay slot */ +1: + +#ifdef CONFIG_SMP + /* Mailbox interrupt is routed to IP[3] */ + andi t1, s0, CAUSEF_IP3 + beqz t1, 2f + nop + jal bcm1480_mailbox_interrupt + move a0, sp + j ret_from_irq + nop /* delay slot */ +2: +#endif + +#ifdef CONFIG_KGDB + /* KGDB (uart 1) interrupt is routed to IP[6] */ + andi t1, s0, CAUSEF_IP6 + beqz t1, 3f + nop /* delay slot */ + jal bcm1480_kgdb_interrupt + move a0, sp + j ret_from_irq + nop /* delay slot */ +3: +#endif + + and t1, s0, CAUSEF_IP2 + beqz t1, 9f + nop + + /* + * Default...we've hit an IP[2] interrupt, which means we've got + * to check the 1480 interrupt registers to figure out what to do + * Need to detect which CPU we're on, now that smp_affinity is + * supported. + */ + PTR_LA v0, CKSEG1 + A_BCM1480_IMR_CPU0_BASE +#ifdef CONFIG_SMP + lw t1, TI_CPU($28) + sll t1, t1, BCM1480_IMR_REGISTER_SPACING_SHIFT + addu v0, v0, t1 +#endif + + /* Read IP[2] status (get both high and low halves of status) */ + ld s0, R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H(v0) + ld s1, R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L(v0) + + move s2, zero /* intr number */ + li s3, 64 + + beqz s0, 9f /* No interrupts. Return. */ + move a1, sp + + xori s4, s0, 1 /* if s0 (_H) == 1, it's a low intr, so... */ + movz s2, s3, s4 /* start the intr number at 64, and */ + movz s0, s1, s4 /* look at the low status value. */ + + dclz s1, s0 /* Find the next interrupt. */ + dsubu a0, zero, s1 + daddiu a0, a0, 63 + jal do_IRQ + daddu a0, a0, s2 + +9: j ret_from_irq + nop + + .set pop + END(bcm1480_irq_handler) diff --git a/arch/mips/sibyte/bcm1480/setup.c b/arch/mips/sibyte/bcm1480/setup.c new file mode 100644 index 000000000000..d90a0b87874c --- /dev/null +++ b/arch/mips/sibyte/bcm1480/setup.c @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include <linux/config.h> +#include <linux/kernel.h> +#include <linux/reboot.h> +#include <linux/string.h> + +#include <asm/bootinfo.h> +#include <asm/mipsregs.h> +#include <asm/io.h> +#include <asm/sibyte/sb1250.h> + +#include <asm/sibyte/bcm1480_regs.h> +#include <asm/sibyte/bcm1480_scd.h> +#include <asm/sibyte/sb1250_scd.h> + +unsigned int sb1_pass; +unsigned int soc_pass; +unsigned int soc_type; +unsigned int periph_rev; +unsigned int zbbus_mhz; + +static unsigned int part_type; + +static char *soc_str; +static char *pass_str; + +static inline int setup_bcm1x80_bcm1x55(void); + +/* Setup code likely to be common to all SiByte platforms */ + +static inline int sys_rev_decode(void) +{ + int ret = 0; + + switch (soc_type) { + case K_SYS_SOC_TYPE_BCM1x80: + if (part_type == K_SYS_PART_BCM1480) + soc_str = "BCM1480"; + else if (part_type == K_SYS_PART_BCM1280) + soc_str = "BCM1280"; + else + soc_str = "BCM1x80"; + ret = setup_bcm1x80_bcm1x55(); + break; + + case K_SYS_SOC_TYPE_BCM1x55: + if (part_type == K_SYS_PART_BCM1455) + soc_str = "BCM1455"; + else if (part_type == K_SYS_PART_BCM1255) + soc_str = "BCM1255"; + else + soc_str = "BCM1x55"; + ret = setup_bcm1x80_bcm1x55(); + break; + + default: + prom_printf("Unknown part type %x\n", part_type); + ret = 1; + break; + } + return ret; +} + +static inline int setup_bcm1x80_bcm1x55(void) +{ + int ret = 0; + + switch (soc_pass) { + case K_SYS_REVISION_BCM1480_S0: + periph_rev = 1; + pass_str = "S0 (pass1)"; + break; + case K_SYS_REVISION_BCM1480_A1: + periph_rev = 1; + pass_str = "A1 (pass1)"; + break; + case K_SYS_REVISION_BCM1480_A2: + periph_rev = 1; + pass_str = "A2 (pass1)"; + break; + case K_SYS_REVISION_BCM1480_A3: + periph_rev = 1; + pass_str = "A3 (pass1)"; + break; + case K_SYS_REVISION_BCM1480_B0: + periph_rev = 1; + pass_str = "B0 (pass2)"; + break; + default: + prom_printf("Unknown %s rev %x\n", soc_str, soc_pass); + periph_rev = 1; + pass_str = "Unknown Revision"; + break; + } + return ret; +} + +void bcm1480_setup(void) +{ + uint64_t sys_rev; + int plldiv; + + sb1_pass = read_c0_prid() & 0xff; + sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); + soc_type = SYS_SOC_TYPE(sys_rev); + part_type = G_SYS_PART(sys_rev); + soc_pass = G_SYS_REVISION(sys_rev); + + if (sys_rev_decode()) { + prom_printf("Restart after failure to identify SiByte chip\n"); + machine_restart(NULL); + } + + plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); + zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25); + + prom_printf("Broadcom SiByte %s %s @ %d MHz (SB-1A rev %d)\n", + soc_str, pass_str, zbbus_mhz * 2, sb1_pass); + prom_printf("Board type: %s\n", get_system_type()); +} diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c new file mode 100644 index 000000000000..584a4b33faac --- /dev/null +++ b/arch/mips/sibyte/bcm1480/smp.c @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2001,2002,2004 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/smp.h> +#include <linux/kernel_stat.h> + +#include <asm/mmu_context.h> +#include <asm/io.h> +#include <asm/sibyte/sb1250.h> +#include <asm/sibyte/bcm1480_regs.h> +#include <asm/sibyte/bcm1480_int.h> + +extern void smp_call_function_interrupt(void); + +/* + * These are routines for dealing with the bcm1480 smp capabilities + * independent of board/firmware + */ + +static void *mailbox_0_set_regs[] = { + IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), + IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), + IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), + IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), +}; + +static void *mailbox_0_clear_regs[] = { + IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), + IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), + IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), + IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), +}; + +static void *mailbox_0_regs[] = { + IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), + IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), + IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), + IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), +}; + +/* + * SMP init and finish on secondary CPUs + */ +void bcm1480_smp_init(void) +{ + unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | + STATUSF_IP1 | STATUSF_IP0; + + /* Set interrupt mask, but don't enable */ + change_c0_status(ST0_IM, imask); +} + +void bcm1480_smp_finish(void) +{ + extern void bcm1480_time_init(void); + bcm1480_time_init(); + local_irq_enable(); +} + +/* + * These are routines for dealing with the sb1250 smp capabilities + * independent of board/firmware + */ + +/* + * Simple enough; everything is set up, so just poke the appropriate mailbox + * register, and we should be set + */ +void core_send_ipi(int cpu, unsigned int action) +{ + __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]); +} + +void bcm1480_mailbox_interrupt(struct pt_regs *regs) +{ + int cpu = smp_processor_id(); + unsigned int action; + + kstat_this_cpu.irqs[K_BCM1480_INT_MBOX_0_0]++; + /* Load the mailbox register to figure out what we're supposed to do */ + action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff; + + /* Clear the mailbox to clear the interrupt */ + __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]); + + /* + * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the + * interrupt will do the reschedule for us + */ + + if (action & SMP_CALL_FUNCTION) + smp_call_function_interrupt(); +} diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c new file mode 100644 index 000000000000..e545752695a1 --- /dev/null +++ b/arch/mips/sibyte/bcm1480/time.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2000,2001,2004 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * These are routines to set up and handle interrupts from the + * bcm1480 general purpose timer 0. We're using the timer as a + * system clock, so we set it up to run at 100 Hz. On every + * interrupt, we update our idea of what the time of day is, + * then call do_timer() in the architecture-independent kernel + * code to do general bookkeeping (e.g. update jiffies, run + * bottom halves, etc.) + */ +#include <linux/config.h> +#include <linux/interrupt.h> +#include <linux/sched.h> +#include <linux/spinlock.h> +#include <linux/kernel_stat.h> + +#include <asm/irq.h> +#include <asm/ptrace.h> +#include <asm/addrspace.h> +#include <asm/time.h> +#include <asm/io.h> + +#include <asm/sibyte/bcm1480_regs.h> +#include <asm/sibyte/sb1250_regs.h> +#include <asm/sibyte/bcm1480_int.h> +#include <asm/sibyte/bcm1480_scd.h> + +#include <asm/sibyte/sb1250.h> + + +#define IMR_IP2_VAL K_BCM1480_INT_MAP_I0 +#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 +#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 + +extern int bcm1480_steal_irq(int irq); + +void bcm1480_time_init(void) +{ + int cpu = smp_processor_id(); + int irq = K_BCM1480_INT_TIMER_0+cpu; + + /* Only have 4 general purpose timers */ + if (cpu > 3) { + BUG(); + } + + if (!cpu) { + /* Use our own gettimeoffset() routine */ + do_gettimeoffset = bcm1480_gettimeoffset; + } + + bcm1480_mask_irq(cpu, irq); + + /* Map the timer interrupt to ip[4] of this cpu */ + __raw_writeq(IMR_IP4_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + + (irq<<3))); + + /* the general purpose timer ticks at 1 Mhz independent of the rest of the system */ + /* Disable the timer and set up the count */ + __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + __raw_writeq( +#ifndef CONFIG_SIMULATION + 1000000/HZ +#else + 50000/HZ +#endif + , IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); + + /* Set the timer running */ + __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + + bcm1480_unmask_irq(cpu, irq); + bcm1480_steal_irq(irq); + /* + * This interrupt is "special" in that it doesn't use the request_irq + * way to hook the irq line. The timer interrupt is initialized early + * enough to make this a major pain, and it's also firing enough to + * warrant a bit of special case code. bcm1480_timer_interrupt is + * called directly from irq_handler.S when IP[4] is set during an + * interrupt + */ +} + +#include <asm/sibyte/sb1250.h> + +void bcm1480_timer_interrupt(struct pt_regs *regs) +{ + int cpu = smp_processor_id(); + int irq = K_BCM1480_INT_TIMER_0+cpu; + + /* Reset the timer */ + __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + + /* + * CPU 0 handles the global timer interrupt job + */ + if (cpu == 0) { + ll_timer_interrupt(irq, regs); + } + + /* + * every CPU should do profiling and process accouting + */ + ll_local_timer_interrupt(irq, regs); +} + +/* + * We use our own do_gettimeoffset() instead of the generic one, + * because the generic one does not work for SMP case. + * In addition, since we use general timer 0 for system time, + * we can get accurate intra-jiffy offset without calibration. + */ +unsigned long bcm1480_gettimeoffset(void) +{ + unsigned long count = + __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT))); + + return 1000000/HZ - count; +} diff --git a/arch/mips/sibyte/cfe/smp.c b/arch/mips/sibyte/cfe/smp.c index e44ce1a9eea9..e8485124b8fc 100644 --- a/arch/mips/sibyte/cfe/smp.c +++ b/arch/mips/sibyte/cfe/smp.c @@ -70,8 +70,15 @@ void prom_boot_secondary(int cpu, struct task_struct *idle) */ void prom_init_secondary(void) { +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) + extern void bcm1480_smp_init(void); + bcm1480_smp_init(); +#elif defined(CONFIG_SIBYTE_SB1250) extern void sb1250_smp_init(void); sb1250_smp_init(); +#else +#error invalid SMP configuration +#endif } /* @@ -80,8 +87,15 @@ void prom_init_secondary(void) */ void prom_smp_finish(void) { +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) + extern void bcm1480_smp_finish(void); + bcm1480_smp_finish(); +#elif defined(CONFIG_SIBYTE_SB1250) extern void sb1250_smp_finish(void); sb1250_smp_finish(); +#else +#error invalid SMP configuration +#endif } /* diff --git a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c index 7f813ae9eaff..992e0d8dbb67 100644 --- a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c +++ b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c @@ -28,6 +28,8 @@ #include <linux/fs.h> #include <linux/errno.h> #include <linux/reboot.h> +#include <linux/smp_lock.h> +#include <linux/wait.h> #include <asm/uaccess.h> #include <asm/io.h> #include <asm/sibyte/sb1250.h> @@ -64,24 +66,25 @@ static void arm_tb(void) u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL; /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to trigger start of trace. XXX vary sampling period */ - bus_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); - scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG)); + __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); + scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); /* Unfortunately, in Pass 2 we must clear all counters to knock down a previous interrupt request. This means that bus profiling requires ALL of the SCD perf counters. */ - bus_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | // keep counters 0,2,3 as is - M_SPC_CFG_ENABLE | // enable counting - M_SPC_CFG_CLEAR | // clear all counters - V_SPC_CFG_SRC1(1), // counter 1 counts cycles - IOADDR(A_SCD_PERF_CNT_CFG)); - bus_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); + __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | + // keep counters 0,2,3 as is + M_SPC_CFG_ENABLE | // enable counting + M_SPC_CFG_CLEAR | // clear all counters + V_SPC_CFG_SRC1(1), // counter 1 counts cycles + IOADDR(A_SCD_PERF_CNT_CFG)); + __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); /* Reset the trace buffer */ - bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); + __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT) /* XXXKW may want to expose control to the data-collector */ tb_options |= M_SCD_TRACE_CFG_FORCECNT; #endif - bus_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG)); + __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG)); sbp.tb_armed = 1; } @@ -93,23 +96,30 @@ static irqreturn_t sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs) /* XXX should use XKPHYS to make writes bypass L2 */ u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++]; /* Read out trace */ - bus_writeq(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG)); + __raw_writeq(M_SCD_TRACE_CFG_START_READ, + IOADDR(A_SCD_TRACE_CFG)); __asm__ __volatile__ ("sync" : : : "memory"); /* Loop runs backwards because bundles are read out in reverse order */ for (i = 256 * 6; i > 0; i -= 6) { // Subscripts decrease to put bundle in the order // t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi - p[i-1] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 hi - p[i-2] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 lo - p[i-3] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 hi - p[i-4] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 lo - p[i-5] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 hi - p[i-6] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 lo + p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); + // read t2 hi + p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); + // read t2 lo + p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); + // read t1 hi + p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); + // read t1 lo + p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); + // read t0 hi + p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); + // read t0 lo } if (!sbp.tb_enable) { DBG(printk(DEVNAME ": tb_intr shutdown\n")); - bus_writeq(M_SCD_TRACE_CFG_RESET, - IOADDR(A_SCD_TRACE_CFG)); + __raw_writeq(M_SCD_TRACE_CFG_RESET, + IOADDR(A_SCD_TRACE_CFG)); sbp.tb_armed = 0; wake_up(&sbp.tb_sync); } else { @@ -118,7 +128,7 @@ static irqreturn_t sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs) } else { /* No more trace buffer samples */ DBG(printk(DEVNAME ": tb_intr full\n")); - bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); + __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); sbp.tb_armed = 0; if (!sbp.tb_enable) { wake_up(&sbp.tb_sync); @@ -152,13 +162,11 @@ int sbprof_zbprof_start(struct file *filp) return -EBUSY; } /* Make sure there isn't a perf-cnt interrupt waiting */ - scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG)); + scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); /* Disable and clear counters, override SRC_1 */ - bus_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) | - M_SPC_CFG_ENABLE | - M_SPC_CFG_CLEAR | - V_SPC_CFG_SRC1(1), - IOADDR(A_SCD_PERF_CNT_CFG)); + __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) | + M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1), + IOADDR(A_SCD_PERF_CNT_CFG)); /* We grab this interrupt to prevent others from trying to use it, even though we don't want to service the interrupts @@ -172,55 +180,55 @@ int sbprof_zbprof_start(struct file *filp) /* I need the core to mask these, but the interrupt mapper to pass them through. I am exploiting my knowledge that cp0_status masks out IP[5]. krw */ - bus_writeq(K_INT_MAP_I3, - IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + - (K_INT_PERF_CNT << 3))); + __raw_writeq(K_INT_MAP_I3, + IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + + (K_INT_PERF_CNT << 3))); /* Initialize address traps */ - bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_1)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_2)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_3)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3)); /* Initialize Trace Event 0-7 */ // when interrupt - bus_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0)); - bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1)); - bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2)); - bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3)); - bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4)); - bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5)); - bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6)); - bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7)); + __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7)); /* Initialize Trace Sequence 0-7 */ // Start on event 0 (interrupt) - bus_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff, - IOADDR(A_SCD_TRACE_SEQUENCE_0)); + __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff, + IOADDR(A_SCD_TRACE_SEQUENCE_0)); // dsamp when d used | asamp when a used - bus_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE | - K_SCD_TRSEQ_TRIGGER_ALL, - IOADDR(A_SCD_TRACE_SEQUENCE_1)); - bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2)); - bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3)); - bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4)); - bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5)); - bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6)); - bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); + __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE | + K_SCD_TRSEQ_TRIGGER_ALL, + IOADDR(A_SCD_TRACE_SEQUENCE_1)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */ - bus_writeq((1ULL << K_INT_PERF_CNT), - IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE))); + __raw_writeq(1ULL << K_INT_PERF_CNT, + IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE))); arm_tb(); @@ -231,6 +239,7 @@ int sbprof_zbprof_start(struct file *filp) int sbprof_zbprof_stop(void) { + DEFINE_WAIT(wait); DBG(printk(DEVNAME ": stopping\n")); if (sbp.tb_enable) { @@ -240,7 +249,9 @@ int sbprof_zbprof_stop(void) this sleep happens. */ if (sbp.tb_armed) { DBG(printk(DEVNAME ": wait for disarm\n")); - interruptible_sleep_on(&sbp.tb_sync); + prepare_to_wait(&sbp.tb_sync, &wait, TASK_INTERRUPTIBLE); + schedule(); + finish_wait(&sbp.tb_sync, &wait); DBG(printk(DEVNAME ": disarm complete\n")); } free_irq(K_INT_TRACE_FREEZE, &sbp); @@ -333,13 +344,13 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf, return count; } -static int sbprof_tb_ioctl(struct inode *inode, - struct file *filp, - unsigned int command, - unsigned long arg) +static long sbprof_tb_ioctl(struct file *filp, + unsigned int command, + unsigned long arg) { int error = 0; + lock_kernel(); switch (command) { case SBPROF_ZBSTART: error = sbprof_zbprof_start(filp); @@ -348,13 +359,17 @@ static int sbprof_tb_ioctl(struct inode *inode, error = sbprof_zbprof_stop(); break; case SBPROF_ZBWAITFULL: - interruptible_sleep_on(&sbp.tb_read); + DEFINE_WAIT(wait); + prepare_to_wait(&sbp.tb_read, &wait, TASK_INTERRUPTIBLE); + schedule(); + finish_wait(&sbp.tb_read, &wait); /* XXXKW check if interrupted? */ return put_user(TB_FULL, (int *) arg); default: error = -EINVAL; break; } + unlock_kernel(); return error; } @@ -364,7 +379,8 @@ static struct file_operations sbprof_tb_fops = { .open = sbprof_tb_open, .release = sbprof_tb_release, .read = sbprof_tb_read, - .ioctl = sbprof_tb_ioctl, + .unlocked_ioctl = sbprof_tb_ioctl, + .compat_ioctl = sbprof_tb_ioctl, .mmap = NULL, }; diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c index 1a97e3127aeb..482dee054e68 100644 --- a/arch/mips/sibyte/sb1250/bus_watcher.c +++ b/arch/mips/sibyte/sb1250/bus_watcher.c @@ -189,7 +189,7 @@ static irqreturn_t sibyte_bw_int(int irq, void *data, struct pt_regs *regs) for (i=0; i<256*6; i++) printk("%016llx\n", - (unsigned long long)bus_readq(IOADDR(A_SCD_TRACE_READ))); + (long long)__raw_readq(IOADDR(A_SCD_TRACE_READ))); csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG)); diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 2725b263cced..589537bfcc3d 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -53,7 +53,7 @@ static void disable_sb1250_irq(unsigned int irq); static unsigned int startup_sb1250_irq(unsigned int irq); static void ack_sb1250_irq(unsigned int irq); #ifdef CONFIG_SMP -static void sb1250_set_affinity(unsigned int irq, unsigned long mask); +static void sb1250_set_affinity(unsigned int irq, cpumask_t mask); #endif #ifdef CONFIG_SIBYTE_HAS_LDT @@ -71,17 +71,15 @@ extern char sb1250_duart_present[]; #endif static struct hw_interrupt_type sb1250_irq_type = { - "SB1250-IMR", - startup_sb1250_irq, - shutdown_sb1250_irq, - enable_sb1250_irq, - disable_sb1250_irq, - ack_sb1250_irq, - end_sb1250_irq, + .typename = "SB1250-IMR", + .startup = startup_sb1250_irq, + .shutdown = shutdown_sb1250_irq, + .enable = enable_sb1250_irq, + .disable = disable_sb1250_irq, + .ack = ack_sb1250_irq, + .end = end_sb1250_irq, #ifdef CONFIG_SMP - sb1250_set_affinity -#else - NULL + .set_affinity = sb1250_set_affinity #endif }; @@ -96,11 +94,11 @@ void sb1250_mask_irq(int cpu, int irq) u64 cur_ints; spin_lock_irqsave(&sb1250_imr_lock, flags); - cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + - R_IMR_INTERRUPT_MASK)); + cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); cur_ints |= (((u64) 1) << irq); - __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + - R_IMR_INTERRUPT_MASK)); + ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); spin_unlock_irqrestore(&sb1250_imr_lock, flags); } @@ -110,32 +108,25 @@ void sb1250_unmask_irq(int cpu, int irq) u64 cur_ints; spin_lock_irqsave(&sb1250_imr_lock, flags); - cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + - R_IMR_INTERRUPT_MASK)); + cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); cur_ints &= ~(((u64) 1) << irq); - __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + - R_IMR_INTERRUPT_MASK)); + ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); spin_unlock_irqrestore(&sb1250_imr_lock, flags); } #ifdef CONFIG_SMP -static void sb1250_set_affinity(unsigned int irq, unsigned long mask) +static void sb1250_set_affinity(unsigned int irq, cpumask_t mask) { int i = 0, old_cpu, cpu, int_on; u64 cur_ints; irq_desc_t *desc = irq_desc + irq; unsigned long flags; - while (mask) { - if (mask & 1) { - mask >>= 1; - break; - } - mask >>= 1; - i++; - } + i = first_cpu(mask); - if (mask) { + if (cpus_weight(mask) > 1) { printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq); return; } @@ -149,23 +140,23 @@ static void sb1250_set_affinity(unsigned int irq, unsigned long mask) /* Swizzle each CPU's IMR (but leave the IP selection alone) */ old_cpu = sb1250_irq_owner[irq]; - cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(old_cpu) + - R_IMR_INTERRUPT_MASK)); + cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) + + R_IMR_INTERRUPT_MASK)); int_on = !(cur_ints & (((u64) 1) << irq)); if (int_on) { /* If it was on, mask it */ cur_ints |= (((u64) 1) << irq); - __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + - R_IMR_INTERRUPT_MASK)); + ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + + R_IMR_INTERRUPT_MASK)); } sb1250_irq_owner[irq] = cpu; if (int_on) { /* unmask for the new CPU */ - cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + - R_IMR_INTERRUPT_MASK)); + cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); cur_ints &= ~(((u64) 1) << irq); - __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + - R_IMR_INTERRUPT_MASK)); + ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); } spin_unlock(&sb1250_imr_lock); spin_unlock_irqrestore(&desc->lock, flags); @@ -208,8 +199,8 @@ static void ack_sb1250_irq(unsigned int irq) * deliver the interrupts to all CPUs (which makes affinity * changing easier for us) */ - pending = bus_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], - R_IMR_LDT_INTERRUPT))); + pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], + R_IMR_LDT_INTERRUPT))); pending &= ((u64)1 << (irq)); if (pending) { int i; @@ -224,8 +215,8 @@ static void ack_sb1250_irq(unsigned int irq) * Clear for all CPUs so an affinity switch * doesn't find an old status */ - bus_writeq(pending, - IOADDR(A_IMR_REGISTER(cpu, + __raw_writeq(pending, + IOADDR(A_IMR_REGISTER(cpu, R_IMR_LDT_INTERRUPT_CLR))); } @@ -340,12 +331,14 @@ void __init arch_init_irq(void) /* Default everything to IP2 */ for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ - bus_writeq(IMR_IP2_VAL, - IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + - (i << 3))); - bus_writeq(IMR_IP2_VAL, - IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + - (i << 3))); + __raw_writeq(IMR_IP2_VAL, + IOADDR(A_IMR_REGISTER(0, + R_IMR_INTERRUPT_MAP_BASE) + + (i << 3))); + __raw_writeq(IMR_IP2_VAL, + IOADDR(A_IMR_REGISTER(1, + R_IMR_INTERRUPT_MAP_BASE) + + (i << 3))); } init_sb1250_irqs(); @@ -355,23 +348,23 @@ void __init arch_init_irq(void) * inter-cpu messages */ /* Was I1 */ - bus_writeq(IMR_IP3_VAL, - IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + - (K_INT_MBOX_0 << 3))); - bus_writeq(IMR_IP3_VAL, - IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + - (K_INT_MBOX_0 << 3))); + __raw_writeq(IMR_IP3_VAL, + IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + + (K_INT_MBOX_0 << 3))); + __raw_writeq(IMR_IP3_VAL, + IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + + (K_INT_MBOX_0 << 3))); /* Clear the mailboxes. The firmware may leave them dirty */ - bus_writeq(0xffffffffffffffffULL, - IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); - bus_writeq(0xffffffffffffffffULL, - IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); + __raw_writeq(0xffffffffffffffffULL, + IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); + __raw_writeq(0xffffffffffffffffULL, + IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); /* Mask everything except the mailbox registers for both cpus */ tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0); - bus_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); - bus_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); + __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); + __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); sb1250_steal_irq(K_INT_MBOX_0); @@ -396,12 +389,14 @@ void __init arch_init_irq(void) sb1250_duart_present[kgdb_port] = 0; #endif /* Setup uart 1 settings, mapper */ - bus_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port))); + __raw_writeq(M_DUART_IMR_BRK, + IOADDR(A_DUART_IMRREG(kgdb_port))); sb1250_steal_irq(kgdb_irq); - bus_writeq(IMR_IP6_VAL, - IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + - (kgdb_irq<<3))); + __raw_writeq(IMR_IP6_VAL, + IOADDR(A_IMR_REGISTER(0, + R_IMR_INTERRUPT_MAP_BASE) + + (kgdb_irq << 3))); sb1250_unmask_irq(0, kgdb_irq); } #endif diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c index f8c605be96c7..df2e266c700c 100644 --- a/arch/mips/sibyte/sb1250/setup.c +++ b/arch/mips/sibyte/sb1250/setup.c @@ -153,7 +153,7 @@ void sb1250_setup(void) int bad_config = 0; sb1_pass = read_c0_prid() & 0xff; - sys_rev = bus_readq(IOADDR(A_SCD_SYSTEM_REVISION)); + sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); soc_type = SYS_SOC_TYPE(sys_rev); soc_pass = G_SYS_REVISION(sys_rev); @@ -162,7 +162,7 @@ void sb1250_setup(void) machine_restart(NULL); } - plldiv = G_SYS_PLL_DIV(bus_readq(IOADDR(A_SCD_SYSTEM_CFG))); + plldiv = G_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25); prom_printf("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n", diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c index be91b3990952..f859db02d3c9 100644 --- a/arch/mips/sibyte/sb1250/smp.c +++ b/arch/mips/sibyte/sb1250/smp.c @@ -29,18 +29,18 @@ #include <asm/sibyte/sb1250_int.h> static void *mailbox_set_regs[] = { - (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU), - (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU) + IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU), + IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU) }; static void *mailbox_clear_regs[] = { - (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU), - (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU) + IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU), + IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU) }; static void *mailbox_regs[] = { - (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU), - (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU) + IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU), + IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU) }; /* @@ -73,7 +73,7 @@ void sb1250_smp_finish(void) */ void core_send_ipi(int cpu, unsigned int action) { - bus_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); + __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); } void sb1250_mailbox_interrupt(struct pt_regs *regs) @@ -83,10 +83,10 @@ void sb1250_mailbox_interrupt(struct pt_regs *regs) kstat_this_cpu.irqs[K_INT_MBOX_0]++; /* Load the mailbox register to figure out what we're supposed to do */ - action = (__bus_readq(mailbox_regs[cpu]) >> 48) & 0xffff; + action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff; /* Clear the mailbox to clear the interrupt */ - __bus_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]); + ____raw_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]); /* * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c index 8b4c848c907b..511c89d65f38 100644 --- a/arch/mips/sibyte/sb1250/time.c +++ b/arch/mips/sibyte/sb1250/time.c @@ -67,24 +67,24 @@ void sb1250_time_init(void) sb1250_mask_irq(cpu, irq); /* Map the timer interrupt to ip[4] of this cpu */ - bus_writeq(IMR_IP4_VAL, - IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + - (irq << 3))); + __raw_writeq(IMR_IP4_VAL, + IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + + (irq << 3))); /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */ /* Disable the timer and set up the count */ - bus_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); #ifdef CONFIG_SIMULATION - bus_writeq(50000 / HZ, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); + __raw_writeq(50000 / HZ, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #else - bus_writeq(1000000/HZ, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); + __raw_writeq(1000000 / HZ, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #endif /* Set the timer running */ - bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); sb1250_unmask_irq(cpu, irq); sb1250_steal_irq(irq); @@ -100,25 +100,25 @@ void sb1250_time_init(void) void sb1250_timer_interrupt(struct pt_regs *regs) { - extern asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs); int cpu = smp_processor_id(); int irq = K_INT_TIMER_0 + cpu; /* Reset the timer */ - __bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); - /* - * CPU 0 handles the global timer interrupt job - */ if (cpu == 0) { + /* + * CPU 0 handles the global timer interrupt job + */ ll_timer_interrupt(irq, regs); } - - /* - * every CPU should do profiling and process accouting - */ - ll_local_timer_interrupt(irq, regs); + else { + /* + * other CPUs should just do profiling and process accounting + */ + ll_local_timer_interrupt(irq, regs); + } } /* @@ -130,7 +130,7 @@ void sb1250_timer_interrupt(struct pt_regs *regs) unsigned long sb1250_gettimeoffset(void) { unsigned long count = - bus_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT))); + __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT))); return 1000000/HZ - count; } diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c index a686bb716ec6..5b4fc26c1b36 100644 --- a/arch/mips/sibyte/swarm/rtc_m41t81.c +++ b/arch/mips/sibyte/swarm/rtc_m41t81.c @@ -82,59 +82,60 @@ #define M41T81REG_SQW 0x13 /* square wave register */ #define M41T81_CCR_ADDRESS 0x68 -#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg)))) + +#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg)) static int m41t81_read(uint8_t addr) { - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); - bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE), - SMB_CSR(R_SMB_START)); + __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); + __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), - SMB_CSR(R_SMB_START)); + __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } - return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); + return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); } static int m41t81_write(uint8_t addr, int b) { - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq((addr & 0xFF), SMB_CSR(R_SMB_CMD)); - bus_writeq((b & 0xff), SMB_CSR(R_SMB_DATA)); - bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, - SMB_CSR(R_SMB_START)); + __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); + __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA)); + __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } /* read the same byte again to make sure it is written */ - bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, - SMB_CSR(R_SMB_START)); + __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; return 0; diff --git a/arch/mips/sibyte/swarm/rtc_xicor1241.c b/arch/mips/sibyte/swarm/rtc_xicor1241.c index 981d21f16e64..d9ff9323f24e 100644 --- a/arch/mips/sibyte/swarm/rtc_xicor1241.c +++ b/arch/mips/sibyte/swarm/rtc_xicor1241.c @@ -57,52 +57,52 @@ #define X1241_CCR_ADDRESS 0x6F -#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg)))) +#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg)) static int xicor_read(uint8_t addr) { - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); - bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); - bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), - SMB_CSR(R_SMB_START)); + __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); + __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA)); + __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), - SMB_CSR(R_SMB_START)); + __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } - return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); + return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); } static int xicor_write(uint8_t addr, int b) { - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq(addr, SMB_CSR(R_SMB_CMD)); - bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); - bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, - SMB_CSR(R_SMB_START)); + __raw_writeq(addr, SMB_CSR(R_SMB_CMD)); + __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); + __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } else { return 0; diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 4daeaa413def..b614ca0ddb69 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation + * Copyright (C) 2000, 2001, 2002, 2003, 2004 Broadcom Corporation * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) * * This program is free software; you can redistribute it and/or @@ -39,11 +39,23 @@ #include <asm/time.h> #include <asm/traps.h> #include <asm/sibyte/sb1250.h> +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +#include <asm/sibyte/bcm1480_regs.h> +#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) #include <asm/sibyte/sb1250_regs.h> +#else +#error invalid SiByte board configuation +#endif #include <asm/sibyte/sb1250_genbus.h> #include <asm/sibyte/board.h> +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +extern void bcm1480_setup(void); +#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) extern void sb1250_setup(void); +#else +#error invalid SiByte board configuation +#endif extern int xicor_probe(void); extern int xicor_set_time(unsigned long); @@ -66,27 +78,34 @@ void __init swarm_timer_setup(struct irqaction *irq) */ /* We only need to setup the generic timer */ - sb1250_time_init(); +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) + bcm1480_time_init(); +#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) + sb1250_time_init(); +#else +#error invalid SiByte board configuation +#endif } int swarm_be_handler(struct pt_regs *regs, int is_fixup) { if (!is_fixup && (regs->cp0_cause & 4)) { /* Data bus error - print PA */ -#ifdef CONFIG_64BIT - printk("DBE physical address: %010lx\n", + printk("DBE physical address: %010Lx\n", __read_64bit_c0_register($26, 1)); -#else - printk("DBE physical address: %010llx\n", - __read_64bit_c0_split($26, 1)); -#endif } return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL); } -static int __init swarm_setup(void) +void __init plat_setup(void) { +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) + bcm1480_setup(); +#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) sb1250_setup(); +#else +#error invalid SiByte board configuation +#endif panic_timeout = 5; /* For debug. */ @@ -133,12 +152,8 @@ static int __init swarm_setup(void) }; /* XXXKW for CFE, get lines/cols from environment */ #endif - - return 0; } -early_initcall(swarm_setup); - #ifdef LEDS_PHYS #ifdef CONFIG_SIBYTE_CARMEL diff --git a/arch/mips/sibyte/swarm/time.c b/arch/mips/sibyte/swarm/time.c index c1f1a9defeeb..97c73c793c35 100644 --- a/arch/mips/sibyte/swarm/time.c +++ b/arch/mips/sibyte/swarm/time.c @@ -79,48 +79,48 @@ static unsigned int usec_bias = 0; static int xicor_read(uint8_t addr) { - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); - bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); - bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), - SMB_CSR(R_SMB_START)); + __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); + __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA)); + __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), - SMB_CSR(R_SMB_START)); + __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } - return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); + return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); } static int xicor_write(uint8_t addr, int b) { - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq(addr, SMB_CSR(R_SMB_CMD)); - bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); - bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, - SMB_CSR(R_SMB_START)); + __raw_writeq(addr, SMB_CSR(R_SMB_CMD)); + __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); + __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } else { return 0; @@ -228,8 +228,8 @@ void __init swarm_time_init(void) /* Establish communication with the Xicor 1241 RTC */ /* XXXKW how do I share the SMBus with the I2C subsystem? */ - bus_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ)); - bus_writeq(0, SMB_CSR(R_SMB_CONTROL)); + __raw_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ)); + __raw_writeq(0, SMB_CSR(R_SMB_CONTROL)); if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) { printk("x1241: couldn't detect on SWARM SMBus 1\n"); diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c index 141a310d74d8..952038aa4b90 100644 --- a/arch/mips/sni/irq.c +++ b/arch/mips/sni/irq.c @@ -58,14 +58,13 @@ static void end_pciasic_irq(unsigned int irq) } static struct hw_interrupt_type pciasic_irq_type = { - "ASIC-PCI", - startup_pciasic_irq, - shutdown_pciasic_irq, - enable_pciasic_irq, - disable_pciasic_irq, - mask_and_ack_pciasic_irq, - end_pciasic_irq, - NULL + .typename = "ASIC-PCI", + .startup = startup_pciasic_irq, + .shutdown = shutdown_pciasic_irq, + .enable = enable_pciasic_irq, + .disable = disable_pciasic_irq, + .ack = mask_and_ack_pciasic_irq, + .end = end_pciasic_irq, }; /* diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c index 1b3f8a0903e1..262c85680709 100644 --- a/arch/mips/sni/setup.c +++ b/arch/mips/sni/setup.c @@ -167,7 +167,7 @@ static inline void sni_pcimt_time_init(void) rtc_set_time = mc146818_set_rtc_mmss; } -static int __init sni_rm200_pci_setup(void) +void __init plat_setup(void) { sni_pcimt_detect(); sni_pcimt_sc_init(); @@ -196,8 +196,4 @@ static int __init sni_rm200_pci_setup(void) #ifdef CONFIG_PCI register_pci_controller(&sni_controller); #endif - - return 0; } - -early_initcall(sni_rm200_pci_setup); diff --git a/arch/mips/tx4927/Kconfig b/arch/mips/tx4927/Kconfig new file mode 100644 index 000000000000..5fbbe12e0fc1 --- /dev/null +++ b/arch/mips/tx4927/Kconfig @@ -0,0 +1,3 @@ +config TOSHIBA_FPCIB0 + bool "FPCIB0 Backplane Support" + depends on TOSHIBA_RBTX4927 diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c index 26d7c53612a8..77c3b66fb959 100644 --- a/arch/mips/tx4927/common/tx4927_setup.c +++ b/arch/mips/tx4927/common/tx4927_setup.c @@ -64,7 +64,7 @@ static void tx4927_write_buffer_flush(void) } -static void __init tx4927_setup(void) +void __init plat_setup(void) { board_time_init = tx4927_time_init; board_timer_setup = tx4927_timer_setup; @@ -76,12 +76,8 @@ static void __init tx4927_setup(void) toshiba_rbtx4927_setup(); } #endif - - return; } -early_initcall(tx4927_setup); - void __init tx4927_time_init(void) { diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c index fc0720599fd9..990fcb294bab 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c @@ -77,6 +77,11 @@ #include <linux/hdreg.h> #include <linux/ide.h> #endif +#ifdef CONFIG_SERIAL_TXX9 +#include <linux/tty.h> +#include <linux/serial.h> +#include <linux/serial_core.h> +#endif #undef TOSHIBA_RBTX4927_SETUP_DEBUG @@ -920,12 +925,30 @@ void __init toshiba_rbtx4927_setup(void) #endif /* CONFIG_PCI */ +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + int i; + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (char *)(0xff1ff300 + i * 0x100); + req.mapbase = 0xff1ff300 + i * 0x100; + req.irq = 32 + i; + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = 50000000; + early_serial_txx9_setup(&req); + } + } #ifdef CONFIG_SERIAL_TXX9_CONSOLE argptr = prom_getcmdline(); if (strstr(argptr, "console=") == NULL) { strcat(argptr, " console=ttyS0,38400"); } #endif +#endif #ifdef CONFIG_ROOT_NFS argptr = prom_getcmdline(); diff --git a/arch/mips/tx4938/Kconfig b/arch/mips/tx4938/Kconfig new file mode 100644 index 000000000000..d90e9cd85138 --- /dev/null +++ b/arch/mips/tx4938/Kconfig @@ -0,0 +1,24 @@ +if TOSHIBA_RBTX4938 + +comment "Multiplex Pin Select" +choice + prompt "PIO[58:61]" + default TOSHIBA_RBTX4938_MPLEX_PIO58_61 + +config TOSHIBA_RBTX4938_MPLEX_PIO58_61 + bool "PIO" +config TOSHIBA_RBTX4938_MPLEX_NAND + bool "NAND" +config TOSHIBA_RBTX4938_MPLEX_ATA + bool "ATA" + +endchoice + +config TX4938_NAND_BOOT + depends on EXPERIMENTAL && TOSHIBA_RBTX4938_MPLEX_NAND + bool "NAND Boot Support (EXPERIMENTAL)" + help + This is only for Toshiba RBTX4938 reference board, which has NAND IPL. + Select this option if you need to use NAND boot. + +endif diff --git a/arch/mips/tx4938/common/Makefile b/arch/mips/tx4938/common/Makefile new file mode 100644 index 000000000000..74c95c5bcdbf --- /dev/null +++ b/arch/mips/tx4938/common/Makefile @@ -0,0 +1,11 @@ +# +# Makefile for common code for Toshiba TX4927 based systems +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +obj-y += prom.o setup.o irq.o irq_handler.o rtc_rx5c348.o +obj-$(CONFIG_KGDB) += dbgio.o + diff --git a/arch/mips/tx4938/common/dbgio.c b/arch/mips/tx4938/common/dbgio.c new file mode 100644 index 000000000000..bea59ff1842a --- /dev/null +++ b/arch/mips/tx4938/common/dbgio.c @@ -0,0 +1,50 @@ +/* + * linux/arch/mips/tx4938/common/dbgio.c + * + * kgdb interface for gdb + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Support for TX4938 in 2.6 - Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp> + */ + +#include <asm/mipsregs.h> +#include <asm/system.h> +#include <asm/tx4938/tx4938_mips.h> + +extern u8 txx9_sio_kdbg_rd(void); +extern int txx9_sio_kdbg_wr( u8 ch ); + +u8 getDebugChar(void) +{ + return (txx9_sio_kdbg_rd()); +} + +int putDebugChar(u8 byte) +{ + return (txx9_sio_kdbg_wr(byte)); +} + diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c new file mode 100644 index 000000000000..4f90d7faf634 --- /dev/null +++ b/arch/mips/tx4938/common/irq.c @@ -0,0 +1,424 @@ +/* + * linux/arch/mps/tx4938/common/irq.c + * + * Common tx4938 irq handler + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kernel_stat.h> +#include <linux/module.h> +#include <linux/signal.h> +#include <linux/sched.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/timex.h> +#include <linux/slab.h> +#include <linux/random.h> +#include <linux/irq.h> +#include <asm/bitops.h> +#include <asm/bootinfo.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/mipsregs.h> +#include <asm/system.h> +#include <asm/tx4938/rbtx4938.h> + +/**********************************************************************************/ +/* Forwad definitions for all pic's */ +/**********************************************************************************/ + +static unsigned int tx4938_irq_cp0_startup(unsigned int irq); +static void tx4938_irq_cp0_shutdown(unsigned int irq); +static void tx4938_irq_cp0_enable(unsigned int irq); +static void tx4938_irq_cp0_disable(unsigned int irq); +static void tx4938_irq_cp0_mask_and_ack(unsigned int irq); +static void tx4938_irq_cp0_end(unsigned int irq); + +static unsigned int tx4938_irq_pic_startup(unsigned int irq); +static void tx4938_irq_pic_shutdown(unsigned int irq); +static void tx4938_irq_pic_enable(unsigned int irq); +static void tx4938_irq_pic_disable(unsigned int irq); +static void tx4938_irq_pic_mask_and_ack(unsigned int irq); +static void tx4938_irq_pic_end(unsigned int irq); + +/**********************************************************************************/ +/* Kernel structs for all pic's */ +/**********************************************************************************/ +DEFINE_SPINLOCK(tx4938_cp0_lock); +DEFINE_SPINLOCK(tx4938_pic_lock); + +#define TX4938_CP0_NAME "TX4938-CP0" +static struct hw_interrupt_type tx4938_irq_cp0_type = { + .typename = TX4938_CP0_NAME, + .startup = tx4938_irq_cp0_startup, + .shutdown = tx4938_irq_cp0_shutdown, + .enable = tx4938_irq_cp0_enable, + .disable = tx4938_irq_cp0_disable, + .ack = tx4938_irq_cp0_mask_and_ack, + .end = tx4938_irq_cp0_end, + .set_affinity = NULL +}; + +#define TX4938_PIC_NAME "TX4938-PIC" +static struct hw_interrupt_type tx4938_irq_pic_type = { + .typename = TX4938_PIC_NAME, + .startup = tx4938_irq_pic_startup, + .shutdown = tx4938_irq_pic_shutdown, + .enable = tx4938_irq_pic_enable, + .disable = tx4938_irq_pic_disable, + .ack = tx4938_irq_pic_mask_and_ack, + .end = tx4938_irq_pic_end, + .set_affinity = NULL +}; + +static struct irqaction tx4938_irq_pic_action = { + .handler = no_action, + .flags = 0, + .mask = CPU_MASK_NONE, + .name = TX4938_PIC_NAME +}; + +/**********************************************************************************/ +/* Functions for cp0 */ +/**********************************************************************************/ + +#define tx4938_irq_cp0_mask(irq) ( 1 << ( irq-TX4938_IRQ_CP0_BEG+8 ) ) + +static void __init +tx4938_irq_cp0_init(void) +{ + int i; + + for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = &tx4938_irq_cp0_type; + } + + return; +} + +static unsigned int +tx4938_irq_cp0_startup(unsigned int irq) +{ + tx4938_irq_cp0_enable(irq); + + return (0); +} + +static void +tx4938_irq_cp0_shutdown(unsigned int irq) +{ + tx4938_irq_cp0_disable(irq); +} + +static void +tx4938_irq_cp0_enable(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&tx4938_cp0_lock, flags); + + set_c0_status(tx4938_irq_cp0_mask(irq)); + + spin_unlock_irqrestore(&tx4938_cp0_lock, flags); +} + +static void +tx4938_irq_cp0_disable(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&tx4938_cp0_lock, flags); + + clear_c0_status(tx4938_irq_cp0_mask(irq)); + + spin_unlock_irqrestore(&tx4938_cp0_lock, flags); + + return; +} + +static void +tx4938_irq_cp0_mask_and_ack(unsigned int irq) +{ + tx4938_irq_cp0_disable(irq); + + return; +} + +static void +tx4938_irq_cp0_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + tx4938_irq_cp0_enable(irq); + } + + return; +} + +/**********************************************************************************/ +/* Functions for pic */ +/**********************************************************************************/ + +u32 +tx4938_irq_pic_addr(int irq) +{ + /* MVMCP -- need to formulize this */ + irq -= TX4938_IRQ_PIC_BEG; + + switch (irq) { + case 17: + case 16: + case 1: + case 0:{ + return (TX4938_MKA(TX4938_IRC_IRLVL0)); + } + case 19: + case 18: + case 3: + case 2:{ + return (TX4938_MKA(TX4938_IRC_IRLVL1)); + } + case 21: + case 20: + case 5: + case 4:{ + return (TX4938_MKA(TX4938_IRC_IRLVL2)); + } + case 23: + case 22: + case 7: + case 6:{ + return (TX4938_MKA(TX4938_IRC_IRLVL3)); + } + case 25: + case 24: + case 9: + case 8:{ + return (TX4938_MKA(TX4938_IRC_IRLVL4)); + } + case 27: + case 26: + case 11: + case 10:{ + return (TX4938_MKA(TX4938_IRC_IRLVL5)); + } + case 29: + case 28: + case 13: + case 12:{ + return (TX4938_MKA(TX4938_IRC_IRLVL6)); + } + case 31: + case 30: + case 15: + case 14:{ + return (TX4938_MKA(TX4938_IRC_IRLVL7)); + } + } + + return (0); +} + +u32 +tx4938_irq_pic_mask(int irq) +{ + /* MVMCP -- need to formulize this */ + irq -= TX4938_IRQ_PIC_BEG; + + switch (irq) { + case 31: + case 29: + case 27: + case 25: + case 23: + case 21: + case 19: + case 17:{ + return (0x07000000); + } + case 30: + case 28: + case 26: + case 24: + case 22: + case 20: + case 18: + case 16:{ + return (0x00070000); + } + case 15: + case 13: + case 11: + case 9: + case 7: + case 5: + case 3: + case 1:{ + return (0x00000700); + } + case 14: + case 12: + case 10: + case 8: + case 6: + case 4: + case 2: + case 0:{ + return (0x00000007); + } + } + return (0x00000000); +} + +static void +tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits) +{ + unsigned long val = 0; + + val = TX4938_RD(pic_reg); + val &= (~clr_bits); + val |= (set_bits); + TX4938_WR(pic_reg, val); + mmiowb(); + TX4938_RD(pic_reg); + + return; +} + +static void __init +tx4938_irq_pic_init(void) +{ + unsigned long flags; + int i; + + for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 2; + irq_desc[i].handler = &tx4938_irq_pic_type; + } + + setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action); + + spin_lock_irqsave(&tx4938_pic_lock, flags); + + TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */ + TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */ + + spin_unlock_irqrestore(&tx4938_pic_lock, flags); + + return; +} + +static unsigned int +tx4938_irq_pic_startup(unsigned int irq) +{ + tx4938_irq_pic_enable(irq); + + return (0); +} + +static void +tx4938_irq_pic_shutdown(unsigned int irq) +{ + tx4938_irq_pic_disable(irq); + + return; +} + +static void +tx4938_irq_pic_enable(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&tx4938_pic_lock, flags); + + tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0, + tx4938_irq_pic_mask(irq)); + + spin_unlock_irqrestore(&tx4938_pic_lock, flags); + + return; +} + +static void +tx4938_irq_pic_disable(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&tx4938_pic_lock, flags); + + tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), + tx4938_irq_pic_mask(irq), 0); + + spin_unlock_irqrestore(&tx4938_pic_lock, flags); + + return; +} + +static void +tx4938_irq_pic_mask_and_ack(unsigned int irq) +{ + tx4938_irq_pic_disable(irq); + + return; +} + +static void +tx4938_irq_pic_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + tx4938_irq_pic_enable(irq); + } + + return; +} + +/**********************************************************************************/ +/* Main init functions */ +/**********************************************************************************/ + +void __init +tx4938_irq_init(void) +{ + extern asmlinkage void tx4938_irq_handler(void); + + tx4938_irq_cp0_init(); + tx4938_irq_pic_init(); + set_except_vector(0, tx4938_irq_handler); + + return; +} + +int +tx4938_irq_nested(void) +{ + int sw_irq = 0; + u32 level2; + + level2 = TX4938_RD(0xff1ff6a0); + if ((level2 & 0x10000) == 0) { + level2 &= 0x1f; + sw_irq = TX4938_IRQ_PIC_BEG + level2; + if (sw_irq == 26) { + { + extern int toshiba_rbtx4938_irq_nested(int sw_irq); + sw_irq = toshiba_rbtx4938_irq_nested(sw_irq); + } + } + } + + wbflush(); + return (sw_irq); +} diff --git a/arch/mips/tx4938/common/irq_handler.S b/arch/mips/tx4938/common/irq_handler.S new file mode 100644 index 000000000000..1b2f72bac42d --- /dev/null +++ b/arch/mips/tx4938/common/irq_handler.S @@ -0,0 +1,84 @@ +/* + * linux/arch/mips/tx4938/common/handler.S + * + * Primary interrupt handler for tx4938 based systems + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include <asm/asm.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/regdef.h> +#include <asm/stackframe.h> +#include <asm/tx4938/rbtx4938.h> + + + .align 5 + NESTED(tx4938_irq_handler, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + + mfc0 t0, CP0_CAUSE + mfc0 t1, CP0_STATUS + and t0, t1 + + andi t1, t0, STATUSF_IP7 /* cpu timer */ + bnez t1, ll_ip7 + + /* IP6..IP3 multiplexed -- do not use */ + + andi t1, t0, STATUSF_IP2 /* tx4938 pic */ + bnez t1, ll_ip2 + + andi t1, t0, STATUSF_IP1 /* user line 1 */ + bnez t1, ll_ip1 + + andi t1, t0, STATUSF_IP0 /* user line 0 */ + bnez t1, ll_ip0 + + .set reorder + + nop + END(tx4938_irq_handler) + + .align 5 + + +ll_ip7: + li a0, TX4938_IRQ_CPU_TIMER + move a1, sp + jal do_IRQ + j ret_from_irq + + +ll_ip2: + jal tx4938_irq_nested + nop + beqz v0, goto_spurious_interrupt + nop + move a0, v0 + move a1, sp + jal do_IRQ + j ret_from_irq + +goto_spurious_interrupt: + j ret_from_irq + +ll_ip1: + li a0, TX4938_IRQ_USER1 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_ip0: + li a0, TX4938_IRQ_USER0 + move a1, sp + jal do_IRQ + j ret_from_irq diff --git a/arch/mips/tx4938/common/prom.c b/arch/mips/tx4938/common/prom.c new file mode 100644 index 000000000000..3189a65f7d7e --- /dev/null +++ b/arch/mips/tx4938/common/prom.c @@ -0,0 +1,129 @@ +/* + * linux/arch/mips/tx4938/common/prom.c + * + * common tx4938 memory interface + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/bootmem.h> + +#include <asm/addrspace.h> +#include <asm/bootinfo.h> +#include <asm/tx4938/tx4938.h> + +static unsigned int __init +tx4938_process_sdccr(u64 * addr) +{ + u64 val; + unsigned int sdccr_ce; + unsigned int sdccr_rs; + unsigned int sdccr_cs; + unsigned int sdccr_mw; + unsigned int rs = 0; + unsigned int cs = 0; + unsigned int mw = 0; + unsigned int bc = 4; + unsigned int msize = 0; + + val = (*((vu64 *) (addr))); + + /* MVMCP -- need #defs for these bits masks */ + sdccr_ce = ((val & (1 << 10)) >> 10); + sdccr_rs = ((val & (3 << 5)) >> 5); + sdccr_cs = ((val & (7 << 2)) >> 2); + sdccr_mw = ((val & (1 << 0)) >> 0); + + if (sdccr_ce) { + switch (sdccr_rs) { + case 0:{ + rs = 2048; + break; + } + case 1:{ + rs = 4096; + break; + } + case 2:{ + rs = 8192; + break; + } + default:{ + rs = 0; + break; + } + } + switch (sdccr_cs) { + case 0:{ + cs = 256; + break; + } + case 1:{ + cs = 512; + break; + } + case 2:{ + cs = 1024; + break; + } + case 3:{ + cs = 2048; + break; + } + case 4:{ + cs = 4096; + break; + } + default:{ + cs = 0; + break; + } + } + switch (sdccr_mw) { + case 0:{ + mw = 8; + break; + } /* 8 bytes = 64 bits */ + case 1:{ + mw = 4; + break; + } /* 4 bytes = 32 bits */ + } + } + + /* bytes per chip MB per chip bank count */ + msize = (((rs * cs * mw) / (1024 * 1024)) * (bc)); + + /* MVMCP -- bc hard coded to 4 from table 9.3.1 */ + /* boad supports bc=2 but no way to detect */ + + return (msize); +} + +unsigned int __init +tx4938_get_mem_size(void) +{ + unsigned int c0; + unsigned int c1; + unsigned int c2; + unsigned int c3; + unsigned int total; + + /* MVMCP -- need #defs for these registers */ + c0 = tx4938_process_sdccr((u64 *) 0xff1f8000); + c1 = tx4938_process_sdccr((u64 *) 0xff1f8008); + c2 = tx4938_process_sdccr((u64 *) 0xff1f8010); + c3 = tx4938_process_sdccr((u64 *) 0xff1f8018); + total = c0 + c1 + c2 + c3; + + return (total); +} diff --git a/arch/mips/tx4938/common/rtc_rx5c348.c b/arch/mips/tx4938/common/rtc_rx5c348.c new file mode 100644 index 000000000000..d249edbb6af4 --- /dev/null +++ b/arch/mips/tx4938/common/rtc_rx5c348.c @@ -0,0 +1,202 @@ +/* + * RTC routines for RICOH Rx5C348 SPI chip. + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/rtc.h> +#include <linux/time.h> +#include <asm/time.h> +#include <asm/tx4938/spi.h> + +#define EPOCH 2000 + +/* registers */ +#define Rx5C348_REG_SECOND 0 +#define Rx5C348_REG_MINUTE 1 +#define Rx5C348_REG_HOUR 2 +#define Rx5C348_REG_WEEK 3 +#define Rx5C348_REG_DAY 4 +#define Rx5C348_REG_MONTH 5 +#define Rx5C348_REG_YEAR 6 +#define Rx5C348_REG_ADJUST 7 +#define Rx5C348_REG_ALARM_W_MIN 8 +#define Rx5C348_REG_ALARM_W_HOUR 9 +#define Rx5C348_REG_ALARM_W_WEEK 10 +#define Rx5C348_REG_ALARM_D_MIN 11 +#define Rx5C348_REG_ALARM_D_HOUR 12 +#define Rx5C348_REG_CTL1 14 +#define Rx5C348_REG_CTL2 15 + +/* register bits */ +#define Rx5C348_BIT_PM 0x20 /* REG_HOUR */ +#define Rx5C348_BIT_Y2K 0x80 /* REG_MONTH */ +#define Rx5C348_BIT_24H 0x20 /* REG_CTL1 */ +#define Rx5C348_BIT_XSTP 0x10 /* REG_CTL2 */ + +/* commands */ +#define Rx5C348_CMD_W(addr) (((addr) << 4) | 0x08) /* single write */ +#define Rx5C348_CMD_R(addr) (((addr) << 4) | 0x0c) /* single read */ +#define Rx5C348_CMD_MW(addr) (((addr) << 4) | 0x00) /* burst write */ +#define Rx5C348_CMD_MR(addr) (((addr) << 4) | 0x04) /* burst read */ + +static struct spi_dev_desc srtc_dev_desc = { + .baud = 1000000, /* 1.0Mbps @ Vdd 2.0V */ + .tcss = 31, + .tcsh = 1, + .tcsr = 62, + /* 31us for Tcss (62us for Tcsr) is required for carry operation) */ + .byteorder = 1, /* MSB-First */ + .polarity = 0, /* High-Active */ + .phase = 1, /* Shift-Then-Sample */ + +}; +static int srtc_chipid; +static int srtc_24h; + +static inline int +spi_rtc_io(unsigned char *inbuf, unsigned char *outbuf, unsigned int count) +{ + unsigned char *inbufs[1], *outbufs[1]; + unsigned int incounts[2], outcounts[2]; + inbufs[0] = inbuf; + incounts[0] = count; + incounts[1] = 0; + outbufs[0] = outbuf; + outcounts[0] = count; + outcounts[1] = 0; + return txx9_spi_io(srtc_chipid, &srtc_dev_desc, + inbufs, incounts, outbufs, outcounts, 0); +} + +/* + * Conversion between binary and BCD. + */ +#ifndef BCD_TO_BIN +#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) +#endif + +#ifndef BIN_TO_BCD +#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) +#endif + +/* RTC-dependent code for time.c */ + +static int +rtc_rx5c348_set_time(unsigned long t) +{ + unsigned char inbuf[8]; + struct rtc_time tm; + u8 year, month, day, hour, minute, second, century; + + /* convert */ + to_tm(t, &tm); + + year = tm.tm_year % 100; + month = tm.tm_mon+1; /* tm_mon starts from 0 to 11 */ + day = tm.tm_mday; + hour = tm.tm_hour; + minute = tm.tm_min; + second = tm.tm_sec; + century = tm.tm_year / 100; + + inbuf[0] = Rx5C348_CMD_MW(Rx5C348_REG_SECOND); + BIN_TO_BCD(second); + inbuf[1] = second; + BIN_TO_BCD(minute); + inbuf[2] = minute; + + if (srtc_24h) { + BIN_TO_BCD(hour); + inbuf[3] = hour; + } else { + /* hour 0 is AM12, noon is PM12 */ + inbuf[3] = 0; + if (hour >= 12) + inbuf[3] = Rx5C348_BIT_PM; + hour = (hour + 11) % 12 + 1; + BIN_TO_BCD(hour); + inbuf[3] |= hour; + } + inbuf[4] = 0; /* ignore week */ + BIN_TO_BCD(day); + inbuf[5] = day; + BIN_TO_BCD(month); + inbuf[6] = month; + if (century >= 20) + inbuf[6] |= Rx5C348_BIT_Y2K; + BIN_TO_BCD(year); + inbuf[7] = year; + /* write in one transfer to avoid data inconsistency */ + return spi_rtc_io(inbuf, NULL, 8); +} + +static unsigned long +rtc_rx5c348_get_time(void) +{ + unsigned char inbuf[8], outbuf[8]; + unsigned int year, month, day, hour, minute, second; + + inbuf[0] = Rx5C348_CMD_MR(Rx5C348_REG_SECOND); + memset(inbuf + 1, 0, 7); + /* read in one transfer to avoid data inconsistency */ + if (spi_rtc_io(inbuf, outbuf, 8)) + return 0; + second = outbuf[1]; + BCD_TO_BIN(second); + minute = outbuf[2]; + BCD_TO_BIN(minute); + if (srtc_24h) { + hour = outbuf[3]; + BCD_TO_BIN(hour); + } else { + hour = outbuf[3] & ~Rx5C348_BIT_PM; + BCD_TO_BIN(hour); + hour %= 12; + if (outbuf[3] & Rx5C348_BIT_PM) + hour += 12; + } + day = outbuf[5]; + BCD_TO_BIN(day); + month = outbuf[6] & ~Rx5C348_BIT_Y2K; + BCD_TO_BIN(month); + year = outbuf[7]; + BCD_TO_BIN(year); + year += EPOCH; + + return mktime(year, month, day, hour, minute, second); +} + +void __init +rtc_rx5c348_init(int chipid) +{ + unsigned char inbuf[2], outbuf[2]; + srtc_chipid = chipid; + /* turn on RTC if it is not on */ + inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL2); + inbuf[1] = 0; + spi_rtc_io(inbuf, outbuf, 2); + if (outbuf[1] & Rx5C348_BIT_XSTP) { + inbuf[0] = Rx5C348_CMD_W(Rx5C348_REG_CTL2); + inbuf[1] = 0; + spi_rtc_io(inbuf, NULL, 2); + } + + inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL1); + inbuf[1] = 0; + spi_rtc_io(inbuf, outbuf, 2); + if (outbuf[1] & Rx5C348_BIT_24H) + srtc_24h = 1; + + /* set the function pointers */ + rtc_get_time = rtc_rx5c348_get_time; + rtc_set_time = rtc_rx5c348_set_time; +} diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c new file mode 100644 index 000000000000..fc992953bf95 --- /dev/null +++ b/arch/mips/tx4938/common/setup.c @@ -0,0 +1,91 @@ +/* + * linux/arch/mips/tx4938/common/setup.c + * + * common tx4938 setup routines + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kernel_stat.h> +#include <linux/module.h> +#include <linux/signal.h> +#include <linux/sched.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/timex.h> +#include <linux/slab.h> +#include <linux/random.h> +#include <linux/irq.h> +#include <asm/bitops.h> +#include <asm/bootinfo.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/mipsregs.h> +#include <asm/system.h> +#include <asm/time.h> +#include <asm/time.h> +#include <asm/tx4938/rbtx4938.h> + +extern void toshiba_rbtx4938_setup(void); +extern void rbtx4938_time_init(void); + +void __init tx4938_setup(void); +void __init tx4938_time_init(void); +void __init tx4938_timer_setup(struct irqaction *irq); +void dump_cp0(char *key); + +void (*__wbflush) (void); + +static void +tx4938_write_buffer_flush(void) +{ + mmiowb(); + + __asm__ __volatile__( + ".set push\n\t" + ".set noreorder\n\t" + "lw $0,%0\n\t" + "nop\n\t" + ".set pop" + : /* no output */ + : "m" (*(int *)KSEG1) + : "memory"); +} + +void __init +plat_setup(void) +{ + board_time_init = tx4938_time_init; + board_timer_setup = tx4938_timer_setup; + __wbflush = tx4938_write_buffer_flush; + toshiba_rbtx4938_setup(); +} + +void __init +tx4938_time_init(void) +{ + rbtx4938_time_init(); +} + +void __init +tx4938_timer_setup(struct irqaction *irq) +{ + u32 count; + u32 c1; + u32 c2; + + setup_irq(TX4938_IRQ_CPU_TIMER, irq); + + c1 = read_c0_count(); + count = c1 + (mips_hpt_frequency / HZ); + write_c0_compare(count); + c2 = read_c0_count(); +} diff --git a/arch/mips/tx4938/toshiba_rbtx4938/Makefile b/arch/mips/tx4938/toshiba_rbtx4938/Makefile new file mode 100644 index 000000000000..226941279d75 --- /dev/null +++ b/arch/mips/tx4938/toshiba_rbtx4938/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for common code for Toshiba TX4927 based systems +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +obj-y += prom.o setup.o irq.o spi_eeprom.o spi_txx9.o diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c new file mode 100644 index 000000000000..230f5a93c2e6 --- /dev/null +++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c @@ -0,0 +1,244 @@ +/* + * linux/arch/mips/tx4938/toshiba_rbtx4938/irq.c + * + * Toshiba RBTX4938 specific interrupt handlers + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +/* +IRQ Device + +16 TX4938-CP0/00 Software 0 +17 TX4938-CP0/01 Software 1 +18 TX4938-CP0/02 Cascade TX4938-CP0 +19 TX4938-CP0/03 Multiplexed -- do not use +20 TX4938-CP0/04 Multiplexed -- do not use +21 TX4938-CP0/05 Multiplexed -- do not use +22 TX4938-CP0/06 Multiplexed -- do not use +23 TX4938-CP0/07 CPU TIMER + +24 TX4938-PIC/00 +25 TX4938-PIC/01 +26 TX4938-PIC/02 Cascade RBTX4938-IOC +27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet +28 TX4938-PIC/04 +29 TX4938-PIC/05 TX4938 ETH1 +30 TX4938-PIC/06 TX4938 ETH0 +31 TX4938-PIC/07 +32 TX4938-PIC/08 TX4938 SIO 0 +33 TX4938-PIC/09 TX4938 SIO 1 +34 TX4938-PIC/10 TX4938 DMA0 +35 TX4938-PIC/11 TX4938 DMA1 +36 TX4938-PIC/12 TX4938 DMA2 +37 TX4938-PIC/13 TX4938 DMA3 +38 TX4938-PIC/14 +39 TX4938-PIC/15 +40 TX4938-PIC/16 TX4938 PCIC +41 TX4938-PIC/17 TX4938 TMR0 +42 TX4938-PIC/18 TX4938 TMR1 +43 TX4938-PIC/19 TX4938 TMR2 +44 TX4938-PIC/20 +45 TX4938-PIC/21 +46 TX4938-PIC/22 TX4938 PCIERR +47 TX4938-PIC/23 +48 TX4938-PIC/24 +49 TX4938-PIC/25 +50 TX4938-PIC/26 +51 TX4938-PIC/27 +52 TX4938-PIC/28 +53 TX4938-PIC/29 +54 TX4938-PIC/30 +55 TX4938-PIC/31 TX4938 SPI + +56 RBTX4938-IOC/00 PCI-D +57 RBTX4938-IOC/01 PCI-C +58 RBTX4938-IOC/02 PCI-B +59 RBTX4938-IOC/03 PCI-A +60 RBTX4938-IOC/04 RTC +61 RBTX4938-IOC/05 ATA +62 RBTX4938-IOC/06 MODEM +63 RBTX4938-IOC/07 SWINT +*/ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/mm.h> +#include <linux/swap.h> +#include <linux/ioport.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/pci.h> +#include <linux/timex.h> +#include <asm/bootinfo.h> +#include <asm/page.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/processor.h> +#include <asm/ptrace.h> +#include <asm/reboot.h> +#include <asm/time.h> +#include <linux/version.h> +#include <linux/bootmem.h> +#include <asm/tx4938/rbtx4938.h> + +static unsigned int toshiba_rbtx4938_irq_ioc_startup(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq); + +DEFINE_SPINLOCK(toshiba_rbtx4938_ioc_lock); + +#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" +static struct hw_interrupt_type toshiba_rbtx4938_irq_ioc_type = { + .typename = TOSHIBA_RBTX4938_IOC_NAME, + .startup = toshiba_rbtx4938_irq_ioc_startup, + .shutdown = toshiba_rbtx4938_irq_ioc_shutdown, + .enable = toshiba_rbtx4938_irq_ioc_enable, + .disable = toshiba_rbtx4938_irq_ioc_disable, + .ack = toshiba_rbtx4938_irq_ioc_mask_and_ack, + .end = toshiba_rbtx4938_irq_ioc_end, + .set_affinity = NULL +}; + +#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000 +#define TOSHIBA_RBTX4938_IOC_INTR_STAT 0xb7f0200a + +int +toshiba_rbtx4938_irq_nested(int sw_irq) +{ + u8 level3; + + level3 = reg_rd08(TOSHIBA_RBTX4938_IOC_INTR_STAT) & 0xff; + if (level3) { + /* must use fls so onboard ATA has priority */ + sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1; + } + + wbflush(); + return sw_irq; +} + +static struct irqaction toshiba_rbtx4938_irq_ioc_action = { + .handler = no_action, + .flags = 0, + .mask = CPU_MASK_NONE, + .name = TOSHIBA_RBTX4938_IOC_NAME, +}; + +/**********************************************************************************/ +/* Functions for ioc */ +/**********************************************************************************/ +static void __init +toshiba_rbtx4938_irq_ioc_init(void) +{ + int i; + + for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; + i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 3; + irq_desc[i].handler = &toshiba_rbtx4938_irq_ioc_type; + } + + setup_irq(RBTX4938_IRQ_IOCINT, + &toshiba_rbtx4938_irq_ioc_action); +} + +static unsigned int +toshiba_rbtx4938_irq_ioc_startup(unsigned int irq) +{ + toshiba_rbtx4938_irq_ioc_enable(irq); + + return 0; +} + +static void +toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq) +{ + toshiba_rbtx4938_irq_ioc_disable(irq); +} + +static void +toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) +{ + unsigned long flags; + volatile unsigned char v; + + spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags); + + v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); + v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); + TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); + mmiowb(); + TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); + + spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags); +} + +static void +toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) +{ + unsigned long flags; + volatile unsigned char v; + + spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags); + + v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); + v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); + TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); + mmiowb(); + TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); + + spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags); +} + +static void +toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq) +{ + toshiba_rbtx4938_irq_ioc_disable(irq); +} + +static void +toshiba_rbtx4938_irq_ioc_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + toshiba_rbtx4938_irq_ioc_enable(irq); + } +} + +extern void __init txx9_spi_irqinit(int irc_irq); + +void __init arch_init_irq(void) +{ + extern void tx4938_irq_init(void); + + /* Now, interrupt control disabled, */ + /* all IRC interrupts are masked, */ + /* all IRC interrupt mode are Low Active. */ + + /* mask all IOC interrupts */ + *rbtx4938_imask_ptr = 0; + + /* clear SoftInt interrupts */ + *rbtx4938_softint_ptr = 0; + tx4938_irq_init(); + toshiba_rbtx4938_irq_ioc_init(); + /* Onboard 10M Ether: High Active */ + TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000040); + + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_SPI_SEL) { + txx9_spi_irqinit(RBTX4938_IRQ_IRC_SPI); + } + + wbflush(); +} diff --git a/arch/mips/tx4938/toshiba_rbtx4938/prom.c b/arch/mips/tx4938/toshiba_rbtx4938/prom.c new file mode 100644 index 000000000000..7df8b32ba265 --- /dev/null +++ b/arch/mips/tx4938/toshiba_rbtx4938/prom.c @@ -0,0 +1,78 @@ +/* + * linux/arch/mips/tx4938/toshiba_rbtx4938/prom.c + * + * rbtx4938 specific prom routines + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include <linux/config.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/bootmem.h> + +#include <asm/addrspace.h> +#include <asm/bootinfo.h> +#include <asm/tx4938/tx4938.h> + +void __init prom_init_cmdline(void) +{ + int argc = (int) fw_arg0; + char **argv = (char **) fw_arg1; + int i; + + /* ignore all built-in args if any f/w args given */ + if (argc > 1) { + *arcs_cmdline = '\0'; + } + + for (i = 1; i < argc; i++) { + if (i != 1) { + strcat(arcs_cmdline, " "); + } + strcat(arcs_cmdline, argv[i]); + } +} + +void __init prom_init(void) +{ + extern int tx4938_get_mem_size(void); + int msize; +#ifndef CONFIG_TX4938_NAND_BOOT + prom_init_cmdline(); +#endif + mips_machgroup = MACH_GROUP_TOSHIBA; + mips_machtype = MACH_TOSHIBA_RBTX4938; + + msize = tx4938_get_mem_size(); + add_memory_region(0, msize << 20, BOOT_MEM_RAM); + + return; +} + +unsigned long __init prom_free_prom_memory(void) +{ + return 0; +} + +void __init prom_fixup_mem_map(unsigned long start, unsigned long end) +{ + return; +} + +const char *get_system_type(void) +{ + return "Toshiba RBTX4938"; +} + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c new file mode 100644 index 000000000000..9f1dcc8ca5a3 --- /dev/null +++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c @@ -0,0 +1,1035 @@ +/* + * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c + * + * Setup pointers to hardware-dependent routines. + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include <linux/config.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/ioport.h> +#include <linux/proc_fs.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/console.h> +#include <linux/pci.h> +#include <asm/wbflush.h> +#include <asm/reboot.h> +#include <asm/irq.h> +#include <asm/time.h> +#include <asm/uaccess.h> +#include <asm/io.h> +#include <asm/bootinfo.h> +#include <asm/tx4938/rbtx4938.h> +#ifdef CONFIG_SERIAL_TXX9 +#include <linux/tty.h> +#include <linux/serial.h> +#include <linux/serial_core.h> +#endif + +extern void rbtx4938_time_init(void) __init; +extern char * __init prom_getcmdline(void); +static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); + +/* These functions are used for rebooting or halting the machine*/ +extern void rbtx4938_machine_restart(char *command); +extern void rbtx4938_machine_halt(void); +extern void rbtx4938_machine_power_off(void); + +/* clocks */ +unsigned int txx9_master_clock; +unsigned int txx9_cpu_clock; +unsigned int txx9_gbus_clock; + +unsigned long rbtx4938_ce_base[8]; +unsigned long rbtx4938_ce_size[8]; +int txboard_pci66_mode; +static int tx4938_pcic_trdyto; /* default: disabled */ +static int tx4938_pcic_retryto; /* default: disabled */ +static int tx4938_ccfg_toeon = 1; + +struct tx4938_pcic_reg *pcicptrs[4] = { + tx4938_pcicptr /* default setting for TX4938 */ +}; + +static struct { + unsigned long base; + unsigned long size; +} phys_regions[16] __initdata; +static int num_phys_regions __initdata; + +#define PHYS_REGION_MINSIZE 0x10000 + +void rbtx4938_machine_halt(void) +{ + printk(KERN_NOTICE "System Halted\n"); + local_irq_disable(); + + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +void rbtx4938_machine_power_off(void) +{ + rbtx4938_machine_halt(); + /* no return */ +} + +void rbtx4938_machine_restart(char *command) +{ + local_irq_disable(); + + printk("Rebooting..."); + *rbtx4938_softresetlock_ptr = 1; + *rbtx4938_sfvol_ptr = 1; + *rbtx4938_softreset_ptr = 1; + wbflush(); + + while(1); +} + +void __init +txboard_add_phys_region(unsigned long base, unsigned long size) +{ + if (num_phys_regions >= ARRAY_SIZE(phys_regions)) { + printk("phys_region overflow\n"); + return; + } + phys_regions[num_phys_regions].base = base; + phys_regions[num_phys_regions].size = size; + num_phys_regions++; +} +unsigned long __init +txboard_find_free_phys_region(unsigned long begin, unsigned long end, + unsigned long size) +{ + unsigned long base; + int i; + + for (base = begin / size * size; base < end; base += size) { + for (i = 0; i < num_phys_regions; i++) { + if (phys_regions[i].size && + base <= phys_regions[i].base + (phys_regions[i].size - 1) && + base + (size - 1) >= phys_regions[i].base) + break; + } + if (i == num_phys_regions) + return base; + } + return 0; +} +unsigned long __init +txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end, + unsigned long *size) +{ + unsigned long sz, base; + for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) { + base = txboard_find_free_phys_region(begin, end, sz); + if (base) { + *size = sz; + return base; + } + } + return 0; +} +unsigned long __init +txboard_request_phys_region_range(unsigned long begin, unsigned long end, + unsigned long size) +{ + unsigned long base; + base = txboard_find_free_phys_region(begin, end, size); + if (base) + txboard_add_phys_region(base, size); + return base; +} +unsigned long __init +txboard_request_phys_region(unsigned long size) +{ + unsigned long base; + unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ + base = txboard_find_free_phys_region(begin, end, size); + if (base) + txboard_add_phys_region(base, size); + return base; +} +unsigned long __init +txboard_request_phys_region_shrink(unsigned long *size) +{ + unsigned long base; + unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ + base = txboard_find_free_phys_region_shrink(begin, end, size); + if (base) + txboard_add_phys_region(base, *size); + return base; +} + +#ifdef CONFIG_PCI +void __init +tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr, + struct pci_controller *channel, + unsigned long pci_io_base, + int extarb) +{ + int i; + + /* Disable All Initiator Space */ + pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)| + TX4938_PCIC_PCICCFG_G2PMEN(1)| + TX4938_PCIC_PCICCFG_G2PMEN(2)| + TX4938_PCIC_PCICCFG_G2PIOEN); + + /* GB->PCI mappings */ + pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4; + pcicptr->g2piogbase = pci_io_base | +#ifdef __BIG_ENDIAN + TX4938_PCIC_G2PIOGBASE_ECHG +#else + TX4938_PCIC_G2PIOGBASE_BSDIS +#endif + ; + pcicptr->g2piopbase = 0; + for (i = 0; i < 3; i++) { + pcicptr->g2pmmask[i] = 0; + pcicptr->g2pmgbase[i] = 0; + pcicptr->g2pmpbase[i] = 0; + } + if (channel->mem_resource->end) { + pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4; + pcicptr->g2pmgbase[0] = channel->mem_resource->start | +#ifdef __BIG_ENDIAN + TX4938_PCIC_G2PMnGBASE_ECHG +#else + TX4938_PCIC_G2PMnGBASE_BSDIS +#endif + ; + pcicptr->g2pmpbase[0] = channel->mem_resource->start; + } + /* PCI->GB mappings (I/O 256B) */ + pcicptr->p2giopbase = 0; /* 256B */ + pcicptr->p2giogbase = 0; + /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ + pcicptr->p2gm0plbase = 0; + pcicptr->p2gm0pubase = 0; + pcicptr->p2gmgbase[0] = 0 | + TX4938_PCIC_P2GMnGBASE_TMEMEN | +#ifdef __BIG_ENDIAN + TX4938_PCIC_P2GMnGBASE_TECHG +#else + TX4938_PCIC_P2GMnGBASE_TBSDIS +#endif + ; + /* PCI->GB mappings (MEM 16MB) */ + pcicptr->p2gm1plbase = 0xffffffff; + pcicptr->p2gm1pubase = 0xffffffff; + pcicptr->p2gmgbase[1] = 0; + /* PCI->GB mappings (MEM 1MB) */ + pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */ + pcicptr->p2gmgbase[2] = 0; + + pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK; + /* Enable Initiator Memory Space */ + if (channel->mem_resource->end) + pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0); + /* Enable Initiator I/O Space */ + if (channel->io_resource->end) + pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN; + /* Enable Initiator Config */ + pcicptr->pciccfg |= + TX4938_PCIC_PCICCFG_ICAEN | + TX4938_PCIC_PCICCFG_TCAR; + + /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ + pcicptr->pcicfg1 = 0; + + pcicptr->g2ptocnt &= ~0xffff; + + if (tx4938_pcic_trdyto >= 0) { + pcicptr->g2ptocnt &= ~0xff; + pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff); + } + + if (tx4938_pcic_retryto >= 0) { + pcicptr->g2ptocnt &= ~0xff00; + pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00); + } + + /* Clear All Local Bus Status */ + pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL; + /* Enable All Local Bus Interrupts */ + pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL; + /* Clear All Initiator Status */ + pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL; + /* Enable All Initiator Interrupts */ + pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL; + /* Clear All PCI Status Error */ + pcicptr->pcistatus = + (pcicptr->pcistatus & 0x0000ffff) | + (TX4938_PCIC_PCISTATUS_ALL << 16); + /* Enable All PCI Status Error Interrupts */ + pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL; + + if (!extarb) { + /* Reset Bus Arbiter */ + pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA; + pcicptr->pbabm = 0; + /* Enable Bus Arbiter */ + pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN; + } + + /* PCIC Int => IRC IRQ16 */ + pcicptr->pcicfg2 = + (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC; + + pcicptr->pcistatus = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; +} + +int __init +tx4938_report_pciclk(void) +{ + unsigned long pcode = TX4938_REV_PCODE(); + int pciclk = 0; + printk("TX%lx PCIC --%s PCICLK:", + pcode, + (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : ""); + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { + + switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) { + case TX4938_CCFG_PCIDIVMODE_4: + pciclk = txx9_cpu_clock / 4; break; + case TX4938_CCFG_PCIDIVMODE_4_5: + pciclk = txx9_cpu_clock * 2 / 9; break; + case TX4938_CCFG_PCIDIVMODE_5: + pciclk = txx9_cpu_clock / 5; break; + case TX4938_CCFG_PCIDIVMODE_5_5: + pciclk = txx9_cpu_clock * 2 / 11; break; + case TX4938_CCFG_PCIDIVMODE_8: + pciclk = txx9_cpu_clock / 8; break; + case TX4938_CCFG_PCIDIVMODE_9: + pciclk = txx9_cpu_clock / 9; break; + case TX4938_CCFG_PCIDIVMODE_10: + pciclk = txx9_cpu_clock / 10; break; + case TX4938_CCFG_PCIDIVMODE_11: + pciclk = txx9_cpu_clock / 11; break; + } + printk("Internal(%dMHz)", pciclk / 1000000); + } else { + printk("External"); + pciclk = -1; + } + printk("\n"); + return pciclk; +} + +void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr) +{ + pcicptrs[ch] = pcicptr; +} + +struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch) +{ + return pcicptrs[ch]; +} + +static struct pci_dev *fake_pci_dev(struct pci_controller *hose, + int top_bus, int busnr, int devfn) +{ + static struct pci_dev dev; + static struct pci_bus bus; + + dev.sysdata = (void *)hose; + dev.devfn = devfn; + bus.number = busnr; + bus.ops = hose->pci_ops; + bus.parent = NULL; + dev.bus = &bus; + + return &dev; +} + +#define EARLY_PCI_OP(rw, size, type) \ +static int early_##rw##_config_##size(struct pci_controller *hose, \ + int top_bus, int bus, int devfn, int offset, type value) \ +{ \ + return pci_##rw##_config_##size( \ + fake_pci_dev(hose, top_bus, bus, devfn), \ + offset, value); \ +} + +EARLY_PCI_OP(read, word, u16 *) + +int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus) +{ + u32 pci_devfn; + unsigned short vid; + int devfn_start = 0; + int devfn_stop = 0xff; + int cap66 = -1; + u16 stat; + + printk("PCI: Checking 66MHz capabilities...\n"); + + for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) { + early_read_config_word(hose, top_bus, current_bus, pci_devfn, + PCI_VENDOR_ID, &vid); + + if (vid == 0xffff) continue; + + /* check 66MHz capability */ + if (cap66 < 0) + cap66 = 1; + if (cap66) { + early_read_config_word(hose, top_bus, current_bus, pci_devfn, + PCI_STATUS, &stat); + if (!(stat & PCI_STATUS_66MHZ)) { + printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n", + current_bus, pci_devfn); + cap66 = 0; + break; + } + } + } + return cap66 > 0; +} + +int __init +tx4938_pciclk66_setup(void) +{ + int pciclk; + + /* Assert M66EN */ + tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66; + /* Double PCICLK (if possible) */ + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { + unsigned int pcidivmode = + tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK; + switch (pcidivmode) { + case TX4938_CCFG_PCIDIVMODE_8: + case TX4938_CCFG_PCIDIVMODE_4: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4; + pciclk = txx9_cpu_clock / 4; + break; + case TX4938_CCFG_PCIDIVMODE_9: + case TX4938_CCFG_PCIDIVMODE_4_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5; + pciclk = txx9_cpu_clock * 2 / 9; + break; + case TX4938_CCFG_PCIDIVMODE_10: + case TX4938_CCFG_PCIDIVMODE_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5; + pciclk = txx9_cpu_clock / 5; + break; + case TX4938_CCFG_PCIDIVMODE_11: + case TX4938_CCFG_PCIDIVMODE_5_5: + default: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5; + pciclk = txx9_cpu_clock * 2 / 11; + break; + } + tx4938_ccfgptr->ccfg = + (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK) + | pcidivmode; + printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", + (unsigned long)tx4938_ccfgptr->ccfg); + } else { + pciclk = -1; + } + return pciclk; +} + +extern struct pci_controller tx4938_pci_controller[]; +static int __init tx4938_pcibios_init(void) +{ + unsigned long mem_base[2]; + unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ + unsigned long io_base[2]; + unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ + /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ + int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); + + PCIBIOS_MIN_IO = 0x00001000UL; + PCIBIOS_MIN_MEM = 0x01000000UL; + + mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]); + io_base[0] = txboard_request_phys_region_shrink(&io_size[0]); + + printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", + (unsigned short)(tx4938_pcicptr->pciid >> 16), + (unsigned short)(tx4938_pcicptr->pciid & 0xffff), + (unsigned short)(tx4938_pcicptr->pciccrev & 0xff), + extarb ? "External" : "Internal"); + + /* setup PCI area */ + tx4938_pci_controller[0].io_resource->start = io_base[0]; + tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1; + tx4938_pci_controller[0].mem_resource->start = mem_base[0]; + tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1; + + set_tx4938_pcicptr(0, tx4938_pcicptr); + + register_pci_controller(&tx4938_pci_controller[0]); + + if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) { + printk("TX4938_CCFG_PCI66 already configured\n"); + txboard_pci66_mode = -1; /* already configured */ + } + + /* Reset PCI Bus */ + *rbtx4938_pcireset_ptr = 0; + /* Reset PCIC */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; + if (txboard_pci66_mode > 0) + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + *rbtx4938_pcireset_ptr = 1; + wbflush(); + tx4938_report_pcic_status1(tx4938_pcicptr); + + tx4938_report_pciclk(); + tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); + if (txboard_pci66_mode == 0 && + txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) { + /* Reset PCI Bus */ + *rbtx4938_pcireset_ptr = 0; + /* Reset PCIC */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + *rbtx4938_pcireset_ptr = 1; + wbflush(); + /* Reinitialize PCIC */ + tx4938_report_pciclk(); + tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); + } + + mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]); + io_base[1] = txboard_request_phys_region_shrink(&io_size[1]); + /* Reset PCIC1 */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST; + /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ + if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD)) + tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66; + else + tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66; + mdelay(10); + /* clear PCIC1 reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; + tx4938_report_pcic_status1(tx4938_pcic1ptr); + + printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x", + (unsigned short)(tx4938_pcic1ptr->pciid >> 16), + (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff), + (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff)); + printk("%s PCICLK:%dMHz\n", + (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "", + txx9_gbus_clock / + ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) / + 1000000); + + /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */ + tx4938_pci_controller[1].io_resource->start = + io_base[1] - io_base[0]; + tx4938_pci_controller[1].io_resource->end = + io_base[1] - io_base[0] + io_size[1] - 1; + tx4938_pci_controller[1].mem_resource->start = mem_base[1]; + tx4938_pci_controller[1].mem_resource->end = + mem_base[1] + mem_size[1] - 1; + set_tx4938_pcicptr(1, tx4938_pcic1ptr); + + register_pci_controller(&tx4938_pci_controller[1]); + + tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb); + + /* map ioport 0 to PCI I/O space address 0 */ + set_io_port_base(KSEG1 + io_base[0]); + + return 0; +} + +arch_initcall(tx4938_pcibios_init); + +#endif /* CONFIG_PCI */ + +/* SPI support */ + +/* chip select for SPI devices */ +#define SEEPROM1_CS 7 /* PIO7 */ +#define SEEPROM2_CS 0 /* IOC */ +#define SEEPROM3_CS 1 /* IOC */ +#define SRTC_CS 2 /* IOC */ + +static int rbtx4938_spi_cs_func(int chipid, int on) +{ + unsigned char bit; + switch (chipid) { + case RBTX4938_SEEPROM1_CHIPID: + if (on) + tx4938_pioptr->dout &= ~(1 << SEEPROM1_CS); + else + tx4938_pioptr->dout |= (1 << SEEPROM1_CS); + return 0; + break; + case RBTX4938_SEEPROM2_CHIPID: + bit = (1 << SEEPROM2_CS); + break; + case RBTX4938_SEEPROM3_CHIPID: + bit = (1 << SEEPROM3_CS); + break; + case RBTX4938_SRTC_CHIPID: + bit = (1 << SRTC_CS); + break; + default: + return -ENODEV; + } + /* bit1,2,4 are low active, bit3 is high active */ + *rbtx4938_spics_ptr = + (*rbtx4938_spics_ptr & ~bit) | + ((on ? (bit ^ 0x0b) : ~(bit ^ 0x0b)) & bit); + return 0; +} + +#ifdef CONFIG_PCI +extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); + +int rbtx4938_get_tx4938_ethaddr(struct pci_dev *dev, unsigned char *addr) +{ + struct pci_controller *channel = (struct pci_controller *)dev->bus->sysdata; + static unsigned char dat[17]; + static int read_dat = 0; + int ch = 0; + + if (channel != &tx4938_pci_controller[1]) + return -ENODEV; + /* TX4938 PCIC1 */ + switch (PCI_SLOT(dev->devfn)) { + case TX4938_PCIC_IDSEL_AD_TO_SLOT(31): + ch = 0; + break; + case TX4938_PCIC_IDSEL_AD_TO_SLOT(30): + ch = 1; + break; + default: + return -ENODEV; + } + if (!read_dat) { + unsigned char sum; + int i; + read_dat = 1; + /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */ + if (spi_eeprom_read(RBTX4938_SEEPROM1_CHIPID, + 0, dat, sizeof(dat))) { + printk(KERN_ERR "seeprom: read error.\n"); + } else { + if (strcmp(dat, "MAC") != 0) + printk(KERN_WARNING "seeprom: bad signature.\n"); + for (i = 0, sum = 0; i < sizeof(dat); i++) + sum += dat[i]; + if (sum) + printk(KERN_WARNING "seeprom: bad checksum.\n"); + } + } + memcpy(addr, &dat[4 + 6 * ch], 6); + return 0; +} +#endif /* CONFIG_PCI */ + +extern void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)); +static void __init rbtx4938_spi_setup(void) +{ + /* set SPI_SEL */ + tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL; + /* chip selects for SPI devices */ + tx4938_pioptr->dout |= (1 << SEEPROM1_CS); + tx4938_pioptr->dir |= (1 << SEEPROM1_CS); + txx9_spi_init(TX4938_SPI_REG, rbtx4938_spi_cs_func); +} + +static struct resource rbtx4938_fpga_resource; + +static char pcode_str[8]; +static struct resource tx4938_reg_resource = { + pcode_str, TX4938_REG_BASE, TX4938_REG_BASE+TX4938_REG_SIZE, IORESOURCE_MEM +}; + +void __init tx4938_board_setup(void) +{ + int i; + unsigned long divmode; + int cpuclk = 0; + unsigned long pcode = TX4938_REV_PCODE(); + + ioport_resource.start = 0x1000; + ioport_resource.end = 0xffffffff; + iomem_resource.start = 0x1000; + iomem_resource.end = 0xffffffff; /* expand to 4GB */ + + sprintf(pcode_str, "TX%lx", pcode); + /* SDRAMC,EBUSC are configured by PROM */ + for (i = 0; i < 8; i++) { + if (!(tx4938_ebuscptr->cr[i] & 0x8)) + continue; /* disabled */ + rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i); + txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i)); + } + + /* clocks */ + if (txx9_master_clock) { + /* calculate gbus_clock and cpu_clock from master_clock */ + divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; + switch (divmode) { + case TX4938_CCFG_DIVMODE_8: + case TX4938_CCFG_DIVMODE_10: + case TX4938_CCFG_DIVMODE_12: + case TX4938_CCFG_DIVMODE_16: + case TX4938_CCFG_DIVMODE_18: + txx9_gbus_clock = txx9_master_clock * 4; break; + default: + txx9_gbus_clock = txx9_master_clock; + } + switch (divmode) { + case TX4938_CCFG_DIVMODE_2: + case TX4938_CCFG_DIVMODE_8: + cpuclk = txx9_gbus_clock * 2; break; + case TX4938_CCFG_DIVMODE_2_5: + case TX4938_CCFG_DIVMODE_10: + cpuclk = txx9_gbus_clock * 5 / 2; break; + case TX4938_CCFG_DIVMODE_3: + case TX4938_CCFG_DIVMODE_12: + cpuclk = txx9_gbus_clock * 3; break; + case TX4938_CCFG_DIVMODE_4: + case TX4938_CCFG_DIVMODE_16: + cpuclk = txx9_gbus_clock * 4; break; + case TX4938_CCFG_DIVMODE_4_5: + case TX4938_CCFG_DIVMODE_18: + cpuclk = txx9_gbus_clock * 9 / 2; break; + } + txx9_cpu_clock = cpuclk; + } else { + if (txx9_cpu_clock == 0) { + txx9_cpu_clock = 300000000; /* 300MHz */ + } + /* calculate gbus_clock and master_clock from cpu_clock */ + cpuclk = txx9_cpu_clock; + divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; + switch (divmode) { + case TX4938_CCFG_DIVMODE_2: + case TX4938_CCFG_DIVMODE_8: + txx9_gbus_clock = cpuclk / 2; break; + case TX4938_CCFG_DIVMODE_2_5: + case TX4938_CCFG_DIVMODE_10: + txx9_gbus_clock = cpuclk * 2 / 5; break; + case TX4938_CCFG_DIVMODE_3: + case TX4938_CCFG_DIVMODE_12: + txx9_gbus_clock = cpuclk / 3; break; + case TX4938_CCFG_DIVMODE_4: + case TX4938_CCFG_DIVMODE_16: + txx9_gbus_clock = cpuclk / 4; break; + case TX4938_CCFG_DIVMODE_4_5: + case TX4938_CCFG_DIVMODE_18: + txx9_gbus_clock = cpuclk * 2 / 9; break; + } + switch (divmode) { + case TX4938_CCFG_DIVMODE_8: + case TX4938_CCFG_DIVMODE_10: + case TX4938_CCFG_DIVMODE_12: + case TX4938_CCFG_DIVMODE_16: + case TX4938_CCFG_DIVMODE_18: + txx9_master_clock = txx9_gbus_clock / 4; break; + default: + txx9_master_clock = txx9_gbus_clock; + } + } + /* change default value to udelay/mdelay take reasonable time */ + loops_per_jiffy = txx9_cpu_clock / HZ / 2; + + /* CCFG */ + /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */ + tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW; + /* clear PCIC1 reset */ + if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST) + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; + + /* enable Timeout BusError */ + if (tx4938_ccfg_toeon) + tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE; + + /* DMA selection */ + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL; + + /* Use external clock for external arbiter */ + if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB)) + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL; + + printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n", + pcode_str, + cpuclk / 1000000, txx9_master_clock / 1000000, + (unsigned long)tx4938_ccfgptr->crir, + tx4938_ccfgptr->ccfg, + tx4938_ccfgptr->pcfg); + + printk("%s SDRAMC --", pcode_str); + for (i = 0; i < 4; i++) { + unsigned long long cr = tx4938_sdramcptr->cr[i]; + unsigned long ram_base, ram_size; + if (!((unsigned long)cr & 0x00000400)) + continue; /* disabled */ + ram_base = (unsigned long)(cr >> 49) << 21; + ram_size = ((unsigned long)(cr >> 33) + 1) << 21; + if (ram_base >= 0x20000000) + continue; /* high memory (ignore) */ + printk(" CR%d:%016Lx", i, cr); + txboard_add_phys_region(ram_base, ram_size); + } + printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); + + /* SRAM */ + if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) { + unsigned int size = 0x800; + unsigned long base = + (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); + txboard_add_phys_region(base, size); + } + + /* IRC */ + /* disable interrupt control */ + tx4938_ircptr->cer = 0; + + /* TMR */ + /* disable all timers */ + for (i = 0; i < TX4938_NR_TMR; i++) { + tx4938_tmrptr(i)->tcr = 0x00000020; + tx4938_tmrptr(i)->tisr = 0; + tx4938_tmrptr(i)->cpra = 0xffffffff; + tx4938_tmrptr(i)->itmr = 0; + tx4938_tmrptr(i)->ccdr = 0; + tx4938_tmrptr(i)->pgmr = 0; + } + + /* enable DMA */ + TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN); + TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN); + + /* PIO */ + tx4938_pioptr->maskcpu = 0; + tx4938_pioptr->maskext = 0; + + /* TX4938 internal registers */ + if (request_resource(&iomem_resource, &tx4938_reg_resource)) + printk("request resource for internal registers failed\n"); +} + +#ifdef CONFIG_PCI +static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr) +{ + unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16); + unsigned long g2pstatus = pcicptr->g2pstatus; + unsigned long pcicstatus = pcicptr->pcicstatus; + static struct { + unsigned long flag; + const char *str; + } pcistat_tbl[] = { + { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, + { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, + { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, + { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, + { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, + { PCI_STATUS_PARITY, "MasterParityError" }, + }, g2pstat_tbl[] = { + { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" }, + { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" }, + }, pcicstat_tbl[] = { + { TX4938_PCIC_PCICSTATUS_PME, "PME" }, + { TX4938_PCIC_PCICSTATUS_TLB, "TLB" }, + { TX4938_PCIC_PCICSTATUS_NIB, "NIB" }, + { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" }, + { TX4938_PCIC_PCICSTATUS_PERR, "PERR" }, + { TX4938_PCIC_PCICSTATUS_SERR, "SERR" }, + { TX4938_PCIC_PCICSTATUS_GBE, "GBE" }, + { TX4938_PCIC_PCICSTATUS_IWB, "IWB" }, + }; + int i; + + printk("pcistat:%04x(", pcistatus); + for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++) + if (pcistatus & pcistat_tbl[i].flag) + printk("%s ", pcistat_tbl[i].str); + printk("), g2pstatus:%08lx(", g2pstatus); + for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) + if (g2pstatus & g2pstat_tbl[i].flag) + printk("%s ", g2pstat_tbl[i].str); + printk("), pcicstatus:%08lx(", pcicstatus); + for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) + if (pcicstatus & pcicstat_tbl[i].flag) + printk("%s ", pcicstat_tbl[i].str); + printk(")\n"); +} + +void tx4938_report_pcic_status(void) +{ + int i; + struct tx4938_pcic_reg *pcicptr; + for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++) + tx4938_report_pcic_status1(pcicptr); +} + +#endif /* CONFIG_PCI */ + +/* We use onchip r4k counter or TMR timer as our system wide timer + * interrupt running at 100HZ. */ + +extern void __init rtc_rx5c348_init(int chipid); +void __init rbtx4938_time_init(void) +{ + rtc_rx5c348_init(RBTX4938_SRTC_CHIPID); + mips_hpt_frequency = txx9_cpu_clock / 2; +} + +void __init toshiba_rbtx4938_setup(void) +{ + unsigned long long pcfg; + char *argptr; + + iomem_resource.end = 0xffffffff; /* 4GB */ + + if (txx9_master_clock == 0) + txx9_master_clock = 25000000; /* 25MHz */ + tx4938_board_setup(); + /* setup irq stuff */ + TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000000); /* irq trigger */ + TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM1), 0x00000000); /* irq trigger */ + /* setup serial stuff */ + TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */ + TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */ + +#ifndef CONFIG_PCI + set_io_port_base(RBTX4938_ETHER_BASE); +#endif + +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + int i; + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (char *)(0xff1ff300 + i * 0x100); + req.mapbase = 0xff1ff300 + i * 0x100; + req.irq = 32 + i; + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = 50000000; + early_serial_txx9_setup(&req); + } + } +#ifdef CONFIG_SERIAL_TXX9_CONSOLE + argptr = prom_getcmdline(); + if (strstr(argptr, "console=") == NULL) { + strcat(argptr, " console=ttyS0,38400"); + } +#endif +#endif + +#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 + printk("PIOSEL: disabling both ata and nand selection\n"); + local_irq_disable(); + tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); +#endif + +#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND + printk("PIOSEL: enabling nand selection\n"); + tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL; + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL; +#endif + +#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA + printk("PIOSEL: enabling ata selection\n"); + tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL; + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL; +#endif + +#ifdef CONFIG_IP_PNP + argptr = prom_getcmdline(); + if (strstr(argptr, "ip=") == NULL) { + strcat(argptr, " ip=any"); + } +#endif + + +#ifdef CONFIG_FB + { + conswitchp = &dummy_con; + } +#endif + + rbtx4938_spi_setup(); + pcfg = tx4938_ccfgptr->pcfg; /* updated */ + /* fixup piosel */ + if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == + TX4938_PCFG_ATA_SEL) { + *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04; + } + else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == + TX4938_PCFG_NDF_SEL) { + *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08; + } + else { + *rbtx4938_piosel_ptr &= ~(0x08 | 0x04); + } + + rbtx4938_fpga_resource.name = "FPGA Registers"; + rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR); + rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; + rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; + if (request_resource(&iomem_resource, &rbtx4938_fpga_resource)) + printk("request resource for fpga failed\n"); + + /* disable all OnBoard I/O interrupts */ + *rbtx4938_imask_ptr = 0; + + _machine_restart = rbtx4938_machine_restart; + _machine_halt = rbtx4938_machine_halt; + _machine_power_off = rbtx4938_machine_power_off; + + *rbtx4938_led_ptr = 0xff; + printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr); + printk(" DIPSW:%02x,%02x\n", + *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr); +} + +#ifdef CONFIG_PROC_FS +extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid); +static int __init tx4938_spi_proc_setup(void) +{ + struct proc_dir_entry *tx4938_spi_eeprom_dir; + + tx4938_spi_eeprom_dir = proc_mkdir("spi_eeprom", 0); + + if (!tx4938_spi_eeprom_dir) + return -ENOMEM; + + /* don't allow user access to RBTX4938_SEEPROM1_CHIPID + * as it contains eth0 and eth1 MAC addresses + */ + spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM2_CHIPID); + spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM3_CHIPID); + + return 0; +} + +__initcall(tx4938_spi_proc_setup); +#endif diff --git a/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c b/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c new file mode 100644 index 000000000000..951a208ee9b3 --- /dev/null +++ b/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c @@ -0,0 +1,219 @@ +/* + * linux/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include <linux/config.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/proc_fs.h> +#include <linux/spinlock.h> +#include <asm/tx4938/spi.h> +#include <asm/tx4938/tx4938.h> + +/* ATMEL 250x0 instructions */ +#define ATMEL_WREN 0x06 +#define ATMEL_WRDI 0x04 +#define ATMEL_RDSR 0x05 +#define ATMEL_WRSR 0x01 +#define ATMEL_READ 0x03 +#define ATMEL_WRITE 0x02 + +#define ATMEL_SR_BSY 0x01 +#define ATMEL_SR_WEN 0x02 +#define ATMEL_SR_BP0 0x04 +#define ATMEL_SR_BP1 0x08 + +DEFINE_SPINLOCK(spi_eeprom_lock); + +static struct spi_dev_desc seeprom_dev_desc = { + .baud = 1500000, /* 1.5Mbps */ + .tcss = 1, + .tcsh = 1, + .tcsr = 1, + .byteorder = 1, /* MSB-First */ + .polarity = 0, /* High-Active */ + .phase = 0, /* Sample-Then-Shift */ + +}; +static inline int +spi_eeprom_io(int chipid, + unsigned char **inbufs, unsigned int *incounts, + unsigned char **outbufs, unsigned int *outcounts) +{ + return txx9_spi_io(chipid, &seeprom_dev_desc, + inbufs, incounts, outbufs, outcounts, 0); +} + +int spi_eeprom_write_enable(int chipid, int enable) +{ + unsigned char inbuf[1]; + unsigned char *inbufs[1]; + unsigned int incounts[2]; + unsigned long flags; + int stat; + inbuf[0] = enable ? ATMEL_WREN : ATMEL_WRDI; + inbufs[0] = inbuf; + incounts[0] = sizeof(inbuf); + incounts[1] = 0; + spin_lock_irqsave(&spi_eeprom_lock, flags); + stat = spi_eeprom_io(chipid, inbufs, incounts, NULL, NULL); + spin_unlock_irqrestore(&spi_eeprom_lock, flags); + return stat; +} + +static int spi_eeprom_read_status_nolock(int chipid) +{ + unsigned char inbuf[2], outbuf[2]; + unsigned char *inbufs[1], *outbufs[1]; + unsigned int incounts[2], outcounts[2]; + int stat; + inbuf[0] = ATMEL_RDSR; + inbuf[1] = 0; + inbufs[0] = inbuf; + incounts[0] = sizeof(inbuf); + incounts[1] = 0; + outbufs[0] = outbuf; + outcounts[0] = sizeof(outbuf); + outcounts[1] = 0; + stat = spi_eeprom_io(chipid, inbufs, incounts, outbufs, outcounts); + if (stat < 0) + return stat; + return outbuf[1]; +} + +int spi_eeprom_read_status(int chipid) +{ + unsigned long flags; + int stat; + spin_lock_irqsave(&spi_eeprom_lock, flags); + stat = spi_eeprom_read_status_nolock(chipid); + spin_unlock_irqrestore(&spi_eeprom_lock, flags); + return stat; +} + +int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len) +{ + unsigned char inbuf[2]; + unsigned char *inbufs[2], *outbufs[2]; + unsigned int incounts[2], outcounts[3]; + unsigned long flags; + int stat; + inbuf[0] = ATMEL_READ; + inbuf[1] = address; + inbufs[0] = inbuf; + inbufs[1] = NULL; + incounts[0] = sizeof(inbuf); + incounts[1] = 0; + outbufs[0] = NULL; + outbufs[1] = buf; + outcounts[0] = 2; + outcounts[1] = len; + outcounts[2] = 0; + spin_lock_irqsave(&spi_eeprom_lock, flags); + stat = spi_eeprom_io(chipid, inbufs, incounts, outbufs, outcounts); + spin_unlock_irqrestore(&spi_eeprom_lock, flags); + return stat; +} + +int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len) +{ + unsigned char inbuf[2]; + unsigned char *inbufs[2]; + unsigned int incounts[3]; + unsigned long flags; + int i, stat; + + if (address / 8 != (address + len - 1) / 8) + return -EINVAL; + stat = spi_eeprom_write_enable(chipid, 1); + if (stat < 0) + return stat; + stat = spi_eeprom_read_status(chipid); + if (stat < 0) + return stat; + if (!(stat & ATMEL_SR_WEN)) + return -EPERM; + + inbuf[0] = ATMEL_WRITE; + inbuf[1] = address; + inbufs[0] = inbuf; + inbufs[1] = buf; + incounts[0] = sizeof(inbuf); + incounts[1] = len; + incounts[2] = 0; + spin_lock_irqsave(&spi_eeprom_lock, flags); + stat = spi_eeprom_io(chipid, inbufs, incounts, NULL, NULL); + if (stat < 0) + goto unlock_return; + + /* write start. max 10ms */ + for (i = 10; i > 0; i--) { + int stat = spi_eeprom_read_status_nolock(chipid); + if (stat < 0) + goto unlock_return; + if (!(stat & ATMEL_SR_BSY)) + break; + mdelay(1); + } + spin_unlock_irqrestore(&spi_eeprom_lock, flags); + if (i == 0) + return -EIO; + return len; + unlock_return: + spin_unlock_irqrestore(&spi_eeprom_lock, flags); + return stat; +} + +#ifdef CONFIG_PROC_FS +#define MAX_SIZE 0x80 /* for ATMEL 25010 */ +static int spi_eeprom_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + unsigned int size = MAX_SIZE; + if (spi_eeprom_read((int)data, 0, (unsigned char *)page, size) < 0) + size = 0; + return size; +} + +static int spi_eeprom_write_proc(struct file *file, const char *buffer, + unsigned long count, void *data) +{ + unsigned int size = MAX_SIZE; + int i; + if (file->f_pos >= size) + return -EIO; + if (file->f_pos + count > size) + count = size - file->f_pos; + for (i = 0; i < count; i += 8) { + int len = count - i < 8 ? count - i : 8; + if (spi_eeprom_write((int)data, file->f_pos, + (unsigned char *)buffer, len) < 0) { + count = -EIO; + break; + } + buffer += len; + file->f_pos += len; + } + return count; +} + +__init void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) +{ + struct proc_dir_entry *entry; + char name[128]; + sprintf(name, "seeprom-%d", chipid); + entry = create_proc_entry(name, 0600, dir); + if (entry) { + entry->read_proc = spi_eeprom_read_proc; + entry->write_proc = spi_eeprom_write_proc; + entry->data = (void *)chipid; + } +} +#endif /* CONFIG_PROC_FS */ diff --git a/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c b/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c new file mode 100644 index 000000000000..fae3136f462d --- /dev/null +++ b/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c @@ -0,0 +1,159 @@ +/* + * linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/sched.h> +#include <linux/spinlock.h> +#include <linux/wait.h> +#include <asm/tx4938/spi.h> +#include <asm/tx4938/tx4938.h> + +static int (*txx9_spi_cs_func)(int chipid, int on); +static DEFINE_SPINLOCK(txx9_spi_lock); + +extern unsigned int txx9_gbus_clock; + +#define SPI_FIFO_SIZE 4 + +void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) +{ + txx9_spi_cs_func = cs_func; + /* enter config mode */ + tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR; +} + +static DECLARE_WAIT_QUEUE_HEAD(txx9_spi_wait); +static void txx9_spi_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + /* disable rx intr */ + tx4938_spiptr->cr0 &= ~TXx9_SPCR0_RBSIE; + wake_up(&txx9_spi_wait); +} +static struct irqaction txx9_spi_action = { + txx9_spi_interrupt, 0, 0, "spi", NULL, NULL, +}; + +void __init txx9_spi_irqinit(int irc_irq) +{ + setup_irq(irc_irq, &txx9_spi_action); +} + +int txx9_spi_io(int chipid, struct spi_dev_desc *desc, + unsigned char **inbufs, unsigned int *incounts, + unsigned char **outbufs, unsigned int *outcounts, + int cansleep) +{ + unsigned int incount, outcount; + unsigned char *inp, *outp; + int ret; + unsigned long flags; + + spin_lock_irqsave(&txx9_spi_lock, flags); + if ((tx4938_spiptr->mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE) { + spin_unlock_irqrestore(&txx9_spi_lock, flags); + return -EBUSY; + } + /* enter config mode */ + tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR; + tx4938_spiptr->cr0 = + (desc->byteorder ? TXx9_SPCR0_SBOS : 0) | + (desc->polarity ? TXx9_SPCR0_SPOL : 0) | + (desc->phase ? TXx9_SPCR0_SPHA : 0) | + 0x08; + tx4938_spiptr->cr1 = + (((TXX9_IMCLK + desc->baud) / (2 * desc->baud) - 1) << 8) | + 0x08 /* 8 bit only */; + /* enter active mode */ + tx4938_spiptr->mcr = TXx9_SPMCR_ACTIVE; + spin_unlock_irqrestore(&txx9_spi_lock, flags); + + /* CS ON */ + if ((ret = txx9_spi_cs_func(chipid, 1)) < 0) { + spin_unlock_irqrestore(&txx9_spi_lock, flags); + return ret; + } + udelay(desc->tcss); + + /* do scatter IO */ + inp = inbufs ? *inbufs : NULL; + outp = outbufs ? *outbufs : NULL; + incount = 0; + outcount = 0; + while (1) { + unsigned char data; + unsigned int count; + int i; + if (!incount) { + incount = incounts ? *incounts++ : 0; + inp = (incount && inbufs) ? *inbufs++ : NULL; + } + if (!outcount) { + outcount = outcounts ? *outcounts++ : 0; + outp = (outcount && outbufs) ? *outbufs++ : NULL; + } + if (!inp && !outp) + break; + count = SPI_FIFO_SIZE; + if (incount) + count = min(count, incount); + if (outcount) + count = min(count, outcount); + + /* now tx must be idle... */ + while (!(tx4938_spiptr->sr & TXx9_SPSR_SIDLE)) + ; + + tx4938_spiptr->cr0 = + (tx4938_spiptr->cr0 & ~TXx9_SPCR0_RXIFL_MASK) | + ((count - 1) << 12); + if (cansleep) { + /* enable rx intr */ + tx4938_spiptr->cr0 |= TXx9_SPCR0_RBSIE; + } + /* send */ + for (i = 0; i < count; i++) + tx4938_spiptr->dr = inp ? *inp++ : 0; + /* wait all rx data */ + if (cansleep) { + wait_event(txx9_spi_wait, + tx4938_spiptr->sr & TXx9_SPSR_SRRDY); + } else { + while (!(tx4938_spiptr->sr & TXx9_SPSR_RBSI)) + ; + } + /* receive */ + for (i = 0; i < count; i++) { + data = tx4938_spiptr->dr; + if (outp) + *outp++ = data; + } + if (incount) + incount -= count; + if (outcount) + outcount -= count; + } + + /* CS OFF */ + udelay(desc->tcsh); + txx9_spi_cs_func(chipid, 0); + udelay(desc->tcsr); + + spin_lock_irqsave(&txx9_spi_lock, flags); + /* enter config mode */ + tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR; + spin_unlock_irqrestore(&txx9_spi_lock, flags); + + return 0; +} diff --git a/arch/mips/vr41xx/Kconfig b/arch/mips/vr41xx/Kconfig new file mode 100644 index 000000000000..a7add16c9aa4 --- /dev/null +++ b/arch/mips/vr41xx/Kconfig @@ -0,0 +1,88 @@ +config CASIO_E55 + bool "Support for CASIO CASSIOPEIA E-10/15/55/65" + depends on MACH_VR41XX + select DMA_NONCOHERENT + select IRQ_CPU + select ISA + select SYS_SUPPORTS_LITTLE_ENDIAN + +config IBM_WORKPAD + bool "Support for IBM WorkPad z50" + depends on MACH_VR41XX + select DMA_NONCOHERENT + select IRQ_CPU + select ISA + select SYS_SUPPORTS_LITTLE_ENDIAN + +config NEC_CMBVR4133 + bool "Support for NEC CMB-VR4133" + depends on MACH_VR41XX + select CPU_VR41XX + select DMA_NONCOHERENT + select IRQ_CPU + select HW_HAS_PCI + +config ROCKHOPPER + bool "Support for Rockhopper baseboard" + depends on NEC_CMBVR4133 + select I8259 + select HAVE_STD_PC_SERIAL_PORT + +config TANBAC_TB022X + bool "Support for TANBAC VR4131 multichip module and TANBAC VR4131DIMM" + depends on MACH_VR41XX + select DMA_NONCOHERENT + select HW_HAS_PCI + select IRQ_CPU + select SYS_SUPPORTS_LITTLE_ENDIAN + help + The TANBAC VR4131 multichip module(TB0225) and + the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms + manufactured by TANBAC. + Please refer to <http://www.tanbac.co.jp/> + about VR4131 multichip module and VR4131DIMM. + +config TANBAC_TB0226 + bool "Support for TANBAC Mbase(TB0226)" + depends on TANBAC_TB022X + select GPIO_VR41XX + help + The TANBAC Mbase(TB0226) is a MIPS-based platform + manufactured by TANBAC. + Please refer to <http://www.tanbac.co.jp/> about Mbase. + +config TANBAC_TB0287 + bool "Support for TANBAC Mini-ITX DIMM base(TB0287)" + depends on TANBAC_TB022X + help + The TANBAC Mini-ITX DIMM base(TB0287) is a MIPS-based platform + manufactured by TANBAC. + Please refer to <http://www.tanbac.co.jp/> about Mini-ITX DIMM base. + +config VICTOR_MPC30X + bool "Support for Victor MP-C303/304" + depends on MACH_VR41XX + select DMA_NONCOHERENT + select HW_HAS_PCI + select IRQ_CPU + select SYS_SUPPORTS_LITTLE_ENDIAN + +config ZAO_CAPCELLA + bool "Support for ZAO Networks Capcella" + depends on MACH_VR41XX + select DMA_NONCOHERENT + select HW_HAS_PCI + select IRQ_CPU + select SYS_SUPPORTS_LITTLE_ENDIAN + +config PCI_VR41XX + bool "Add PCI control unit support of NEC VR4100 series" + depends on MACH_VR41XX && HW_HAS_PCI + default y + select PCI + +config VRC4173 + tristate "Add NEC VRC4173 companion chip support" + depends on MACH_VR41XX && PCI_VR41XX + help + The NEC VRC4173 is a companion chip for NEC VR4122/VR4131. diff --git a/arch/mips/vr41xx/common/cmu.c b/arch/mips/vr41xx/common/cmu.c index fcd3cb8cdd9d..d758e432961b 100644 --- a/arch/mips/vr41xx/common/cmu.c +++ b/arch/mips/vr41xx/common/cmu.c @@ -69,7 +69,7 @@ static void __iomem *cmu_base; static uint16_t cmuclkmsk, cmuclkmsk2; -static spinlock_t cmu_lock; +static DEFINE_SPINLOCK(cmu_lock); #define cmu_read(offset) readw(cmu_base + (offset)) #define cmu_write(offset, value) writew((value), cmu_base + (offset)) diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c index e03be896cbc4..578f6496ffd4 100644 --- a/arch/mips/vr41xx/common/init.c +++ b/arch/mips/vr41xx/common/init.c @@ -58,6 +58,14 @@ static void __init timer_init(void) board_timer_setup = setup_timer_irq; } +void __init plat_setup(void) +{ + vr41xx_calculate_clock_frequency(); + + timer_init(); + iomem_resource_init(); +} + void __init prom_init(void) { int argc, i; @@ -71,12 +79,6 @@ void __init prom_init(void) if (i < (argc - 1)) strcat(arcs_cmdline, " "); } - - vr41xx_calculate_clock_frequency(); - - timer_init(); - - iomem_resource_init(); } unsigned long __init prom_free_prom_memory (void) diff --git a/arch/mips/vr41xx/common/vrc4173.c b/arch/mips/vr41xx/common/vrc4173.c index ba58764ef8ea..462a9af30eef 100644 --- a/arch/mips/vr41xx/common/vrc4173.c +++ b/arch/mips/vr41xx/common/vrc4173.c @@ -81,8 +81,8 @@ EXPORT_SYMBOL(vrc4173_io_offset); static int vrc4173_initialized; static uint16_t vrc4173_cmuclkmsk; static uint16_t vrc4173_selectreg; -static spinlock_t vrc4173_cmu_lock; -static spinlock_t vrc4173_giu_lock; +static DEFINE_SPINLOCK(vrc4173_cmu_lock); +static DEFINE_SPINLOCK(vrc4173_giu_lock); static inline void set_cmusrst(uint16_t val) { diff --git a/arch/mips/vr41xx/nec-cmbvr4133/setup.c b/arch/mips/vr41xx/nec-cmbvr4133/setup.c index db686ce42e85..53272a5c3cbe 100644 --- a/arch/mips/vr41xx/nec-cmbvr4133/setup.c +++ b/arch/mips/vr41xx/nec-cmbvr4133/setup.c @@ -56,7 +56,7 @@ static struct mtd_partition cmbvr4133_mtd_parts[] = { extern void i8259_init(void); -static int __init nec_cmbvr4133_setup(void) +static void __init nec_cmbvr4133_setup(void) { #ifdef CONFIG_ROCKHOPPER extern void disable_pcnet(void); @@ -90,7 +90,4 @@ static int __init nec_cmbvr4133_setup(void) #ifdef CONFIG_ROCKHOPPER i8259_init(); #endif - return 0; } - -early_initcall(nec_cmbvr4133_setup); diff --git a/drivers/char/lcd.c b/drivers/char/lcd.c index b77161146144..29963d8be667 100644 --- a/drivers/char/lcd.c +++ b/drivers/char/lcd.c @@ -575,8 +575,8 @@ static inline int button_pressed(void) static int lcd_waiters = 0; -static long lcd_read(struct inode *inode, struct file *file, char *buf, - unsigned long count) +static ssize_t lcd_read(struct file *file, char *buf, + size_t count, loff_t *ofs) { long buttons_now; diff --git a/drivers/char/lcd.h b/drivers/char/lcd.h index 878a95280e87..a8d4ae737158 100644 --- a/drivers/char/lcd.h +++ b/drivers/char/lcd.h @@ -22,7 +22,7 @@ static int timeout(volatile unsigned long); #define MAX_IDLE_TIME 120 struct lcd_display { - unsigned long buttons; + unsigned buttons; int size1; int size2; unsigned char line1[LCD_CHARS_PER_LINE]; diff --git a/drivers/char/qtronix.c b/drivers/char/qtronix.c index 40a3cf62e1a8..601d09baf9d7 100644 --- a/drivers/char/qtronix.c +++ b/drivers/char/qtronix.c @@ -591,6 +591,11 @@ static int __init psaux_init(void) return retval; queue = (struct aux_queue *) kmalloc(sizeof(*queue), GFP_KERNEL); + if (!queue) { + misc_deregister(&psaux_mouse); + return -ENOMEM; + } + memset(queue, 0, sizeof(*queue)); queue->head = queue->tail = 0; init_waitqueue_head(&queue->proc_list); diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig index 1cadd2c3cadd..a737886e39d1 100644 --- a/drivers/ide/Kconfig +++ b/drivers/ide/Kconfig @@ -778,6 +778,35 @@ config BLK_DEV_IDE_PMAC_BLINK This option enables the use of the sleep LED as a hard drive activity LED. +config BLK_DEV_IDE_AU1XXX + bool "IDE for AMD Alchemy Au1200" + depends on SOC_AU1200 +choice + prompt "IDE Mode for AMD Alchemy Au1200" + default CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA + depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX + +config BLK_DEV_IDE_AU1XXX_PIO_DBDMA + bool "PIO+DbDMA IDE for AMD Alchemy Au1200" + +config BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA + bool "MDMA2+DbDMA IDE for AMD Alchemy Au1200" + depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX +endchoice + +config BLK_DEV_IDE_AU1XXX_BURSTABLE_ON + bool "Enable burstable Mode on DbDMA" + default false + depends BLK_DEV_IDE_AU1XXX + help + This option enable the burstable Flag on DbDMA controller + (cf. "AMD Alchemy 'Au1200' Processor Data Book - PRELIMINARY"). + +config BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ + int "Maximum transfer size (KB) per request (up to 128)" + default "128" + depends BLK_DEV_IDE_AU1XXX + config IDE_ARM def_bool ARM && (ARCH_A5K || ARCH_CLPS7500 || ARCH_RPC || ARCH_SHARK) @@ -1013,7 +1042,7 @@ config BLK_DEV_UMC8672 endif config BLK_DEV_IDEDMA - def_bool BLK_DEV_IDEDMA_PCI || BLK_DEV_IDEDMA_PMAC || BLK_DEV_IDEDMA_ICS + def_bool BLK_DEV_IDEDMA_PCI || BLK_DEV_IDEDMA_PMAC || BLK_DEV_IDEDMA_ICS || BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA config IDEDMA_IVB bool "IGNORE word93 Validation BITS" diff --git a/drivers/ide/ide-proc.c b/drivers/ide/ide-proc.c index 4063d2c34e3d..84665e2ba3c8 100644 --- a/drivers/ide/ide-proc.c +++ b/drivers/ide/ide-proc.c @@ -64,6 +64,7 @@ static int proc_ide_read_imodel case ide_cy82c693: name = "cy82c693"; break; case ide_4drives: name = "4drives"; break; case ide_pmac: name = "mac-io"; break; + case ide_au1xxx: name = "au1xxx"; break; default: name = "(unknown)"; break; } len = sprintf(page, "%s\n", name); diff --git a/drivers/ide/mips/au1xxx-ide.c b/drivers/ide/mips/au1xxx-ide.c new file mode 100644 index 000000000000..2b6327c576b9 --- /dev/null +++ b/drivers/ide/mips/au1xxx-ide.c @@ -0,0 +1,1250 @@ +/* + * linux/drivers/ide/mips/au1xxx-ide.c version 01.30.00 Aug. 02 2005 + * + * BRIEF MODULE DESCRIPTION + * AMD Alchemy Au1xxx IDE interface routines over the Static Bus + * + * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any later + * version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE + * Interface and Linux Device Driver" Application Note. + */ +#undef REALLY_SLOW_IO /* most systems can safely undef this */ + +#include <linux/config.h> /* for CONFIG_BLK_DEV_IDEPCI */ +#include <linux/types.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/timer.h> +#include <linux/mm.h> +#include <linux/ioport.h> +#include <linux/hdreg.h> +#include <linux/init.h> +#include <linux/ide.h> +#include <linux/sysdev.h> + +#include <linux/dma-mapping.h> + +#include <asm/io.h> +#include <asm/mach-au1x00/au1xxx.h> +#include <asm/mach-au1x00/au1xxx_dbdma.h> + +#if CONFIG_PM +#include <asm/mach-au1x00/au1xxx_pm.h> +#endif + +#include <asm/mach-au1x00/au1xxx_ide.h> + +#define DRV_NAME "au1200-ide" +#define DRV_VERSION "1.0" +#define DRV_AUTHOR "AMD PCS / Pete Popov <ppopov@embeddedalley.com>" +#define DRV_DESC "Au1200 IDE" + +static _auide_hwif auide_hwif; +static spinlock_t ide_tune_drive_spin_lock = SPIN_LOCK_UNLOCKED; +static spinlock_t ide_tune_chipset_spin_lock = SPIN_LOCK_UNLOCKED; +static int dbdma_init_done = 0; + +/* + * local I/O functions + */ +u8 auide_inb(unsigned long port) +{ + return (au_readb(port)); +} + +u16 auide_inw(unsigned long port) +{ + return (au_readw(port)); +} + +u32 auide_inl(unsigned long port) +{ + return (au_readl(port)); +} + +void auide_insw(unsigned long port, void *addr, u32 count) +{ +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) + + _auide_hwif *ahwif = &auide_hwif; + chan_tab_t *ctp; + au1x_ddma_desc_t *dp; + + if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1, + DDMA_FLAGS_NOIE)) { + printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__); + return; + } + ctp = *((chan_tab_t **)ahwif->rx_chan); + dp = ctp->cur_ptr; + while (dp->dscr_cmd0 & DSCR_CMD0_V) + ; + ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); +#else + while (count--) + { + *(u16 *)addr = au_readw(port); + addr +=2 ; + } +#endif +} + +void auide_insl(unsigned long port, void *addr, u32 count) +{ + while (count--) + { + *(u32 *)addr = au_readl(port); + /* NOTE: For IDE interfaces over PCMCIA, + * 32-bit access does not work + */ + addr += 4; + } +} + +void auide_outb(u8 addr, unsigned long port) +{ + return (au_writeb(addr, port)); +} + +void auide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port) +{ + return (au_writeb(addr, port)); +} + +void auide_outw(u16 addr, unsigned long port) +{ + return (au_writew(addr, port)); +} + +void auide_outl(u32 addr, unsigned long port) +{ + return (au_writel(addr, port)); +} + +void auide_outsw(unsigned long port, void *addr, u32 count) +{ +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) + _auide_hwif *ahwif = &auide_hwif; + chan_tab_t *ctp; + au1x_ddma_desc_t *dp; + + if(!put_source_flags(ahwif->tx_chan, (void*)addr, + count << 1, DDMA_FLAGS_NOIE)) { + printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__); + return; + } + ctp = *((chan_tab_t **)ahwif->tx_chan); + dp = ctp->cur_ptr; + while (dp->dscr_cmd0 & DSCR_CMD0_V) + ; + ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); +#else + while (count--) + { + au_writew(*(u16 *)addr, port); + addr += 2; + } +#endif +} + +void auide_outsl(unsigned long port, void *addr, u32 count) +{ + while (count--) + { + au_writel(*(u32 *)addr, port); + /* NOTE: For IDE interfaces over PCMCIA, + * 32-bit access does not work + */ + addr += 4; + } +} + +static void auide_tune_drive(ide_drive_t *drive, byte pio) +{ + int mem_sttime; + int mem_stcfg; + unsigned long flags; + u8 speed; + + /* get the best pio mode for the drive */ + pio = ide_get_best_pio_mode(drive, pio, 4, NULL); + + printk("%s: setting Au1XXX IDE to PIO mode%d\n", + drive->name, pio); + + spin_lock_irqsave(&ide_tune_drive_spin_lock, flags); + + mem_sttime = 0; + mem_stcfg = au_readl(MEM_STCFG2); + + /* set pio mode! */ + switch(pio) { + case 0: + /* set timing parameters for RCS2# */ + mem_sttime = SBC_IDE_PIO0_TWCS + | SBC_IDE_PIO0_TCSH + | SBC_IDE_PIO0_TCSOFF + | SBC_IDE_PIO0_TWP + | SBC_IDE_PIO0_TCSW + | SBC_IDE_PIO0_TPM + | SBC_IDE_PIO0_TA; + /* set configuration for RCS2# */ + mem_stcfg |= TS_MASK; + mem_stcfg &= ~TCSOE_MASK; + mem_stcfg &= ~TOECS_MASK; + mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS; + + au_writel(mem_sttime,MEM_STTIME2); + au_writel(mem_stcfg,MEM_STCFG2); + break; + + case 1: + /* set timing parameters for RCS2# */ + mem_sttime = SBC_IDE_PIO1_TWCS + | SBC_IDE_PIO1_TCSH + | SBC_IDE_PIO1_TCSOFF + | SBC_IDE_PIO1_TWP + | SBC_IDE_PIO1_TCSW + | SBC_IDE_PIO1_TPM + | SBC_IDE_PIO1_TA; + /* set configuration for RCS2# */ + mem_stcfg |= TS_MASK; + mem_stcfg &= ~TCSOE_MASK; + mem_stcfg &= ~TOECS_MASK; + mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS; + break; + + case 2: + /* set timing parameters for RCS2# */ + mem_sttime = SBC_IDE_PIO2_TWCS + | SBC_IDE_PIO2_TCSH + | SBC_IDE_PIO2_TCSOFF + | SBC_IDE_PIO2_TWP + | SBC_IDE_PIO2_TCSW + | SBC_IDE_PIO2_TPM + | SBC_IDE_PIO2_TA; + /* set configuration for RCS2# */ + mem_stcfg &= ~TS_MASK; + mem_stcfg &= ~TCSOE_MASK; + mem_stcfg &= ~TOECS_MASK; + mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS; + break; + + case 3: + /* set timing parameters for RCS2# */ + mem_sttime = SBC_IDE_PIO3_TWCS + | SBC_IDE_PIO3_TCSH + | SBC_IDE_PIO3_TCSOFF + | SBC_IDE_PIO3_TWP + | SBC_IDE_PIO3_TCSW + | SBC_IDE_PIO3_TPM + | SBC_IDE_PIO3_TA; + /* set configuration for RCS2# */ + mem_stcfg |= TS_MASK; + mem_stcfg &= ~TS_MASK; + mem_stcfg &= ~TCSOE_MASK; + mem_stcfg &= ~TOECS_MASK; + mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS; + + break; + + case 4: + /* set timing parameters for RCS2# */ + mem_sttime = SBC_IDE_PIO4_TWCS + | SBC_IDE_PIO4_TCSH + | SBC_IDE_PIO4_TCSOFF + | SBC_IDE_PIO4_TWP + | SBC_IDE_PIO4_TCSW + | SBC_IDE_PIO4_TPM + | SBC_IDE_PIO4_TA; + /* set configuration for RCS2# */ + mem_stcfg &= ~TS_MASK; + mem_stcfg &= ~TCSOE_MASK; + mem_stcfg &= ~TOECS_MASK; + mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS; + break; + } + + au_writel(mem_sttime,MEM_STTIME2); + au_writel(mem_stcfg,MEM_STCFG2); + + spin_unlock_irqrestore(&ide_tune_drive_spin_lock, flags); + + speed = pio + XFER_PIO_0; + ide_config_drive_speed(drive, speed); +} + +static int auide_tune_chipset (ide_drive_t *drive, u8 speed) +{ + u8 mode = 0; + int mem_sttime; + int mem_stcfg; + unsigned long flags; +#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA + struct hd_driveid *id = drive->id; + + /* + * Now see what the current drive is capable of, + * selecting UDMA only if the mate said it was ok. + */ + if (id && (id->capability & 1) && drive->autodma && + !__ide_dma_bad_drive(drive)) { + if (!mode && (id->field_valid & 2) && (id->dma_mword & 7)) { + if (id->dma_mword & 4) + mode = XFER_MW_DMA_2; + else if (id->dma_mword & 2) + mode = XFER_MW_DMA_1; + else if (id->dma_mword & 1) + mode = XFER_MW_DMA_0; + } + } +#endif + + spin_lock_irqsave(&ide_tune_chipset_spin_lock, flags); + + mem_sttime = 0; + mem_stcfg = au_readl(MEM_STCFG2); + + switch(speed) { + case XFER_PIO_4: + case XFER_PIO_3: + case XFER_PIO_2: + case XFER_PIO_1: + case XFER_PIO_0: + auide_tune_drive(drive, (speed - XFER_PIO_0)); + break; +#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA + case XFER_MW_DMA_2: + /* set timing parameters for RCS2# */ + mem_sttime = SBC_IDE_MDMA2_TWCS + | SBC_IDE_MDMA2_TCSH + | SBC_IDE_MDMA2_TCSOFF + | SBC_IDE_MDMA2_TWP + | SBC_IDE_MDMA2_TCSW + | SBC_IDE_MDMA2_TPM + | SBC_IDE_MDMA2_TA; + /* set configuration for RCS2# */ + mem_stcfg &= ~TS_MASK; + mem_stcfg &= ~TCSOE_MASK; + mem_stcfg &= ~TOECS_MASK; + mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS; + + mode = XFER_MW_DMA_2; + break; + case XFER_MW_DMA_1: + /* set timing parameters for RCS2# */ + mem_sttime = SBC_IDE_MDMA1_TWCS + | SBC_IDE_MDMA1_TCSH + | SBC_IDE_MDMA1_TCSOFF + | SBC_IDE_MDMA1_TWP + | SBC_IDE_MDMA1_TCSW + | SBC_IDE_MDMA1_TPM + | SBC_IDE_MDMA1_TA; + /* set configuration for RCS2# */ + mem_stcfg &= ~TS_MASK; + mem_stcfg &= ~TCSOE_MASK; + mem_stcfg &= ~TOECS_MASK; + mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS; + + mode = XFER_MW_DMA_1; + break; + case XFER_MW_DMA_0: + /* set timing parameters for RCS2# */ + mem_sttime = SBC_IDE_MDMA0_TWCS + | SBC_IDE_MDMA0_TCSH + | SBC_IDE_MDMA0_TCSOFF + | SBC_IDE_MDMA0_TWP + | SBC_IDE_MDMA0_TCSW + | SBC_IDE_MDMA0_TPM + | SBC_IDE_MDMA0_TA; + /* set configuration for RCS2# */ + mem_stcfg |= TS_MASK; + mem_stcfg &= ~TCSOE_MASK; + mem_stcfg &= ~TOECS_MASK; + mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS; + + mode = XFER_MW_DMA_0; + break; +#endif + default: + return 1; + } + + /* + * Tell the drive to switch to the new mode; abort on failure. + */ + if (!mode || ide_config_drive_speed(drive, mode)) + { + return 1; /* failure */ + } + + + au_writel(mem_sttime,MEM_STTIME2); + au_writel(mem_stcfg,MEM_STCFG2); + + spin_unlock_irqrestore(&ide_tune_chipset_spin_lock, flags); + + return 0; +} + +/* + * Multi-Word DMA + DbDMA functions + */ +#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA + +static int in_drive_list(struct hd_driveid *id, + const struct drive_list_entry *drive_table) +{ + for ( ; drive_table->id_model ; drive_table++){ + if ((!strcmp(drive_table->id_model, id->model)) && + ((strstr(drive_table->id_firmware, id->fw_rev)) || + (!strcmp(drive_table->id_firmware, "ALL"))) + ) + return 1; + } + return 0; +} + +static int auide_build_sglist(ide_drive_t *drive, struct request *rq) +{ + ide_hwif_t *hwif = drive->hwif; + _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data; + struct scatterlist *sg = hwif->sg_table; + + ide_map_sg(drive, rq); + + if (rq_data_dir(rq) == READ) + hwif->sg_dma_direction = DMA_FROM_DEVICE; + else + hwif->sg_dma_direction = DMA_TO_DEVICE; + + return dma_map_sg(ahwif->dev, sg, hwif->sg_nents, + hwif->sg_dma_direction); +} + +static int auide_build_dmatable(ide_drive_t *drive) +{ + int i, iswrite, count = 0; + ide_hwif_t *hwif = HWIF(drive); + + struct request *rq = HWGROUP(drive)->rq; + + _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data; + struct scatterlist *sg; + + iswrite = (rq_data_dir(rq) == WRITE); + /* Save for interrupt context */ + ahwif->drive = drive; + + /* Build sglist */ + hwif->sg_nents = i = auide_build_sglist(drive, rq); + + if (!i) + return 0; + + /* fill the descriptors */ + sg = hwif->sg_table; + while (i && sg_dma_len(sg)) { + u32 cur_addr; + u32 cur_len; + + cur_addr = sg_dma_address(sg); + cur_len = sg_dma_len(sg); + + while (cur_len) { + u32 flags = DDMA_FLAGS_NOIE; + unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00; + + if (++count >= PRD_ENTRIES) { + printk(KERN_WARNING "%s: DMA table too small\n", + drive->name); + goto use_pio_instead; + } + + /* Lets enable intr for the last descriptor only */ + if (1==i) + flags = DDMA_FLAGS_IE; + else + flags = DDMA_FLAGS_NOIE; + + if (iswrite) { + if(!put_source_flags(ahwif->tx_chan, + (void*)(page_address(sg->page) + + sg->offset), + tc, flags)) { + printk(KERN_ERR "%s failed %d\n", + __FUNCTION__, __LINE__); + } + } else + { + if(!put_dest_flags(ahwif->rx_chan, + (void*)(page_address(sg->page) + + sg->offset), + tc, flags)) { + printk(KERN_ERR "%s failed %d\n", + __FUNCTION__, __LINE__); + } + } + + cur_addr += tc; + cur_len -= tc; + } + sg++; + i--; + } + + if (count) + return 1; + +use_pio_instead: + dma_unmap_sg(ahwif->dev, + hwif->sg_table, + hwif->sg_nents, + hwif->sg_dma_direction); + + return 0; /* revert to PIO for this request */ +} + +static int auide_dma_end(ide_drive_t *drive) +{ + ide_hwif_t *hwif = HWIF(drive); + _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data; + + if (hwif->sg_nents) { + dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents, + hwif->sg_dma_direction); + hwif->sg_nents = 0; + } + + return 0; +} + +static void auide_dma_start(ide_drive_t *drive ) +{ +// printk("%s\n", __FUNCTION__); +} + +ide_startstop_t auide_dma_intr(ide_drive_t *drive) +{ + //printk("%s\n", __FUNCTION__); + + u8 stat = 0, dma_stat = 0; + + dma_stat = HWIF(drive)->ide_dma_end(drive); + stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */ + if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) { + if (!dma_stat) { + struct request *rq = HWGROUP(drive)->rq; + + ide_end_request(drive, 1, rq->nr_sectors); + return ide_stopped; + } + printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n", + drive->name, dma_stat); + } + return ide_error(drive, "dma_intr", stat); +} + +static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command) +{ + //printk("%s\n", __FUNCTION__); + + /* issue cmd to drive */ + ide_execute_command(drive, command, &auide_dma_intr, + (2*WAIT_CMD), NULL); +} + +static int auide_dma_setup(ide_drive_t *drive) +{ +// printk("%s\n", __FUNCTION__); + + if (drive->media != ide_disk) + return 1; + + if (!auide_build_dmatable(drive)) + /* try PIO instead of DMA */ + return 1; + + drive->waiting_for_dma = 1; + + return 0; +} + +static int auide_dma_check(ide_drive_t *drive) +{ +// printk("%s\n", __FUNCTION__); + +#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA + if( !dbdma_init_done ){ + auide_hwif.white_list = in_drive_list(drive->id, + dma_white_list); + auide_hwif.black_list = in_drive_list(drive->id, + dma_black_list); + auide_hwif.drive = drive; + auide_ddma_init(&auide_hwif); + dbdma_init_done = 1; + } +#endif + + /* Is the drive in our DMA black list? */ + if ( auide_hwif.black_list ) { + drive->using_dma = 0; + printk("%s found in dma_blacklist[]! Disabling DMA.\n", + drive->id->model); + } + else + drive->using_dma = 1; + + return HWIF(drive)->ide_dma_host_on(drive); +} + +static int auide_dma_test_irq(ide_drive_t *drive) +{ +// printk("%s\n", __FUNCTION__); + + if (!drive->waiting_for_dma) + printk(KERN_WARNING "%s: ide_dma_test_irq \ + called while not waiting\n", drive->name); + + /* If dbdma didn't execute the STOP command yet, the + * active bit is still set + */ + drive->waiting_for_dma++; + if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) { + printk(KERN_WARNING "%s: timeout waiting for ddma to \ + complete\n", drive->name); + return 1; + } + udelay(10); + return 0; +} + +static int auide_dma_host_on(ide_drive_t *drive) +{ +// printk("%s\n", __FUNCTION__); + return 0; +} + +static int auide_dma_on(ide_drive_t *drive) +{ +// printk("%s\n", __FUNCTION__); + drive->using_dma = 1; + return auide_dma_host_on(drive); +} + + +static int auide_dma_host_off(ide_drive_t *drive) +{ +// printk("%s\n", __FUNCTION__); + return 0; +} + +static int auide_dma_off_quietly(ide_drive_t *drive) +{ +// printk("%s\n", __FUNCTION__); + drive->using_dma = 0; + return auide_dma_host_off(drive); +} + +static int auide_dma_lostirq(ide_drive_t *drive) +{ +// printk("%s\n", __FUNCTION__); + + printk(KERN_ERR "%s: IRQ lost\n", drive->name); + return 0; +} + +static void auide_ddma_tx_callback(int irq, void *param, struct pt_regs *regs) +{ +// printk("%s\n", __FUNCTION__); + + _auide_hwif *ahwif = (_auide_hwif*)param; + ahwif->drive->waiting_for_dma = 0; + return; +} + +static void auide_ddma_rx_callback(int irq, void *param, struct pt_regs *regs) +{ +// printk("%s\n", __FUNCTION__); + + _auide_hwif *ahwif = (_auide_hwif*)param; + ahwif->drive->waiting_for_dma = 0; + return; +} + +static int auide_dma_timeout(ide_drive_t *drive) +{ +// printk("%s\n", __FUNCTION__); + + printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name); + + if (HWIF(drive)->ide_dma_test_irq(drive)) + return 0; + + return HWIF(drive)->ide_dma_end(drive); +} +#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ + + +static int auide_ddma_init( _auide_hwif *auide ) +{ +// printk("%s\n", __FUNCTION__); + + dbdev_tab_t source_dev_tab; +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) + dbdev_tab_t target_dev_tab; + ide_hwif_t *hwif = auide->hwif; + char warning_output [2][80]; + int i; +#endif + + /* Add our custom device to DDMA device table */ + /* Create our new device entries in the table */ +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) + source_dev_tab.dev_id = AU1XXX_ATA_DDMA_REQ; + + if( auide->white_list || auide->black_list ){ + source_dev_tab.dev_tsize = 8; + source_dev_tab.dev_devwidth = 32; + source_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR; + source_dev_tab.dev_intlevel = 0; + source_dev_tab.dev_intpolarity = 0; + + /* init device table for target - static bus controller - */ + target_dev_tab.dev_id = DSCR_CMD0_ALWAYS; + target_dev_tab.dev_tsize = 8; + target_dev_tab.dev_devwidth = 32; + target_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR; + target_dev_tab.dev_intlevel = 0; + target_dev_tab.dev_intpolarity = 0; + target_dev_tab.dev_flags = DEV_FLAGS_ANYUSE; + } + else{ + source_dev_tab.dev_tsize = 1; + source_dev_tab.dev_devwidth = 16; + source_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR; + source_dev_tab.dev_intlevel = 0; + source_dev_tab.dev_intpolarity = 0; + + /* init device table for target - static bus controller - */ + target_dev_tab.dev_id = DSCR_CMD0_ALWAYS; + target_dev_tab.dev_tsize = 1; + target_dev_tab.dev_devwidth = 16; + target_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR; + target_dev_tab.dev_intlevel = 0; + target_dev_tab.dev_intpolarity = 0; + target_dev_tab.dev_flags = DEV_FLAGS_ANYUSE; + + sprintf(&warning_output[0][0], + "%s is not on ide driver white list.", + auide_hwif.drive->id->model); + for ( i=strlen(&warning_output[0][0]) ; i<76; i++ ){ + sprintf(&warning_output[0][i]," "); + } + + sprintf(&warning_output[1][0], + "To add %s please read 'Documentation/mips/AU1xxx_IDE.README'.", + auide_hwif.drive->id->model); + for ( i=strlen(&warning_output[1][0]) ; i<76; i++ ){ + sprintf(&warning_output[1][i]," "); + } + + printk("\n****************************************"); + printk("****************************************\n"); + printk("* %s *\n",&warning_output[0][0]); + printk("* Switch to safe MWDMA Mode! "); + printk(" *\n"); + printk("* %s *\n",&warning_output[1][0]); + printk("****************************************"); + printk("****************************************\n\n"); + } +#else + source_dev_tab.dev_id = DSCR_CMD0_ALWAYS; + source_dev_tab.dev_tsize = 8; + source_dev_tab.dev_devwidth = 32; + source_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR; + source_dev_tab.dev_intlevel = 0; + source_dev_tab.dev_intpolarity = 0; +#endif + +#if CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON + /* set flags for tx channel */ + source_dev_tab.dev_flags = DEV_FLAGS_OUT + | DEV_FLAGS_SYNC + | DEV_FLAGS_BURSTABLE; + auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); + /* set flags for rx channel */ + source_dev_tab.dev_flags = DEV_FLAGS_IN + | DEV_FLAGS_SYNC + | DEV_FLAGS_BURSTABLE; + auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); +#else + /* set flags for tx channel */ + source_dev_tab.dev_flags = DEV_FLAGS_OUT | DEV_FLAGS_SYNC; + auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); + /* set flags for rx channel */ + source_dev_tab.dev_flags = DEV_FLAGS_IN | DEV_FLAGS_SYNC; + auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); +#endif + +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) + + auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); + + /* Get a channel for TX */ + auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id, + auide->tx_dev_id, + auide_ddma_tx_callback, + (void*)auide); + /* Get a channel for RX */ + auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, + auide->target_dev_id, + auide_ddma_rx_callback, + (void*)auide); +#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */ + /* + * Note: if call back is not enabled, update ctp->cur_ptr manually + */ + auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS, + auide->tx_dev_id, + NULL, + (void*)auide); + auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, + DSCR_CMD0_ALWAYS, + NULL, + (void*)auide); +#endif + auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, + NUM_DESCRIPTORS); + auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, + NUM_DESCRIPTORS); + +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) + hwif->dmatable_cpu = dma_alloc_coherent(auide->dev, + PRD_ENTRIES * PRD_BYTES, /* 1 Page */ + &hwif->dmatable_dma, GFP_KERNEL); + + auide->sg_table = kmalloc(sizeof(struct scatterlist) * PRD_ENTRIES, + GFP_KERNEL|GFP_DMA); + if (auide->sg_table == NULL) { + return -ENOMEM; + } +#endif + au1xxx_dbdma_start( auide->tx_chan ); + au1xxx_dbdma_start( auide->rx_chan ); + return 0; +} + +static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif) +{ + int i; +#define ide_ioreg_t unsigned long + ide_ioreg_t *ata_regs = hw->io_ports; + + /* fixme */ + for (i = 0; i < IDE_CONTROL_OFFSET; i++) { + *ata_regs++ = (ide_ioreg_t) ahwif->regbase + + (ide_ioreg_t)(i << AU1XXX_ATA_REG_OFFSET); + } + + /* set the Alternative Status register */ + *ata_regs = (ide_ioreg_t) ahwif->regbase + + (ide_ioreg_t)(14 << AU1XXX_ATA_REG_OFFSET); +} + +static int au_ide_probe(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + _auide_hwif *ahwif = &auide_hwif; + ide_hwif_t *hwif; + struct resource *res; + int ret = 0; + +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) + char *mode = "MWDMA2"; +#elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) + char *mode = "PIO+DDMA(offload)"; +#endif + + memset(&auide_hwif, 0, sizeof(_auide_hwif)); + auide_hwif.dev = 0; + + ahwif->dev = dev; + ahwif->irq = platform_get_irq(pdev, 0); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (res == NULL) { + pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id); + ret = -ENODEV; + goto out; + } + + if (!request_mem_region (res->start, res->end-res->start, pdev->name)) { + pr_debug("%s: request_mem_region failed\n", DRV_NAME); + ret = -EBUSY; + goto out; + } + + ahwif->regbase = (u32)ioremap(res->start, res->end-res->start); + if (ahwif->regbase == 0) { + ret = -ENOMEM; + goto out; + } + + hwif = &ide_hwifs[pdev->id]; + hw_regs_t *hw = &hwif->hw; + hwif->irq = hw->irq = ahwif->irq; + hwif->chipset = ide_au1xxx; + + auide_setup_ports(hw, ahwif); + memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports)); + +#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ + hwif->rqsize = CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ; + hwif->rqsize = ((hwif->rqsize > AU1XXX_ATA_RQSIZE) + || (hwif->rqsize < 32)) ? AU1XXX_ATA_RQSIZE : hwif->rqsize; +#else /* if kernel config is not set */ + hwif->rqsize = AU1XXX_ATA_RQSIZE; +#endif + + hwif->ultra_mask = 0x0; /* Disable Ultra DMA */ +#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA + hwif->mwdma_mask = 0x07; /* Multimode-2 DMA */ + hwif->swdma_mask = 0x07; +#else + hwif->mwdma_mask = 0x0; + hwif->swdma_mask = 0x0; +#endif + //hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET]; + hwif->noprobe = 0; + hwif->drives[0].unmask = 1; + hwif->drives[1].unmask = 1; + + /* hold should be on in all cases */ + hwif->hold = 1; + hwif->mmio = 2; + + /* set up local I/O function entry points */ + hwif->INB = auide_inb; + hwif->INW = auide_inw; + hwif->INL = auide_inl; + hwif->INSW = auide_insw; + hwif->INSL = auide_insl; + hwif->OUTB = auide_outb; + hwif->OUTBSYNC = auide_outbsync; + hwif->OUTW = auide_outw; + hwif->OUTL = auide_outl; + hwif->OUTSW = auide_outsw; + hwif->OUTSL = auide_outsl; + + hwif->tuneproc = &auide_tune_drive; + hwif->speedproc = &auide_tune_chipset; + +#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA + hwif->ide_dma_off_quietly = &auide_dma_off_quietly; + hwif->ide_dma_timeout = &auide_dma_timeout; + + hwif->ide_dma_check = &auide_dma_check; + hwif->dma_exec_cmd = &auide_dma_exec_cmd; + hwif->dma_start = &auide_dma_start; + hwif->ide_dma_end = &auide_dma_end; + hwif->dma_setup = &auide_dma_setup; + hwif->ide_dma_test_irq = &auide_dma_test_irq; + hwif->ide_dma_host_off = &auide_dma_host_off; + hwif->ide_dma_host_on = &auide_dma_host_on; + hwif->ide_dma_lostirq = &auide_dma_lostirq; + hwif->ide_dma_on = &auide_dma_on; + + hwif->autodma = 1; + hwif->drives[0].autodma = hwif->autodma; + hwif->drives[1].autodma = hwif->autodma; + hwif->atapi_dma = 1; + hwif->drives[0].using_dma = 1; + hwif->drives[1].using_dma = 1; +#else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ + hwif->autodma = 0; + hwif->channel = 0; + hwif->hold = 1; + hwif->select_data = 0; /* no chipset-specific code */ + hwif->config_data = 0; /* no chipset-specific code */ + + hwif->drives[0].autodma = 0; + hwif->drives[0].drive_data = 0; /* no drive data */ + hwif->drives[0].using_dma = 0; + hwif->drives[0].waiting_for_dma = 0; + hwif->drives[0].autotune = 1; /* 1=autotune, 2=noautotune, 0=default */ + /* secondary hdd not supported */ + hwif->drives[1].autodma = 0; + + hwif->drives[1].drive_data = 0; + hwif->drives[1].using_dma = 0; + hwif->drives[1].waiting_for_dma = 0; + hwif->drives[1].autotune = 2; /* 1=autotune, 2=noautotune, 0=default */ +#endif + hwif->drives[0].io_32bit = 0; /* 0=16-bit, 1=32-bit, 2/3=32bit+sync */ + hwif->drives[1].io_32bit = 0; /* 0=16-bit, 1=32-bit, 2/3=32bit+sync */ + + /*Register Driver with PM Framework*/ +#ifdef CONFIG_PM + auide_hwif.pm.lock = SPIN_LOCK_UNLOCKED; + auide_hwif.pm.stopped = 0; + + auide_hwif.pm.dev = new_au1xxx_power_device( "ide", + &au1200ide_pm_callback, + NULL); + if ( auide_hwif.pm.dev == NULL ) + printk(KERN_INFO "Unable to create a power management \ + device entry for the au1200-IDE.\n"); + else + printk(KERN_INFO "Power management device entry for the \ + au1200-IDE loaded.\n"); +#endif + + auide_hwif.hwif = hwif; + hwif->hwif_data = &auide_hwif; + +#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA + auide_ddma_init(&auide_hwif); + dbdma_init_done = 1; +#endif + + probe_hwif_init(hwif); + dev_set_drvdata(dev, hwif); + + printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode ); + +out: + return ret; +} + +static int au_ide_remove(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct resource *res; + ide_hwif_t *hwif = dev_get_drvdata(dev); + _auide_hwif *ahwif = &auide_hwif; + + ide_unregister(hwif - ide_hwifs); + + iounmap((void *)ahwif->regbase); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, res->end - res->start); + + return 0; +} + +static struct device_driver au1200_ide_driver = { + .name = "au1200-ide", + .bus = &platform_bus_type, + .probe = au_ide_probe, + .remove = au_ide_remove, +}; + +static int __init au_ide_init(void) +{ + return driver_register(&au1200_ide_driver); +} + +static void __init au_ide_exit(void) +{ + driver_unregister(&au1200_ide_driver); +} + +#ifdef CONFIG_PM +int au1200ide_pm_callback( au1xxx_power_dev_t *dev,\ + au1xxx_request_t request, void *data) { + + unsigned int d, err = 0; + unsigned long flags; + + spin_lock_irqsave(auide_hwif.pm.lock, flags); + + switch (request){ + case AU1XXX_PM_SLEEP: + err = au1xxxide_pm_sleep(dev); + break; + case AU1XXX_PM_WAKEUP: + d = *((unsigned int*)data); + if ( d > 0 && d <= 99) { + err = au1xxxide_pm_standby(dev); + } + else { + err = au1xxxide_pm_resume(dev); + } + break; + case AU1XXX_PM_GETSTATUS: + err = au1xxxide_pm_getstatus(dev); + break; + case AU1XXX_PM_ACCESS: + err = au1xxxide_pm_access(dev); + break; + case AU1XXX_PM_IDLE: + err = au1xxxide_pm_idle(dev); + break; + case AU1XXX_PM_CLEANUP: + err = au1xxxide_pm_cleanup(dev); + break; + default: + err = -1; + break; + } + + spin_unlock_irqrestore(auide_hwif.pm.lock, flags); + + return err; +} + +static int au1xxxide_pm_standby( au1xxx_power_dev_t *dev ) { + return 0; +} + +static int au1xxxide_pm_sleep( au1xxx_power_dev_t *dev ) { + + int retval; + ide_hwif_t *hwif = auide_hwif.hwif; + struct request rq; + struct request_pm_state rqpm; + ide_task_t args; + + if(auide_hwif.pm.stopped) + return -1; + + /* + * wait until hard disc is ready + */ + if ( wait_for_ready(&hwif->drives[0], 35000) ) { + printk("Wait for drive sleep timeout!\n"); + retval = -1; + } + + /* + * sequenz to tell the high level ide driver that pm is resuming + */ + memset(&rq, 0, sizeof(rq)); + memset(&rqpm, 0, sizeof(rqpm)); + memset(&args, 0, sizeof(args)); + rq.flags = REQ_PM_SUSPEND; + rq.special = &args; + rq.pm = &rqpm; + rqpm.pm_step = ide_pm_state_start_suspend; + rqpm.pm_state = PMSG_SUSPEND; + + retval = ide_do_drive_cmd(&hwif->drives[0], &rq, ide_wait); + + if (wait_for_ready (&hwif->drives[0], 35000)) { + printk("Wait for drive sleep timeout!\n"); + retval = -1; + } + + /* + * stop dbdma channels + */ + au1xxx_dbdma_reset(auide_hwif.tx_chan); + au1xxx_dbdma_reset(auide_hwif.rx_chan); + + auide_hwif.pm.stopped = 1; + + return retval; +} + +static int au1xxxide_pm_resume( au1xxx_power_dev_t *dev ) { + + int retval; + ide_hwif_t *hwif = auide_hwif.hwif; + struct request rq; + struct request_pm_state rqpm; + ide_task_t args; + + if(!auide_hwif.pm.stopped) + return -1; + + /* + * start dbdma channels + */ + au1xxx_dbdma_start(auide_hwif.tx_chan); + au1xxx_dbdma_start(auide_hwif.rx_chan); + + /* + * wait until hard disc is ready + */ + if (wait_for_ready ( &hwif->drives[0], 35000)) { + printk("Wait for drive wake up timeout!\n"); + retval = -1; + } + + /* + * sequenz to tell the high level ide driver that pm is resuming + */ + memset(&rq, 0, sizeof(rq)); + memset(&rqpm, 0, sizeof(rqpm)); + memset(&args, 0, sizeof(args)); + rq.flags = REQ_PM_RESUME; + rq.special = &args; + rq.pm = &rqpm; + rqpm.pm_step = ide_pm_state_start_resume; + rqpm.pm_state = PMSG_ON; + + retval = ide_do_drive_cmd(&hwif->drives[0], &rq, ide_head_wait); + + /* + * wait for hard disc + */ + if ( wait_for_ready(&hwif->drives[0], 35000) ) { + printk("Wait for drive wake up timeout!\n"); + retval = -1; + } + + auide_hwif.pm.stopped = 0; + + return retval; +} + +static int au1xxxide_pm_getstatus( au1xxx_power_dev_t *dev ) { + return dev->cur_state; +} + +static int au1xxxide_pm_access( au1xxx_power_dev_t *dev ) { + if (dev->cur_state != AWAKE_STATE) + return 0; + else + return -1; +} + +static int au1xxxide_pm_idle( au1xxx_power_dev_t *dev ) { + return 0; +} + +static int au1xxxide_pm_cleanup( au1xxx_power_dev_t *dev ) { + return 0; +} +#endif /* CONFIG_PM */ + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("AU1200 IDE driver"); + +module_init(au_ide_init); +module_exit(au_ide_exit); diff --git a/drivers/media/video/indycam.c b/drivers/media/video/indycam.c index b2b0384cd4b9..26dd06ec89a2 100644 --- a/drivers/media/video/indycam.c +++ b/drivers/media/video/indycam.c @@ -9,16 +9,16 @@ * published by the Free Software Foundation. */ -#include <linux/module.h> -#include <linux/init.h> #include <linux/delay.h> #include <linux/errno.h> #include <linux/fs.h> +#include <linux/init.h> #include <linux/kernel.h> #include <linux/major.h> -#include <linux/slab.h> +#include <linux/module.h> #include <linux/mm.h> #include <linux/sched.h> +#include <linux/slab.h> #include <linux/videodev.h> /* IndyCam decodes stream of photons into digital image representation ;-) */ @@ -44,8 +44,6 @@ MODULE_LICENSE("GPL"); #define indycam_regdump(client) #endif -#define VINO_ADAPTER (I2C_ALGO_SGI | I2C_HW_SGI_VINO) - struct indycam { struct i2c_client *client; int version; @@ -300,7 +298,7 @@ out_free_client: static int indycam_probe(struct i2c_adapter *adap) { /* Indy specific crap */ - if (adap->id == VINO_ADAPTER) + if (adap->id == I2C_HW_SGI_VINO) return indycam_attach(adap, INDYCAM_ADDR, 0); /* Feel free to add probe here :-) */ return -ENODEV; diff --git a/drivers/media/video/saa7191.c b/drivers/media/video/saa7191.c index 454f5c1199b4..3ddbb62312be 100644 --- a/drivers/media/video/saa7191.c +++ b/drivers/media/video/saa7191.c @@ -9,16 +9,16 @@ * published by the Free Software Foundation. */ -#include <linux/module.h> -#include <linux/init.h> #include <linux/delay.h> #include <linux/errno.h> #include <linux/fs.h> +#include <linux/init.h> #include <linux/kernel.h> #include <linux/major.h> -#include <linux/slab.h> +#include <linux/module.h> #include <linux/mm.h> #include <linux/sched.h> +#include <linux/slab.h> #include <linux/videodev.h> #include <linux/video_decoder.h> @@ -33,8 +33,6 @@ MODULE_VERSION(SAA7191_MODULE_VERSION); MODULE_AUTHOR("Mikael Nousiainen <tmnousia@cc.hut.fi>"); MODULE_LICENSE("GPL"); -#define VINO_ADAPTER (I2C_ALGO_SGI | I2C_HW_SGI_VINO) - struct saa7191 { struct i2c_client *client; @@ -337,7 +335,7 @@ out_free_client: static int saa7191_probe(struct i2c_adapter *adap) { /* Always connected to VINO */ - if (adap->id == VINO_ADAPTER) + if (adap->id == I2C_HW_SGI_VINO) return saa7191_attach(adap, SAA7191_ADDR, 0); /* Feel free to add probe here :-) */ return -ENODEV; @@ -364,7 +362,7 @@ static int saa7191_command(struct i2c_client *client, unsigned int cmd, cap->flags = VIDEO_DECODER_PAL | VIDEO_DECODER_NTSC | VIDEO_DECODER_SECAM | VIDEO_DECODER_AUTO; - cap->inputs = (client->adapter->id == VINO_ADAPTER) ? 2 : 1; + cap->inputs = (client->adapter->id == I2C_HW_SGI_VINO) ? 2 : 1; cap->outputs = 1; break; } @@ -422,7 +420,7 @@ static int saa7191_command(struct i2c_client *client, unsigned int cmd, int *iarg = arg; switch (client->adapter->id) { - case VINO_ADAPTER: + case I2C_HW_SGI_VINO: return saa7191_set_input(client, *iarg); default: if (*iarg != 0) diff --git a/drivers/media/video/vino.c b/drivers/media/video/vino.c index d8a0f763ca10..ed4394e854ab 100644 --- a/drivers/media/video/vino.c +++ b/drivers/media/video/vino.c @@ -26,14 +26,15 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/delay.h> +#include <linux/dma-mapping.h> #include <linux/errno.h> #include <linux/fs.h> +#include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/mm.h> -#include <linux/interrupt.h> -#include <linux/dma-mapping.h> -#include <linux/time.h> #include <linux/moduleparam.h> +#include <linux/time.h> +#include <linux/version.h> #ifdef CONFIG_KMOD #include <linux/kmod.h> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 4991bbd054f3..c483a863b116 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -60,4 +60,13 @@ config MMC_WBSD If unsure, say N. +config MMC_AU1X + tristate "Alchemy AU1XX0 MMC Card Interface support" + depends on SOC_AU1X00 && MMC + help + This selects the AMD Alchemy(R) Multimedia card interface. + iIf you have a Alchemy platform with a MMC slot, say Y or M here. + + If unsure, say N. + endmenu diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 89510c2086c7..e351e71146e9 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -18,5 +18,6 @@ obj-$(CONFIG_MMC_BLOCK) += mmc_block.o obj-$(CONFIG_MMC_ARMMMCI) += mmci.o obj-$(CONFIG_MMC_PXA) += pxamci.o obj-$(CONFIG_MMC_WBSD) += wbsd.o +obj-$(CONFIG_MMC_AU1X) += au1xmmc.o mmc_core-y := mmc.o mmc_queue.o mmc_sysfs.o diff --git a/drivers/mmc/au1xmmc.c b/drivers/mmc/au1xmmc.c new file mode 100644 index 000000000000..aaf04638054e --- /dev/null +++ b/drivers/mmc/au1xmmc.c @@ -0,0 +1,1026 @@ +/* + * linux/drivers/mmc/au1xmmc.c - AU1XX0 MMC driver + * + * Copyright (c) 2005, Advanced Micro Devices, Inc. + * + * Developed with help from the 2.4.30 MMC AU1XXX controller including + * the following copyright notices: + * Copyright (c) 2003-2004 Embedded Edge, LLC. + * Portions Copyright (C) 2002 Embedix, Inc + * Copyright 2002 Hewlett-Packard Company + + * 2.6 version of this driver inspired by: + * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman, + * All Rights Reserved. + * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King, + * All Rights Reserved. + * + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* Why is a timer used to detect insert events? + * + * From the AU1100 MMC application guide: + * If the Au1100-based design is intended to support both MultiMediaCards + * and 1- or 4-data bit SecureDigital cards, then the solution is to + * connect a weak (560KOhm) pull-up resistor to connector pin 1. + * In doing so, a MMC card never enters SPI-mode communications, + * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective + * (the low to high transition will not occur). + * + * So we use the timer to check the status manually. + */ + +#include <linux/config.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/mm.h> +#include <linux/interrupt.h> +#include <linux/dma-mapping.h> + +#include <linux/mmc/host.h> +#include <linux/mmc/protocol.h> +#include <asm/io.h> +#include <asm/mach-au1x00/au1000.h> +#include <asm/mach-au1x00/au1xxx_dbdma.h> +#include <asm/mach-au1x00/au1100_mmc.h> +#include <asm/scatterlist.h> + +#include <au1xxx.h> +#include "au1xmmc.h" + +#define DRIVER_NAME "au1xxx-mmc" + +/* Set this to enable special debugging macros */ +/* #define MMC_DEBUG */ + +#ifdef MMC_DEBUG +#define DEBUG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args) +#else +#define DEBUG(fmt, idx, args...) +#endif + +const struct { + u32 iobase; + u32 tx_devid, rx_devid; + u16 bcsrpwr; + u16 bcsrstatus; + u16 wpstatus; +} au1xmmc_card_table[] = { + { SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0, + BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP }, +#ifndef CONFIG_MIPS_DB1200 + { SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1, + BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP } +#endif +}; + +#define AU1XMMC_CONTROLLER_COUNT \ + (sizeof(au1xmmc_card_table) / sizeof(au1xmmc_card_table[0])) + +/* This array stores pointers for the hosts (used by the IRQ handler) */ +struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT]; +static int dma = 1; + +#ifdef MODULE +MODULE_PARM(dma, "i"); +MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)"); +#endif + +static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) +{ + u32 val = au_readl(HOST_CONFIG(host)); + val |= mask; + au_writel(val, HOST_CONFIG(host)); + au_sync(); +} + +static inline void FLUSH_FIFO(struct au1xmmc_host *host) +{ + u32 val = au_readl(HOST_CONFIG2(host)); + + au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host)); + au_sync_delay(1); + + /* SEND_STOP will turn off clock control - this re-enables it */ + val &= ~SD_CONFIG2_DF; + + au_writel(val, HOST_CONFIG2(host)); + au_sync(); +} + +static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask) +{ + u32 val = au_readl(HOST_CONFIG(host)); + val &= ~mask; + au_writel(val, HOST_CONFIG(host)); + au_sync(); +} + +static inline void SEND_STOP(struct au1xmmc_host *host) +{ + + /* We know the value of CONFIG2, so avoid a read we don't need */ + u32 mask = SD_CONFIG2_EN; + + WARN_ON(host->status != HOST_S_DATA); + host->status = HOST_S_STOP; + + au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host)); + au_sync(); + + /* Send the stop commmand */ + au_writel(STOP_CMD, HOST_CMD(host)); +} + +static void au1xmmc_set_power(struct au1xmmc_host *host, int state) +{ + + u32 val = au1xmmc_card_table[host->id].bcsrpwr; + + bcsr->board &= ~val; + if (state) bcsr->board |= val; + + au_sync_delay(1); +} + +static inline int au1xmmc_card_inserted(struct au1xmmc_host *host) +{ + return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus) + ? 1 : 0; +} + +static inline int au1xmmc_card_readonly(struct au1xmmc_host *host) +{ + return (bcsr->status & au1xmmc_card_table[host->id].wpstatus) + ? 1 : 0; +} + +static void au1xmmc_finish_request(struct au1xmmc_host *host) +{ + + struct mmc_request *mrq = host->mrq; + + host->mrq = NULL; + host->flags &= HOST_F_ACTIVE; + + host->dma.len = 0; + host->dma.dir = 0; + + host->pio.index = 0; + host->pio.offset = 0; + host->pio.len = 0; + + host->status = HOST_S_IDLE; + + bcsr->disk_leds |= (1 << 8); + + mmc_request_done(host->mmc, mrq); +} + +static void au1xmmc_tasklet_finish(unsigned long param) +{ + struct au1xmmc_host *host = (struct au1xmmc_host *) param; + au1xmmc_finish_request(host); +} + +static int au1xmmc_send_command(struct au1xmmc_host *host, int wait, + struct mmc_command *cmd) +{ + + u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT); + + switch(cmd->flags) { + case MMC_RSP_R1: + mmccmd |= SD_CMD_RT_1; + break; + case MMC_RSP_R1B: + mmccmd |= SD_CMD_RT_1B; + break; + case MMC_RSP_R2: + mmccmd |= SD_CMD_RT_2; + break; + case MMC_RSP_R3: + mmccmd |= SD_CMD_RT_3; + break; + } + + switch(cmd->opcode) { + case MMC_READ_SINGLE_BLOCK: + case SD_APP_SEND_SCR: + mmccmd |= SD_CMD_CT_2; + break; + case MMC_READ_MULTIPLE_BLOCK: + mmccmd |= SD_CMD_CT_4; + break; + case MMC_WRITE_BLOCK: + mmccmd |= SD_CMD_CT_1; + break; + + case MMC_WRITE_MULTIPLE_BLOCK: + mmccmd |= SD_CMD_CT_3; + break; + case MMC_STOP_TRANSMISSION: + mmccmd |= SD_CMD_CT_7; + break; + } + + au_writel(cmd->arg, HOST_CMDARG(host)); + au_sync(); + + if (wait) + IRQ_OFF(host, SD_CONFIG_CR); + + au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host)); + au_sync(); + + /* Wait for the command to go on the line */ + + while(1) { + if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO)) + break; + } + + /* Wait for the command to come back */ + + if (wait) { + u32 status = au_readl(HOST_STATUS(host)); + + while(!(status & SD_STATUS_CR)) + status = au_readl(HOST_STATUS(host)); + + /* Clear the CR status */ + au_writel(SD_STATUS_CR, HOST_STATUS(host)); + + IRQ_ON(host, SD_CONFIG_CR); + } + + return MMC_ERR_NONE; +} + +static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) +{ + + struct mmc_request *mrq = host->mrq; + struct mmc_data *data; + u32 crc; + + WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP); + + if (host->mrq == NULL) + return; + + data = mrq->cmd->data; + + if (status == 0) + status = au_readl(HOST_STATUS(host)); + + /* The transaction is really over when the SD_STATUS_DB bit is clear */ + + while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB)) + status = au_readl(HOST_STATUS(host)); + + data->error = MMC_ERR_NONE; + dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir); + + /* Process any errors */ + + crc = (status & (SD_STATUS_WC | SD_STATUS_RC)); + if (host->flags & HOST_F_XMIT) + crc |= ((status & 0x07) == 0x02) ? 0 : 1; + + if (crc) + data->error = MMC_ERR_BADCRC; + + /* Clear the CRC bits */ + au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host)); + + data->bytes_xfered = 0; + + if (data->error == MMC_ERR_NONE) { + if (host->flags & HOST_F_DMA) { + u32 chan = DMA_CHANNEL(host); + + chan_tab_t *c = *((chan_tab_t **) chan); + au1x_dma_chan_t *cp = c->chan_ptr; + data->bytes_xfered = cp->ddma_bytecnt; + } + else + data->bytes_xfered = + (data->blocks * (1 << data->blksz_bits)) - + host->pio.len; + } + + au1xmmc_finish_request(host); +} + +static void au1xmmc_tasklet_data(unsigned long param) +{ + struct au1xmmc_host *host = (struct au1xmmc_host *) param; + + u32 status = au_readl(HOST_STATUS(host)); + au1xmmc_data_complete(host, status); +} + +#define AU1XMMC_MAX_TRANSFER 8 + +static void au1xmmc_send_pio(struct au1xmmc_host *host) +{ + + struct mmc_data *data = 0; + int sg_len, max, count = 0; + unsigned char *sg_ptr; + u32 status = 0; + struct scatterlist *sg; + + data = host->mrq->data; + + if (!(host->flags & HOST_F_XMIT)) + return; + + /* This is the pointer to the data buffer */ + sg = &data->sg[host->pio.index]; + sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset; + + /* This is the space left inside the buffer */ + sg_len = data->sg[host->pio.index].length - host->pio.offset; + + /* Check to if we need less then the size of the sg_buffer */ + + max = (sg_len > host->pio.len) ? host->pio.len : sg_len; + if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER; + + for(count = 0; count < max; count++ ) { + unsigned char val; + + status = au_readl(HOST_STATUS(host)); + + if (!(status & SD_STATUS_TH)) + break; + + val = *sg_ptr++; + + au_writel((unsigned long) val, HOST_TXPORT(host)); + au_sync(); + } + + host->pio.len -= count; + host->pio.offset += count; + + if (count == sg_len) { + host->pio.index++; + host->pio.offset = 0; + } + + if (host->pio.len == 0) { + IRQ_OFF(host, SD_CONFIG_TH); + + if (host->flags & HOST_F_STOP) + SEND_STOP(host); + + tasklet_schedule(&host->data_task); + } +} + +static void au1xmmc_receive_pio(struct au1xmmc_host *host) +{ + + struct mmc_data *data = 0; + int sg_len = 0, max = 0, count = 0; + unsigned char *sg_ptr = 0; + u32 status = 0; + struct scatterlist *sg; + + data = host->mrq->data; + + if (!(host->flags & HOST_F_RECV)) + return; + + max = host->pio.len; + + if (host->pio.index < host->dma.len) { + sg = &data->sg[host->pio.index]; + sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset; + + /* This is the space left inside the buffer */ + sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset; + + /* Check to if we need less then the size of the sg_buffer */ + if (sg_len < max) max = sg_len; + } + + if (max > AU1XMMC_MAX_TRANSFER) + max = AU1XMMC_MAX_TRANSFER; + + for(count = 0; count < max; count++ ) { + u32 val; + status = au_readl(HOST_STATUS(host)); + + if (!(status & SD_STATUS_NE)) + break; + + if (status & SD_STATUS_RC) { + DEBUG("RX CRC Error [%d + %d].\n", host->id, + host->pio.len, count); + break; + } + + if (status & SD_STATUS_RO) { + DEBUG("RX Overrun [%d + %d]\n", host->id, + host->pio.len, count); + break; + } + else if (status & SD_STATUS_RU) { + DEBUG("RX Underrun [%d + %d]\n", host->id, + host->pio.len, count); + break; + } + + val = au_readl(HOST_RXPORT(host)); + + if (sg_ptr) + *sg_ptr++ = (unsigned char) (val & 0xFF); + } + + host->pio.len -= count; + host->pio.offset += count; + + if (sg_len && count == sg_len) { + host->pio.index++; + host->pio.offset = 0; + } + + if (host->pio.len == 0) { + //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); + IRQ_OFF(host, SD_CONFIG_NE); + + if (host->flags & HOST_F_STOP) + SEND_STOP(host); + + tasklet_schedule(&host->data_task); + } +} + +/* static void au1xmmc_cmd_complete + This is called when a command has been completed - grab the response + and check for errors. Then start the data transfer if it is indicated. +*/ + +static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) +{ + + struct mmc_request *mrq = host->mrq; + struct mmc_command *cmd; + int trans; + + if (!host->mrq) + return; + + cmd = mrq->cmd; + cmd->error = MMC_ERR_NONE; + + if ((cmd->flags & MMC_RSP_MASK) == MMC_RSP_SHORT) { + + /* Techincally, we should be getting all 48 bits of the response + * (SD_RESP1 + SD_RESP2), but because our response omits the CRC, + * our data ends up being shifted 8 bits to the right. In this case, + * that means that the OSR data starts at bit 31, so we can just + * read RESP0 and return that + */ + + cmd->resp[0] = au_readl(host->iobase + SD_RESP0); + } + else if ((cmd->flags & MMC_RSP_MASK) == MMC_RSP_LONG) { + u32 r[4]; + int i; + + r[0] = au_readl(host->iobase + SD_RESP3); + r[1] = au_readl(host->iobase + SD_RESP2); + r[2] = au_readl(host->iobase + SD_RESP1); + r[3] = au_readl(host->iobase + SD_RESP0); + + /* The CRC is omitted from the response, so really we only got + * 120 bytes, but the engine expects 128 bits, so we have to shift + * things up + */ + + for(i = 0; i < 4; i++) { + cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8; + if (i != 3) cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24; + } + } + + /* Figure out errors */ + + if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC)) + cmd->error = MMC_ERR_BADCRC; + + trans = host->flags & (HOST_F_XMIT | HOST_F_RECV); + + if (!trans || cmd->error != MMC_ERR_NONE) { + + IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF); + tasklet_schedule(&host->finish_task); + return; + } + + host->status = HOST_S_DATA; + + if (host->flags & HOST_F_DMA) { + u32 channel = DMA_CHANNEL(host); + + /* Start the DMA as soon as the buffer gets something in it */ + + if (host->flags & HOST_F_RECV) { + u32 mask = SD_STATUS_DB | SD_STATUS_NE; + + while((status & mask) != mask) + status = au_readl(HOST_STATUS(host)); + } + + au1xxx_dbdma_start(channel); + } +} + +static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) +{ + + unsigned int pbus = get_au1x00_speed(); + unsigned int divisor; + u32 config; + + /* From databook: + divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1 + */ + + pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2); + pbus /= 2; + + divisor = ((pbus / rate) / 2) - 1; + + config = au_readl(HOST_CONFIG(host)); + + config &= ~(SD_CONFIG_DIV); + config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE; + + au_writel(config, HOST_CONFIG(host)); + au_sync(); +} + +static int +au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) +{ + + int datalen = data->blocks * (1 << data->blksz_bits); + + if (dma != 0) + host->flags |= HOST_F_DMA; + + if (data->flags & MMC_DATA_READ) + host->flags |= HOST_F_RECV; + else + host->flags |= HOST_F_XMIT; + + if (host->mrq->stop) + host->flags |= HOST_F_STOP; + + host->dma.dir = DMA_BIDIRECTIONAL; + + host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg, + data->sg_len, host->dma.dir); + + if (host->dma.len == 0) + return MMC_ERR_TIMEOUT; + + au_writel((1 << data->blksz_bits) - 1, HOST_BLKSIZE(host)); + + if (host->flags & HOST_F_DMA) { + int i; + u32 channel = DMA_CHANNEL(host); + + au1xxx_dbdma_stop(channel); + + for(i = 0; i < host->dma.len; i++) { + u32 ret = 0, flags = DDMA_FLAGS_NOIE; + struct scatterlist *sg = &data->sg[i]; + int sg_len = sg->length; + + int len = (datalen > sg_len) ? sg_len : datalen; + + if (i == host->dma.len - 1) + flags = DDMA_FLAGS_IE; + + if (host->flags & HOST_F_XMIT){ + ret = au1xxx_dbdma_put_source_flags(channel, + (void *) (page_address(sg->page) + + sg->offset), + len, flags); + } + else { + ret = au1xxx_dbdma_put_dest_flags(channel, + (void *) (page_address(sg->page) + + sg->offset), + len, flags); + } + + if (!ret) + goto dataerr; + + datalen -= len; + } + } + else { + host->pio.index = 0; + host->pio.offset = 0; + host->pio.len = datalen; + + if (host->flags & HOST_F_XMIT) + IRQ_ON(host, SD_CONFIG_TH); + else + IRQ_ON(host, SD_CONFIG_NE); + //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF); + } + + return MMC_ERR_NONE; + + dataerr: + dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir); + return MMC_ERR_TIMEOUT; +} + +/* static void au1xmmc_request + This actually starts a command or data transaction +*/ + +static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) +{ + + struct au1xmmc_host *host = mmc_priv(mmc); + int ret = MMC_ERR_NONE; + + WARN_ON(irqs_disabled()); + WARN_ON(host->status != HOST_S_IDLE); + + host->mrq = mrq; + host->status = HOST_S_CMD; + + bcsr->disk_leds &= ~(1 << 8); + + if (mrq->data) { + FLUSH_FIFO(host); + ret = au1xmmc_prepare_data(host, mrq->data); + } + + if (ret == MMC_ERR_NONE) + ret = au1xmmc_send_command(host, 0, mrq->cmd); + + if (ret != MMC_ERR_NONE) { + mrq->cmd->error = ret; + au1xmmc_finish_request(host); + } +} + +static void au1xmmc_reset_controller(struct au1xmmc_host *host) +{ + + /* Apply the clock */ + au_writel(SD_ENABLE_CE, HOST_ENABLE(host)); + au_sync_delay(1); + + au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host)); + au_sync_delay(5); + + au_writel(~0, HOST_STATUS(host)); + au_sync(); + + au_writel(0, HOST_BLKSIZE(host)); + au_writel(0x001fffff, HOST_TIMEOUT(host)); + au_sync(); + + au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); + au_sync(); + + au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host)); + au_sync_delay(1); + + au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); + au_sync(); + + /* Configure interrupts */ + au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host)); + au_sync(); +} + + +static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios) +{ + struct au1xmmc_host *host = mmc_priv(mmc); + + DEBUG("set_ios (power=%u, clock=%uHz, vdd=%u, mode=%u)\n", + host->id, ios->power_mode, ios->clock, ios->vdd, + ios->bus_mode); + + if (ios->power_mode == MMC_POWER_OFF) + au1xmmc_set_power(host, 0); + else if (ios->power_mode == MMC_POWER_ON) { + au1xmmc_set_power(host, 1); + } + + if (ios->clock && ios->clock != host->clock) { + au1xmmc_set_clock(host, ios->clock); + host->clock = ios->clock; + } +} + +static void au1xmmc_dma_callback(int irq, void *dev_id, struct pt_regs *regs) +{ + struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id; + u32 status; + + /* Avoid spurious interrupts */ + + if (!host->mrq) + return; + + if (host->flags & HOST_F_STOP) + SEND_STOP(host); + + tasklet_schedule(&host->data_task); +} + +#define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT) +#define STATUS_DATA_IN (SD_STATUS_NE) +#define STATUS_DATA_OUT (SD_STATUS_TH) + +static irqreturn_t au1xmmc_irq(int irq, void *dev_id, struct pt_regs *regs) +{ + + u32 status; + int i, ret = 0; + + disable_irq(AU1100_SD_IRQ); + + for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) { + struct au1xmmc_host * host = au1xmmc_hosts[i]; + u32 handled = 1; + + status = au_readl(HOST_STATUS(host)); + + if (host->mrq && (status & STATUS_TIMEOUT)) { + if (status & SD_STATUS_RAT) + host->mrq->cmd->error = MMC_ERR_TIMEOUT; + + else if (status & SD_STATUS_DT) + host->mrq->data->error = MMC_ERR_TIMEOUT; + + /* In PIO mode, interrupts might still be enabled */ + IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH); + + //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF); + tasklet_schedule(&host->finish_task); + } +#if 0 + else if (status & SD_STATUS_DD) { + + /* Sometimes we get a DD before a NE in PIO mode */ + + if (!(host->flags & HOST_F_DMA) && + (status & SD_STATUS_NE)) + au1xmmc_receive_pio(host); + else { + au1xmmc_data_complete(host, status); + //tasklet_schedule(&host->data_task); + } + } +#endif + else if (status & (SD_STATUS_CR)) { + if (host->status == HOST_S_CMD) + au1xmmc_cmd_complete(host,status); + } + else if (!(host->flags & HOST_F_DMA)) { + if ((host->flags & HOST_F_XMIT) && + (status & STATUS_DATA_OUT)) + au1xmmc_send_pio(host); + else if ((host->flags & HOST_F_RECV) && + (status & STATUS_DATA_IN)) + au1xmmc_receive_pio(host); + } + else if (status & 0x203FBC70) { + DEBUG("Unhandled status %8.8x\n", host->id, status); + handled = 0; + } + + au_writel(status, HOST_STATUS(host)); + au_sync(); + + ret |= handled; + } + + enable_irq(AU1100_SD_IRQ); + return ret; +} + +static void au1xmmc_poll_event(unsigned long arg) +{ + struct au1xmmc_host *host = (struct au1xmmc_host *) arg; + + int card = au1xmmc_card_inserted(host); + int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0; + + if (card != controller) { + host->flags &= ~HOST_F_ACTIVE; + if (card) host->flags |= HOST_F_ACTIVE; + mmc_detect_change(host->mmc, 0); + } + + if (host->mrq != NULL) { + u32 status = au_readl(HOST_STATUS(host)); + DEBUG("PENDING - %8.8x\n", host->id, status); + } + + mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT); +} + +static dbdev_tab_t au1xmmc_mem_dbdev = +{ + DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0 +}; + +static void au1xmmc_init_dma(struct au1xmmc_host *host) +{ + + u32 rxchan, txchan; + + int txid = au1xmmc_card_table[host->id].tx_devid; + int rxid = au1xmmc_card_table[host->id].rx_devid; + + /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride + of 8 bits. And since devices are shared, we need to create + our own to avoid freaking out other devices + */ + + int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); + + txchan = au1xxx_dbdma_chan_alloc(memid, txid, + au1xmmc_dma_callback, (void *) host); + + rxchan = au1xxx_dbdma_chan_alloc(rxid, memid, + au1xmmc_dma_callback, (void *) host); + + au1xxx_dbdma_set_devwidth(txchan, 8); + au1xxx_dbdma_set_devwidth(rxchan, 8); + + au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT); + au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT); + + host->tx_chan = txchan; + host->rx_chan = rxchan; +} + +struct mmc_host_ops au1xmmc_ops = { + .request = au1xmmc_request, + .set_ios = au1xmmc_set_ios, +}; + +static int au1xmmc_probe(struct device *dev) +{ + + int i, ret = 0; + + /* THe interrupt is shared among all controllers */ + ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, SA_INTERRUPT, "MMC", 0); + + if (ret) { + printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n", + AU1100_SD_IRQ, ret); + return -ENXIO; + } + + disable_irq(AU1100_SD_IRQ); + + for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) { + struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), dev); + struct au1xmmc_host *host = 0; + + if (!mmc) { + printk(DRIVER_NAME "ERROR: no mem for host %d\n", i); + au1xmmc_hosts[i] = 0; + continue; + } + + mmc->ops = &au1xmmc_ops; + + mmc->f_min = 450000; + mmc->f_max = 24000000; + + mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE; + mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT; + + mmc->ocr_avail = AU1XMMC_OCR; + + host = mmc_priv(mmc); + host->mmc = mmc; + + host->id = i; + host->iobase = au1xmmc_card_table[host->id].iobase; + host->clock = 0; + host->power_mode = MMC_POWER_OFF; + + host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0; + host->status = HOST_S_IDLE; + + init_timer(&host->timer); + + host->timer.function = au1xmmc_poll_event; + host->timer.data = (unsigned long) host; + host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT; + + tasklet_init(&host->data_task, au1xmmc_tasklet_data, + (unsigned long) host); + + tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, + (unsigned long) host); + + spin_lock_init(&host->lock); + + if (dma != 0) + au1xmmc_init_dma(host); + + au1xmmc_reset_controller(host); + + mmc_add_host(mmc); + au1xmmc_hosts[i] = host; + + add_timer(&host->timer); + + printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n", + host->id, host->iobase, dma ? "dma" : "pio"); + } + + enable_irq(AU1100_SD_IRQ); + + return 0; +} + +static int au1xmmc_remove(struct device *dev) +{ + + int i; + + disable_irq(AU1100_SD_IRQ); + + for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) { + struct au1xmmc_host *host = au1xmmc_hosts[i]; + if (!host) continue; + + tasklet_kill(&host->data_task); + tasklet_kill(&host->finish_task); + + del_timer_sync(&host->timer); + au1xmmc_set_power(host, 0); + + mmc_remove_host(host->mmc); + + au1xxx_dbdma_chan_free(host->tx_chan); + au1xxx_dbdma_chan_free(host->rx_chan); + + au_writel(0x0, HOST_ENABLE(host)); + au_sync(); + } + + free_irq(AU1100_SD_IRQ, 0); + return 0; +} + +static struct device_driver au1xmmc_driver = { + .name = DRIVER_NAME, + .bus = &platform_bus_type, + .probe = au1xmmc_probe, + .remove = au1xmmc_remove, + .suspend = NULL, + .resume = NULL +}; + +static int __init au1xmmc_init(void) +{ + return driver_register(&au1xmmc_driver); +} + +static void __exit au1xmmc_exit(void) +{ + driver_unregister(&au1xmmc_driver); +} + +module_init(au1xmmc_init); +module_exit(au1xmmc_exit); + +#ifdef MODULE +MODULE_AUTHOR("Advanced Micro Devices, Inc"); +MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX"); +MODULE_LICENSE("GPL"); +#endif + diff --git a/drivers/mmc/au1xmmc.h b/drivers/mmc/au1xmmc.h new file mode 100644 index 000000000000..341cbdf0baca --- /dev/null +++ b/drivers/mmc/au1xmmc.h @@ -0,0 +1,96 @@ +#ifndef _AU1XMMC_H_ +#define _AU1XMMC_H_ + +/* Hardware definitions */ + +#define AU1XMMC_DESCRIPTOR_COUNT 1 +#define AU1XMMC_DESCRIPTOR_SIZE 2048 + +#define AU1XMMC_OCR ( MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \ + MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \ + MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36) + +/* Easy access macros */ + +#define HOST_STATUS(h) ((h)->iobase + SD_STATUS) +#define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG) +#define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE) +#define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT) +#define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT) +#define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG) +#define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE) +#define HOST_CMD(h) ((h)->iobase + SD_CMD) +#define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2) +#define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT) +#define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG) + +#define DMA_CHANNEL(h) \ + ( ((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan) + +/* This gives us a hard value for the stop command that we can write directly + * to the command register + */ + +#define STOP_CMD (SD_CMD_RT_1B|SD_CMD_CT_7|(0xC << SD_CMD_CI_SHIFT)|SD_CMD_GO) + +/* This is the set of interrupts that we configure by default */ + +#if 0 +#define AU1XMMC_INTERRUPTS (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_DD | \ + SD_CONFIG_RAT | SD_CONFIG_CR | SD_CONFIG_I) +#endif + +#define AU1XMMC_INTERRUPTS (SD_CONFIG_SC | SD_CONFIG_DT | \ + SD_CONFIG_RAT | SD_CONFIG_CR | SD_CONFIG_I) +/* The poll event (looking for insert/remove events runs twice a second */ +#define AU1XMMC_DETECT_TIMEOUT (HZ/2) + +struct au1xmmc_host { + struct mmc_host *mmc; + struct mmc_request *mrq; + + u32 id; + + u32 flags; + u32 iobase; + u32 clock; + u32 bus_width; + u32 power_mode; + + int status; + + struct { + int len; + int dir; + } dma; + + struct { + int index; + int offset; + int len; + } pio; + + u32 tx_chan; + u32 rx_chan; + + struct timer_list timer; + struct tasklet_struct finish_task; + struct tasklet_struct data_task; + + spinlock_t lock; +}; + +/* Status flags used by the host structure */ + +#define HOST_F_XMIT 0x0001 +#define HOST_F_RECV 0x0002 +#define HOST_F_DMA 0x0010 +#define HOST_F_ACTIVE 0x0100 +#define HOST_F_STOP 0x1000 + +#define HOST_S_IDLE 0x0001 +#define HOST_S_CMD 0x0002 +#define HOST_S_DATA 0x0003 +#define HOST_S_STOP 0x0004 + +#endif diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index a41fbb38fdcb..77ecee7f987b 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -42,9 +42,11 @@ pxa2xx_core-y += soc_common.o pxa2xx_base.o au1x00_ss-y += au1000_generic.o au1x00_ss-$(CONFIG_MIPS_PB1000) += au1000_pb1x00.o au1x00_ss-$(CONFIG_MIPS_PB1100) += au1000_pb1x00.o +au1x00_ss-$(CONFIG_MIPS_PB1200) += au1000_db1x00.o au1x00_ss-$(CONFIG_MIPS_PB1500) += au1000_pb1x00.o au1x00_ss-$(CONFIG_MIPS_DB1000) += au1000_db1x00.o au1x00_ss-$(CONFIG_MIPS_DB1100) += au1000_db1x00.o +au1x00_ss-$(CONFIG_MIPS_DB1200) += au1000_db1x00.o au1x00_ss-$(CONFIG_MIPS_DB1500) += au1000_db1x00.o au1x00_ss-$(CONFIG_MIPS_DB1550) += au1000_db1x00.o au1x00_ss-$(CONFIG_MIPS_XXS1500) += au1000_xxs1500.o diff --git a/drivers/pcmcia/au1000_db1x00.c b/drivers/pcmcia/au1000_db1x00.c index 42cf8bfbcc98..24cfee1a412c 100644 --- a/drivers/pcmcia/au1000_db1x00.c +++ b/drivers/pcmcia/au1000_db1x00.c @@ -40,7 +40,15 @@ #include <asm/irq.h> #include <asm/signal.h> #include <asm/mach-au1x00/au1000.h> -#include <asm/mach-db1x00/db1x00.h> + +#if defined(CONFIG_MIPS_DB1200) + #include <db1200.h> +#elif defined(CONFIG_MIPS_PB1200) + #include <pb1200.h> +#else + #include <asm/mach-db1x00/db1x00.h> + static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; +#endif #include "au1000_generic.h" @@ -50,7 +58,6 @@ #define debug(x,args...) #endif -static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; struct au1000_pcmcia_socket au1000_pcmcia_socket[PCMCIA_NUM_SOCKS]; extern int au1x00_pcmcia_socket_probe(struct device *, struct pcmcia_low_level *, int, int); @@ -59,6 +66,8 @@ static int db1x00_pcmcia_hw_init(struct au1000_pcmcia_socket *skt) { #ifdef CONFIG_MIPS_DB1550 skt->irq = skt->nr ? AU1000_GPIO_5 : AU1000_GPIO_3; +#elif defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200) + skt->irq = skt->nr ? BOARD_PC1_INT : BOARD_PC0_INT; #else skt->irq = skt->nr ? AU1000_GPIO_5 : AU1000_GPIO_2; #endif @@ -85,11 +94,19 @@ db1x00_pcmcia_socket_state(struct au1000_pcmcia_socket *skt, struct pcmcia_state switch (skt->nr) { case 0: vs = bcsr->status & 0x3; +#if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200) + inserted = BOARD_CARD_INSERTED(0); +#else inserted = !(bcsr->status & (1<<4)); +#endif break; case 1: vs = (bcsr->status & 0xC)>>2; +#if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200) + inserted = BOARD_CARD_INSERTED(1); +#else inserted = !(bcsr->status & (1<<5)); +#endif break; default:/* should never happen */ return; diff --git a/drivers/pcmcia/au1000_generic.c b/drivers/pcmcia/au1000_generic.c index d90a634cebf5..ba48cef3a9dc 100644 --- a/drivers/pcmcia/au1000_generic.c +++ b/drivers/pcmcia/au1000_generic.c @@ -490,7 +490,7 @@ int au1x00_drv_pcmcia_remove(struct device *dev) flush_scheduled_work(); skt->ops->hw_shutdown(skt); au1x00_pcmcia_config_skt(skt, &dead_socket); - iounmap(skt->virt_io); + iounmap(skt->virt_io + (u32)mips_io_port_base); skt->virt_io = NULL; } @@ -528,10 +528,6 @@ static struct device_driver au1x00_pcmcia_driver = { .resume = pcmcia_socket_dev_resume, }; -static struct platform_device au1x00_device = { - .name = "au1x00-pcmcia", - .id = 0, -}; /* au1x00_pcmcia_init() * @@ -545,7 +541,6 @@ static int __init au1x00_pcmcia_init(void) int error = 0; if ((error = driver_register(&au1x00_pcmcia_driver))) return error; - platform_device_register(&au1x00_device); return error; } @@ -556,7 +551,6 @@ static int __init au1x00_pcmcia_init(void) static void __exit au1x00_pcmcia_exit(void) { driver_unregister(&au1x00_pcmcia_driver); - platform_device_unregister(&au1x00_device); } module_init(au1x00_pcmcia_init); diff --git a/drivers/pcmcia/au1000_generic.h b/drivers/pcmcia/au1000_generic.h index d5122b1ea94b..b0e7908392a7 100644 --- a/drivers/pcmcia/au1000_generic.h +++ b/drivers/pcmcia/au1000_generic.h @@ -44,13 +44,13 @@ /* pcmcia socket 1 needs external glue logic so the memory map * differs from board to board. */ -#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_PB1550) +#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_PB1200) #define AU1X_SOCK1_IO 0xF08000000 #define AU1X_SOCK1_PHYS_ATTR 0xF48000000 #define AU1X_SOCK1_PHYS_MEM 0xF88000000 #define AU1X_SOCK1_PSEUDO_PHYS_ATTR 0xF4800000 #define AU1X_SOCK1_PSEUDO_PHYS_MEM 0xF8800000 -#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) +#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) || defined(CONFIG_MIPS_DB1200) #define AU1X_SOCK1_IO 0xF04000000 #define AU1X_SOCK1_PHYS_ATTR 0xF44000000 #define AU1X_SOCK1_PHYS_MEM 0xF84000000 diff --git a/drivers/scsi/dec_esp.c b/drivers/scsi/dec_esp.c index 315f95a0d6c0..4f39890b44ac 100644 --- a/drivers/scsi/dec_esp.c +++ b/drivers/scsi/dec_esp.c @@ -228,7 +228,7 @@ static int dec_esp_detect(Scsi_Host_Template * tpnt) mem_start = get_tc_base_addr(slot); /* Store base addr into esp struct */ - esp->slot = PHYSADDR(mem_start); + esp->slot = CPHYSADDR(mem_start); esp->dregs = 0; esp->eregs = (struct ESP_regs *) (mem_start + DEC_SCSI_SREG); diff --git a/drivers/tc/tc.c b/drivers/tc/tc.c index a89ef4df80c3..a0e5af638e0e 100644 --- a/drivers/tc/tc.c +++ b/drivers/tc/tc.c @@ -8,33 +8,31 @@ * for more details. * * Copyright (c) Harald Koerfgen, 1998 - * Copyright (c) 2001, 2003 Maciej W. Rozycki + * Copyright (c) 2001, 2003, 2005 Maciej W. Rozycki */ -#include <linux/string.h> #include <linux/init.h> -#include <linux/ioport.h> #include <linux/kernel.h> #include <linux/module.h> +#include <linux/string.h> +#include <linux/types.h> #include <asm/addrspace.h> +#include <asm/bug.h> #include <asm/errno.h> +#include <asm/io.h> +#include <asm/paccess.h> + #include <asm/dec/machtype.h> #include <asm/dec/prom.h> #include <asm/dec/tcinfo.h> #include <asm/dec/tcmodule.h> #include <asm/dec/interrupts.h> -#include <asm/paccess.h> -#include <asm/ptrace.h> - -#define TC_DEBUG MODULE_LICENSE("GPL"); slot_info tc_bus[MAX_SLOT]; static int num_tcslots; static tcinfo *info; -unsigned long system_base; - /* * Interface to the world. Read comment in include/asm-mips/tc.h. */ @@ -97,13 +95,16 @@ unsigned long get_tc_speed(void) static void __init tc_probe(unsigned long startaddr, unsigned long size, int slots) { + unsigned long slotaddr; int i, slot, err; long offset; - unsigned char pattern[4]; - unsigned char *module; + u8 pattern[4]; + volatile u8 *module; for (slot = 0; slot < slots; slot++) { - module = (char *)(startaddr + slot * size); + slotaddr = startaddr + slot * size; + module = ioremap_nocache(slotaddr, size); + BUG_ON(!module); offset = OLDCARD; @@ -112,8 +113,10 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size, err |= get_dbe(pattern[1], module + OLDCARD + TC_PATTERN1); err |= get_dbe(pattern[2], module + OLDCARD + TC_PATTERN2); err |= get_dbe(pattern[3], module + OLDCARD + TC_PATTERN3); - if (err) + if (err) { + iounmap(module); continue; + } if (pattern[0] != 0x55 || pattern[1] != 0x00 || pattern[2] != 0xaa || pattern[3] != 0xff) { @@ -124,16 +127,20 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size, err |= get_dbe(pattern[1], module + TC_PATTERN1); err |= get_dbe(pattern[2], module + TC_PATTERN2); err |= get_dbe(pattern[3], module + TC_PATTERN3); - if (err) + if (err) { + iounmap(module); continue; + } } if (pattern[0] != 0x55 || pattern[1] != 0x00 || - pattern[2] != 0xaa || pattern[3] != 0xff) + pattern[2] != 0xaa || pattern[3] != 0xff) { + iounmap(module); continue; + } - tc_bus[slot].base_addr = (unsigned long)module; - for(i = 0; i < 8; i++) { + tc_bus[slot].base_addr = slotaddr; + for (i = 0; i < 8; i++) { tc_bus[slot].firmware[i] = module[TC_FIRM_VER + offset + 4 * i]; tc_bus[slot].vendor[i] = @@ -171,13 +178,15 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size, tc_bus[slot].interrupt = -1; break; } + + iounmap(module); } } /* * the main entry */ -void __init tc_init(void) +static int __init tc_init(void) { int tc_clock; int i; @@ -185,7 +194,7 @@ void __init tc_init(void) unsigned long slot_size; if (!TURBOCHANNEL) - return; + return 0; for (i = 0; i < MAX_SLOT; i++) { tc_bus[i].base_addr = 0; @@ -196,8 +205,8 @@ void __init tc_init(void) tc_bus[i].flags = FREE; } - info = (tcinfo *) rex_gettcinfo(); - slot0addr = (unsigned long)KSEG1ADDR(rex_slot_address(0)); + info = rex_gettcinfo(); + slot0addr = CPHYSADDR((long)rex_slot_address(0)); switch (mips_machtype) { case MACH_DS5000_200: @@ -216,37 +225,24 @@ void __init tc_init(void) tc_clock = 10000 / info->clk_period; - if (TURBOCHANNEL && info->slot_size && slot0addr) { - printk("TURBOchannel rev. %1d at %2d.%1d MHz ", info->revision, - tc_clock / 10, tc_clock % 10); - printk("(with%s parity)\n", info->parity ? "" : "out"); + if (info->slot_size && slot0addr) { + pr_info("TURBOchannel rev. %d at %d.%d MHz (with%s parity)\n", + info->revision, tc_clock / 10, tc_clock % 10, + info->parity ? "" : "out"); slot_size = info->slot_size << 20; tc_probe(slot0addr, slot_size, num_tcslots); - /* - * All TURBOchannel DECstations have the onboard devices - * where the (num_tcslots + 0 or 1 on DS5k/xx) Option Module - * would be. - */ - if(mips_machtype == MACH_DS5000_XX) - i = 1; - else - i = 0; - - system_base = slot0addr + slot_size * (num_tcslots + i); - -#ifdef TC_DEBUG - for (i = 0; i < num_tcslots; i++) - if (tc_bus[i].base_addr) { - printk(" slot %d: ", i); - printk("%s %s %s\n", tc_bus[i].vendor, - tc_bus[i].name, tc_bus[i].firmware); - } -#endif - ioport_resource.end = KSEG2 - 1; + for (i = 0; i < num_tcslots; i++) { + if (!tc_bus[i].base_addr) + continue; + pr_info(" slot %d: %s %s %s\n", i, tc_bus[i].vendor, + tc_bus[i].name, tc_bus[i].firmware); + } } + + return 0; } subsys_initcall(tc_init); @@ -257,4 +253,3 @@ EXPORT_SYMBOL(release_tc_card); EXPORT_SYMBOL(get_tc_base_addr); EXPORT_SYMBOL(get_tc_irq_nr); EXPORT_SYMBOL(get_tc_speed); -EXPORT_SYMBOL(system_base); diff --git a/drivers/tc/zs.c b/drivers/tc/zs.c index 6bed8713897e..c52af73a251b 100644 --- a/drivers/tc/zs.c +++ b/drivers/tc/zs.c @@ -65,14 +65,14 @@ #include <asm/system.h> #include <asm/uaccess.h> #include <asm/bootinfo.h> -#include <asm/dec/serial.h> -#ifdef CONFIG_MACH_DECSTATION #include <asm/dec/interrupts.h> +#include <asm/dec/ioasic_addrs.h> #include <asm/dec/machtype.h> +#include <asm/dec/serial.h> +#include <asm/dec/system.h> #include <asm/dec/tc.h> -#include <asm/dec/ioasic_addrs.h> -#endif + #ifdef CONFIG_KGDB #include <asm/kgdb.h> #endif @@ -192,18 +192,6 @@ static void probe_sccs(void); static void change_speed(struct dec_serial *info); static void rs_wait_until_sent(struct tty_struct *tty, int timeout); -/* - * tmp_buf is used as a temporary buffer by serial_write. We need to - * lock it in case the copy_from_user blocks while swapping in a page, - * and some other program tries to do a serial write at the same time. - * Since the lock will only come under contention when the system is - * swapping and available memory is low, it makes sense to share one - * buffer across all the serial ports, since it significantly saves - * memory if large numbers of serial ports are open. - */ -static unsigned char tmp_buf[4096]; /* This is cheating */ -static DECLARE_MUTEX(tmp_buf_sem); - static inline int serial_paranoia_check(struct dec_serial *info, char *name, const char *routine) { @@ -1628,30 +1616,22 @@ static void __init probe_sccs(void) return; } - /* - * When serial console is activated, tc_init has not been called yet - * and system_base is undefined. Unfortunately we have to hardcode - * system_base for this case :-(. HK - */ switch(mips_machtype) { #ifdef CONFIG_MACH_DECSTATION case MACH_DS5000_2X0: case MACH_DS5900: - system_base = KSEG1ADDR(0x1f800000); n_chips = 2; zs_parms = &ds_parms; zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0]; zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1]; break; case MACH_DS5000_1XX: - system_base = KSEG1ADDR(0x1c000000); n_chips = 2; zs_parms = &ds_parms; zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0]; zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1]; break; case MACH_DS5000_XX: - system_base = KSEG1ADDR(0x1c000000); n_chips = 1; zs_parms = &ds_parms; zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0]; @@ -1673,10 +1653,10 @@ static void __init probe_sccs(void) * The sccs reside on the high byte of the 16 bit IOBUS */ zs_channels[n_channels].control = - (volatile unsigned char *)system_base + + (volatile void *)CKSEG1ADDR(dec_kn_slot_base + (0 == chip ? zs_parms->scc0 : zs_parms->scc1) + (0 == channel ? zs_parms->channel_a_offset : - zs_parms->channel_b_offset); + zs_parms->channel_b_offset)); zs_channels[n_channels].data = zs_channels[n_channels].control + 4; diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 1cd942abb580..7e297947a2b2 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -1376,7 +1376,7 @@ config FB_HIT config FB_PMAG_AA bool "PMAG-AA TURBOchannel framebuffer support" - depends on (FB = y) && MACH_DECSTATION && TC + depends on (FB = y) && TC select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT @@ -1387,7 +1387,7 @@ config FB_PMAG_AA config FB_PMAG_BA bool "PMAG-BA TURBOchannel framebuffer support" - depends on (FB = y) && MACH_DECSTATION && TC + depends on (FB = y) && TC select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT @@ -1398,7 +1398,7 @@ config FB_PMAG_BA config FB_PMAGB_B bool "PMAGB-B TURBOchannel framebuffer support" - depends on (FB = y) && MACH_DECSTATION && TC + depends on (FB = y) && TC select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT @@ -1410,7 +1410,7 @@ config FB_PMAGB_B config FB_MAXINE bool "Maxine (Personal DECstation) onboard framebuffer support" - depends on (FB = y) && MACH_DECSTATION && TC + depends on (FB = y) && MACH_DECSTATION select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 1fff29f48ca8..97c5d03ac8d9 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -86,7 +86,7 @@ obj-$(CONFIG_FB_CIRRUS) += cirrusfb.o obj-$(CONFIG_FB_ASILIANT) += asiliantfb.o obj-$(CONFIG_FB_PXA) += pxafb.o obj-$(CONFIG_FB_W100) += w100fb.o -obj-$(CONFIG_FB_AU1100) += au1100fb.o fbgen.o +obj-$(CONFIG_FB_AU1100) += au1100fb.o obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o diff --git a/drivers/video/au1100fb.c b/drivers/video/au1100fb.c index b6fe30c3ad62..a5129806172f 100644 --- a/drivers/video/au1100fb.c +++ b/drivers/video/au1100fb.c @@ -2,6 +2,11 @@ * BRIEF MODULE DESCRIPTION * Au1100 LCD Driver. * + * Rewritten for 2.6 by Embedded Alley Solutions + * <source@embeddedalley.com>, based on submissions by + * Karl Lessard <klessard@sunrisetelecom.com> + * <c.pellegrin@exadron.com> + * * Copyright 2002 MontaVista Software * Author: MontaVista Software, Inc. * ppopov@mvista.com or source@mvista.com @@ -33,298 +38,253 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ - +#include <linux/config.h> #include <linux/module.h> #include <linux/kernel.h> #include <linux/errno.h> #include <linux/string.h> #include <linux/mm.h> -#include <linux/tty.h> -#include <linux/slab.h> -#include <linux/delay.h> #include <linux/fb.h> #include <linux/init.h> -#include <linux/pci.h> +#include <linux/interrupt.h> +#include <linux/ctype.h> +#include <linux/dma-mapping.h> -#include <asm/au1000.h> -#include <asm/pb1100.h> -#include "au1100fb.h" +#include <asm/mach-au1x00/au1000.h> -#include <video/fbcon.h> -#include <video/fbcon-mfb.h> -#include <video/fbcon-cfb2.h> -#include <video/fbcon-cfb4.h> -#include <video/fbcon-cfb8.h> -#include <video/fbcon-cfb16.h> +#define DEBUG 0 + +#include "au1100fb.h" /* * Sanity check. If this is a new Au1100 based board, search for * the PB1100 ifdefs to make sure you modify the code accordingly. */ -#if defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_HYDROGEN3) +#if defined(CONFIG_MIPS_PB1100) + #include <asm/mach-pb1x00/pb1100.h> +#elif defined(CONFIG_MIPS_DB1100) + #include <asm/mach-db1x00/db1x00.h> #else -error Unknown Au1100 board + #error "Unknown Au1100 board, Au1100 FB driver not supported" #endif -#define CMAPSIZE 16 - -static int my_lcd_index; /* default is zero */ -struct known_lcd_panels *p_lcd; -AU1100_LCD *p_lcd_reg = (AU1100_LCD *)AU1100_LCD_ADDR; - -struct au1100fb_info { - struct fb_info_gen gen; - unsigned long fb_virt_start; - unsigned long fb_size; - unsigned long fb_phys; - int mmaped; - int nohwcursor; +#define DRIVER_NAME "au1100fb" +#define DRIVER_DESC "LCD controller driver for AU1100 processors" - struct { unsigned red, green, blue, pad; } palette[256]; +#define to_au1100fb_device(_info) \ + (_info ? container_of(_info, struct au1100fb_device, info) : NULL); -#if defined(FBCON_HAS_CFB16) - u16 fbcon_cmap16[16]; -#endif +/* Bitfields format supported by the controller. Note that the order of formats + * SHOULD be the same as in the LCD_CONTROL_SBPPF field, so we can retrieve the + * right pixel format by doing rgb_bitfields[LCD_CONTROL_SBPPF_XXX >> LCD_CONTROL_SBPPF] + */ +struct fb_bitfield rgb_bitfields[][4] = +{ + /* Red, Green, Blue, Transp */ + { { 10, 6, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 0, 0, 0 } }, + { { 11, 5, 0 }, { 5, 6, 0 }, { 0, 5, 0 }, { 0, 0, 0 } }, + { { 11, 5, 0 }, { 6, 5, 0 }, { 0, 6, 0 }, { 0, 0, 0 } }, + { { 10, 5, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 15, 1, 0 } }, + { { 11, 5, 0 }, { 6, 5, 0 }, { 1, 5, 0 }, { 0, 1, 0 } }, + + /* The last is used to describe 12bpp format */ + { { 8, 4, 0 }, { 4, 4, 0 }, { 0, 4, 0 }, { 0, 0, 0 } }, }; - -struct au1100fb_par { - struct fb_var_screeninfo var; - - int line_length; // in bytes - int cmap_len; // color-map length +static struct fb_fix_screeninfo au1100fb_fix __initdata = { + .id = "AU1100 FB", + .xpanstep = 1, + .ypanstep = 1, + .type = FB_TYPE_PACKED_PIXELS, + .accel = FB_ACCEL_NONE, }; - -static struct au1100fb_info fb_info; -static struct au1100fb_par current_par; -static struct display disp; - -int au1100fb_init(void); -void au1100fb_setup(char *options, int *ints); -static int au1100fb_mmap(struct fb_info *fb, struct file *file, - struct vm_area_struct *vma); -static int au1100_blank(int blank_mode, struct fb_info_gen *info); -static int au1100fb_ioctl(struct inode *inode, struct file *file, u_int cmd, - u_long arg, int con, struct fb_info *info); - -void au1100_nocursor(struct display *p, int mode, int xx, int yy){}; - -static struct fb_ops au1100fb_ops = { - .owner = THIS_MODULE, - .fb_get_fix = fbgen_get_fix, - .fb_get_var = fbgen_get_var, - .fb_set_var = fbgen_set_var, - .fb_get_cmap = fbgen_get_cmap, - .fb_set_cmap = fbgen_set_cmap, - .fb_pan_display = fbgen_pan_display, - .fb_ioctl = au1100fb_ioctl, - .fb_mmap = au1100fb_mmap, +static struct fb_var_screeninfo au1100fb_var __initdata = { + .activate = FB_ACTIVATE_NOW, + .height = -1, + .width = -1, + .vmode = FB_VMODE_NONINTERLACED, }; -static void au1100_detect(void) -{ - /* - * This function should detect the current video mode settings - * and store it as the default video mode - */ +static struct au1100fb_drv_info drv_info; - /* - * Yeh, well, we're not going to change any settings so we're - * always stuck with the default ... +/* + * Set hardware with var settings. This will enable the controller with a specific + * mode, normally validated with the fb_check_var method */ - -} - -static int au1100_encode_fix(struct fb_fix_screeninfo *fix, - const void *_par, struct fb_info_gen *_info) +int au1100fb_setmode(struct au1100fb_device *fbdev) { - struct au1100fb_info *info = (struct au1100fb_info *) _info; - struct au1100fb_par *par = (struct au1100fb_par *) _par; - struct fb_var_screeninfo *var = &par->var; - - memset(fix, 0, sizeof(struct fb_fix_screeninfo)); - - fix->smem_start = info->fb_phys; - fix->smem_len = info->fb_size; - fix->type = FB_TYPE_PACKED_PIXELS; - fix->type_aux = 0; - fix->visual = (var->bits_per_pixel == 8) ? - FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; - fix->ywrapstep = 0; - fix->xpanstep = 1; - fix->ypanstep = 1; - fix->line_length = current_par.line_length; - return 0; -} + struct fb_info *info = &fbdev->info; + u32 words; + int index; -static void set_color_bitfields(struct fb_var_screeninfo *var) -{ - switch (var->bits_per_pixel) { - case 8: - var->red.offset = 0; - var->red.length = 8; - var->green.offset = 0; - var->green.length = 8; - var->blue.offset = 0; - var->blue.length = 8; - var->transp.offset = 0; - var->transp.length = 0; - break; - case 16: /* RGB 565 */ - var->red.offset = 11; - var->red.length = 5; - var->green.offset = 5; - var->green.length = 6; - var->blue.offset = 0; - var->blue.length = 5; - var->transp.offset = 0; - var->transp.length = 0; - break; + if (!fbdev) + return -EINVAL; + + /* Update var-dependent FB info */ + if (panel_is_active(fbdev->panel) || panel_is_color(fbdev->panel)) { + if (info->var.bits_per_pixel <= 8) { + /* palettized */ + info->var.red.offset = 0; + info->var.red.length = info->var.bits_per_pixel; + info->var.red.msb_right = 0; + + info->var.green.offset = 0; + info->var.green.length = info->var.bits_per_pixel; + info->var.green.msb_right = 0; + + info->var.blue.offset = 0; + info->var.blue.length = info->var.bits_per_pixel; + info->var.blue.msb_right = 0; + + info->var.transp.offset = 0; + info->var.transp.length = 0; + info->var.transp.msb_right = 0; + + info->fix.visual = FB_VISUAL_PSEUDOCOLOR; + info->fix.line_length = info->var.xres_virtual / + (8/info->var.bits_per_pixel); + } else { + /* non-palettized */ + index = (fbdev->panel->control_base & LCD_CONTROL_SBPPF_MASK) >> LCD_CONTROL_SBPPF_BIT; + info->var.red = rgb_bitfields[index][0]; + info->var.green = rgb_bitfields[index][1]; + info->var.blue = rgb_bitfields[index][2]; + info->var.transp = rgb_bitfields[index][3]; + + info->fix.visual = FB_VISUAL_TRUECOLOR; + info->fix.line_length = info->var.xres_virtual << 1; /* depth=16 */ + } + } else { + /* mono */ + info->fix.visual = FB_VISUAL_MONO10; + info->fix.line_length = info->var.xres_virtual / 8; } - var->red.msb_right = 0; - var->green.msb_right = 0; - var->blue.msb_right = 0; - var->transp.msb_right = 0; -} + info->screen_size = info->fix.line_length * info->var.yres_virtual; -static int au1100_decode_var(const struct fb_var_screeninfo *var, - void *_par, struct fb_info_gen *_info) -{ + /* Determine BPP mode and format */ + fbdev->regs->lcd_control = fbdev->panel->control_base | + ((info->var.rotate/90) << LCD_CONTROL_SM_BIT); - struct au1100fb_par *par = (struct au1100fb_par *)_par; + fbdev->regs->lcd_intenable = 0; + fbdev->regs->lcd_intstatus = 0; - /* - * Don't allow setting any of these yet: xres and yres don't - * make sense for LCD panels. - */ - if (var->xres != p_lcd->xres || - var->yres != p_lcd->yres || - var->xres != p_lcd->xres || - var->yres != p_lcd->yres) { - return -EINVAL; - } - if(var->bits_per_pixel != p_lcd->bpp) { - return -EINVAL; - } + fbdev->regs->lcd_horztiming = fbdev->panel->horztiming; - memset(par, 0, sizeof(struct au1100fb_par)); - par->var = *var; - - /* FIXME */ - switch (var->bits_per_pixel) { - case 8: - par->var.bits_per_pixel = 8; - break; - case 16: - par->var.bits_per_pixel = 16; - break; - default: - printk("color depth %d bpp not supported\n", - var->bits_per_pixel); - return -EINVAL; + fbdev->regs->lcd_verttiming = fbdev->panel->verttiming; + + fbdev->regs->lcd_clkcontrol = fbdev->panel->clkcontrol_base; + fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(fbdev->fb_phys); + + if (panel_is_dual(fbdev->panel)) { + /* Second panel display seconf half of screen if possible, + * otherwise display the same as the first panel */ + if (info->var.yres_virtual >= (info->var.yres << 1)) { + fbdev->regs->lcd_dmaaddr1 = LCD_DMA_SA_N(fbdev->fb_phys + + (info->fix.line_length * + (info->var.yres_virtual >> 1))); + } else { + fbdev->regs->lcd_dmaaddr1 = LCD_DMA_SA_N(fbdev->fb_phys); + } } - set_color_bitfields(&par->var); - par->cmap_len = (par->var.bits_per_pixel == 8) ? 256 : 16; - return 0; -} -static int au1100_encode_var(struct fb_var_screeninfo *var, - const void *par, struct fb_info_gen *_info) -{ + words = info->fix.line_length / sizeof(u32); + if (!info->var.rotate || (info->var.rotate == 180)) { + words *= info->var.yres_virtual; + if (info->var.rotate /* 180 */) { + words -= (words % 8); /* should be divisable by 8 */ + } + } + fbdev->regs->lcd_words = LCD_WRD_WRDS_N(words); - *var = ((struct au1100fb_par *)par)->var; - return 0; -} + fbdev->regs->lcd_pwmdiv = 0; + fbdev->regs->lcd_pwmhi = 0; -static void -au1100_get_par(void *_par, struct fb_info_gen *_info) -{ - *(struct au1100fb_par *)_par = current_par; -} + /* Resume controller */ + fbdev->regs->lcd_control |= LCD_CONTROL_GO; -static void au1100_set_par(const void *par, struct fb_info_gen *info) -{ - /* nothing to do: we don't change any settings */ + return 0; } -static int au1100_getcolreg(unsigned regno, unsigned *red, unsigned *green, - unsigned *blue, unsigned *transp, - struct fb_info *info) +/* fb_setcolreg + * Set color in LCD palette. + */ +int au1100fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *fbi) { + struct au1100fb_device *fbdev = to_au1100fb_device(fbi); + u32 *palette = fbdev->regs->lcd_pallettebase; + u32 value; - struct au1100fb_info* i = (struct au1100fb_info*)info; - - if (regno > 255) - return 1; + if (regno > (AU1100_LCD_NBR_PALETTE_ENTRIES - 1)) + return -EINVAL; - *red = i->palette[regno].red; - *green = i->palette[regno].green; - *blue = i->palette[regno].blue; - *transp = 0; + if (fbi->var.grayscale) { + /* Convert color to grayscale */ + red = green = blue = + (19595 * red + 38470 * green + 7471 * blue) >> 16; + } - return 0; -} + if (fbi->fix.visual == FB_VISUAL_TRUECOLOR) { + /* Place color in the pseudopalette */ + if (regno > 16) + return -EINVAL; -static int au1100_setcolreg(unsigned regno, unsigned red, unsigned green, - unsigned blue, unsigned transp, - struct fb_info *info) -{ - struct au1100fb_info* i = (struct au1100fb_info *)info; - u32 rgbcol; - - if (regno > 255) - return 1; - - i->palette[regno].red = red; - i->palette[regno].green = green; - i->palette[regno].blue = blue; - - switch(p_lcd->bpp) { -#ifdef FBCON_HAS_CFB8 - case 8: - red >>= 10; - green >>= 10; - blue >>= 10; - p_lcd_reg->lcd_pallettebase[regno] = (blue&0x1f) | - ((green&0x3f)<<5) | ((red&0x1f)<<11); - break; -#endif -#ifdef FBCON_HAS_CFB16 - case 16: - i->fbcon_cmap16[regno] = - ((red & 0xf800) >> 0) | - ((green & 0xfc00) >> 5) | - ((blue & 0xf800) >> 11); - break; -#endif - default: - break; + palette = (u32*)fbi->pseudo_palette; + + red >>= (16 - fbi->var.red.length); + green >>= (16 - fbi->var.green.length); + blue >>= (16 - fbi->var.blue.length); + + value = (red << fbi->var.red.offset) | + (green << fbi->var.green.offset)| + (blue << fbi->var.blue.offset); + value &= 0xFFFF; + + } else if (panel_is_active(fbdev->panel)) { + /* COLOR TFT PALLETTIZED (use RGB 565) */ + value = (red & 0xF800)|((green >> 5) & 0x07E0)|((blue >> 11) & 0x001F); + value &= 0xFFFF; + + } else if (panel_is_color(fbdev->panel)) { + /* COLOR STN MODE */ + value = (((panel_swap_rgb(fbdev->panel) ? blue : red) >> 12) & 0x000F) | + ((green >> 8) & 0x00F0) | + (((panel_swap_rgb(fbdev->panel) ? red : blue) >> 4) & 0x0F00); + value &= 0xFFF; + } else { + /* MONOCHROME MODE */ + value = (green >> 12) & 0x000F; + value &= 0xF; } + palette[regno] = value; + return 0; } - -static int au1100_blank(int blank_mode, struct fb_info_gen *_info) +/* fb_blank + * Blank the screen. Depending on the mode, the screen will be + * activated with the backlight color, or desactivated + */ +int au1100fb_fb_blank(int blank_mode, struct fb_info *fbi) { + struct au1100fb_device *fbdev = to_au1100fb_device(fbi); + + print_dbg("fb_blank %d %p", blank_mode, fbi); switch (blank_mode) { + case VESA_NO_BLANKING: - /* turn on panel */ - //printk("turn on panel\n"); + /* Turn on panel */ + fbdev->regs->lcd_control |= LCD_CONTROL_GO; #ifdef CONFIG_MIPS_PB1100 - p_lcd_reg->lcd_control |= LCD_CONTROL_GO; - au_writew(au_readw(PB1100_G_CONTROL) | p_lcd->mode_backlight, + if (drv_info.panel_idx == 1) { + au_writew(au_readw(PB1100_G_CONTROL) + | (PB1100_G_CONTROL_BL | PB1100_G_CONTROL_VDD), PB1100_G_CONTROL); -#endif -#ifdef CONFIG_MIPS_HYDROGEN3 - /* Turn controller & power supply on, GPIO213 */ - au_writel(0x20002000, 0xB1700008); - au_writel(0x00040000, 0xB1900108); - au_writel(0x01000100, 0xB1700008); + } #endif au_sync(); break; @@ -332,12 +292,14 @@ static int au1100_blank(int blank_mode, struct fb_info_gen *_info) case VESA_VSYNC_SUSPEND: case VESA_HSYNC_SUSPEND: case VESA_POWERDOWN: - /* turn off panel */ - //printk("turn off panel\n"); + /* Turn off panel */ + fbdev->regs->lcd_control &= ~LCD_CONTROL_GO; #ifdef CONFIG_MIPS_PB1100 - au_writew(au_readw(PB1100_G_CONTROL) & ~p_lcd->mode_backlight, + if (drv_info.panel_idx == 1) { + au_writew(au_readw(PB1100_G_CONTROL) + & ~(PB1100_G_CONTROL_BL | PB1100_G_CONTROL_VDD), PB1100_G_CONTROL); - p_lcd_reg->lcd_control &= ~LCD_CONTROL_GO; + } #endif au_sync(); break; @@ -348,49 +310,87 @@ static int au1100_blank(int blank_mode, struct fb_info_gen *_info) return 0; } -static void au1100_set_disp(const void *unused, struct display *disp, - struct fb_info_gen *info) +/* fb_pan_display + * Pan display in x and/or y as specified + */ +int au1100fb_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fbi) { - disp->screen_base = (char *)fb_info.fb_virt_start; - - switch (disp->var.bits_per_pixel) { -#ifdef FBCON_HAS_CFB8 - case 8: - disp->dispsw = &fbcon_cfb8; - if (fb_info.nohwcursor) - fbcon_cfb8.cursor = au1100_nocursor; - break; -#endif -#ifdef FBCON_HAS_CFB16 - case 16: - disp->dispsw = &fbcon_cfb16; - disp->dispsw_data = fb_info.fbcon_cmap16; - if (fb_info.nohwcursor) - fbcon_cfb16.cursor = au1100_nocursor; - break; -#endif - default: - disp->dispsw = &fbcon_dummy; - disp->dispsw_data = NULL; - break; + struct au1100fb_device *fbdev = to_au1100fb_device(fbi); + int dy; + + print_dbg("fb_pan_display %p %p", var, fbi); + + if (!var || !fbdev) { + return -EINVAL; + } + + if (var->xoffset - fbi->var.xoffset) { + /* No support for X panning for now! */ + return -EINVAL; + } + + print_dbg("fb_pan_display 2 %p %p", var, fbi); + dy = var->yoffset - fbi->var.yoffset; + if (dy) { + + u32 dmaaddr; + + print_dbg("Panning screen of %d lines", dy); + + dmaaddr = fbdev->regs->lcd_dmaaddr0; + dmaaddr += (fbi->fix.line_length * dy); + + /* TODO: Wait for current frame to finished */ + fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(dmaaddr); + + if (panel_is_dual(fbdev->panel)) { + dmaaddr = fbdev->regs->lcd_dmaaddr1; + dmaaddr += (fbi->fix.line_length * dy); + fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(dmaaddr); + } + } + print_dbg("fb_pan_display 3 %p %p", var, fbi); + + return 0; +} + +/* fb_rotate + * Rotate the display of this angle. This doesn't seems to be used by the core, + * but as our hardware supports it, so why not implementing it... + */ +void au1100fb_fb_rotate(struct fb_info *fbi, int angle) +{ + struct au1100fb_device *fbdev = to_au1100fb_device(fbi); + + print_dbg("fb_rotate %p %d", fbi, angle); + + if (fbdev && (angle > 0) && !(angle % 90)) { + + fbdev->regs->lcd_control &= ~LCD_CONTROL_GO; + + fbdev->regs->lcd_control &= ~(LCD_CONTROL_SM_MASK); + fbdev->regs->lcd_control |= ((angle/90) << LCD_CONTROL_SM_BIT); + + fbdev->regs->lcd_control |= LCD_CONTROL_GO; } } -static int -au1100fb_mmap(struct fb_info *_fb, - struct file *file, - struct vm_area_struct *vma) +/* fb_mmap + * Map video memory in user space. We don't use the generic fb_mmap method mainly + * to allow the use of the TLB streaming flag (CCA=6) + */ +int au1100fb_fb_mmap(struct fb_info *fbi, struct file *file, struct vm_area_struct *vma) { + struct au1100fb_device *fbdev = to_au1100fb_device(fbi); unsigned int len; unsigned long start=0, off; - struct au1100fb_info *fb = (struct au1100fb_info *)_fb; if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) { return -EINVAL; } - start = fb_info.fb_phys & PAGE_MASK; - len = PAGE_ALIGN((start & ~PAGE_MASK) + fb_info.fb_size); + start = fbdev->fb_phys & PAGE_MASK; + len = PAGE_ALIGN((start & ~PAGE_MASK) + fbdev->fb_len); off = vma->vm_pgoff << PAGE_SHIFT; @@ -401,276 +401,309 @@ au1100fb_mmap(struct fb_info *_fb, off += start; vma->vm_pgoff = off >> PAGE_SHIFT; - pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK; - //pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_NONCOHERENT; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); pgprot_val(vma->vm_page_prot) |= (6 << 9); //CCA=6 - /* This is an IO map - tell maydump to skip this VMA */ vma->vm_flags |= VM_IO; - if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT, + if (io_remap_page_range(vma, vma->vm_start, off, vma->vm_end - vma->vm_start, vma->vm_page_prot)) { return -EAGAIN; } - fb->mmaped = 1; return 0; } -int au1100_pan_display(const struct fb_var_screeninfo *var, - struct fb_info_gen *info) +static struct fb_ops au1100fb_ops = { - return 0; -} + .owner = THIS_MODULE, + .fb_setcolreg = au1100fb_fb_setcolreg, + .fb_blank = au1100fb_fb_blank, + .fb_pan_display = au1100fb_fb_pan_display, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, + .fb_rotate = au1100fb_fb_rotate, + .fb_mmap = au1100fb_fb_mmap, +}; -static int au1100fb_ioctl(struct inode *inode, struct file *file, u_int cmd, - u_long arg, int con, struct fb_info *info) -{ - /* nothing to do yet */ - return -EINVAL; -} -static struct fbgen_hwswitch au1100_switch = { - au1100_detect, - au1100_encode_fix, - au1100_decode_var, - au1100_encode_var, - au1100_get_par, - au1100_set_par, - au1100_getcolreg, - au1100_setcolreg, - au1100_pan_display, - au1100_blank, - au1100_set_disp -}; +/*-------------------------------------------------------------------------*/ +/* AU1100 LCD controller device driver */ -int au1100_setmode(void) +int au1100fb_drv_probe(struct device *dev) { - int words; - - /* FIXME Need to accomodate for swivel mode and 12bpp, <8bpp*/ - switch (p_lcd->mode_control & LCD_CONTROL_SM) - { - case LCD_CONTROL_SM_0: - case LCD_CONTROL_SM_180: - words = (p_lcd->xres * p_lcd->yres * p_lcd->bpp) / 32; - break; - case LCD_CONTROL_SM_90: - case LCD_CONTROL_SM_270: - /* is this correct? */ - words = (p_lcd->xres * p_lcd->bpp) / 8; - break; - default: - printk("mode_control reg not initialized\n"); + struct au1100fb_device *fbdev = NULL; + struct resource *regs_res; + unsigned long page; + u32 sys_clksrc; + + if (!dev) return -EINVAL; + + /* Allocate new device private */ + if (!(fbdev = kmalloc(sizeof(struct au1100fb_device), GFP_KERNEL))) { + print_err("fail to allocate device private record"); + return -ENOMEM; } + memset((void*)fbdev, 0, sizeof(struct au1100fb_device)); - /* - * Setup LCD controller - */ + fbdev->panel = &known_lcd_panels[drv_info.panel_idx]; - p_lcd_reg->lcd_control = p_lcd->mode_control; - p_lcd_reg->lcd_intstatus = 0; - p_lcd_reg->lcd_intenable = 0; - p_lcd_reg->lcd_horztiming = p_lcd->mode_horztiming; - p_lcd_reg->lcd_verttiming = p_lcd->mode_verttiming; - p_lcd_reg->lcd_clkcontrol = p_lcd->mode_clkcontrol; - p_lcd_reg->lcd_words = words - 1; - p_lcd_reg->lcd_dmaaddr0 = fb_info.fb_phys; + dev_set_drvdata(dev, (void*)fbdev); - /* turn on panel */ -#ifdef CONFIG_MIPS_PB1100 - au_writew(au_readw(PB1100_G_CONTROL) | p_lcd->mode_backlight, - PB1100_G_CONTROL); -#endif -#ifdef CONFIG_MIPS_HYDROGEN3 - /* Turn controller & power supply on, GPIO213 */ - au_writel(0x20002000, 0xB1700008); - au_writel(0x00040000, 0xB1900108); - au_writel(0x01000100, 0xB1700008); -#endif + /* Allocate region for our registers and map them */ + if (!(regs_res = platform_get_resource(to_platform_device(dev), + IORESOURCE_MEM, 0))) { + print_err("fail to retrieve registers resource"); + return -EFAULT; + } - p_lcd_reg->lcd_control |= LCD_CONTROL_GO; + au1100fb_fix.mmio_start = regs_res->start; + au1100fb_fix.mmio_len = regs_res->end - regs_res->start + 1; - return 0; -} + if (!request_mem_region(au1100fb_fix.mmio_start, au1100fb_fix.mmio_len, + DRIVER_NAME)) { + print_err("fail to lock memory region at 0x%08x", + au1100fb_fix.mmio_start); + return -EBUSY; + } + fbdev->regs = (struct au1100fb_regs*)KSEG1ADDR(au1100fb_fix.mmio_start); -int __init au1100fb_init(void) -{ - uint32 sys_clksrc; - unsigned long page; + print_dbg("Register memory map at %p", fbdev->regs); + print_dbg("phys=0x%08x, size=%d", fbdev->regs_phys, fbdev->regs_len); - /* - * Get the panel information/display mode and update the registry - */ - p_lcd = &panels[my_lcd_index]; - - switch (p_lcd->mode_control & LCD_CONTROL_SM) - { - case LCD_CONTROL_SM_0: - case LCD_CONTROL_SM_180: - p_lcd->xres = - (p_lcd->mode_horztiming & LCD_HORZTIMING_PPL) + 1; - p_lcd->yres = - (p_lcd->mode_verttiming & LCD_VERTTIMING_LPP) + 1; - break; - case LCD_CONTROL_SM_90: - case LCD_CONTROL_SM_270: - p_lcd->yres = - (p_lcd->mode_horztiming & LCD_HORZTIMING_PPL) + 1; - p_lcd->xres = - (p_lcd->mode_verttiming & LCD_VERTTIMING_LPP) + 1; - break; - } - /* - * Panel dimensions x bpp must be divisible by 32 - */ - if (((p_lcd->yres * p_lcd->bpp) % 32) != 0) - printk("VERT %% 32\n"); - if (((p_lcd->xres * p_lcd->bpp) % 32) != 0) - printk("HORZ %% 32\n"); - /* - * Allocate LCD framebuffer from system memory - */ - fb_info.fb_size = (p_lcd->xres * p_lcd->yres * p_lcd->bpp) / 8; - - current_par.var.xres = p_lcd->xres; - current_par.var.xres_virtual = p_lcd->xres; - current_par.var.yres = p_lcd->yres; - current_par.var.yres_virtual = p_lcd->yres; - current_par.var.bits_per_pixel = p_lcd->bpp; - - /* FIX!!! only works for 8/16 bpp */ - current_par.line_length = p_lcd->xres * p_lcd->bpp / 8; /* in bytes */ - fb_info.fb_virt_start = (unsigned long ) - __get_free_pages(GFP_ATOMIC | GFP_DMA, - get_order(fb_info.fb_size + 0x1000)); - if (!fb_info.fb_virt_start) { - printk("Unable to allocate fb memory\n"); + /* Allocate the framebuffer to the maximum screen size * nbr of video buffers */ + fbdev->fb_len = fbdev->panel->xres * fbdev->panel->yres * + (fbdev->panel->bpp >> 3) * AU1100FB_NBR_VIDEO_BUFFERS; + + fbdev->fb_mem = dma_alloc_coherent(dev, PAGE_ALIGN(fbdev->fb_len), + &fbdev->fb_phys, GFP_KERNEL); + if (!fbdev->fb_mem) { + print_err("fail to allocate frambuffer (size: %dK))", + fbdev->fb_len / 1024); return -ENOMEM; } - fb_info.fb_phys = virt_to_bus((void *)fb_info.fb_virt_start); + + au1100fb_fix.smem_start = fbdev->fb_phys; + au1100fb_fix.smem_len = fbdev->fb_len; /* * Set page reserved so that mmap will work. This is necessary * since we'll be remapping normal memory. */ - for (page = fb_info.fb_virt_start; - page < PAGE_ALIGN(fb_info.fb_virt_start + fb_info.fb_size); + for (page = (unsigned long)fbdev->fb_mem; + page < PAGE_ALIGN((unsigned long)fbdev->fb_mem + fbdev->fb_len); page += PAGE_SIZE) { +#if CONFIG_DMA_NONCOHERENT + SetPageReserved(virt_to_page(CAC_ADDR(page))); +#else SetPageReserved(virt_to_page(page)); +#endif } - memset((void *)fb_info.fb_virt_start, 0, fb_info.fb_size); - - /* set freqctrl now to allow more time to stabilize */ - /* zero-out out LCD bits */ - sys_clksrc = au_readl(SYS_CLKSRC) & ~0x000003e0; - sys_clksrc |= p_lcd->mode_toyclksrc; - au_writel(sys_clksrc, SYS_CLKSRC); - - /* FIXME add check to make sure auxpll is what is expected! */ - au1100_setmode(); - - fb_info.gen.parsize = sizeof(struct au1100fb_par); - fb_info.gen.fbhw = &au1100_switch; - - strcpy(fb_info.gen.info.modename, "Au1100 LCD"); - fb_info.gen.info.changevar = NULL; - fb_info.gen.info.node = -1; - - fb_info.gen.info.fbops = &au1100fb_ops; - fb_info.gen.info.disp = &disp; - fb_info.gen.info.switch_con = &fbgen_switch; - fb_info.gen.info.updatevar = &fbgen_update_var; - fb_info.gen.info.blank = &fbgen_blank; - fb_info.gen.info.flags = FBINFO_FLAG_DEFAULT; - - /* This should give a reasonable default video mode */ - fbgen_get_var(&disp.var, -1, &fb_info.gen.info); - fbgen_do_set_var(&disp.var, 1, &fb_info.gen); - fbgen_set_disp(-1, &fb_info.gen); - fbgen_install_cmap(0, &fb_info.gen); - if (register_framebuffer(&fb_info.gen.info) < 0) - return -EINVAL; - printk(KERN_INFO "fb%d: %s frame buffer device\n", - GET_FB_IDX(fb_info.gen.info.node), - fb_info.gen.info.modename); + print_dbg("Framebuffer memory map at %p", fbdev->fb_mem); + print_dbg("phys=0x%08x, size=%dK", fbdev->fb_phys, fbdev->fb_len / 1024); + + /* Setup LCD clock to AUX (48 MHz) */ + sys_clksrc = au_readl(SYS_CLKSRC) & ~(SYS_CS_ML_MASK | SYS_CS_DL | SYS_CS_CL); + au_writel((sys_clksrc | (1 << SYS_CS_ML_BIT)), SYS_CLKSRC); + + /* load the panel info into the var struct */ + au1100fb_var.bits_per_pixel = fbdev->panel->bpp; + au1100fb_var.xres = fbdev->panel->xres; + au1100fb_var.xres_virtual = au1100fb_var.xres; + au1100fb_var.yres = fbdev->panel->yres; + au1100fb_var.yres_virtual = au1100fb_var.yres; + + fbdev->info.screen_base = fbdev->fb_mem; + fbdev->info.fbops = &au1100fb_ops; + fbdev->info.fix = au1100fb_fix; + + if (!(fbdev->info.pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL))) { + return -ENOMEM; + } + memset(fbdev->info.pseudo_palette, 0, sizeof(u32) * 16); + + if (fb_alloc_cmap(&fbdev->info.cmap, AU1100_LCD_NBR_PALETTE_ENTRIES, 0) < 0) { + print_err("Fail to allocate colormap (%d entries)", + AU1100_LCD_NBR_PALETTE_ENTRIES); + kfree(fbdev->info.pseudo_palette); + return -EFAULT; + } + + fbdev->info.var = au1100fb_var; + + /* Set h/w registers */ + au1100fb_setmode(fbdev); + + /* Register new framebuffer */ + if (register_framebuffer(&fbdev->info) < 0) { + print_err("cannot register new framebuffer"); + goto failed; + } + + return 0; + +failed: + if (fbdev->regs) { + release_mem_region(fbdev->regs_phys, fbdev->regs_len); + } + if (fbdev->fb_mem) { + dma_free_noncoherent(dev, fbdev->fb_len, fbdev->fb_mem, fbdev->fb_phys); + } + if (fbdev->info.cmap.len != 0) { + fb_dealloc_cmap(&fbdev->info.cmap); + } + kfree(fbdev); + dev_set_drvdata(dev, NULL); return 0; } +int au1100fb_drv_remove(struct device *dev) +{ + struct au1100fb_device *fbdev = NULL; + + if (!dev) + return -ENODEV; + + fbdev = (struct au1100fb_device*) dev_get_drvdata(dev); + +#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO) + au1100fb_fb_blank(VESA_POWERDOWN, &fbdev->info); +#endif + fbdev->regs->lcd_control &= ~LCD_CONTROL_GO; -void au1100fb_cleanup(struct fb_info *info) + /* Clean up all probe data */ + unregister_framebuffer(&fbdev->info); + + release_mem_region(fbdev->regs_phys, fbdev->regs_len); + + dma_free_coherent(dev, PAGE_ALIGN(fbdev->fb_len), fbdev->fb_mem, fbdev->fb_phys); + + fb_dealloc_cmap(&fbdev->info.cmap); + kfree(fbdev->info.pseudo_palette); + kfree((void*)fbdev); + + return 0; +} + +int au1100fb_drv_suspend(struct device *dev, u32 state, u32 level) +{ + /* TODO */ + return 0; +} + +int au1100fb_drv_resume(struct device *dev, u32 level) { - unregister_framebuffer(info); + /* TODO */ + return 0; } +static struct device_driver au1100fb_driver = { + .name = "au1100-lcd", + .bus = &platform_bus_type, -void au1100fb_setup(char *options, int *ints) + .probe = au1100fb_drv_probe, + .remove = au1100fb_drv_remove, + .suspend = au1100fb_drv_suspend, + .resume = au1100fb_drv_resume, +}; + +/*-------------------------------------------------------------------------*/ + +/* Kernel driver */ + +int au1100fb_setup(char *options) { char* this_opt; - int i; - int num_panels = sizeof(panels)/sizeof(struct known_lcd_panels); + int num_panels = ARRAY_SIZE(known_lcd_panels); + char* mode = NULL; + int panel_idx = 0; + if (num_panels <= 0) { + print_err("No LCD panels supported by driver!"); + return -EFAULT; + } - if (!options || !*options) - return; - - for(this_opt=strtok(options, ","); this_opt; - this_opt=strtok(NULL, ",")) { + if (options) { + while ((this_opt = strsep(&options,",")) != NULL) { + /* Panel option */ if (!strncmp(this_opt, "panel:", 6)) { -#if defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) - /* Read Pb1100 Switch S10 ? */ - if (!strncmp(this_opt+6, "s10", 3)) - { - int panel; - panel = *(volatile int *)0xAE000008; /* BCSR SWITCHES */ - panel >>= 8; - panel &= 0x0F; - if (panel >= num_panels) panel = 0; - my_lcd_index = panel; - } - else -#endif - /* Get the panel name, everything else if fixed */ - for (i=0; i<num_panels; i++) { - if (!strncmp(this_opt+6, panels[i].panel_name, + int i; + this_opt += 6; + for (i = 0; i < num_panels; i++) { + if (!strncmp(this_opt, + known_lcd_panels[i].name, strlen(this_opt))) { - my_lcd_index = i; + panel_idx = i; break; } } + if (i >= num_panels) { + print_warn("Panel %s not supported!", this_opt); + } + } + /* Mode option (only option that start with digit) */ + else if (isdigit(this_opt[0])) { + mode = kmalloc(strlen(this_opt) + 1, GFP_KERNEL); + strncpy(mode, this_opt, strlen(this_opt) + 1); + } + /* Unsupported option */ + else { + print_warn("Unsupported option \"%s\"", this_opt); } - else if (!strncmp(this_opt, "nohwcursor", 10)) { - printk("nohwcursor\n"); - fb_info.nohwcursor = 1; } } - printk("au1100fb: Panel %d %s\n", my_lcd_index, - panels[my_lcd_index].panel_name); -} + drv_info.panel_idx = panel_idx; + drv_info.opt_mode = mode; + print_info("Panel=%s Mode=%s", + known_lcd_panels[drv_info.panel_idx].name, + drv_info.opt_mode ? drv_info.opt_mode : "default"); + return 0; +} -#ifdef MODULE -MODULE_LICENSE("GPL"); -int init_module(void) +int __init au1100fb_init(void) { - return au1100fb_init(); + char* options; + int ret; + + print_info("" DRIVER_DESC ""); + + memset(&drv_info, 0, sizeof(drv_info)); + + if (fb_get_options(DRIVER_NAME, &options)) + return -ENODEV; + + /* Setup driver with options */ + ret = au1100fb_setup(options); + if (ret < 0) { + print_err("Fail to setup driver"); + return ret; + } + + return driver_register(&au1100fb_driver); } -void cleanup_module(void) +void __exit au1100fb_cleanup(void) { - au1100fb_cleanup(void); + driver_unregister(&au1100fb_driver); + + if (drv_info.opt_mode) + kfree(drv_info.opt_mode); } -MODULE_AUTHOR("Pete Popov <ppopov@mvista.com>"); -MODULE_DESCRIPTION("Au1100 LCD framebuffer device driver"); -#endif /* MODULE */ +module_init(au1100fb_init); +module_exit(au1100fb_cleanup); + +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/au1100fb.h b/drivers/video/au1100fb.h index 657c560ab73c..2855534dc235 100644 --- a/drivers/video/au1100fb.h +++ b/drivers/video/au1100fb.h @@ -30,352 +30,352 @@ #ifndef _AU1100LCD_H #define _AU1100LCD_H +#include <asm/mach-au1x00/au1000.h> + +#define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg) +#define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg) +#define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg) + +#if DEBUG +#define print_dbg(f, arg...) printk(__FILE__ ": " f "\n", ## arg) +#else +#define print_dbg(f, arg...) do {} while (0) +#endif + +#if defined(__BIG_ENDIAN) +#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11 +#else +#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00 +#endif +#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565 + /********************************************************************/ -#define uint32 unsigned long -typedef volatile struct -{ - uint32 lcd_control; - uint32 lcd_intstatus; - uint32 lcd_intenable; - uint32 lcd_horztiming; - uint32 lcd_verttiming; - uint32 lcd_clkcontrol; - uint32 lcd_dmaaddr0; - uint32 lcd_dmaaddr1; - uint32 lcd_words; - uint32 lcd_pwmdiv; - uint32 lcd_pwmhi; - uint32 reserved[(0x0400-0x002C)/4]; - uint32 lcd_pallettebase[256]; - -} AU1100_LCD; + +/* LCD controller restrictions */ +#define AU1100_LCD_MAX_XRES 800 +#define AU1100_LCD_MAX_YRES 600 +#define AU1100_LCD_MAX_BPP 16 +#define AU1100_LCD_MAX_CLK 48000000 +#define AU1100_LCD_NBR_PALETTE_ENTRIES 256 + +/* Default number of visible screen buffer to allocate */ +#define AU1100FB_NBR_VIDEO_BUFFERS 4 /********************************************************************/ -#define AU1100_LCD_ADDR 0xB5000000 +struct au1100fb_panel +{ + const char name[25]; /* Full name <vendor>_<model> */ -/* - * Register bit definitions - */ + u32 control_base; /* Mode-independent control values */ + u32 clkcontrol_base; /* Panel pixclock preferences */ -/* lcd_control */ -#define LCD_CONTROL_SBPPF (7<<18) -#define LCD_CONTROL_SBPPF_655 (0<<18) -#define LCD_CONTROL_SBPPF_565 (1<<18) -#define LCD_CONTROL_SBPPF_556 (2<<18) -#define LCD_CONTROL_SBPPF_1555 (3<<18) -#define LCD_CONTROL_SBPPF_5551 (4<<18) -#define LCD_CONTROL_WP (1<<17) -#define LCD_CONTROL_WD (1<<16) -#define LCD_CONTROL_C (1<<15) -#define LCD_CONTROL_SM (3<<13) -#define LCD_CONTROL_SM_0 (0<<13) -#define LCD_CONTROL_SM_90 (1<<13) -#define LCD_CONTROL_SM_180 (2<<13) -#define LCD_CONTROL_SM_270 (3<<13) -#define LCD_CONTROL_DB (1<<12) -#define LCD_CONTROL_CCO (1<<11) -#define LCD_CONTROL_DP (1<<10) -#define LCD_CONTROL_PO (3<<8) -#define LCD_CONTROL_PO_00 (0<<8) -#define LCD_CONTROL_PO_01 (1<<8) -#define LCD_CONTROL_PO_10 (2<<8) -#define LCD_CONTROL_PO_11 (3<<8) -#define LCD_CONTROL_MPI (1<<7) -#define LCD_CONTROL_PT (1<<6) -#define LCD_CONTROL_PC (1<<5) -#define LCD_CONTROL_BPP (7<<1) -#define LCD_CONTROL_BPP_1 (0<<1) -#define LCD_CONTROL_BPP_2 (1<<1) -#define LCD_CONTROL_BPP_4 (2<<1) -#define LCD_CONTROL_BPP_8 (3<<1) -#define LCD_CONTROL_BPP_12 (4<<1) -#define LCD_CONTROL_BPP_16 (5<<1) -#define LCD_CONTROL_GO (1<<0) - -/* lcd_intstatus, lcd_intenable */ -#define LCD_INT_SD (1<<7) -#define LCD_INT_OF (1<<6) -#define LCD_INT_UF (1<<5) -#define LCD_INT_SA (1<<3) -#define LCD_INT_SS (1<<2) -#define LCD_INT_S1 (1<<1) -#define LCD_INT_S0 (1<<0) - -/* lcd_horztiming */ -#define LCD_HORZTIMING_HN2 (255<<24) -#define LCD_HORZTIMING_HN2_N(N) (((N)-1)<<24) -#define LCD_HORZTIMING_HN1 (255<<16) -#define LCD_HORZTIMING_HN1_N(N) (((N)-1)<<16) -#define LCD_HORZTIMING_HPW (63<<10) -#define LCD_HORZTIMING_HPW_N(N) (((N)-1)<<10) -#define LCD_HORZTIMING_PPL (1023<<0) -#define LCD_HORZTIMING_PPL_N(N) (((N)-1)<<0) - -/* lcd_verttiming */ -#define LCD_VERTTIMING_VN2 (255<<24) -#define LCD_VERTTIMING_VN2_N(N) (((N)-1)<<24) -#define LCD_VERTTIMING_VN1 (255<<16) -#define LCD_VERTTIMING_VN1_N(N) (((N)-1)<<16) -#define LCD_VERTTIMING_VPW (63<<10) -#define LCD_VERTTIMING_VPW_N(N) (((N)-1)<<10) -#define LCD_VERTTIMING_LPP (1023<<0) -#define LCD_VERTTIMING_LPP_N(N) (((N)-1)<<0) - -/* lcd_clkcontrol */ -#define LCD_CLKCONTROL_IB (1<<18) -#define LCD_CLKCONTROL_IC (1<<17) -#define LCD_CLKCONTROL_IH (1<<16) -#define LCD_CLKCONTROL_IV (1<<15) -#define LCD_CLKCONTROL_BF (31<<10) -#define LCD_CLKCONTROL_BF_N(N) (((N)-1)<<10) -#define LCD_CLKCONTROL_PCD (1023<<0) -#define LCD_CLKCONTROL_PCD_N(N) ((N)<<0) - -/* lcd_pwmdiv */ -#define LCD_PWMDIV_EN (1<<12) -#define LCD_PWMDIV_PWMDIV (2047<<0) -#define LCD_PWMDIV_PWMDIV_N(N) (((N)-1)<<0) - -/* lcd_pwmhi */ -#define LCD_PWMHI_PWMHI1 (2047<<12) -#define LCD_PWMHI_PWMHI1_N(N) ((N)<<12) -#define LCD_PWMHI_PWMHI0 (2047<<0) -#define LCD_PWMHI_PWMHI0_N(N) ((N)<<0) - -/* lcd_pallettebase - MONOCHROME */ -#define LCD_PALLETTE_MONO_MI (15<<0) -#define LCD_PALLETTE_MONO_MI_N(N) ((N)<<0) - -/* lcd_pallettebase - COLOR */ -#define LCD_PALLETTE_COLOR_BI (15<<8) -#define LCD_PALLETTE_COLOR_BI_N(N) ((N)<<8) -#define LCD_PALLETTE_COLOR_GI (15<<4) -#define LCD_PALLETTE_COLOR_GI_N(N) ((N)<<4) -#define LCD_PALLETTE_COLOR_RI (15<<0) -#define LCD_PALLETTE_COLOR_RI_N(N) ((N)<<0) - -/* lcd_palletebase - COLOR TFT PALLETIZED */ -#define LCD_PALLETTE_TFT_DC (65535<<0) -#define LCD_PALLETTE_TFT_DC_N(N) ((N)<<0) + u32 horztiming; + u32 verttiming; -/********************************************************************/ + u32 xres; /* Maximum horizontal resolution */ + u32 yres; /* Maximum vertical resolution */ + u32 bpp; /* Maximum depth supported */ +}; -struct known_lcd_panels +struct au1100fb_regs { - uint32 xres; - uint32 yres; - uint32 bpp; - unsigned char panel_name[256]; - uint32 mode_control; - uint32 mode_horztiming; - uint32 mode_verttiming; - uint32 mode_clkcontrol; - uint32 mode_pwmdiv; - uint32 mode_pwmhi; - uint32 mode_toyclksrc; - uint32 mode_backlight; + u32 lcd_control; + u32 lcd_intstatus; + u32 lcd_intenable; + u32 lcd_horztiming; + u32 lcd_verttiming; + u32 lcd_clkcontrol; + u32 lcd_dmaaddr0; + u32 lcd_dmaaddr1; + u32 lcd_words; + u32 lcd_pwmdiv; + u32 lcd_pwmhi; + u32 reserved[(0x0400-0x002C)/4]; + u32 lcd_pallettebase[256]; +}; + +struct au1100fb_device { + + struct fb_info info; /* FB driver info record */ + struct au1100fb_panel *panel; /* Panel connected to this device */ + + struct au1100fb_regs* regs; /* Registers memory map */ + size_t regs_len; + unsigned int regs_phys; + + unsigned char* fb_mem; /* FrameBuffer memory map */ + size_t fb_len; + dma_addr_t fb_phys; }; -#if defined(__BIG_ENDIAN) -#define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_11 -#else -#define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_00 -#endif +/********************************************************************/ -/* - * The fb driver assumes that AUX PLL is at 48MHz. That can - * cover up to 800x600 resolution; if you need higher resolution, - * you should modify the driver as needed, not just this structure. +#define LCD_CONTROL (AU1100_LCD_BASE + 0x0) + #define LCD_CONTROL_SBB_BIT 21 + #define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT) + #define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT) + #define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT) + #define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT) + #define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT) + #define LCD_CONTROL_SBPPF_BIT 18 + #define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT) + #define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT) + #define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT) + #define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT) + #define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT) + #define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT) + #define LCD_CONTROL_WP (1<<17) + #define LCD_CONTROL_WD (1<<16) + #define LCD_CONTROL_C (1<<15) + #define LCD_CONTROL_SM_BIT 13 + #define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT) + #define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT) + #define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT) + #define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT) + #define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT) + #define LCD_CONTROL_DB (1<<12) + #define LCD_CONTROL_CCO (1<<11) + #define LCD_CONTROL_DP (1<<10) + #define LCD_CONTROL_PO_BIT 8 + #define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT) + #define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT) + #define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT) + #define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT) + #define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT) + #define LCD_CONTROL_MPI (1<<7) + #define LCD_CONTROL_PT (1<<6) + #define LCD_CONTROL_PC (1<<5) + #define LCD_CONTROL_BPP_BIT 1 + #define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT) + #define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT) + #define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT) + #define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT) + #define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT) + #define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT) + #define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT) + #define LCD_CONTROL_GO (1<<0) + +#define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4) +#define LCD_INTENABLE (AU1100_LCD_BASE + 0x8) + #define LCD_INT_SD (1<<7) + #define LCD_INT_OF (1<<6) + #define LCD_INT_UF (1<<5) + #define LCD_INT_SA (1<<3) + #define LCD_INT_SS (1<<2) + #define LCD_INT_S1 (1<<1) + #define LCD_INT_S0 (1<<0) + +#define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC) + #define LCD_HORZTIMING_HN2_BIT 24 + #define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT) + #define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK) + #define LCD_HORZTIMING_HN1_BIT 16 + #define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT) + #define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK) + #define LCD_HORZTIMING_HPW_BIT 10 + #define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT) + #define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK) + #define LCD_HORZTIMING_PPL_BIT 0 + #define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT) + #define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK) + +#define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10) + #define LCD_VERTTIMING_VN2_BIT 24 + #define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT) + #define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK) + #define LCD_VERTTIMING_VN1_BIT 16 + #define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT) + #define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK) + #define LCD_VERTTIMING_VPW_BIT 10 + #define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT) + #define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK) + #define LCD_VERTTIMING_LPP_BIT 0 + #define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT) + #define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK) + +#define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14) + #define LCD_CLKCONTROL_IB (1<<18) + #define LCD_CLKCONTROL_IC (1<<17) + #define LCD_CLKCONTROL_IH (1<<16) + #define LCD_CLKCONTROL_IV (1<<15) + #define LCD_CLKCONTROL_BF_BIT 10 + #define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT) + #define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK) + #define LCD_CLKCONTROL_PCD_BIT 0 + #define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT) + #define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK) + +#define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18) +#define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C) + #define LCD_DMA_SA_BIT 5 + #define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT) + #define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK) + +#define LCD_WORDS (AU1100_LCD_BASE + 0x20) + #define LCD_WRD_WRDS_BIT 0 + #define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT) + #define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK) + +#define LCD_PWMDIV (AU1100_LCD_BASE + 0x24) + #define LCD_PWMDIV_EN (1<<12) + #define LCD_PWMDIV_PWMDIV_BIT 0 + #define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT) + #define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK) + +#define LCD_PWMHI (AU1100_LCD_BASE + 0x28) + #define LCD_PWMHI_PWMHI1_BIT 12 + #define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT) + #define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK) + #define LCD_PWMHI_PWMHI0_BIT 0 + #define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT) + #define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK) + +#define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400) + #define LCD_PALLETTE_MONO_MI_BIT 0 + #define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT) + #define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK) + + #define LCD_PALLETTE_COLOR_RI_BIT 8 + #define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT) + #define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK) + #define LCD_PALLETTE_COLOR_GI_BIT 4 + #define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT) + #define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK) + #define LCD_PALLETTE_COLOR_BI_BIT 0 + #define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT) + #define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK) + + #define LCD_PALLETTE_TFT_DC_BIT 0 + #define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT) + #define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK) + +/********************************************************************/ + +/* List of panels known to work with the AU1100 LCD controller. + * To add a new panel, enter the same specifications as the + * Generic_TFT one, and MAKE SURE that it doesn't conflicts + * with the controller restrictions. Restrictions are: + * + * STN color panels: max_bpp <= 12 + * STN mono panels: max_bpp <= 4 + * TFT panels: max_bpp <= 16 + * max_xres <= 800 + * max_yres <= 600 */ -struct known_lcd_panels panels[] = +static struct au1100fb_panel known_lcd_panels[] = { - { /* 0: Pb1100 LCDA: Sharp 320x240 TFT panel */ - 320, /* xres */ - 240, /* yres */ - 16, /* bpp */ - - "Sharp_320x240_16", - /* mode_control */ + /* 800x600x16bpp CRT */ + [0] = { + .name = "CRT_800x600_16", + .xres = 800, + .yres = 600, + .bpp = 16, + .control_base = 0x0004886A | + LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF | + LCD_CONTROL_BPP_16, + .clkcontrol_base = 0x00020000, + .horztiming = 0x005aff1f, + .verttiming = 0x16000e57, + }, + /* just the standard LCD */ + [1] = { + .name = "WWPC LCD", + .xres = 240, + .yres = 320, + .bpp = 16, + .control_base = 0x0006806A, + .horztiming = 0x0A1010EF, + .verttiming = 0x0301013F, + .clkcontrol_base = 0x00018001, + }, + /* Sharp 320x240 TFT panel */ + [2] = { + .name = "Sharp_LQ038Q5DR01", + .xres = 320, + .yres = 240, + .bpp = 16, + .control_base = ( LCD_CONTROL_SBPPF_565 - /*LCD_CONTROL_WP*/ - /*LCD_CONTROL_WD*/ | LCD_CONTROL_C | LCD_CONTROL_SM_0 - /*LCD_CONTROL_DB*/ - /*LCD_CONTROL_CCO*/ - /*LCD_CONTROL_DP*/ - | LCD_DEFAULT_PIX_FORMAT - /*LCD_CONTROL_MPI*/ + | LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_PT | LCD_CONTROL_PC | LCD_CONTROL_BPP_16 ), - - /* mode_horztiming */ + .horztiming = ( LCD_HORZTIMING_HN2_N(8) | LCD_HORZTIMING_HN1_N(60) | LCD_HORZTIMING_HPW_N(12) | LCD_HORZTIMING_PPL_N(320) ), - - /* mode_verttiming */ + .verttiming = ( LCD_VERTTIMING_VN2_N(5) | LCD_VERTTIMING_VN1_N(17) | LCD_VERTTIMING_VPW_N(1) | LCD_VERTTIMING_LPP_N(240) ), - - /* mode_clkcontrol */ - ( 0 - /*LCD_CLKCONTROL_IB*/ - /*LCD_CLKCONTROL_IC*/ - /*LCD_CLKCONTROL_IH*/ - /*LCD_CLKCONTROL_IV*/ - | LCD_CLKCONTROL_PCD_N(1) ), - - /* mode_pwmdiv */ - 0, - - /* mode_pwmhi */ - 0, - - /* mode_toyclksrc */ - ((1<<7) | (1<<6) | (1<<5)), - - /* mode_backlight */ - 6 + .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1), }, - { /* 1: Pb1100 LCDC 640x480 TFT panel */ - 640, /* xres */ - 480, /* yres */ - 16, /* bpp */ - - "Generic_640x480_16", - - /* mode_control */ - 0x004806a | LCD_DEFAULT_PIX_FORMAT, - - /* mode_horztiming */ - 0x3434d67f, - - /* mode_verttiming */ - 0x0e0e39df, - - /* mode_clkcontrol */ - ( 0 - /*LCD_CLKCONTROL_IB*/ - /*LCD_CLKCONTROL_IC*/ - /*LCD_CLKCONTROL_IH*/ - /*LCD_CLKCONTROL_IV*/ - | LCD_CLKCONTROL_PCD_N(1) ), - - /* mode_pwmdiv */ - 0, - - /* mode_pwmhi */ - 0, - - /* mode_toyclksrc */ - ((1<<7) | (1<<6) | (0<<5)), - - /* mode_backlight */ - 7 + /* Hitachi SP14Q005 and possibly others */ + [3] = { + .name = "Hitachi_SP14Qxxx", + .xres = 320, + .yres = 240, + .bpp = 4, + .control_base = + ( LCD_CONTROL_C + | LCD_CONTROL_BPP_4 ), + .horztiming = + ( LCD_HORZTIMING_HN2_N(1) + | LCD_HORZTIMING_HN1_N(1) + | LCD_HORZTIMING_HPW_N(1) + | LCD_HORZTIMING_PPL_N(320) ), + .verttiming = + ( LCD_VERTTIMING_VN2_N(1) + | LCD_VERTTIMING_VN1_N(1) + | LCD_VERTTIMING_VPW_N(1) + | LCD_VERTTIMING_LPP_N(240) ), + .clkcontrol_base = LCD_CLKCONTROL_PCD_N(4), }, - { /* 2: Pb1100 LCDB 640x480 PrimeView TFT panel */ - 640, /* xres */ - 480, /* yres */ - 16, /* bpp */ - - "PrimeView_640x480_16", - - /* mode_control */ - 0x0004886a | LCD_DEFAULT_PIX_FORMAT, - - /* mode_horztiming */ - 0x0e4bfe7f, - - /* mode_verttiming */ - 0x210805df, - - /* mode_clkcontrol */ - 0x00038001, - - /* mode_pwmdiv */ - 0, - - /* mode_pwmhi */ - 0, - - /* mode_toyclksrc */ - ((1<<7) | (1<<6) | (0<<5)), - - /* mode_backlight */ - 7 + /* Generic 640x480 TFT panel */ + [4] = { + .name = "TFT_640x480_16", + .xres = 640, + .yres = 480, + .bpp = 16, + .control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO, + .horztiming = 0x3434d67f, + .verttiming = 0x0e0e39df, + .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1), }, - { /* 3: Pb1100 800x600x16bpp NEON CRT */ - 800, /* xres */ - 600, /* yres */ - 16, /* bpp */ - - "NEON_800x600_16", - - /* mode_control */ - 0x0004886A | LCD_DEFAULT_PIX_FORMAT, - - /* mode_horztiming */ - 0x005AFF1F, - - /* mode_verttiming */ - 0x16000E57, - - /* mode_clkcontrol */ - 0x00020000, - - /* mode_pwmdiv */ - 0, - - /* mode_pwmhi */ - 0, - - /* mode_toyclksrc */ - ((1<<7) | (1<<6) | (0<<5)), - - /* mode_backlight */ - 7 + /* Pb1100 LCDB 640x480 PrimeView TFT panel */ + [5] = { + .name = "PrimeView_640x480_16", + .xres = 640, + .yres = 480, + .bpp = 16, + .control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO, + .horztiming = 0x0e4bfe7f, + .verttiming = 0x210805df, + .clkcontrol_base = 0x00038001, }, +}; - { /* 4: Pb1100 640x480x16bpp NEON CRT */ - 640, /* xres */ - 480, /* yres */ - 16, /* bpp */ - - "NEON_640x480_16", - - /* mode_control */ - 0x0004886A | LCD_DEFAULT_PIX_FORMAT, - - /* mode_horztiming */ - 0x0052E27F, - - /* mode_verttiming */ - 0x18000DDF, - - /* mode_clkcontrol */ - 0x00020000, +struct au1100fb_drv_info { + int panel_idx; + char *opt_mode; +}; - /* mode_pwmdiv */ - 0, +/********************************************************************/ - /* mode_pwmhi */ - 0, +/* Inline helpers */ - /* mode_toyclksrc */ - ((1<<7) | (1<<6) | (0<<5)), +#define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP) +#define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT) +#define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC) +#define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO) - /* mode_backlight */ - 7 - }, -}; #endif /* _AU1100LCD_H */ diff --git a/drivers/video/console/newport_con.c b/drivers/video/console/newport_con.c index e793ffd39db5..762c7a593141 100644 --- a/drivers/video/console/newport_con.c +++ b/drivers/video/console/newport_con.c @@ -32,7 +32,6 @@ #include <linux/font.h> -extern struct font_desc font_vga_8x16; extern unsigned long sgi_gfxaddr; #define FONT_DATA ((unsigned char *)font_vga_8x16.data) diff --git a/drivers/video/gbefb.c b/drivers/video/gbefb.c index d3c1922cb13a..485604cd4462 100644 --- a/drivers/video/gbefb.c +++ b/drivers/video/gbefb.c @@ -1126,7 +1126,7 @@ static int __init gbefb_probe(struct device *dev) gbefb_setup(options); #endif - if (!request_mem_region(GBE_BASE, sizeof(struct sgi_gbe), "GBE")) { + if (!request_region(GBE_BASE, sizeof(struct sgi_gbe), "GBE")) { printk(KERN_ERR "gbefb: couldn't reserve mmio region\n"); ret = -EBUSY; goto out_release_framebuffer; @@ -1152,12 +1152,24 @@ static int __init gbefb_probe(struct device *dev) if (gbe_mem_phys) { /* memory was allocated at boot time */ gbe_mem = ioremap_nocache(gbe_mem_phys, gbe_mem_size); + if (!gbe_mem) { + printk(KERN_ERR "gbefb: couldn't map framebuffer\n"); + ret = -ENOMEM; + goto out_tiles_free; + } + gbe_dma_addr = 0; } else { /* try to allocate memory with the classical allocator * this has high chance to fail on low memory machines */ gbe_mem = dma_alloc_coherent(NULL, gbe_mem_size, &gbe_dma_addr, GFP_KERNEL); + if (!gbe_mem) { + printk(KERN_ERR "gbefb: couldn't allocate framebuffer memory\n"); + ret = -ENOMEM; + goto out_tiles_free; + } + gbe_mem_phys = (unsigned long) gbe_dma_addr; } @@ -1165,12 +1177,6 @@ static int __init gbefb_probe(struct device *dev) mtrr_add(gbe_mem_phys, gbe_mem_size, MTRR_TYPE_WRCOMB, 1); #endif - if (!gbe_mem) { - printk(KERN_ERR "gbefb: couldn't map framebuffer\n"); - ret = -ENXIO; - goto out_tiles_free; - } - /* map framebuffer memory into tiles table */ for (i = 0; i < (gbe_mem_size >> TILE_SHIFT); i++) gbe_tiles.cpu[i] = (gbe_mem_phys >> TILE_SHIFT) + i; diff --git a/include/asm-mips/abi.h b/include/asm-mips/abi.h new file mode 100644 index 000000000000..2e7e651c3e3f --- /dev/null +++ b/include/asm-mips/abi.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005 by Ralf Baechle + * Copyright (C) 2005 MIPS Technologies, Inc. + */ +#ifndef _ASM_ABI_H +#define _ASM_ABI_H + +#include <asm/signal.h> +#include <asm/siginfo.h> + +struct mips_abi { + int (* const do_signal)(sigset_t *oldset, struct pt_regs *regs); + int (* const setup_frame)(struct k_sigaction * ka, + struct pt_regs *regs, int signr, + sigset_t *set); + int (* const setup_rt_frame)(struct k_sigaction * ka, + struct pt_regs *regs, int signr, + sigset_t *set, siginfo_t *info); +}; + +#endif /* _ASM_ABI_H */ diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index 7dc2619f5006..42520cc84b0f 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -20,10 +20,12 @@ #define _ATYPE_ #define _ATYPE32_ #define _ATYPE64_ +#define _LLCONST_(x) x #else #define _ATYPE_ __PTRDIFF_TYPE__ #define _ATYPE32_ int #define _ATYPE64_ long long +#define _LLCONST_(x) x ## LL #endif /* @@ -45,8 +47,9 @@ /* * Returns the physical address of a CKSEGx / XKPHYS address */ -#define CPHYSADDR(a) ((_ACAST32_ (a)) & 0x1fffffff) -#define XPHYSADDR(a) ((_ACAST64_ (a)) & 0x000000ffffffffff) +#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) +#define XPHYSADDR(a) ((_ACAST64_(a)) & \ + _LLCONST_(0x000000ffffffffff)) #ifdef CONFIG_64BIT @@ -55,14 +58,14 @@ * The compatibility segments use the full 64-bit sign extended value. Note * the R8000 doesn't have them so don't reference these in generic MIPS code. */ -#define XKUSEG 0x0000000000000000 -#define XKSSEG 0x4000000000000000 -#define XKPHYS 0x8000000000000000 -#define XKSEG 0xc000000000000000 -#define CKSEG0 0xffffffff80000000 -#define CKSEG1 0xffffffffa0000000 -#define CKSSEG 0xffffffffc0000000 -#define CKSEG3 0xffffffffe0000000 +#define XKUSEG _LLCONST_(0x0000000000000000) +#define XKSSEG _LLCONST_(0x4000000000000000) +#define XKPHYS _LLCONST_(0x8000000000000000) +#define XKSEG _LLCONST_(0xc000000000000000) +#define CKSEG0 _LLCONST_(0xffffffff80000000) +#define CKSEG1 _LLCONST_(0xffffffffa0000000) +#define CKSSEG _LLCONST_(0xffffffffc0000000) +#define CKSEG3 _LLCONST_(0xffffffffe0000000) #define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) @@ -120,7 +123,8 @@ #define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p)) #define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p)) #define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) -#define PHYS_TO_XKPHYS(cm,a) (0x8000000000000000 | ((cm)<<59) | (a)) +#define PHYS_TO_XKPHYS(cm,a) (_LLCONST_(0x8000000000000000) | \ + ((cm)<<59) | (a)) #if defined (CONFIG_CPU_R4300) \ || defined (CONFIG_CPU_R4X00) \ @@ -128,46 +132,56 @@ || defined (CONFIG_CPU_NEVADA) \ || defined (CONFIG_CPU_TX49XX) \ || defined (CONFIG_CPU_MIPS64) -#define KUSIZE 0x0000010000000000 /* 2^^40 */ -#define KUSIZE_64 0x0000010000000000 /* 2^^40 */ -#define K0SIZE 0x0000001000000000 /* 2^^36 */ -#define K1SIZE 0x0000001000000000 /* 2^^36 */ -#define K2SIZE 0x000000ff80000000 -#define KSEGSIZE 0x000000ff80000000 /* max syssegsz */ -#define TO_PHYS_MASK 0x0000000fffffffff /* 2^^36 - 1 */ +#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ +#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */ +#define K0SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */ +#define K1SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */ +#define K2SIZE _LLCONST_(0x000000ff80000000) +#define KSEGSIZE _LLCONST_(0x000000ff80000000) /* max syssegsz */ +#define TO_PHYS_MASK _LLCONST_(0x0000000fffffffff) /* 2^^36 - 1 */ #endif #if defined (CONFIG_CPU_R8000) /* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */ -#define KUSIZE 0x0000010000000000 /* 2^^40 */ -#define KUSIZE_64 0x0000010000000000 /* 2^^40 */ -#define K0SIZE 0x0000010000000000 /* 2^^40 */ -#define K1SIZE 0x0000010000000000 /* 2^^40 */ -#define K2SIZE 0x0001000000000000 -#define KSEGSIZE 0x0000010000000000 /* max syssegsz */ -#define TO_PHYS_MASK 0x000000ffffffffff /* 2^^40 - 1 */ +#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ +#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */ +#define K0SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ +#define K1SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ +#define K2SIZE _LLCONST_(0x0001000000000000) +#define KSEGSIZE _LLCONST_(0x0000010000000000) /* max syssegsz */ +#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */ #endif #if defined (CONFIG_CPU_R10000) -#define KUSIZE 0x0000010000000000 /* 2^^40 */ -#define KUSIZE_64 0x0000010000000000 /* 2^^40 */ -#define K0SIZE 0x0000010000000000 /* 2^^40 */ -#define K1SIZE 0x0000010000000000 /* 2^^40 */ -#define K2SIZE 0x00000fff80000000 -#define KSEGSIZE 0x00000fff80000000 /* max syssegsz */ -#define TO_PHYS_MASK 0x000000ffffffffff /* 2^^40 - 1 */ +#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ +#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */ +#define K0SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ +#define K1SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ +#define K2SIZE _LLCONST_(0x00000fff80000000) +#define KSEGSIZE _LLCONST_(0x00000fff80000000) /* max syssegsz */ +#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */ +#endif + +#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A) +#define KUSIZE _LLCONST_(0x0000100000000000) /* 2^^44 */ +#define KUSIZE_64 _LLCONST_(0x0000100000000000) /* 2^^44 */ +#define K0SIZE _LLCONST_(0x0000100000000000) /* 2^^44 */ +#define K1SIZE _LLCONST_(0x0000100000000000) /* 2^^44 */ +#define K2SIZE _LLCONST_(0x0000ffff80000000) +#define KSEGSIZE _LLCONST_(0x0000ffff80000000) /* max syssegsz */ +#define TO_PHYS_MASK _LLCONST_(0x00000fffffffffff) /* 2^^44 - 1 */ #endif /* * Further names for SGI source compatibility. These are stolen from * IRIX's <sys/mips_addrspace.h>. */ -#define KUBASE 0 -#define KUSIZE_32 0x0000000080000000 /* KUSIZE +#define KUBASE _LLCONST_(0) +#define KUSIZE_32 _LLCONST_(0x0000000080000000) /* KUSIZE for a 32 bit proc */ -#define K0BASE_EXL_WR 0xa800000000000000 /* exclusive on write */ -#define K0BASE_NONCOH 0x9800000000000000 /* noncoherent */ -#define K0BASE_EXL 0xa000000000000000 /* exclusive */ +#define K0BASE_EXL_WR _LLCONST_(0xa800000000000000) /* exclusive on write */ +#define K0BASE_NONCOH _LLCONST_(0x9800000000000000) /* noncoherent */ +#define K0BASE_EXL _LLCONST_(0xa000000000000000) /* exclusive */ #ifndef CONFIG_CPU_R8000 @@ -176,7 +190,7 @@ * in order to catch bugs in the source code. */ -#define COMPAT_K1BASE32 0xffffffffa0000000 +#define COMPAT_K1BASE32 _LLCONST_(0xffffffffa0000000) #define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ #endif diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h index f53237772985..4b090f3142e0 100644 --- a/include/asm-mips/asm.h +++ b/include/asm-mips/asm.h @@ -107,6 +107,7 @@ symbol = value /* * Print formatted string */ +#ifdef CONFIG_PRINTK #define PRINT(string) \ .set push; \ .set reorder; \ @@ -114,6 +115,9 @@ symbol = value jal printk; \ .set pop; \ TEXT(string) +#else +#define PRINT(string) +#endif #define TEXT(msg) \ .pushsection .data; \ diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index c0bd8d014e14..6202eb8a14b7 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h @@ -62,20 +62,24 @@ static __inline__ void atomic_add(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: ll %0, %1 # atomic_add \n" " addu %0, %2 \n" " sc %0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else if (cpu_has_llsc) { unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: ll %0, %1 # atomic_add \n" " addu %0, %2 \n" " sc %0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else { @@ -100,20 +104,24 @@ static __inline__ void atomic_sub(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: ll %0, %1 # atomic_sub \n" " subu %0, %2 \n" " sc %0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else if (cpu_has_llsc) { unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: ll %0, %1 # atomic_sub \n" " subu %0, %2 \n" " sc %0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else { @@ -136,12 +144,14 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: ll %1, %2 # atomic_add_return \n" " addu %0, %1, %3 \n" " sc %0, %2 \n" " beqzl %0, 1b \n" " addu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -149,12 +159,14 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: ll %1, %2 # atomic_add_return \n" " addu %0, %1, %3 \n" " sc %0, %2 \n" " beqz %0, 1b \n" " addu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -179,12 +191,14 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: ll %1, %2 # atomic_sub_return \n" " subu %0, %1, %3 \n" " sc %0, %2 \n" " beqzl %0, 1b \n" " subu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -192,12 +206,14 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: ll %1, %2 # atomic_sub_return \n" " subu %0, %1, %3 \n" " sc %0, %2 \n" " beqz %0, 1b \n" " subu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -229,6 +245,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: ll %1, %2 # atomic_sub_if_positive\n" " subu %0, %1, %3 \n" " bltz %0, 1f \n" @@ -236,6 +253,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) " beqzl %0, 1b \n" " sync \n" "1: \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -243,6 +261,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: ll %1, %2 # atomic_sub_if_positive\n" " subu %0, %1, %3 \n" " bltz %0, 1f \n" @@ -250,6 +269,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) " beqz %0, 1b \n" " sync \n" "1: \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -367,20 +387,24 @@ static __inline__ void atomic64_add(long i, atomic64_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %0, %1 # atomic64_add \n" " addu %0, %2 \n" " scd %0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else if (cpu_has_llsc) { unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %0, %1 # atomic64_add \n" " addu %0, %2 \n" " scd %0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else { @@ -405,20 +429,24 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %0, %1 # atomic64_sub \n" " subu %0, %2 \n" " scd %0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else if (cpu_has_llsc) { unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %0, %1 # atomic64_sub \n" " subu %0, %2 \n" " scd %0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else { @@ -441,12 +469,14 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %1, %2 # atomic64_add_return \n" " addu %0, %1, %3 \n" " scd %0, %2 \n" " beqzl %0, 1b \n" " addu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -454,12 +484,14 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %1, %2 # atomic64_add_return \n" " addu %0, %1, %3 \n" " scd %0, %2 \n" " beqz %0, 1b \n" " addu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -484,12 +516,14 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %1, %2 # atomic64_sub_return \n" " subu %0, %1, %3 \n" " scd %0, %2 \n" " beqzl %0, 1b \n" " subu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -497,12 +531,14 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %1, %2 # atomic64_sub_return \n" " subu %0, %1, %3 \n" " scd %0, %2 \n" " beqz %0, 1b \n" " subu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -534,6 +570,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %1, %2 # atomic64_sub_if_positive\n" " dsubu %0, %1, %3 \n" " bltz %0, 1f \n" @@ -541,6 +578,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) " beqzl %0, 1b \n" " sync \n" "1: \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -548,6 +586,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %1, %2 # atomic64_sub_if_positive\n" " dsubu %0, %1, %3 \n" " bltz %0, 1f \n" @@ -555,6 +594,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) " beqz %0, 1b \n" " sync \n" "1: \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index eb8d79dba11c..5496f9064a6a 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -12,20 +12,21 @@ #include <linux/config.h> #include <linux/compiler.h> #include <linux/types.h> +#include <asm/bug.h> #include <asm/byteorder.h> /* sigh ... */ #include <asm/cpu-features.h> #if (_MIPS_SZLONG == 32) #define SZLONG_LOG 5 #define SZLONG_MASK 31UL -#define __LL "ll " -#define __SC "sc " +#define __LL "ll " +#define __SC "sc " #define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) #elif (_MIPS_SZLONG == 64) #define SZLONG_LOG 6 #define SZLONG_MASK 63UL -#define __LL "lld " -#define __SC "scd " +#define __LL "lld " +#define __SC "scd " #define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) #endif @@ -72,18 +73,22 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( + " .set mips3 \n" "1: " __LL "%0, %1 # set_bit \n" " or %0, %2 \n" - " "__SC "%0, %1 \n" + " " __SC "%0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); } else if (cpu_has_llsc) { __asm__ __volatile__( + " .set mips3 \n" "1: " __LL "%0, %1 # set_bit \n" " or %0, %2 \n" - " "__SC "%0, %1 \n" + " " __SC "%0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); } else { @@ -132,18 +137,22 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( + " .set mips3 \n" "1: " __LL "%0, %1 # clear_bit \n" " and %0, %2 \n" " " __SC "%0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); } else if (cpu_has_llsc) { __asm__ __volatile__( + " .set mips3 \n" "1: " __LL "%0, %1 # clear_bit \n" " and %0, %2 \n" " " __SC "%0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); } else { @@ -191,10 +200,12 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: " __LL "%0, %1 # change_bit \n" " xor %0, %2 \n" - " "__SC "%0, %1 \n" + " " __SC "%0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); } else if (cpu_has_llsc) { @@ -202,10 +213,12 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: " __LL "%0, %1 # change_bit \n" " xor %0, %2 \n" - " "__SC "%0, %1 \n" + " " __SC "%0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); } else { @@ -253,14 +266,16 @@ static inline int test_and_set_bit(unsigned long nr, unsigned long temp, res; __asm__ __volatile__( + " .set mips3 \n" "1: " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" " beqzl %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP - "sync \n" + " sync \n" #endif + " .set mips0 \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -271,16 +286,18 @@ static inline int test_and_set_bit(unsigned long nr, unsigned long temp, res; __asm__ __volatile__( - " .set noreorder # test_and_set_bit \n" - "1: " __LL "%0, %1 \n" + " .set push \n" + " .set noreorder \n" + " .set mips3 \n" + "1: " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" " beqz %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP - "sync \n" + " sync \n" #endif - ".set\treorder" + " .set pop \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -343,15 +360,17 @@ static inline int test_and_clear_bit(unsigned long nr, unsigned long temp, res; __asm__ __volatile__( + " .set mips3 \n" "1: " __LL "%0, %1 # test_and_clear_bit \n" " or %2, %0, %3 \n" " xor %2, %3 \n" - __SC "%2, %1 \n" + " " __SC "%2, %1 \n" " beqzl %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP " sync \n" #endif + " .set mips0 \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -362,17 +381,19 @@ static inline int test_and_clear_bit(unsigned long nr, unsigned long temp, res; __asm__ __volatile__( - " .set noreorder # test_and_clear_bit \n" - "1: " __LL "%0, %1 \n" + " .set push \n" + " .set noreorder \n" + " .set mips3 \n" + "1: " __LL "%0, %1 # test_and_clear_bit \n" " or %2, %0, %3 \n" " xor %2, %3 \n" - __SC "%2, %1 \n" + " " __SC "%2, %1 \n" " beqz %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP " sync \n" #endif - " .set reorder \n" + " .set pop \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -435,14 +456,16 @@ static inline int test_and_change_bit(unsigned long nr, unsigned long temp, res; __asm__ __volatile__( - "1: " __LL " %0, %1 # test_and_change_bit \n" + " .set mips3 \n" + "1: " __LL "%0, %1 # test_and_change_bit \n" " xor %2, %0, %3 \n" - " "__SC "%2, %1 \n" + " " __SC "%2, %1 \n" " beqzl %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP " sync \n" #endif + " .set mips0 \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -453,16 +476,18 @@ static inline int test_and_change_bit(unsigned long nr, unsigned long temp, res; __asm__ __volatile__( - " .set noreorder # test_and_change_bit \n" - "1: " __LL " %0, %1 \n" + " .set push \n" + " .set noreorder \n" + " .set mips3 \n" + "1: " __LL "%0, %1 # test_and_change_bit \n" " xor %2, %0, %3 \n" - " "__SC "\t%2, %1 \n" + " " __SC "\t%2, %1 \n" " beqz %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP " sync \n" #endif - " .set reorder \n" + " .set pop \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -523,22 +548,60 @@ static inline int test_bit(unsigned long nr, const volatile unsigned long *addr) } /* - * ffz - find first zero in word. + * Return the bit position (0..63) of the most significant 1 bit in a word + * Returns -1 if no 1 bit exists + */ +static inline int __ilog2(unsigned long x) +{ + int lz; + + if (sizeof(x) == 4) { + __asm__ ( + " .set push \n" + " .set mips32 \n" + " clz %0, %1 \n" + " .set pop \n" + : "=r" (lz) + : "r" (x)); + + return 31 - lz; + } + + BUG_ON(sizeof(x) != 8); + + __asm__ ( + " .set push \n" + " .set mips64 \n" + " dclz %0, %1 \n" + " .set pop \n" + : "=r" (lz) + : "r" (x)); + + return 63 - lz; +} + +/* + * __ffs - find first bit in word. * @word: The word to search * - * Undefined if no zero exists, so code should check against ~0UL first. + * Returns 0..SZLONG-1 + * Undefined if no bit exists, so code should check against 0 first. */ -static inline unsigned long ffz(unsigned long word) +static inline unsigned long __ffs(unsigned long word) { +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) + return __ilog2(word & -word); +#else int b = 0, s; - word = ~word; #ifdef CONFIG_32BIT s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s; s = 8; if (word << 24 != 0) s = 0; b += s; word >>= s; s = 4; if (word << 28 != 0) s = 0; b += s; word >>= s; s = 2; if (word << 30 != 0) s = 0; b += s; word >>= s; s = 1; if (word << 31 != 0) s = 0; b += s; + + return b; #endif #ifdef CONFIG_64BIT s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s; @@ -547,27 +610,92 @@ static inline unsigned long ffz(unsigned long word) s = 4; if (word << 60 != 0) s = 0; b += s; word >>= s; s = 2; if (word << 62 != 0) s = 0; b += s; word >>= s; s = 1; if (word << 63 != 0) s = 0; b += s; -#endif return b; +#endif +#endif } /* - * __ffs - find first bit in word. + * ffs - find first bit set. * @word: The word to search * - * Undefined if no bit exists, so code should check against 0 first. + * Returns 1..SZLONG + * Returns 0 if no bit exists */ -static inline unsigned long __ffs(unsigned long word) + +static inline unsigned long ffs(unsigned long word) { - return ffz(~word); + if (!word) + return 0; + + return __ffs(word) + 1; } /* - * fls: find last bit set. + * ffz - find first zero in word. + * @word: The word to search + * + * Undefined if no zero exists, so code should check against ~0UL first. + */ +static inline unsigned long ffz(unsigned long word) +{ + return __ffs (~word); +} + +/* + * flz - find last zero in word. + * @word: The word to search + * + * Returns 0..SZLONG-1 + * Undefined if no zero exists, so code should check against ~0UL first. + */ +static inline unsigned long flz(unsigned long word) +{ +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) + return __ilog2(~word); +#else +#ifdef CONFIG_32BIT + int r = 31, s; + word = ~word; + s = 16; if ((word & 0xffff0000)) s = 0; r -= s; word <<= s; + s = 8; if ((word & 0xff000000)) s = 0; r -= s; word <<= s; + s = 4; if ((word & 0xf0000000)) s = 0; r -= s; word <<= s; + s = 2; if ((word & 0xc0000000)) s = 0; r -= s; word <<= s; + s = 1; if ((word & 0x80000000)) s = 0; r -= s; + + return r; +#endif +#ifdef CONFIG_64BIT + int r = 63, s; + word = ~word; + s = 32; if ((word & 0xffffffff00000000UL)) s = 0; r -= s; word <<= s; + s = 16; if ((word & 0xffff000000000000UL)) s = 0; r -= s; word <<= s; + s = 8; if ((word & 0xff00000000000000UL)) s = 0; r -= s; word <<= s; + s = 4; if ((word & 0xf000000000000000UL)) s = 0; r -= s; word <<= s; + s = 2; if ((word & 0xc000000000000000UL)) s = 0; r -= s; word <<= s; + s = 1; if ((word & 0x8000000000000000UL)) s = 0; r -= s; + + return r; +#endif +#endif +} + +/* + * fls - find last bit set. + * @word: The word to search + * + * Returns 1..SZLONG + * Returns 0 if no bit exists */ +static inline unsigned long fls(unsigned long word) +{ + if (word == 0) + return 0; + + return flz(~word) + 1; +} -#define fls(x) generic_fls(x) /* * find_next_zero_bit - find the first zero bit in a memory region @@ -704,17 +832,6 @@ static inline int sched_find_first_bit(const unsigned long *b) } /* - * ffs - find first bit set - * @x: the word to search - * - * This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ - -#define ffs(x) generic_ffs(x) - -/* * hweightN - returns the hamming weight of a N-bit word * @x: the word to weigh * diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index b1e57d783604..14fc88f27226 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -77,6 +77,7 @@ #define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */ #define MACH_SGI_IP28 2 /* Indigo2 Impact */ #define MACH_SGI_IP32 3 /* O2 */ +#define MACH_SGI_IP30 4 /* Octane, Octane2 */ /* * Valid machtype for group COBALT @@ -136,6 +137,7 @@ #define MACH_GROUP_PHILIPS 14 #define MACH_PHILIPS_NINO 0 /* Nino */ #define MACH_PHILIPS_VELO 1 /* Velo */ +#define MACH_PHILIPS_JBS 2 /* JBS */ /* * Valid machtype for group Globespan @@ -159,6 +161,7 @@ #define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */ #define MACH_TOSHIBA_RBTX4927 4 #define MACH_TOSHIBA_RBTX4937 5 +#define MACH_TOSHIBA_RBTX4938 6 #define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \ "RBTX4927", "RBTX4937" } @@ -177,6 +180,8 @@ #define MACH_MTX1 7 /* 4G MTX-1 Au1500-based board */ #define MACH_PB1550 8 /* Au1550-based eval board */ #define MACH_DB1550 9 /* Au1550-based eval board */ +#define MACH_PB1200 10 /* Au1200-based eval board */ +#define MACH_DB1200 11 /* Au1200-based eval board */ /* * Valid machtype for group NEC_VR41XX diff --git a/include/asm-mips/break.h b/include/asm-mips/break.h index 2e6de788f207..25b980c91e7e 100644 --- a/include/asm-mips/break.h +++ b/include/asm-mips/break.h @@ -28,6 +28,7 @@ #define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ #define BRK_BUG 512 /* Used by BUG() */ +#define BRK_KDB 513 /* Used in KDB_ENTER() */ #define BRK_MULOVF 1023 /* Multiply overflow */ #endif /* __ASM_BREAK_H */ diff --git a/include/asm-mips/bug.h b/include/asm-mips/bug.h index 3f594b440abc..87d49a5bdc63 100644 --- a/include/asm-mips/bug.h +++ b/include/asm-mips/bug.h @@ -1,16 +1,21 @@ #ifndef __ASM_BUG_H #define __ASM_BUG_H -#include <asm/break.h> +#include <linux/config.h> #ifdef CONFIG_BUG -#define HAVE_ARCH_BUG + +#include <asm/break.h> + #define BUG() \ do { \ __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); \ } while (0) + +#define HAVE_ARCH_BUG + #endif #include <asm-generic/bug.h> -#endif +#endif /* __ASM_BUG_H */ diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h index b14b961c2100..cb2ea7c15c7a 100644 --- a/include/asm-mips/bugs.h +++ b/include/asm-mips/bugs.h @@ -8,12 +8,18 @@ #define _ASM_BUGS_H #include <linux/config.h> +#include <linux/delay.h> +#include <asm/cpu.h> +#include <asm/cpu-info.h> extern void check_bugs32(void); extern void check_bugs64(void); static inline void check_bugs(void) { + unsigned int cpu = smp_processor_id(); + + cpu_data[cpu].udelay_val = loops_per_jiffy; check_bugs32(); #ifdef CONFIG_64BIT check_bugs64(); diff --git a/include/asm-mips/cache.h b/include/asm-mips/cache.h index 4517bdf20953..1a5d1a669db3 100644 --- a/include/asm-mips/cache.h +++ b/include/asm-mips/cache.h @@ -10,6 +10,7 @@ #define _ASM_CACHE_H #include <linux/config.h> +#include <kmalloc.h> #define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) @@ -18,6 +19,4 @@ #define SMP_CACHE_SHIFT L1_CACHE_SHIFT #define SMP_CACHE_BYTES L1_CACHE_BYTES -#define ARCH_KMALLOC_MINALIGN 8 - #endif /* _ASM_CACHE_H */ diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h index 635f1bfb403e..a18ba2edc0b6 100644 --- a/include/asm-mips/cacheflush.h +++ b/include/asm-mips/cacheflush.h @@ -49,17 +49,29 @@ static inline void flush_dcache_page(struct page *page) extern void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); -extern void (*flush_icache_range)(unsigned long start, unsigned long end); +extern void (*flush_icache_range)(unsigned long __user start, + unsigned long __user end); #define flush_cache_vmap(start, end) flush_cache_all() #define flush_cache_vunmap(start, end) flush_cache_all() -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ -do { \ - memcpy(dst, (void *) src, len); \ - flush_icache_page(vma, page); \ -} while (0) -#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) +static inline void copy_to_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, void *dst, const void *src, + unsigned long len) +{ + if (cpu_has_dc_aliases) + flush_cache_page(vma, vaddr, page_to_pfn(page)); + memcpy(dst, src, len); + flush_icache_page(vma, page); +} + +static inline void copy_from_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, void *dst, const void *src, + unsigned long len) +{ + if (cpu_has_dc_aliases) + flush_cache_page(vma, vaddr, page_to_pfn(page)); + memcpy(dst, src, len); +} extern void (*flush_cache_sigtramp)(unsigned long addr); extern void (*flush_icache_all)(void); @@ -78,4 +90,7 @@ extern void (*flush_data_cache_page)(unsigned long addr); #define ClearPageDcacheDirty(page) \ clear_bit(PG_dcache_dirty, &(page)->flags) +/* Run kernel code uncached, useful for cache probing functions. */ +unsigned long __init run_uncached(void *func); + #endif /* _ASM_CACHEFLUSH_H */ diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h index c1ea5a8714f3..b09f8971e95d 100644 --- a/include/asm-mips/checksum.h +++ b/include/asm-mips/checksum.h @@ -34,8 +34,9 @@ unsigned int csum_partial(const unsigned char *buff, int len, unsigned int sum); * this is a new version of the above that records errors it finds in *errp, * but continues and zeros the rest of the buffer. */ -unsigned int csum_partial_copy_from_user(const unsigned char *src, unsigned char *dst, int len, - unsigned int sum, int *errp); +unsigned int csum_partial_copy_from_user(const unsigned char __user *src, + unsigned char *dst, int len, + unsigned int sum, int *errp); /* * Copy and checksum to user @@ -70,14 +71,15 @@ unsigned int csum_partial_copy_nocheck(const unsigned char *src, unsigned char * static inline unsigned short int csum_fold(unsigned int sum) { __asm__( - ".set\tnoat\t\t\t# csum_fold\n\t" - "sll\t$1,%0,16\n\t" - "addu\t%0,$1\n\t" - "sltu\t$1,%0,$1\n\t" - "srl\t%0,%0,16\n\t" - "addu\t%0,$1\n\t" - "xori\t%0,0xffff\n\t" - ".set\tat" + " .set push # csum_fold\n" + " .set noat \n" + " sll $1, %0, 16 \n" + " addu %0, $1 \n" + " sltu $1, %0, $1 \n" + " srl %0, %0, 16 \n" + " addu %0, $1 \n" + " xori %0, 0xffff \n" + " .set pop" : "=r" (sum) : "0" (sum)); @@ -127,29 +129,30 @@ static inline unsigned int csum_tcpudp_nofold(unsigned long saddr, unsigned int sum) { __asm__( - ".set\tnoat\t\t\t# csum_tcpudp_nofold\n\t" + " .set push # csum_tcpudp_nofold\n" + " .set noat \n" #ifdef CONFIG_32BIT - "addu\t%0, %2\n\t" - "sltu\t$1, %0, %2\n\t" - "addu\t%0, $1\n\t" + " addu %0, %2 \n" + " sltu $1, %0, %2 \n" + " addu %0, $1 \n" - "addu\t%0, %3\n\t" - "sltu\t$1, %0, %3\n\t" - "addu\t%0, $1\n\t" + " addu %0, %3 \n" + " sltu $1, %0, %3 \n" + " addu %0, $1 \n" - "addu\t%0, %4\n\t" - "sltu\t$1, %0, %4\n\t" - "addu\t%0, $1\n\t" + " addu %0, %4 \n" + " sltu $1, %0, %4 \n" + " addu %0, $1 \n" #endif #ifdef CONFIG_64BIT - "daddu\t%0, %2\n\t" - "daddu\t%0, %3\n\t" - "daddu\t%0, %4\n\t" - "dsll32\t$1, %0, 0\n\t" - "daddu\t%0, $1\n\t" - "dsrl32\t%0, %0, 0\n\t" + " daddu %0, %2 \n" + " daddu %0, %3 \n" + " daddu %0, %4 \n" + " dsll32 $1, %0, 0 \n" + " daddu %0, $1 \n" + " dsra32 %0, %0, 0 \n" #endif - ".set\tat" + " .set pop" : "=r" (sum) : "0" (daddr), "r"(saddr), #ifdef __MIPSEL__ @@ -192,57 +195,57 @@ static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr, unsigned int sum) { __asm__( - ".set\tpush\t\t\t# csum_ipv6_magic\n\t" - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "addu\t%0, %5\t\t\t# proto (long in network byte order)\n\t" - "sltu\t$1, %0, %5\n\t" - "addu\t%0, $1\n\t" - - "addu\t%0, %6\t\t\t# csum\n\t" - "sltu\t$1, %0, %6\n\t" - "lw\t%1, 0(%2)\t\t\t# four words source address\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "lw\t%1, 4(%2)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "lw\t%1, 8(%2)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "lw\t%1, 12(%2)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "lw\t%1, 0(%3)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "lw\t%1, 4(%3)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "lw\t%1, 8(%3)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "lw\t%1, 12(%3)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "addu\t%0, $1\t\t\t# Add final carry\n\t" - ".set\tpop" + " .set push # csum_ipv6_magic\n" + " .set noreorder \n" + " .set noat \n" + " addu %0, %5 # proto (long in network byte order)\n" + " sltu $1, %0, %5 \n" + " addu %0, $1 \n" + + " addu %0, %6 # csum\n" + " sltu $1, %0, %6 \n" + " lw %1, 0(%2) # four words source address\n" + " addu %0, $1 \n" + " addu %0, %1 \n" + " sltu $1, %0, %1 \n" + + " lw %1, 4(%2) \n" + " addu %0, $1 \n" + " addu %0, %1 \n" + " sltu $1, %0, %1 \n" + + " lw %1, 8(%2) \n" + " addu %0, $1 \n" + " addu %0, %1 \n" + " sltu $1, %0, %1 \n" + + " lw %1, 12(%2) \n" + " addu %0, $1 \n" + " addu %0, %1 \n" + " sltu $1, %0, %1 \n" + + " lw %1, 0(%3) \n" + " addu %0, $1 \n" + " addu %0, %1 \n" + " sltu $1, %0, %1 \n" + + " lw %1, 4(%3) \n" + " addu %0, $1 \n" + " addu %0, %1 \n" + " sltu $1, %0, %1 \n" + + " lw %1, 8(%3) \n" + " addu %0, $1 \n" + " addu %0, %1 \n" + " sltu $1, %0, %1 \n" + + " lw %1, 12(%3) \n" + " addu %0, $1 \n" + " addu %0, %1 \n" + " sltu $1, %0, %1 \n" + + " addu %0, $1 # Add final carry\n" + " .set pop" : "=r" (sum), "=r" (proto) : "r" (saddr), "r" (daddr), "0" (htonl(len)), "1" (htonl(proto)), "r" (sum)); diff --git a/include/asm-mips/cobalt/cobalt.h b/include/asm-mips/cobalt/cobalt.h index ca1fbc0579fe..78e1df2095fb 100644 --- a/include/asm-mips/cobalt/cobalt.h +++ b/include/asm-mips/cobalt/cobalt.h @@ -19,18 +19,23 @@ * 9 - PCI * 14 - IDE0 * 15 - IDE1 - * + */ +#define COBALT_QUBE_SLOT_IRQ 9 + +/* * CPU IRQs are 16 ... 23 */ -#define COBALT_TIMER_IRQ 18 -#define COBALT_SCC_IRQ 19 /* pre-production has 85C30 */ -#define COBALT_RAQ_SCSI_IRQ 19 -#define COBALT_ETH0_IRQ 19 -#define COBALT_ETH1_IRQ 20 -#define COBALT_SERIAL_IRQ 21 -#define COBALT_SCSI_IRQ 21 -#define COBALT_VIA_IRQ 22 /* Chained to VIA ISA bridge */ -#define COBALT_QUBE_SLOT_IRQ 23 +#define COBALT_CPU_IRQ 16 + +#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) +#define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */ +#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3) +#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3) +#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4) +#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4) +#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5) +#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5) +#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */ /* * PCI configuration space manifest constants. These are wired into @@ -69,16 +74,21 @@ * Most of this really should go into a separate GT64111 header file. */ #define GT64111_IO_BASE 0x10000000UL +#define GT64111_IO_END 0x11ffffffUL +#define GT64111_MEM_BASE 0x12000000UL +#define GT64111_MEM_END 0x13ffffffUL #define GT64111_BASE 0x14000000UL -#define GALILEO_REG(ofs) (KSEG0 + GT64111_BASE + (unsigned long)(ofs)) +#define GALILEO_REG(ofs) CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs)) #define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port)) #define GALILEO_OUTL(val, port) \ do { \ - *(volatile unsigned int *) GALILEO_REG(port) = (port); \ + *(volatile unsigned int *) GALILEO_REG(port) = (val); \ } while (0) -#define GALILEO_T0EXP 0x0100 +#define GALILEO_INTR_T0EXP (1 << 8) +#define GALILEO_INTR_RETRY_CTR (1 << 20) + #define GALILEO_ENTC0 0x01 #define GALILEO_SELTC0 0x02 @@ -86,5 +96,21 @@ do { \ GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \ (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS) +#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) +# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ +# define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */ +# define COBALT_LED_WEB (1 << 2) /* RaQ */ +# define COBALT_LED_POWER_OFF (1 << 3) /* RaQ */ +# define COBALT_LED_RESET 0x0f + +#define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK) +# define COBALT_KEY_CLEAR (1 << 1) +# define COBALT_KEY_LEFT (1 << 2) +# define COBALT_KEY_UP (1 << 3) +# define COBALT_KEY_DOWN (1 << 4) +# define COBALT_KEY_RIGHT (1 << 5) +# define COBALT_KEY_ENTER (1 << 6) +# define COBALT_KEY_SELECT (1 << 7) +# define COBALT_KEY_MASK 0xfe #endif /* __ASM_COBALT_H */ diff --git a/include/asm-mips/cobalt/mach-gt64120.h b/include/asm-mips/cobalt/mach-gt64120.h new file mode 100644 index 000000000000..587fc4378f44 --- /dev/null +++ b/include/asm-mips/cobalt/mach-gt64120.h @@ -0,0 +1 @@ +/* there's something here ... in the dark */ diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h index 2c084cd4bc0a..35d2604fe69c 100644 --- a/include/asm-mips/compat.h +++ b/include/asm-mips/compat.h @@ -15,10 +15,10 @@ typedef s32 compat_clock_t; typedef s32 compat_suseconds_t; typedef s32 compat_pid_t; -typedef u32 __compat_uid_t; -typedef u32 __compat_gid_t; -typedef u32 __compat_uid32_t; -typedef u32 __compat_gid32_t; +typedef s32 __compat_uid_t; +typedef s32 __compat_gid_t; +typedef __compat_uid_t __compat_uid32_t; +typedef __compat_gid_t __compat_gid32_t; typedef u32 compat_mode_t; typedef u32 compat_ino_t; typedef u32 compat_dev_t; @@ -54,8 +54,8 @@ struct compat_stat { compat_ino_t st_ino; compat_mode_t st_mode; compat_nlink_t st_nlink; - __compat_uid32_t st_uid; - __compat_gid32_t st_gid; + __compat_uid_t st_uid; + __compat_gid_t st_gid; compat_dev_t st_rdev; s32 st_pad2[2]; compat_off_t st_size; diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 9a2de642eee6..03627cfb3e45 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -4,6 +4,7 @@ * for more details. * * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki */ #ifndef __ASM_CPU_FEATURES_H #define __ASM_CPU_FEATURES_H @@ -24,8 +25,19 @@ #ifndef cpu_has_4kex #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) #endif -#ifndef cpu_has_4ktlb -#define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB) +#ifndef cpu_has_3k_cache +#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE) +#endif +#define cpu_has_6k_cache 0 +#define cpu_has_8k_cache 0 +#ifndef cpu_has_4k_cache +#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE) +#endif +#ifndef cpu_has_tx39_cache +#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) +#endif +#ifndef cpu_has_sb1_cache +#define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE) #endif #ifndef cpu_has_fpu #define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU) @@ -39,9 +51,6 @@ #ifndef cpu_has_watch #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) #endif -#ifndef cpu_has_mips16 -#define cpu_has_mips16 (cpu_data[0].options & MIPS_CPU_MIPS16) -#endif #ifndef cpu_has_divec #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) #endif @@ -66,6 +75,18 @@ #ifndef cpu_has_llsc #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) #endif +#ifndef cpu_has_mips16 +#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) +#endif +#ifndef cpu_has_mdmx +#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) +#endif +#ifndef cpu_has_mips3d +#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) +#endif +#ifndef cpu_has_smartmips +#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) +#endif #ifndef cpu_has_vtag_icache #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) #endif @@ -95,15 +116,16 @@ #endif #endif -/* - * Certain CPUs may throw bizarre exceptions if not the whole cacheline - * contains valid instructions. For these we ensure proper alignment of - * signal trampolines and pad them to the size of a full cache lines with - * nops. This is also used in structure definitions so can't be a test macro - * like the others. - */ -#ifndef PLAT_TRAMPOLINE_STUFF_LINE -#define PLAT_TRAMPOLINE_STUFF_LINE 0UL +#ifndef cpu_has_dsp +#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) +#endif + +#ifdef CONFIG_MIPS_MT +#ifndef cpu_has_mipsmt +# define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) +#endif +#else +# define cpu_has_mipsmt 0 #endif #ifdef CONFIG_32BIT @@ -142,6 +164,22 @@ # endif #endif +#ifdef CONFIG_CPU_MIPSR2 +# if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) +# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) +# else +# define cpu_has_vint 0 +# endif +# if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) +# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) +# else +# define cpu_has_veic 0 +# endif +#else +# define cpu_has_vint 0 +# define cpu_has_veic 0 +#endif + #ifndef cpu_has_subset_pcaches #define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES) #endif diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h index 20a35b15a31d..d5cf519f8fcc 100644 --- a/include/asm-mips/cpu-info.h +++ b/include/asm-mips/cpu-info.h @@ -7,6 +7,7 @@ * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle * Copyright (C) 1996 Paul M. Antoine * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 2004 Maciej W. Rozycki */ #ifndef __ASM_CPU_INFO_H #define __ASM_CPU_INFO_H @@ -61,6 +62,7 @@ struct cpuinfo_mips { * Capability and feature descriptor structure for MIPS CPU */ unsigned long options; + unsigned long ases; unsigned int processor_id; unsigned int fpu_id; unsigned int cputype; diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index dec060b49556..48eac296060f 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -3,6 +3,7 @@ * various MIPS cpu types. * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 2004 Maciej W. Rozycki */ #ifndef _ASM_CPU_H #define _ASM_CPU_H @@ -22,12 +23,17 @@ spec. */ -#define PRID_COMP_LEGACY 0x000000 -#define PRID_COMP_MIPS 0x010000 -#define PRID_COMP_BROADCOM 0x020000 -#define PRID_COMP_ALCHEMY 0x030000 -#define PRID_COMP_SIBYTE 0x040000 -#define PRID_COMP_SANDCRAFT 0x050000 +#define PRID_COMP_LEGACY 0x000000 +#define PRID_COMP_MIPS 0x010000 +#define PRID_COMP_BROADCOM 0x020000 +#define PRID_COMP_ALCHEMY 0x030000 +#define PRID_COMP_SIBYTE 0x040000 +#define PRID_COMP_SANDCRAFT 0x050000 +#define PRID_COMP_PHILIPS 0x060000 +#define PRID_COMP_TOSHIBA 0x070000 +#define PRID_COMP_LSI 0x080000 +#define PRID_COMP_LEXRA 0x0b0000 + /* * Assigned values for the product ID register. In order to detect a @@ -46,6 +52,7 @@ #define PRID_IMP_VR41XX 0x0c00 #define PRID_IMP_R12000 0x0e00 #define PRID_IMP_R8000 0x1000 +#define PRID_IMP_PR4450 0x1200 #define PRID_IMP_R4600 0x2000 #define PRID_IMP_R4700 0x2100 #define PRID_IMP_TX39 0x2200 @@ -60,6 +67,13 @@ #define PRID_IMP_RM9000 0x3400 #define PRID_IMP_R5432 0x5400 #define PRID_IMP_R5500 0x5500 + +#define PRID_IMP_UNKNOWN 0xff00 + +/* + * These are the PRID's for when 23:16 == PRID_COMP_MIPS + */ + #define PRID_IMP_4KC 0x8000 #define PRID_IMP_5KC 0x8100 #define PRID_IMP_20KC 0x8200 @@ -71,14 +85,15 @@ #define PRID_IMP_4KEMPR2 0x9100 #define PRID_IMP_4KSD 0x9200 #define PRID_IMP_24K 0x9300 - -#define PRID_IMP_UNKNOWN 0xff00 +#define PRID_IMP_34K 0x9500 +#define PRID_IMP_24KE 0x9600 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE */ #define PRID_IMP_SB1 0x0100 +#define PRID_IMP_SB1A 0x1100 /* * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT @@ -177,7 +192,11 @@ #define CPU_VR4133 56 #define CPU_AU1550 57 #define CPU_24K 58 -#define CPU_LAST 58 +#define CPU_AU1200 59 +#define CPU_34K 60 +#define CPU_PR4450 61 +#define CPU_SB1A 62 +#define CPU_LAST 62 /* * ISA Level encodings @@ -200,23 +219,37 @@ * CPU Option encodings */ #define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ -/* Leave a spare bit for variant MMU types... */ -#define MIPS_CPU_4KEX 0x00000004 /* "R4K" exception model */ -#define MIPS_CPU_4KTLB 0x00000008 /* "R4K" TLB handler */ -#define MIPS_CPU_FPU 0x00000010 /* CPU has FPU */ -#define MIPS_CPU_32FPR 0x00000020 /* 32 dbl. prec. FP registers */ -#define MIPS_CPU_COUNTER 0x00000040 /* Cycle count/compare */ -#define MIPS_CPU_WATCH 0x00000080 /* watchpoint registers */ -#define MIPS_CPU_MIPS16 0x00000100 /* code compression */ -#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ -#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ -#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ -#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ -#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ -#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ -#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ -#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ -#define MIPS_CPU_SUBSET_CACHES 0x00020000 /* P-cache subset enforced */ -#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ +#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */ +#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ +#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ +#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ +#define MIPS_CPU_SB1_CACHE 0x00000020 /* SB1-style caches */ +#define MIPS_CPU_FPU 0x00000040 /* CPU has FPU */ +#define MIPS_CPU_32FPR 0x00000080 /* 32 dbl. prec. FP registers */ +#define MIPS_CPU_COUNTER 0x00000100 /* Cycle count/compare */ +#define MIPS_CPU_WATCH 0x00000200 /* watchpoint registers */ +#define MIPS_CPU_DIVEC 0x00000400 /* dedicated interrupt vector */ +#define MIPS_CPU_VCE 0x00000800 /* virt. coherence conflict possible */ +#define MIPS_CPU_CACHE_CDEX_P 0x00001000 /* Create_Dirty_Exclusive CACHE op */ +#define MIPS_CPU_CACHE_CDEX_S 0x00002000 /* ... same for seconary cache ... */ +#define MIPS_CPU_MCHECK 0x00004000 /* Machine check exception */ +#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ +#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ +#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ +#define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */ +#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ +#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ +#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ + +/* + * CPU ASE encodings + */ +#define MIPS_ASE_MIPS16 0x00000001 /* code compression */ +#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ +#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ +#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ +#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ +#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ + #endif /* _ASM_CPU_H */ diff --git a/include/asm-mips/dec/ecc.h b/include/asm-mips/dec/ecc.h index 724908b0bf13..19495a490e72 100644 --- a/include/asm-mips/dec/ecc.h +++ b/include/asm-mips/dec/ecc.h @@ -49,7 +49,8 @@ struct pt_regs; extern void dec_ecc_be_init(void); extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup); -extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs); +extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, + struct pt_regs *regs); #endif #endif /* __ASM_MIPS_DEC_ECC_H */ diff --git a/include/asm-mips/dec/ioasic_addrs.h b/include/asm-mips/dec/ioasic_addrs.h index 5e18a7510592..4cbc1f8a1129 100644 --- a/include/asm-mips/dec/ioasic_addrs.h +++ b/include/asm-mips/dec/ioasic_addrs.h @@ -45,7 +45,8 @@ /* - * Offsets for I/O ASIC registers (relative to (system_base + IOASIC_IOCTL)). + * Offsets for I/O ASIC registers + * (relative to (dec_kn_slot_base + IOASIC_IOCTL)). */ /* all systems */ #define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */ diff --git a/include/asm-mips/dec/kn01.h b/include/asm-mips/dec/kn01.h index 946943502f83..eb522aa1e226 100644 --- a/include/asm-mips/dec/kn01.h +++ b/include/asm-mips/dec/kn01.h @@ -8,14 +8,12 @@ * * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions * are by courtesy of Chris Fraser. - * Copyright (C) 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki */ #ifndef __ASM_MIPS_DEC_KN01_H #define __ASM_MIPS_DEC_KN01_H -#include <asm/addrspace.h> - -#define KN01_SLOT_BASE KSEG1ADDR(0x10000000) +#define KN01_SLOT_BASE 0x10000000 #define KN01_SLOT_SIZE 0x01000000 /* @@ -41,17 +39,9 @@ /* - * Some port addresses... - */ -#define KN01_LANCE_BASE (KN01_SLOT_BASE + KN01_LANCE) /* 0xB8000000 */ -#define KN01_DZ11_BASE (KN01_SLOT_BASE + KN01_DZ11) /* 0xBC000000 */ -#define KN01_RTC_BASE (KN01_SLOT_BASE + KN01_RTC) /* 0xBD000000 */ - - -/* * Frame buffer memory address. */ -#define KN01_VFB_MEM KSEG1ADDR(0x0fc00000) +#define KN01_VFB_MEM 0x0fc00000 /* * CPU interrupt bits. @@ -80,4 +70,22 @@ #define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */ #define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ + +#ifndef __ASSEMBLY__ + +#include <linux/interrupt.h> +#include <linux/spinlock.h> +#include <linux/types.h> + +struct pt_regs; + +extern u16 cached_kn01_csr; +extern spinlock_t kn01_lock; + +extern void dec_kn01_be_init(void); +extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup); +extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id, + struct pt_regs *regs); +#endif + #endif /* __ASM_MIPS_DEC_KN01_H */ diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h index f797f7045920..8319ad77b250 100644 --- a/include/asm-mips/dec/kn02.h +++ b/include/asm-mips/dec/kn02.h @@ -8,21 +8,12 @@ * * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions * are by courtesy of Chris Fraser. - * Copyright (C) 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki */ #ifndef __ASM_MIPS_DEC_KN02_H #define __ASM_MIPS_DEC_KN02_H -#ifndef __ASSEMBLY__ -#include <linux/spinlock.h> -#include <linux/types.h> -#endif - -#include <asm/addrspace.h> -#include <asm/dec/ecc.h> - - -#define KN02_SLOT_BASE KSEG1ADDR(0x1fc00000) +#define KN02_SLOT_BASE 0x1fc00000 #define KN02_SLOT_SIZE 0x00080000 /* @@ -39,22 +30,14 @@ /* - * Some port addresses... - */ -#define KN02_DZ11_BASE (KN02_SLOT_BASE + KN02_DZ11) /* DZ11 */ -#define KN02_RTC_BASE (KN02_SLOT_BASE + KN02_RTC) /* RTC */ -#define KN02_CSR_BASE (KN02_SLOT_BASE + KN02_CSR) /* CSR */ - - -/* * System Control & Status Register bits. */ #define KN02_CSR_RES_28 (0xf<<28) /* unused */ #define KN02_CSR_PSU (1<<27) /* power supply unit warning */ #define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */ #define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */ -#define KN03_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */ -#define KN03_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */ +#define KN02_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */ +#define KN02_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */ #define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */ #define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */ #define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */ @@ -63,8 +46,8 @@ #define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */ #define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */ #define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */ -#define KN03_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */ -#define KN03_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ +#define KN02_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */ +#define KN02_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ /* @@ -98,6 +81,10 @@ #ifndef __ASSEMBLY__ + +#include <linux/spinlock.h> +#include <linux/types.h> + extern u32 cached_kn02_csr; extern spinlock_t kn02_lock; extern void init_kn02_irqs(int base); diff --git a/include/asm-mips/dec/kn02xa.h b/include/asm-mips/dec/kn02xa.h index 648c4dcbba1d..a25f3d7da7f7 100644 --- a/include/asm-mips/dec/kn02xa.h +++ b/include/asm-mips/dec/kn02xa.h @@ -9,7 +9,7 @@ * * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions * are by courtesy of Chris Fraser. - * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki * * These are addresses which have to be known early in the boot process. * For other addresses refer to tc.h, ioasic_addrs.h and friends. @@ -17,31 +17,23 @@ #ifndef __ASM_MIPS_DEC_KN02XA_H #define __ASM_MIPS_DEC_KN02XA_H -#include <asm/addrspace.h> #include <asm/dec/ioasic_addrs.h> -#define KN02XA_SLOT_BASE KSEG1ADDR(0x1c000000) - -/* - * Some port addresses... - */ -#define KN02XA_IOASIC_BASE (KN02XA_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */ -#define KN02XA_RTC_BASE (KN02XA_SLOT_BASE + IOASIC_TOY) /* RTC */ - +#define KN02XA_SLOT_BASE 0x1c000000 /* * Memory control ASIC registers. */ -#define KN02XA_MER KSEG1ADDR(0x0c400000) /* memory error register */ -#define KN02XA_MSR KSEG1ADDR(0x0c800000) /* memory size register */ +#define KN02XA_MER 0x0c400000 /* memory error register */ +#define KN02XA_MSR 0x0c800000 /* memory size register */ /* * CPU control ASIC registers. */ -#define KN02XA_MEM_CONF KSEG1ADDR(0x0e000000) /* write timeout config */ -#define KN02XA_EAR KSEG1ADDR(0x0e000004) /* error address register */ -#define KN02XA_BOOT0 KSEG1ADDR(0x0e000008) /* boot 0 register */ -#define KN02XA_MEM_INTR KSEG1ADDR(0x0e00000c) /* write err IRQ stat & ack */ +#define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */ +#define KN02XA_EAR 0x0e000004 /* error address register */ +#define KN02XA_BOOT0 0x0e000008 /* boot 0 register */ +#define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */ /* * Memory Error Register bits, common definitions. @@ -52,8 +44,13 @@ #define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */ #define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */ #define KN02XA_MER_PARDIS (1<<14) /* parity error disable */ -#define KN02XA_MER_RES_12 (0x3<<12) /* unused */ -#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask */ +#define KN02XA_MER_SIZE (1<<13) /* r/o mirror of MSR_SIZE */ +#define KN02XA_MER_RES_12 (1<<12) /* unused */ +#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */ +#define KN02XA_MER_BYTERR_3 (0x8<<8) /* byte lane #3 */ +#define KN02XA_MER_BYTERR_2 (0x4<<8) /* byte lane #2 */ +#define KN02XA_MER_BYTERR_1 (0x2<<8) /* byte lane #1 */ +#define KN02XA_MER_BYTERR_0 (0x1<<8) /* byte lane #0 */ #define KN02XA_MER_RES_0 (0xff<<0) /* unused */ /* @@ -72,4 +69,17 @@ #define KN02XA_EAR_ADDRESS (0x7ffffff<<2) /* address involved */ #define KN02XA_EAR_RES_0 (0x3<<0) /* unused */ + +#ifndef __ASSEMBLY__ + +#include <linux/interrupt.h> + +struct pt_regs; + +extern void dec_kn02xa_be_init(void); +extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup); +extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id, + struct pt_regs *regs); +#endif + #endif /* __ASM_MIPS_DEC_KN02XA_H */ diff --git a/include/asm-mips/dec/kn03.h b/include/asm-mips/dec/kn03.h index 676abd17c6a4..edede923ffb8 100644 --- a/include/asm-mips/dec/kn03.h +++ b/include/asm-mips/dec/kn03.h @@ -10,24 +10,15 @@ * * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions * are by courtesy of Chris Fraser. - * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki */ #ifndef __ASM_MIPS_DEC_KN03_H #define __ASM_MIPS_DEC_KN03_H -#include <asm/addrspace.h> #include <asm/dec/ecc.h> #include <asm/dec/ioasic_addrs.h> -#define KN03_SLOT_BASE KSEG1ADDR(0x1f800000) - -/* - * Some port addresses... - */ -#define KN03_IOASIC_BASE (KN03_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */ -#define KN03_RTC_BASE (KN03_SLOT_BASE + IOASIC_TOY) /* RTC */ -#define KN03_MCR_BASE (KN03_SLOT_BASE + IOASIC_MCR) /* MCR */ - +#define KN03_SLOT_BASE 0x1f800000 /* * CPU interrupt bits. diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h index b120362b8f13..15fe8f881e60 100644 --- a/include/asm-mips/dec/kn05.h +++ b/include/asm-mips/dec/kn05.h @@ -1,10 +1,12 @@ /* * include/asm-mips/dec/kn05.h * - * DECstation 5000/260 (4max+ or KN05) and DECsystem 5900/260 + * DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min + * or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or + * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC * definitions. * - * Copyright (C) 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -13,8 +15,8 @@ * * WARNING! All this information is pure guesswork based on the * ROM. It is provided here in hope it will give someone some - * food for thought. No documentation for the KN05 module has - * been located so far. + * food for thought. No documentation for the KN05 nor the KN04 + * module has been located so far. */ #ifndef __ASM_MIPS_DEC_KN05_H #define __ASM_MIPS_DEC_KN05_H @@ -24,48 +26,50 @@ /* * The oncard MB (Memory Buffer) ASIC provides an additional address * decoder. Certain address ranges within the "high" 16 slots are - * passed to the I/O ASIC's decoder like with the KN03. Others are - * handled locally. "Low" slots are always passed. + * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA. + * Others are handled locally. "Low" slots are always passed. */ -#define KN05_MB_ROM (16*IOASIC_SLOT_SIZE) /* KN05 card ROM */ -#define KN05_IOCTL (17*IOASIC_SLOT_SIZE) /* I/O ASIC */ -#define KN05_ESAR (18*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ -#define KN05_LANCE (19*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ -#define KN05_MB_INT (20*IOASIC_SLOT_SIZE) /* MB interrupt register */ -#define KN05_MB_EA (21*IOASIC_SLOT_SIZE) /* MB error address? */ -#define KN05_MB_EC (22*IOASIC_SLOT_SIZE) /* MB error ??? */ -#define KN05_MB_CSR (23*IOASIC_SLOT_SIZE) /* MB control & status */ -#define KN05_RES_24 (24*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_RES_25 (25*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_RES_26 (26*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_RES_27 (27*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_SCSI (28*IOASIC_SLOT_SIZE) /* ASC SCSI */ -#define KN05_RES_29 (29*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_RES_30 (30*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_RES_31 (31*IOASIC_SLOT_SIZE) /* unused? */ +#define KN4K_SLOT_BASE 0x1fc00000 + +#define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */ +#define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */ +#define KN4K_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ +#define KN4K_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ +#define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */ +#define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */ +#define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */ +#define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */ +#define KN4K_RES_08 (8*IOASIC_SLOT_SIZE) /* unused? */ +#define KN4K_RES_09 (9*IOASIC_SLOT_SIZE) /* unused? */ +#define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */ +#define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */ +#define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ +#define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */ +#define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */ +#define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ /* * Bits for the MB interrupt register. * The register appears read-only. */ -#define KN05_MB_INT_TC (1<<0) /* TURBOchannel? */ -#define KN05_MB_INT_RTC (1<<1) /* RTC? */ -#define KN05_MB_INT_MT (1<<3) /* ??? */ +#define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */ +#define KN4K_MB_INT_RTC (1<<1) /* RTC? */ +#define KN4K_MB_INT_MT (1<<3) /* ??? */ /* * Bits for the MB control & status register. * Set to 0x00bf8001 on my system by the ROM. */ -#define KN05_MB_CSR_PF (1<<0) /* PreFetching enable? */ -#define KN05_MB_CSR_F (1<<1) /* ??? */ -#define KN05_MB_CSR_ECC (0xff<<2) /* ??? */ -#define KN05_MB_CSR_OD (1<<10) /* ??? */ -#define KN05_MB_CSR_CP (1<<11) /* ??? */ -#define KN05_MB_CSR_UNC (1<<12) /* ??? */ -#define KN05_MB_CSR_IM (1<<13) /* ??? */ -#define KN05_MB_CSR_NC (1<<14) /* ??? */ -#define KN05_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ -#define KN05_MB_CSR_MSK (0x1f<<16) /* ??? */ -#define KN05_MB_CSR_FW (1<<21) /* ??? */ +#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */ +#define KN4K_MB_CSR_F (1<<1) /* ??? */ +#define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */ +#define KN4K_MB_CSR_OD (1<<10) /* ??? */ +#define KN4K_MB_CSR_CP (1<<11) /* ??? */ +#define KN4K_MB_CSR_UNC (1<<12) /* ??? */ +#define KN4K_MB_CSR_IM (1<<13) /* ??? */ +#define KN4K_MB_CSR_NC (1<<14) /* ??? */ +#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ +#define KN4K_MB_CSR_MSK (0x1f<<16) /* ??? */ +#define KN4K_MB_CSR_FW (1<<21) /* ??? */ #endif /* __ASM_MIPS_DEC_KN05_H */ diff --git a/include/asm-mips/dec/prom.h b/include/asm-mips/dec/prom.h index a05d6d3395fe..1384dd0964b9 100644 --- a/include/asm-mips/dec/prom.h +++ b/include/asm-mips/dec/prom.h @@ -24,7 +24,7 @@ * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's. * Many of these will work for MIPSen as well! */ -#define VEC_RESET (u64 *)KSEG1ADDR(0x1fc00000) +#define VEC_RESET (u64 *)CKSEG1ADDR(0x1fc00000) /* Prom base address */ #define PMAX_PROM_ENTRY(x) (VEC_RESET + (x)) /* Prom jump table */ @@ -111,19 +111,21 @@ extern int (*__pmax_close)(int); * On MIPS64 we have to call PROM functions via a helper * dispatcher to accomodate ABI incompatibilities. */ -#define __DEC_PROM_O32 __attribute__((alias("call_o32"))) - -int _rex_bootinit(int (*)(void)) __DEC_PROM_O32; -int _rex_bootread(int (*)(void)) __DEC_PROM_O32; -int _rex_getbitmap(int (*)(memmap *), memmap *) __DEC_PROM_O32; -unsigned long *_rex_slot_address(unsigned long *(*)(int), int) __DEC_PROM_O32; -void *_rex_gettcinfo(void *(*)(void)) __DEC_PROM_O32; -int _rex_getsysid(int (*)(void)) __DEC_PROM_O32; -void _rex_clear_cache(void (*)(void)) __DEC_PROM_O32; - -int _prom_getchar(int (*)(void)) __DEC_PROM_O32; -char *_prom_getenv(char *(*)(char *), char *) __DEC_PROM_O32; -int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32; +#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \ + __asm__(#fun " = call_o32") + +int __DEC_PROM_O32(_rex_bootinit, (int (*)(void))); +int __DEC_PROM_O32(_rex_bootread, (int (*)(void))); +int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), memmap *)); +unsigned long *__DEC_PROM_O32(_rex_slot_address, + (unsigned long *(*)(int), int)); +void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void))); +int __DEC_PROM_O32(_rex_getsysid, (int (*)(void))); +void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void))); + +int __DEC_PROM_O32(_prom_getchar, (int (*)(void))); +char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), char *)); +int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), char *, ...)); #define rex_bootinit() _rex_bootinit(__rex_bootinit) diff --git a/include/asm-mips/dec/system.h b/include/asm-mips/dec/system.h new file mode 100644 index 000000000000..78af51fbc797 --- /dev/null +++ b/include/asm-mips/dec/system.h @@ -0,0 +1,18 @@ +/* + * include/asm-mips/dec/system.h + * + * Generic DECstation/DECsystem bits. + * + * Copyright (C) 2005 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef __ASM_DEC_SYSTEM_H +#define __ASM_DEC_SYSTEM_H + +extern unsigned long dec_kn_slot_base, dec_kn_slot_size; + +#endif /* __ASM_DEC_SYSTEM_H */ diff --git a/include/asm-mips/dec/tc.h b/include/asm-mips/dec/tc.h index d7bba43f863a..9cb51f24d42c 100644 --- a/include/asm-mips/dec/tc.h +++ b/include/asm-mips/dec/tc.h @@ -7,10 +7,8 @@ * * Copyright (c) 1998 Harald Koerfgen */ -#ifndef ASM_TC_H -#define ASM_TC_H - -extern unsigned long system_base; +#ifndef __ASM_DEC_TC_H +#define __ASM_DEC_TC_H /* * Search for a TURBOchannel Option Module @@ -36,8 +34,8 @@ extern unsigned long get_tc_base_addr(int); */ extern unsigned long get_tc_irq_nr(int); /* - * Return TURBOchannel clock frequency in hz + * Return TURBOchannel clock frequency in Hz */ extern unsigned long get_tc_speed(void); -#endif +#endif /* __ASM_DEC_TC_H */ diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h index a606dbee0412..85435a8d4e52 100644 --- a/include/asm-mips/delay.h +++ b/include/asm-mips/delay.h @@ -12,11 +12,9 @@ #include <linux/config.h> #include <linux/param.h> - +#include <linux/smp.h> #include <asm/compiler.h> -extern unsigned long loops_per_jiffy; - static inline void __delay(unsigned long loops) { if (sizeof(long) == 4) @@ -82,11 +80,7 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj) __delay(usecs); } -#ifdef CONFIG_SMP #define __udelay_val cpu_data[smp_processor_id()].udelay_val -#else -#define __udelay_val loops_per_jiffy -#endif #define udelay(usecs) __udelay((usecs),__udelay_val) diff --git a/include/asm-mips/dsp.h b/include/asm-mips/dsp.h new file mode 100644 index 000000000000..50f556bb4978 --- /dev/null +++ b/include/asm-mips/dsp.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2005 Mips Technologies + * Author: Chris Dearman, chris@mips.com derived from fpu.h + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef _ASM_DSP_H +#define _ASM_DSP_H + +#include <asm/cpu.h> +#include <asm/cpu-features.h> +#include <asm/hazards.h> +#include <asm/mipsregs.h> + +#define DSP_DEFAULT 0x00000000 +#define DSP_MASK 0x1f + +#define __enable_dsp_hazard() \ +do { \ + asm("_ehb"); \ +} while (0) + +static inline void __init_dsp(void) +{ + mthi1(0); + mtlo1(0); + mthi2(0); + mtlo2(0); + mthi3(0); + mtlo3(0); + wrdsp(DSP_DEFAULT, DSP_MASK); +} + +static inline void init_dsp(void) +{ + if (cpu_has_dsp) + __init_dsp(); +} + +#define __save_dsp(tsk) \ +do { \ + tsk->thread.dsp.dspr[0] = mfhi1(); \ + tsk->thread.dsp.dspr[1] = mflo1(); \ + tsk->thread.dsp.dspr[2] = mfhi2(); \ + tsk->thread.dsp.dspr[3] = mflo2(); \ + tsk->thread.dsp.dspr[4] = mfhi3(); \ + tsk->thread.dsp.dspr[5] = mflo3(); \ +} while (0) + +#define save_dsp(tsk) \ +do { \ + if (cpu_has_dsp) \ + __save_dsp(tsk); \ +} while (0) + +#define __restore_dsp(tsk) \ +do { \ + mthi1(tsk->thread.dsp.dspr[0]); \ + mtlo1(tsk->thread.dsp.dspr[1]); \ + mthi2(tsk->thread.dsp.dspr[2]); \ + mtlo2(tsk->thread.dsp.dspr[3]); \ + mthi3(tsk->thread.dsp.dspr[4]); \ + mtlo3(tsk->thread.dsp.dspr[5]); \ +} while (0) + +#define restore_dsp(tsk) \ +do { \ + if (cpu_has_dsp) \ + __restore_dsp(tsk); \ +} while (0) + +#define __get_dsp_regs(tsk) \ +({ \ + if (tsk == current) \ + __save_dsp(current); \ + \ + tsk->thread.dsp.dspr; \ +}) + +#endif /* _ASM_DSP_H */ diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h index e48811440015..7420f12742bb 100644 --- a/include/asm-mips/elf.h +++ b/include/asm-mips/elf.h @@ -2,6 +2,8 @@ * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. + * + * Much of this is taken from binutils and GNU libc ... */ #ifndef _ASM_ELF_H #define _ASM_ELF_H @@ -17,6 +19,8 @@ #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ #define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */ #define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */ +#define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32 R2 code. */ +#define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64 R2 code. */ /* The ABI of a file. */ #define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */ @@ -105,7 +109,11 @@ #define R_MIPS_LOVENDOR 100 #define R_MIPS_HIVENDOR 127 -#define SHN_MIPS_ACCOMON 0xff00 +#define SHN_MIPS_ACCOMON 0xff00 /* Allocated common symbols */ +#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ +#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ +#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ +#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ #define SHT_MIPS_LIST 0x70000000 #define SHT_MIPS_CONFLICT 0x70000002 @@ -193,50 +201,92 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #ifdef __KERNEL__ +struct mips_abi; + +extern struct mips_abi mips_abi; +extern struct mips_abi mips_abi_32; +extern struct mips_abi mips_abi_n32; + #ifdef CONFIG_32BIT -#define SET_PERSONALITY(ex, ibcs2) \ -do { \ - if (ibcs2) \ - set_personality(PER_SVR4); \ - set_personality(PER_LINUX); \ +#define SET_PERSONALITY(ex, ibcs2) \ +do { \ + if (ibcs2) \ + set_personality(PER_SVR4); \ + set_personality(PER_LINUX); \ + \ + current->thread.abi = &mips_abi; \ } while (0) #endif /* CONFIG_32BIT */ #ifdef CONFIG_64BIT -#define SET_PERSONALITY(ex, ibcs2) \ -do { current->thread.mflags &= ~MF_ABI_MASK; \ - if ((ex).e_ident[EI_CLASS] == ELFCLASS32) { \ - if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \ - ((ex).e_flags & EF_MIPS_ABI) == 0) \ - current->thread.mflags |= MF_N32; \ - else \ - current->thread.mflags |= MF_O32; \ - } else \ - current->thread.mflags |= MF_N64; \ - if (ibcs2) \ - set_personality(PER_SVR4); \ - else if (current->personality != PER_LINUX32) \ - set_personality(PER_LINUX); \ +#ifdef CONFIG_MIPS32_N32 +#define __SET_PERSONALITY32_N32() \ + do { \ + current->thread.mflags |= MF_N32; \ + current->thread.abi = &mips_abi_n32; \ + } while (0) +#else +#define __SET_PERSONALITY32_N32() \ + do { } while (0) +#endif + +#ifdef CONFIG_MIPS32_O32 +#define __SET_PERSONALITY32_O32() \ + do { \ + current->thread.mflags |= MF_O32; \ + current->thread.abi = &mips_abi_32; \ + } while (0) +#else +#define __SET_PERSONALITY32_O32() \ + do { } while (0) +#endif + +#ifdef CONFIG_MIPS32_COMPAT +#define __SET_PERSONALITY32(ex) \ +do { \ + if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \ + ((ex).e_flags & EF_MIPS_ABI) == 0) \ + __SET_PERSONALITY32_N32(); \ + else \ + __SET_PERSONALITY32_O32(); \ +} while (0) +#else +#define __SET_PERSONALITY32(ex) do { } while (0) +#endif + +#define SET_PERSONALITY(ex, ibcs2) \ +do { \ + current->thread.mflags &= ~MF_ABI_MASK; \ + if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ + __SET_PERSONALITY32(ex); \ + else { \ + current->thread.mflags |= MF_N64; \ + current->thread.abi = &mips_abi; \ + } \ + \ + if (ibcs2) \ + set_personality(PER_SVR4); \ + else if (current->personality != PER_LINUX32) \ + set_personality(PER_LINUX); \ } while (0) #endif /* CONFIG_64BIT */ extern void dump_regs(elf_greg_t *, struct pt_regs *regs); +extern int dump_task_regs (struct task_struct *, elf_gregset_t *); extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); #define ELF_CORE_COPY_REGS(elf_regs, regs) \ dump_regs((elf_greg_t *)&(elf_regs), regs); +#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs) #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \ dump_task_fpu(tsk, elf_fpregs) #endif /* __KERNEL__ */ -/* This one accepts IRIX binaries. */ -#define irix_elf_check_arch(hdr) ((hdr)->e_flags & RHF_SGI_ONLY) - #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE PAGE_SIZE diff --git a/include/asm-mips/errno.h b/include/asm-mips/errno.h index 3c0d840e4577..9d3e6e7cdb92 100644 --- a/include/asm-mips/errno.h +++ b/include/asm-mips/errno.h @@ -119,6 +119,10 @@ #define EOWNERDEAD 165 /* Owner died */ #define ENOTRECOVERABLE 166 /* State not recoverable */ +/* for robust mutexes */ +#define EOWNERDEAD 165 /* Owner died */ +#define ENOTRECOVERABLE 166 /* State not recoverable */ + #define EDQUOT 1133 /* Quota exceeded */ #ifdef __KERNEL__ diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h index 06c5d13faf66..43d047a9a6af 100644 --- a/include/asm-mips/fcntl.h +++ b/include/asm-mips/fcntl.h @@ -3,11 +3,13 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995, 96, 97, 98, 99, 2003 Ralf Baechle + * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle */ #ifndef _ASM_FCNTL_H #define _ASM_FCNTL_H +#include <linux/config.h> + #define O_APPEND 0x0008 #define O_SYNC 0x0010 #define O_NONBLOCK 0x0080 @@ -40,13 +42,13 @@ * contain all the same fields as struct flock. */ -#ifndef __mips64 +#ifdef CONFIG_32BIT struct flock { short l_type; short l_whence; - __kernel_off_t l_start; - __kernel_off_t l_len; + off_t l_start; + off_t l_len; long l_sysid; __kernel_pid_t l_pid; long pad[4]; @@ -54,13 +56,8 @@ struct flock { #define HAVE_ARCH_STRUCT_FLOCK -#endif +#endif /* CONFIG_32BIT */ #include <asm-generic/fcntl.h> -typedef struct flock flock_t; -#ifndef __mips64 -typedef struct flock64 flock64_t; -#endif - #endif /* _ASM_FCNTL_H */ diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h index 26b6a90a690b..73a3028dd9f9 100644 --- a/include/asm-mips/fixmap.h +++ b/include/asm-mips/fixmap.h @@ -107,4 +107,11 @@ static inline unsigned long virt_to_fix(const unsigned long vaddr) return __virt_to_fix(vaddr); } +/* + * Called from pgtable_init() + */ +extern void fixrange_init(unsigned long start, unsigned long end, + pgd_t *pgd_base); + + #endif diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index ea24e733b1bc..9c828b1f8218 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -80,9 +80,14 @@ do { \ #define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU) +static inline int __is_fpu_owner(void) +{ + return test_thread_flag(TIF_USEDFPU); +} + static inline int is_fpu_owner(void) { - return cpu_has_fpu && test_thread_flag(TIF_USEDFPU); + return cpu_has_fpu && __is_fpu_owner(); } static inline void own_fpu(void) @@ -127,7 +132,7 @@ static inline void restore_fp(struct task_struct *tsk) static inline fpureg_t *get_fpu_regs(struct task_struct *tsk) { if (cpu_has_fpu) { - if ((tsk == current) && is_fpu_owner()) + if ((tsk == current) && __is_fpu_owner()) _save_fp(current); return tsk->thread.fpu.hard.fpr; } diff --git a/include/asm-mips/fpu_emulator.h b/include/asm-mips/fpu_emulator.h index 46972ae2b95d..16cb4d11dd0b 100644 --- a/include/asm-mips/fpu_emulator.h +++ b/include/asm-mips/fpu_emulator.h @@ -23,16 +23,15 @@ #ifndef _ASM_FPU_EMULATOR_H #define _ASM_FPU_EMULATOR_H -struct mips_fpu_emulator_private { - unsigned int eir; - struct { - unsigned int emulated; - unsigned int loads; - unsigned int stores; - unsigned int cp1ops; - unsigned int cp1xops; - unsigned int errors; - } stats; +struct mips_fpu_emulator_stats { + unsigned int emulated; + unsigned int loads; + unsigned int stores; + unsigned int cp1ops; + unsigned int cp1xops; + unsigned int errors; }; +extern struct mips_fpu_emulator_stats fpuemustats; + #endif /* _ASM_FPU_EMULATOR_H */ diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h index 9feff4ce1424..2454c44a8f54 100644 --- a/include/asm-mips/futex.h +++ b/include/asm-mips/futex.h @@ -3,10 +3,45 @@ #ifdef __KERNEL__ +#include <linux/config.h> #include <linux/futex.h> #include <asm/errno.h> #include <asm/uaccess.h> +#ifdef CONFIG_SMP +#define __FUTEX_SMP_SYNC " sync \n" +#else +#define __FUTEX_SMP_SYNC +#endif + +#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ +{ \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " .set mips3 \n" \ + "1: ll %1, (%3) # __futex_atomic_op1 \n" \ + " .set mips0 \n" \ + " " insn " \n" \ + " .set mips3 \n" \ + "2: sc $1, (%3) \n" \ + " beqzl $1, 1b \n" \ + __FUTEX_SMP_SYNC \ + "3: \n" \ + " .set pop \n" \ + " .set mips0 \n" \ + " .section .fixup,\"ax\" \n" \ + "4: li %0, %5 \n" \ + " j 2b \n" \ + " .previous \n" \ + " .section __ex_table,\"a\" \n" \ + " "__UA_ADDR "\t1b, 4b \n" \ + " "__UA_ADDR "\t2b, 4b \n" \ + " .previous \n" \ + : "=r" (ret), "=r" (oldval) \ + : "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \ +} + static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr) { @@ -25,10 +60,25 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr) switch (op) { case FUTEX_OP_SET: + __futex_atomic_op("move $1, %z4", ret, oldval, uaddr, oparg); + break; + case FUTEX_OP_ADD: + __futex_atomic_op("addu $1, %1, %z4", + ret, oldval, uaddr, oparg); + break; case FUTEX_OP_OR: + __futex_atomic_op("or $1, %1, %z4", + ret, oldval, uaddr, oparg); + break; case FUTEX_OP_ANDN: + __futex_atomic_op("and $1, %1, %z4", + ret, oldval, uaddr, ~oparg); + break; case FUTEX_OP_XOR: + __futex_atomic_op("xor $1, %1, %z4", + ret, oldval, uaddr, oparg); + break; default: ret = -ENOSYS; } diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index f524eaccd5f1..7517189e469f 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -74,7 +74,8 @@ #define irq_disable_hazard _ehb -#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) +#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \ + defined(CONFIG_CPU_SB1) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. @@ -107,6 +108,7 @@ __asm__( " .endm \n\t"); #ifdef CONFIG_CPU_RM9000 + /* * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent * use of the JTLB for instructions should not occur for 4 cpu cycles and use @@ -124,6 +126,9 @@ __asm__( ".set\tmips32\n\t" \ "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \ ".set\tmips0") + +#define back_to_back_c0_hazard() do { } while (0) + #else /* @@ -144,15 +149,13 @@ __asm__( #endif /* - * mtc0->mfc0 hazard - * The 24K has a 2 cycle mtc0/mfc0 execution hazard. - * It is a MIPS32R2 processor so ehb will clear the hazard. + * Interrupt enable/disable hazards + * Some processors have hazards when modifying + * the status register to change the interrupt state */ #ifdef CONFIG_CPU_MIPSR2 -/* - * Use a macro for ehb unless explicit support for MIPSR2 is enabled - */ + __asm__( " .macro\tirq_enable_hazard \n\t" " _ehb \n\t" @@ -160,17 +163,26 @@ __asm__( " \n\t" " .macro\tirq_disable_hazard \n\t" " _ehb \n\t" + " .endm \n\t" + " \n\t" + " .macro\tback_to_back_c0_hazard \n\t" + " _ehb \n\t" " .endm"); #define irq_enable_hazard() \ __asm__ __volatile__( \ - "_ehb\t\t\t\t# irq_enable_hazard") + "irq_enable_hazard") #define irq_disable_hazard() \ __asm__ __volatile__( \ - "_ehb\t\t\t\t# irq_disable_hazard") + "irq_disable_hazard") + +#define back_to_back_c0_hazard() \ + __asm__ __volatile__( \ + "back_to_back_c0_hazard") -#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) +#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \ + defined(CONFIG_CPU_SB1) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. @@ -186,6 +198,8 @@ __asm__( #define irq_enable_hazard() do { } while (0) #define irq_disable_hazard() do { } while (0) +#define back_to_back_c0_hazard() do { } while (0) + #else /* @@ -208,10 +222,32 @@ __asm__( #define irq_enable_hazard() do { } while (0) #define irq_disable_hazard() \ __asm__ __volatile__( \ - "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard") + "irq_disable_hazard") + +#define back_to_back_c0_hazard() \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " nop; nop; nop \n" \ + " .set reorder \n") #endif +#ifdef CONFIG_CPU_MIPSR2 +#define instruction_hazard() \ +do { \ +__label__ __next; \ + __asm__ __volatile__( \ + " jr.hb %0 \n" \ + : \ + : "r" (&&__next)); \ +__next: \ + ; \ +} while (0) + +#else +#define instruction_hazard() do { } while (0) +#endif + #endif /* __ASSEMBLY__ */ #endif /* _ASM_HAZARDS_H */ diff --git a/include/asm-mips/highmem.h b/include/asm-mips/highmem.h index f49930d947d4..8cf598402492 100644 --- a/include/asm-mips/highmem.h +++ b/include/asm-mips/highmem.h @@ -75,6 +75,7 @@ static inline void *kmap_atomic(struct page *page, enum km_type type) } static inline void kunmap_atomic(void *kvaddr, enum km_type type) { } +#define kmap_atomic_pfn(pfn, idx) page_address(pfn_to_page(pfn)) #define kmap_atomic_to_page(ptr) virt_to_page(ptr) @@ -86,6 +87,7 @@ extern void *__kmap(struct page *page); extern void __kunmap(struct page *page); extern void *__kmap_atomic(struct page *page, enum km_type type); extern void __kunmap_atomic(void *kvaddr, enum km_type type); +extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type); extern struct page *__kmap_atomic_to_page(void *ptr); #define kmap __kmap diff --git a/include/asm-mips/inst.h b/include/asm-mips/inst.h index 6ad517241768..e0745f4ff624 100644 --- a/include/asm-mips/inst.h +++ b/include/asm-mips/inst.h @@ -28,7 +28,7 @@ enum major_op { sdl_op, sdr_op, swr_op, cache_op, ll_op, lwc1_op, lwc2_op, pref_op, lld_op, ldc1_op, ldc2_op, ld_op, - sc_op, swc1_op, swc2_op, major_3b_op, /* Opcode 0x3b is unused */ + sc_op, swc1_op, swc2_op, rdhwr_op, scd_op, sdc1_op, sdc2_op, sd_op }; @@ -62,10 +62,10 @@ enum rt_op { spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, tgei_op, tgeiu_op, tlti_op, tltiu_op, teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, - bltzal_op, bgezal_op, bltzall_op, bgezall_op - /* - * The others (0x14 - 0x1f) are unused. - */ + bltzal_op, bgezal_op, bltzall_op, bgezall_op, + rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17, + rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b, + bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f }; /* diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/interrupt.h index e8357f5379fa..a5735761f5e5 100644 --- a/include/asm-mips/interrupt.h +++ b/include/asm-mips/interrupt.h @@ -11,20 +11,25 @@ #ifndef _ASM_INTERRUPT_H #define _ASM_INTERRUPT_H +#include <linux/config.h> #include <asm/hazards.h> __asm__ ( - ".macro\tlocal_irq_enable\n\t" - ".set\tpush\n\t" - ".set\treorder\n\t" - ".set\tnoat\n\t" - "mfc0\t$1,$12\n\t" - "ori\t$1,0x1f\n\t" - "xori\t$1,0x1e\n\t" - "mtc0\t$1,$12\n\t" - "irq_enable_hazard\n\t" - ".set\tpop\n\t" - ".endm"); + " .macro local_irq_enable \n" + " .set push \n" + " .set reorder \n" + " .set noat \n" +#ifdef CONFIG_CPU_MIPSR2 + " ei \n" +#else + " mfc0 $1,$12 \n" + " ori $1,0x1f \n" + " xori $1,0x1e \n" + " mtc0 $1,$12 \n" +#endif + " irq_enable_hazard \n" + " .set pop \n" + " .endm"); static inline void local_irq_enable(void) { @@ -43,17 +48,21 @@ static inline void local_irq_enable(void) * no nops at all. */ __asm__ ( - ".macro\tlocal_irq_disable\n\t" - ".set\tpush\n\t" - ".set\tnoat\n\t" - "mfc0\t$1,$12\n\t" - "ori\t$1,1\n\t" - "xori\t$1,1\n\t" - ".set\tnoreorder\n\t" - "mtc0\t$1,$12\n\t" - "irq_disable_hazard\n\t" - ".set\tpop\n\t" - ".endm"); + " .macro local_irq_disable\n" + " .set push \n" + " .set noat \n" +#ifdef CONFIG_CPU_MIPSR2 + " di \n" +#else + " mfc0 $1,$12 \n" + " ori $1,1 \n" + " xori $1,1 \n" + " .set noreorder \n" + " mtc0 $1,$12 \n" +#endif + " irq_disable_hazard \n" + " .set pop \n" + " .endm \n"); static inline void local_irq_disable(void) { @@ -65,12 +74,12 @@ static inline void local_irq_disable(void) } __asm__ ( - ".macro\tlocal_save_flags flags\n\t" - ".set\tpush\n\t" - ".set\treorder\n\t" - "mfc0\t\\flags, $12\n\t" - ".set\tpop\n\t" - ".endm"); + " .macro local_save_flags flags \n" + " .set push \n" + " .set reorder \n" + " mfc0 \\flags, $12 \n" + " .set pop \n" + " .endm \n"); #define local_save_flags(x) \ __asm__ __volatile__( \ @@ -78,18 +87,22 @@ __asm__ __volatile__( \ : "=r" (x)) __asm__ ( - ".macro\tlocal_irq_save result\n\t" - ".set\tpush\n\t" - ".set\treorder\n\t" - ".set\tnoat\n\t" - "mfc0\t\\result, $12\n\t" - "ori\t$1, \\result, 1\n\t" - "xori\t$1, 1\n\t" - ".set\tnoreorder\n\t" - "mtc0\t$1, $12\n\t" - "irq_disable_hazard\n\t" - ".set\tpop\n\t" - ".endm"); + " .macro local_irq_save result \n" + " .set push \n" + " .set reorder \n" + " .set noat \n" +#ifdef CONFIG_CPU_MIPSR2 + " di \\result \n" +#else + " mfc0 \\result, $12 \n" + " ori $1, \\result, 1 \n" + " xori $1, 1 \n" + " .set noreorder \n" + " mtc0 $1, $12 \n" +#endif + " irq_disable_hazard \n" + " .set pop \n" + " .endm \n"); #define local_irq_save(x) \ __asm__ __volatile__( \ @@ -99,19 +112,37 @@ __asm__ __volatile__( \ : "memory") __asm__ ( - ".macro\tlocal_irq_restore flags\n\t" - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "mfc0\t$1, $12\n\t" - "andi\t\\flags, 1\n\t" - "ori\t$1, 1\n\t" - "xori\t$1, 1\n\t" - "or\t\\flags, $1\n\t" - "mtc0\t\\flags, $12\n\t" - "irq_disable_hazard\n\t" - ".set\tat\n\t" - ".set\treorder\n\t" - ".endm"); + " .macro local_irq_restore flags \n" + " .set noreorder \n" + " .set noat \n" +#if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) + /* + * Slow, but doesn't suffer from a relativly unlikely race + * condition we're having since days 1. + */ + " beqz \\flags, 1f \n" + " di \n" + " ei \n" + "1: \n" +#elif defined(CONFIG_CPU_MIPSR2) + /* + * Fast, dangerous. Life is fun, life is good. + */ + " mfc0 $1, $12 \n" + " ins $1, \\flags, 0, 1 \n" + " mtc0 $1, $12 \n" +#else + " mfc0 $1, $12 \n" + " andi \\flags, 1 \n" + " ori $1, 1 \n" + " xori $1, 1 \n" + " or \\flags, $1 \n" + " mtc0 \\flags, $12 \n" +#endif + " irq_disable_hazard \n" + " .set at \n" + " .set reorder \n" + " .endm \n"); #define local_irq_restore(flags) \ do { \ diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h index 4cd36fe98173..92d90f75a636 100644 --- a/include/asm-mips/inventory.h +++ b/include/asm-mips/inventory.h @@ -4,6 +4,8 @@ #ifndef __ASM_INVENTORY_H #define __ASM_INVENTORY_H +#include <linux/compiler.h> + typedef struct inventory_s { struct inventory_s *inv_next; int inv_class; @@ -14,7 +16,9 @@ typedef struct inventory_s { } inventory_t; extern int inventory_items; -void add_to_inventory (int class, int type, int controller, int unit, int state); -int dump_inventory_to_user (void *userbuf, int size); + +extern void add_to_inventory (int class, int type, int controller, int unit, int state); +extern int dump_inventory_to_user (void __user *userbuf, int size); +extern int __init init_inventory(void); #endif /* __ASM_INVENTORY_H */ diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 039845f2e6b0..3061870b7f6c 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -25,7 +25,9 @@ #include <asm/page.h> #include <asm/pgtable-bits.h> #include <asm/processor.h> +#include <asm/string.h> +#include <ioremap.h> #include <mangle-port.h> /* @@ -34,7 +36,7 @@ #undef CONF_SLOWDOWN_IO /* - * Raw operations are never swapped in software. Otoh values that raw + * Raw operations are never swapped in software. OTOH values that raw * operations are working on may or may not have been swapped by the bus * hardware. An example use would be for flash memory that's used for * execute in place. @@ -43,45 +45,53 @@ # define __raw_ioswabw(x) (x) # define __raw_ioswabl(x) (x) # define __raw_ioswabq(x) (x) +# define ____raw_ioswabq(x) (x) /* * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware; * less sane hardware forces software to fiddle with this... + * + * Regardless, if the host bus endianness mismatches that of PCI/ISA, then + * you can't have the numerical value of data and byte addresses within + * multibyte quantities both preserved at the same time. Hence two + * variations of functions: non-prefixed ones that preserve the value + * and prefixed ones that preserve byte addresses. The latters are + * typically used for moving raw data between a peripheral and memory (cf. + * string I/O functions), hence the "mem_" prefix. */ #if defined(CONFIG_SWAP_IO_SPACE) # define ioswabb(x) (x) +# define mem_ioswabb(x) (x) # ifdef CONFIG_SGI_IP22 /* * IP22 seems braindead enough to swap 16bits values in hardware, but * not 32bits. Go figure... Can't tell without documentation. */ # define ioswabw(x) (x) +# define mem_ioswabw(x) le16_to_cpu(x) # else # define ioswabw(x) le16_to_cpu(x) +# define mem_ioswabw(x) (x) # endif # define ioswabl(x) le32_to_cpu(x) +# define mem_ioswabl(x) (x) # define ioswabq(x) le64_to_cpu(x) +# define mem_ioswabq(x) (x) #else # define ioswabb(x) (x) +# define mem_ioswabb(x) (x) # define ioswabw(x) (x) +# define mem_ioswabw(x) cpu_to_le16(x) # define ioswabl(x) (x) +# define mem_ioswabl(x) cpu_to_le32(x) # define ioswabq(x) (x) +# define mem_ioswabq(x) cpu_to_le32(x) #endif -/* - * Native bus accesses never swapped. - */ -#define bus_ioswabb(x) (x) -#define bus_ioswabw(x) (x) -#define bus_ioswabl(x) (x) -#define bus_ioswabq(x) (x) - -#define __bus_ioswabq bus_ioswabq - #define IO_SPACE_LIMIT 0xffff /* @@ -194,12 +204,14 @@ extern unsigned long isa_slot_offset; */ #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) -extern void * __ioremap(phys_t offset, phys_t size, unsigned long flags); +extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags); extern void __iounmap(volatile void __iomem *addr); -static inline void * __ioremap_mode(phys_t offset, unsigned long size, +static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, unsigned long flags) { +#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL)) + if (cpu_has_64bit_addresses) { u64 base = UNCAC_BASE; @@ -209,10 +221,30 @@ static inline void * __ioremap_mode(phys_t offset, unsigned long size, */ if (flags == _CACHE_UNCACHED) base = (u64) IO_BASE; - return (void *) (unsigned long) (base + offset); + return (void __iomem *) (unsigned long) (base + offset); + } else if (__builtin_constant_p(offset) && + __builtin_constant_p(size) && __builtin_constant_p(flags)) { + phys_t phys_addr, last_addr; + + phys_addr = fixup_bigphys_addr(offset, size); + + /* Don't allow wraparound or zero size. */ + last_addr = phys_addr + size - 1; + if (!size || last_addr < phys_addr) + return NULL; + + /* + * Map uncached objects in the low 512MB of address + * space using KSEG1. + */ + if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) && + flags == _CACHE_UNCACHED) + return (void __iomem *)CKSEG1ADDR(phys_addr); } return __ioremap(offset, size, flags); + +#undef __IS_LOW512 } /* @@ -264,12 +296,16 @@ static inline void * __ioremap_mode(phys_t offset, unsigned long size, static inline void iounmap(volatile void __iomem *addr) { - if (cpu_has_64bit_addresses) +#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) + + if (cpu_has_64bit_addresses || + (__builtin_constant_p(addr) && __IS_KSEG1(addr))) return; __iounmap(addr); -} +#undef __IS_KSEG1 +} #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ \ @@ -319,7 +355,8 @@ static inline type pfx##read##bwlq(volatile void __iomem *mem) \ else if (cpu_has_64bits) { \ unsigned long __flags; \ \ - local_irq_save(__flags); \ + if (irq) \ + local_irq_save(__flags); \ __asm__ __volatile__( \ ".set mips3" "\t\t# __readq" "\n\t" \ "ld %L0, %1" "\n\t" \ @@ -328,7 +365,8 @@ static inline type pfx##read##bwlq(volatile void __iomem *mem) \ ".set mips0" "\n" \ : "=r" (__val) \ : "m" (*__mem)); \ - local_irq_restore(__flags); \ + if (irq) \ + local_irq_restore(__flags); \ } else { \ __val = 0; \ BUG(); \ @@ -349,11 +387,11 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \ \ __val = pfx##ioswab##bwlq(val); \ \ - if (sizeof(type) != sizeof(u64)) { \ - *__addr = __val; \ - slow; \ - } else \ - BUILD_BUG(); \ + /* Really, we want this to be atomic */ \ + BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ + \ + *__addr = __val; \ + slow; \ } \ \ static inline type pfx##in##bwlq##p(unsigned long port) \ @@ -364,13 +402,10 @@ static inline type pfx##in##bwlq##p(unsigned long port) \ port = __swizzle_addr_##bwlq(port); \ __addr = (void *)(mips_io_port_base + port); \ \ - if (sizeof(type) != sizeof(u64)) { \ - __val = *__addr; \ - slow; \ - } else { \ - __val = 0; \ - BUILD_BUG(); \ - } \ + BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ + \ + __val = *__addr; \ + slow; \ \ return pfx##ioswab##bwlq(__val); \ } @@ -379,27 +414,35 @@ static inline type pfx##in##bwlq##p(unsigned long port) \ \ __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1) -#define __BUILD_IOPORT_PFX(bus, bwlq, type) \ - \ -__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ -__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) - -#define BUILDIO(bwlq, type) \ +#define BUILDIO_MEM(bwlq, type) \ \ -__BUILD_MEMORY_PFX(, bwlq, type) \ __BUILD_MEMORY_PFX(__raw_, bwlq, type) \ -__BUILD_MEMORY_PFX(bus_, bwlq, type) \ -__BUILD_IOPORT_PFX(, bwlq, type) \ -__BUILD_IOPORT_PFX(__raw_, bwlq, type) +__BUILD_MEMORY_PFX(, bwlq, type) \ +__BUILD_MEMORY_PFX(mem_, bwlq, type) \ + +BUILDIO_MEM(b, u8) +BUILDIO_MEM(w, u16) +BUILDIO_MEM(l, u32) +BUILDIO_MEM(q, u64) + +#define __BUILD_IOPORT_PFX(bus, bwlq, type) \ + __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ + __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) + +#define BUILDIO_IOPORT(bwlq, type) \ + __BUILD_IOPORT_PFX(, bwlq, type) \ + __BUILD_IOPORT_PFX(mem_, bwlq, type) + +BUILDIO_IOPORT(b, u8) +BUILDIO_IOPORT(w, u16) +BUILDIO_IOPORT(l, u32) +#ifdef CONFIG_64BIT +BUILDIO_IOPORT(q, u64) +#endif #define __BUILDIO(bwlq, type) \ \ -__BUILD_MEMORY_SINGLE(__bus_, bwlq, type, 0) - -BUILDIO(b, u8) -BUILDIO(w, u16) -BUILDIO(l, u32) -BUILDIO(q, u64) +__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0) __BUILDIO(q, u64) @@ -422,7 +465,7 @@ static inline void writes##bwlq(volatile void __iomem *mem, void *addr, \ volatile type *__addr = addr; \ \ while (count--) { \ - __raw_write##bwlq(*__addr, mem); \ + mem_write##bwlq(*__addr, mem); \ __addr++; \ } \ } \ @@ -433,20 +476,20 @@ static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ volatile type *__addr = addr; \ \ while (count--) { \ - *__addr = __raw_read##bwlq(mem); \ + *__addr = mem_read##bwlq(mem); \ __addr++; \ } \ } #define __BUILD_IOPORT_STRING(bwlq, type) \ \ -static inline void outs##bwlq(unsigned long port, void *addr, \ +static inline void outs##bwlq(unsigned long port, const void *addr, \ unsigned int count) \ { \ - volatile type *__addr = addr; \ + const volatile type *__addr = addr; \ \ while (count--) { \ - __raw_out##bwlq(*__addr, port); \ + mem_out##bwlq(*__addr, port); \ __addr++; \ } \ } \ @@ -457,7 +500,7 @@ static inline void ins##bwlq(unsigned long port, void *addr, \ volatile type *__addr = addr; \ \ while (count--) { \ - *__addr = __raw_in##bwlq(port); \ + *__addr = mem_in##bwlq(port); \ __addr++; \ } \ } @@ -470,15 +513,26 @@ __BUILD_IOPORT_STRING(bwlq, type) BUILDSTRING(b, u8) BUILDSTRING(w, u16) BUILDSTRING(l, u32) +#ifdef CONFIG_64BIT BUILDSTRING(q, u64) +#endif /* Depends on MIPS II instruction set */ #define mmiowb() asm volatile ("sync" ::: "memory") -#define memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) +static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) +{ + memset((void __force *) addr, val, count); +} +static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) +{ + memcpy(dst, (void __force *) src, count); +} +static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) +{ + memcpy((void __force *) dst, src, count); +} /* * Memory Mapped I/O diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h index 3f2470e9e678..8a342ccb34a8 100644 --- a/include/asm-mips/irq.h +++ b/include/asm-mips/irq.h @@ -24,11 +24,9 @@ static inline int irq_canonicalize(int irq) struct pt_regs; -#ifdef CONFIG_PREEMPT - extern asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs); -#else +#ifdef CONFIG_PREEMPT /* * do_IRQ handles all normal device IRQ's (the special diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h index 86df317b4078..baf412967afa 100644 --- a/include/asm-mips/jmr3927/jmr3927.h +++ b/include/asm-mips/jmr3927/jmr3927.h @@ -202,20 +202,6 @@ static inline int jmr3927_have_isac(void) #endif /* !__ASSEMBLY__ */ /* - * UART defines for serial.h - */ - -/* use Pre-scaler T0 (1/2) */ -#define JMR3927_BASE_BAUD (JMR3927_IMCLK / 2 / 16) - -#define UART0_ADDR 0xfffef300 -#define UART1_ADDR 0xfffef400 -#define UART0_INT JMR3927_IRQ_IRC_SIO0 -#define UART1_INT JMR3927_IRQ_IRC_SIO1 -#define UART0_FLAGS ASYNC_BOOT_AUTOCONF -#define UART1_FLAGS 0 - -/* * IRQ mappings */ diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 148bae2fa7d3..8327ec341c18 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -60,59 +60,36 @@ void static inline au_sync_delay(int ms) mdelay(ms); } -void static inline au_writeb(u8 val, int reg) +void static inline au_writeb(u8 val, unsigned long reg) { *(volatile u8 *)(reg) = val; } -void static inline au_writew(u16 val, int reg) +void static inline au_writew(u16 val, unsigned long reg) { *(volatile u16 *)(reg) = val; } -void static inline au_writel(u32 val, int reg) +void static inline au_writel(u32 val, unsigned long reg) { *(volatile u32 *)(reg) = val; } -static inline u8 au_readb(unsigned long port) +static inline u8 au_readb(unsigned long reg) { - return (*(volatile u8 *)port); + return (*(volatile u8 *)reg); } -static inline u16 au_readw(unsigned long port) +static inline u16 au_readw(unsigned long reg) { - return (*(volatile u16 *)port); + return (*(volatile u16 *)reg); } -static inline u32 au_readl(unsigned long port) +static inline u32 au_readl(unsigned long reg) { - return (*(volatile u32 *)port); + return (*(volatile u32 *)reg); } -/* These next three functions should be a generic part of the MIPS - * kernel (with the 'au_' removed from the name) and selected for - * processors that support the instructions. - * Taken from PPC tree. -- Dan - */ -/* Return the bit position of the most significant 1 bit in a word */ -static __inline__ int __ilog2(unsigned int x) -{ - int lz; - - asm volatile ( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips32\n\t" - "clz\t%0,%1\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (lz) - : "r" (x)); - - return 31 - lz; -} static __inline__ int au_ffz(unsigned int x) { @@ -162,28 +139,293 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) #endif -/* SDRAM Controller */ +/* + * SDRAM Register Offsets + */ #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100) -#define MEM_SDMODE0 0xB4000000 -#define MEM_SDMODE1 0xB4000004 -#define MEM_SDMODE2 0xB4000008 +#define MEM_SDMODE0 (0x0000) +#define MEM_SDMODE1 (0x0004) +#define MEM_SDMODE2 (0x0008) +#define MEM_SDADDR0 (0x000C) +#define MEM_SDADDR1 (0x0010) +#define MEM_SDADDR2 (0x0014) +#define MEM_SDREFCFG (0x0018) +#define MEM_SDPRECMD (0x001C) +#define MEM_SDAUTOREF (0x0020) +#define MEM_SDWRMD0 (0x0024) +#define MEM_SDWRMD1 (0x0028) +#define MEM_SDWRMD2 (0x002C) +#define MEM_SDSLEEP (0x0030) +#define MEM_SDSMCKE (0x0034) -#define MEM_SDADDR0 0xB400000C -#define MEM_SDADDR1 0xB4000010 -#define MEM_SDADDR2 0xB4000014 +/* + * MEM_SDMODE register content definitions + */ +#define MEM_SDMODE_F (1<<22) +#define MEM_SDMODE_SR (1<<21) +#define MEM_SDMODE_BS (1<<20) +#define MEM_SDMODE_RS (3<<18) +#define MEM_SDMODE_CS (7<<15) +#define MEM_SDMODE_TRAS (15<<11) +#define MEM_SDMODE_TMRD (3<<9) +#define MEM_SDMODE_TWR (3<<7) +#define MEM_SDMODE_TRP (3<<5) +#define MEM_SDMODE_TRCD (3<<3) +#define MEM_SDMODE_TCL (7<<0) + +#define MEM_SDMODE_BS_2Bank (0<<20) +#define MEM_SDMODE_BS_4Bank (1<<20) +#define MEM_SDMODE_RS_11Row (0<<18) +#define MEM_SDMODE_RS_12Row (1<<18) +#define MEM_SDMODE_RS_13Row (2<<18) +#define MEM_SDMODE_RS_N(N) ((N)<<18) +#define MEM_SDMODE_CS_7Col (0<<15) +#define MEM_SDMODE_CS_8Col (1<<15) +#define MEM_SDMODE_CS_9Col (2<<15) +#define MEM_SDMODE_CS_10Col (3<<15) +#define MEM_SDMODE_CS_11Col (4<<15) +#define MEM_SDMODE_CS_N(N) ((N)<<15) +#define MEM_SDMODE_TRAS_N(N) ((N)<<11) +#define MEM_SDMODE_TMRD_N(N) ((N)<<9) +#define MEM_SDMODE_TWR_N(N) ((N)<<7) +#define MEM_SDMODE_TRP_N(N) ((N)<<5) +#define MEM_SDMODE_TRCD_N(N) ((N)<<3) +#define MEM_SDMODE_TCL_N(N) ((N)<<0) -#define MEM_SDREFCFG 0xB4000018 -#define MEM_SDPRECMD 0xB400001C -#define MEM_SDAUTOREF 0xB4000020 +/* + * MEM_SDADDR register contents definitions + */ +#define MEM_SDADDR_E (1<<20) +#define MEM_SDADDR_CSBA (0x03FF<<10) +#define MEM_SDADDR_CSMASK (0x03FF<<0) +#define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12) +#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22) + +/* + * MEM_SDREFCFG register content definitions + */ +#define MEM_SDREFCFG_TRC (15<<28) +#define MEM_SDREFCFG_TRPM (3<<26) +#define MEM_SDREFCFG_E (1<<25) +#define MEM_SDREFCFG_RE (0x1ffffff<<0) +#define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC) +#define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM) +#define MEM_SDREFCFG_REF_N(N) (N) +#endif -#define MEM_SDWRMD0 0xB4000024 -#define MEM_SDWRMD1 0xB4000028 -#define MEM_SDWRMD2 0xB400002C +/***********************************************************************/ -#define MEM_SDSLEEP 0xB4000030 -#define MEM_SDSMCKE 0xB4000034 +/* + * Au1550 SDRAM Register Offsets + */ + +/***********************************************************************/ + +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) +#define MEM_SDMODE0 (0x0800) +#define MEM_SDMODE1 (0x0808) +#define MEM_SDMODE2 (0x0810) +#define MEM_SDADDR0 (0x0820) +#define MEM_SDADDR1 (0x0828) +#define MEM_SDADDR2 (0x0830) +#define MEM_SDCONFIGA (0x0840) +#define MEM_SDCONFIGB (0x0848) +#define MEM_SDSTAT (0x0850) +#define MEM_SDERRADDR (0x0858) +#define MEM_SDSTRIDE0 (0x0860) +#define MEM_SDSTRIDE1 (0x0868) +#define MEM_SDSTRIDE2 (0x0870) +#define MEM_SDWRMD0 (0x0880) +#define MEM_SDWRMD1 (0x0888) +#define MEM_SDWRMD2 (0x0890) +#define MEM_SDPRECMD (0x08C0) +#define MEM_SDAUTOREF (0x08C8) +#define MEM_SDSREF (0x08D0) +#define MEM_SDSLEEP MEM_SDSREF + +#endif + +/* + * Physical base addresses for integrated peripherals + */ + +#ifdef CONFIG_SOC_AU1000 +#define MEM_PHYS_ADDR 0x14000000 +#define STATIC_MEM_PHYS_ADDR 0x14001000 +#define DMA0_PHYS_ADDR 0x14002000 +#define DMA1_PHYS_ADDR 0x14002100 +#define DMA2_PHYS_ADDR 0x14002200 +#define DMA3_PHYS_ADDR 0x14002300 +#define DMA4_PHYS_ADDR 0x14002400 +#define DMA5_PHYS_ADDR 0x14002500 +#define DMA6_PHYS_ADDR 0x14002600 +#define DMA7_PHYS_ADDR 0x14002700 +#define IC0_PHYS_ADDR 0x10400000 +#define IC1_PHYS_ADDR 0x11800000 +#define AC97_PHYS_ADDR 0x10000000 +#define USBH_PHYS_ADDR 0x10100000 +#define USBD_PHYS_ADDR 0x10200000 +#define IRDA_PHYS_ADDR 0x10300000 +#define MAC0_PHYS_ADDR 0x10500000 +#define MAC1_PHYS_ADDR 0x10510000 +#define MACEN_PHYS_ADDR 0x10520000 +#define MACDMA0_PHYS_ADDR 0x14004000 +#define MACDMA1_PHYS_ADDR 0x14004200 +#define I2S_PHYS_ADDR 0x11000000 +#define UART0_PHYS_ADDR 0x11100000 +#define UART1_PHYS_ADDR 0x11200000 +#define UART2_PHYS_ADDR 0x11300000 +#define UART3_PHYS_ADDR 0x11400000 +#define SSI0_PHYS_ADDR 0x11600000 +#define SSI1_PHYS_ADDR 0x11680000 +#define SYS_PHYS_ADDR 0x11900000 +#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL #endif +/********************************************************************/ + +#ifdef CONFIG_SOC_AU1500 +#define MEM_PHYS_ADDR 0x14000000 +#define STATIC_MEM_PHYS_ADDR 0x14001000 +#define DMA0_PHYS_ADDR 0x14002000 +#define DMA1_PHYS_ADDR 0x14002100 +#define DMA2_PHYS_ADDR 0x14002200 +#define DMA3_PHYS_ADDR 0x14002300 +#define DMA4_PHYS_ADDR 0x14002400 +#define DMA5_PHYS_ADDR 0x14002500 +#define DMA6_PHYS_ADDR 0x14002600 +#define DMA7_PHYS_ADDR 0x14002700 +#define IC0_PHYS_ADDR 0x10400000 +#define IC1_PHYS_ADDR 0x11800000 +#define AC97_PHYS_ADDR 0x10000000 +#define USBH_PHYS_ADDR 0x10100000 +#define USBD_PHYS_ADDR 0x10200000 +#define PCI_PHYS_ADDR 0x14005000 +#define MAC0_PHYS_ADDR 0x11500000 +#define MAC1_PHYS_ADDR 0x11510000 +#define MACEN_PHYS_ADDR 0x11520000 +#define MACDMA0_PHYS_ADDR 0x14004000 +#define MACDMA1_PHYS_ADDR 0x14004200 +#define I2S_PHYS_ADDR 0x11000000 +#define UART0_PHYS_ADDR 0x11100000 +#define UART3_PHYS_ADDR 0x11400000 +#define GPIO2_PHYS_ADDR 0x11700000 +#define SYS_PHYS_ADDR 0x11900000 +#define PCI_MEM_PHYS_ADDR 0x400000000ULL +#define PCI_IO_PHYS_ADDR 0x500000000ULL +#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL +#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL +#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL +#endif + +/********************************************************************/ + +#ifdef CONFIG_SOC_AU1100 +#define MEM_PHYS_ADDR 0x14000000 +#define STATIC_MEM_PHYS_ADDR 0x14001000 +#define DMA0_PHYS_ADDR 0x14002000 +#define DMA1_PHYS_ADDR 0x14002100 +#define DMA2_PHYS_ADDR 0x14002200 +#define DMA3_PHYS_ADDR 0x14002300 +#define DMA4_PHYS_ADDR 0x14002400 +#define DMA5_PHYS_ADDR 0x14002500 +#define DMA6_PHYS_ADDR 0x14002600 +#define DMA7_PHYS_ADDR 0x14002700 +#define IC0_PHYS_ADDR 0x10400000 +#define SD0_PHYS_ADDR 0x10600000 +#define SD1_PHYS_ADDR 0x10680000 +#define IC1_PHYS_ADDR 0x11800000 +#define AC97_PHYS_ADDR 0x10000000 +#define USBH_PHYS_ADDR 0x10100000 +#define USBD_PHYS_ADDR 0x10200000 +#define IRDA_PHYS_ADDR 0x10300000 +#define MAC0_PHYS_ADDR 0x10500000 +#define MACEN_PHYS_ADDR 0x10520000 +#define MACDMA0_PHYS_ADDR 0x14004000 +#define MACDMA1_PHYS_ADDR 0x14004200 +#define I2S_PHYS_ADDR 0x11000000 +#define UART0_PHYS_ADDR 0x11100000 +#define UART1_PHYS_ADDR 0x11200000 +#define UART3_PHYS_ADDR 0x11400000 +#define SSI0_PHYS_ADDR 0x11600000 +#define SSI1_PHYS_ADDR 0x11680000 +#define GPIO2_PHYS_ADDR 0x11700000 +#define SYS_PHYS_ADDR 0x11900000 +#define LCD_PHYS_ADDR 0x15000000 +#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL +#endif + +/***********************************************************************/ + +#ifdef CONFIG_SOC_AU1550 +#define MEM_PHYS_ADDR 0x14000000 +#define STATIC_MEM_PHYS_ADDR 0x14001000 +#define IC0_PHYS_ADDR 0x10400000 +#define IC1_PHYS_ADDR 0x11800000 +#define USBH_PHYS_ADDR 0x14020000 +#define USBD_PHYS_ADDR 0x10200000 +#define PCI_PHYS_ADDR 0x14005000 +#define MAC0_PHYS_ADDR 0x10500000 +#define MAC1_PHYS_ADDR 0x10510000 +#define MACEN_PHYS_ADDR 0x10520000 +#define MACDMA0_PHYS_ADDR 0x14004000 +#define MACDMA1_PHYS_ADDR 0x14004200 +#define UART0_PHYS_ADDR 0x11100000 +#define UART1_PHYS_ADDR 0x11200000 +#define UART3_PHYS_ADDR 0x11400000 +#define GPIO2_PHYS_ADDR 0x11700000 +#define SYS_PHYS_ADDR 0x11900000 +#define DDMA_PHYS_ADDR 0x14002000 +#define PE_PHYS_ADDR 0x14008000 +#define PSC0_PHYS_ADDR 0x11A00000 +#define PSC1_PHYS_ADDR 0x11B00000 +#define PSC2_PHYS_ADDR 0x10A00000 +#define PSC3_PHYS_ADDR 0x10B00000 +#define PCI_MEM_PHYS_ADDR 0x400000000ULL +#define PCI_IO_PHYS_ADDR 0x500000000ULL +#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL +#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL +#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL +#endif + +/***********************************************************************/ + +#ifdef CONFIG_SOC_AU1200 +#define MEM_PHYS_ADDR 0x14000000 +#define STATIC_MEM_PHYS_ADDR 0x14001000 +#define AES_PHYS_ADDR 0x10300000 +#define CIM_PHYS_ADDR 0x14004000 +#define IC0_PHYS_ADDR 0x10400000 +#define IC1_PHYS_ADDR 0x11800000 +#define USBM_PHYS_ADDR 0x14020000 +#define USBH_PHYS_ADDR 0x14020100 +#define UART0_PHYS_ADDR 0x11100000 +#define UART1_PHYS_ADDR 0x11200000 +#define GPIO2_PHYS_ADDR 0x11700000 +#define SYS_PHYS_ADDR 0x11900000 +#define DDMA_PHYS_ADDR 0x14002000 +#define PSC0_PHYS_ADDR 0x11A00000 +#define PSC1_PHYS_ADDR 0x11B00000 +#define SD0_PHYS_ADDR 0x10600000 +#define SD1_PHYS_ADDR 0x10680000 +#define LCD_PHYS_ADDR 0x15000000 +#define SWCNT_PHYS_ADDR 0x1110010C +#define MAEFE_PHYS_ADDR 0x14012000 +#define MAEBE_PHYS_ADDR 0x14010000 +#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL +#endif + + /* Static Bus Controller */ #define MEM_STCFG0 0xB4001000 #define MEM_STTIME0 0xB4001004 @@ -369,7 +611,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define AU1000_MAC0_ENABLE 0xB0520000 #define AU1000_MAC1_ENABLE 0xB0520004 #define NUM_ETH_INTERFACES 2 -#endif // CONFIG_SOC_AU1000 +#endif /* CONFIG_SOC_AU1000 */ /* Au1500 */ #ifdef CONFIG_SOC_AU1500 @@ -429,6 +671,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define AU1500_GPIO_207 62 #define AU1500_GPIO_208_215 63 +/* shortcuts */ +#define INTA AU1000_PCI_INTA +#define INTB AU1000_PCI_INTB +#define INTC AU1000_PCI_INTC +#define INTD AU1000_PCI_INTD + #define UART0_ADDR 0xB1100000 #define UART3_ADDR 0xB1400000 @@ -440,7 +688,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define AU1500_MAC0_ENABLE 0xB1520000 #define AU1500_MAC1_ENABLE 0xB1520004 #define NUM_ETH_INTERFACES 2 -#endif // CONFIG_SOC_AU1500 +#endif /* CONFIG_SOC_AU1500 */ /* Au1100 */ #ifdef CONFIG_SOC_AU1100 @@ -485,6 +733,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define AU1000_GPIO_13 45 #define AU1000_GPIO_14 46 #define AU1000_GPIO_15 47 +#define AU1000_GPIO_16 48 +#define AU1000_GPIO_17 49 +#define AU1000_GPIO_18 50 +#define AU1000_GPIO_19 51 +#define AU1000_GPIO_20 52 +#define AU1000_GPIO_21 53 +#define AU1000_GPIO_22 54 +#define AU1000_GPIO_23 55 +#define AU1000_GPIO_24 56 +#define AU1000_GPIO_25 57 +#define AU1000_GPIO_26 58 +#define AU1000_GPIO_27 59 +#define AU1000_GPIO_28 60 +#define AU1000_GPIO_29 61 +#define AU1000_GPIO_30 62 +#define AU1000_GPIO_31 63 #define UART0_ADDR 0xB1100000 #define UART1_ADDR 0xB1200000 @@ -496,7 +760,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define AU1100_ETH0_BASE 0xB0500000 #define AU1100_MAC0_ENABLE 0xB0520000 #define NUM_ETH_INTERFACES 1 -#endif // CONFIG_SOC_AU1100 +#endif /* CONFIG_SOC_AU1100 */ #ifdef CONFIG_SOC_AU1550 #define AU1550_UART0_INT 0 @@ -513,14 +777,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define AU1550_PSC1_INT 11 #define AU1550_PSC2_INT 12 #define AU1550_PSC3_INT 13 -#define AU1550_TOY_INT 14 -#define AU1550_TOY_MATCH0_INT 15 -#define AU1550_TOY_MATCH1_INT 16 -#define AU1550_TOY_MATCH2_INT 17 -#define AU1550_RTC_INT 18 -#define AU1550_RTC_MATCH0_INT 19 -#define AU1550_RTC_MATCH1_INT 20 -#define AU1550_RTC_MATCH2_INT 21 +#define AU1000_TOY_INT 14 +#define AU1000_TOY_MATCH0_INT 15 +#define AU1000_TOY_MATCH1_INT 16 +#define AU1000_TOY_MATCH2_INT 17 +#define AU1000_RTC_INT 18 +#define AU1000_RTC_MATCH0_INT 19 +#define AU1000_RTC_MATCH1_INT 20 +#define AU1000_RTC_MATCH2_INT 21 #define AU1550_NAND_INT 23 #define AU1550_USB_DEV_REQ_INT 24 #define AU1550_USB_DEV_SUS_INT 25 @@ -563,6 +827,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define AU1500_GPIO_207 62 #define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218 +/* shortcuts */ +#define INTA AU1550_PCI_INTA +#define INTB AU1550_PCI_INTB +#define INTC AU1550_PCI_INTC +#define INTD AU1550_PCI_INTD + #define UART0_ADDR 0xB1100000 #define UART1_ADDR 0xB1200000 #define UART3_ADDR 0xB1400000 @@ -575,7 +845,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define AU1550_MAC0_ENABLE 0xB0520000 #define AU1550_MAC1_ENABLE 0xB0520004 #define NUM_ETH_INTERFACES 2 -#endif // CONFIG_SOC_AU1550 +#endif /* CONFIG_SOC_AU1550 */ #ifdef CONFIG_SOC_AU1200 #define AU1200_UART0_INT 0 @@ -592,14 +862,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define AU1200_PSC1_INT 11 #define AU1200_AES_INT 12 #define AU1200_CAMERA_INT 13 -#define AU1200_TOY_INT 14 -#define AU1200_TOY_MATCH0_INT 15 -#define AU1200_TOY_MATCH1_INT 16 -#define AU1200_TOY_MATCH2_INT 17 -#define AU1200_RTC_INT 18 -#define AU1200_RTC_MATCH0_INT 19 -#define AU1200_RTC_MATCH1_INT 20 -#define AU1200_RTC_MATCH2_INT 21 +#define AU1000_TOY_INT 14 +#define AU1000_TOY_MATCH0_INT 15 +#define AU1000_TOY_MATCH1_INT 16 +#define AU1000_TOY_MATCH2_INT 17 +#define AU1000_RTC_INT 18 +#define AU1000_RTC_MATCH0_INT 19 +#define AU1000_RTC_MATCH1_INT 20 +#define AU1000_RTC_MATCH2_INT 21 #define AU1200_NAND_INT 23 #define AU1200_GPIO_204 24 #define AU1200_GPIO_205 25 @@ -607,6 +877,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define AU1200_GPIO_207 27 #define AU1200_GPIO_208_215 28 // Logical OR of 208:215 #define AU1200_USB_INT 29 +#define AU1000_USB_HOST_INT AU1200_USB_INT #define AU1200_LCD_INT 30 #define AU1200_MAE_BOTH_INT 31 #define AU1000_GPIO_0 32 @@ -645,20 +916,36 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define UART0_ADDR 0xB1100000 #define UART1_ADDR 0xB1200000 -#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap -#define USB_HOST_CONFIG 0xB4027ffc - -// these are here for prototyping on au1550 (do not exist on au1200) -#define AU1200_ETH0_BASE 0xB0500000 -#define AU1200_ETH1_BASE 0xB0510000 -#define AU1200_MAC0_ENABLE 0xB0520000 -#define AU1200_MAC1_ENABLE 0xB0520004 -#define NUM_ETH_INTERFACES 2 -#endif // CONFIG_SOC_AU1200 +#define USB_UOC_BASE 0x14020020 +#define USB_UOC_LEN 0x20 +#define USB_OHCI_BASE 0x14020100 +#define USB_OHCI_LEN 0x100 +#define USB_EHCI_BASE 0x14020200 +#define USB_EHCI_LEN 0x100 +#define USB_UDC_BASE 0x14022000 +#define USB_UDC_LEN 0x2000 +#define USB_MSR_BASE 0xB4020000 +#define USB_MSR_MCFG 4 +#define USBMSRMCFG_OMEMEN 0 +#define USBMSRMCFG_OBMEN 1 +#define USBMSRMCFG_EMEMEN 2 +#define USBMSRMCFG_EBMEN 3 +#define USBMSRMCFG_DMEMEN 4 +#define USBMSRMCFG_DBMEN 5 +#define USBMSRMCFG_GMEMEN 6 +#define USBMSRMCFG_OHCCLKEN 16 +#define USBMSRMCFG_EHCCLKEN 17 +#define USBMSRMCFG_UDCCLKEN 18 +#define USBMSRMCFG_PHYPLLEN 19 +#define USBMSRMCFG_RDCOMB 30 +#define USBMSRMCFG_PFEN 31 + +#endif /* CONFIG_SOC_AU1200 */ #define AU1000_LAST_INTC0_INT 31 +#define AU1000_LAST_INTC1_INT 63 #define AU1000_MAX_INTR 63 - +#define INTX 0xFF /* not valid */ /* Programmable Counters 0 and 1 */ #define SYS_BASE 0xB1900000 @@ -730,6 +1017,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define I2S_CONTROL_D (1<<1) #define I2S_CONTROL_CE (1<<0) +#ifndef CONFIG_SOC_AU1200 + /* USB Host Controller */ #define USB_OHCI_LEN 0x00100000 @@ -775,6 +1064,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define USBDEV_ENABLE (1<<1) #define USBDEV_CE (1<<0) +#endif /* !CONFIG_SOC_AU1200 */ + /* Ethernet Controllers */ /* 4 byte offsets from AU1000_ETH_BASE */ @@ -1173,6 +1464,37 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define SYS_PF_PSC1_S1 (1 << 1) #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) +/* Au1200 Only */ +#ifdef CONFIG_SOC_AU1200 +#define SYS_PINFUNC_DMA (1<<31) +#define SYS_PINFUNC_S0A (1<<30) +#define SYS_PINFUNC_S1A (1<<29) +#define SYS_PINFUNC_LP0 (1<<28) +#define SYS_PINFUNC_LP1 (1<<27) +#define SYS_PINFUNC_LD16 (1<<26) +#define SYS_PINFUNC_LD8 (1<<25) +#define SYS_PINFUNC_LD1 (1<<24) +#define SYS_PINFUNC_LD0 (1<<23) +#define SYS_PINFUNC_P1A (3<<21) +#define SYS_PINFUNC_P1B (1<<20) +#define SYS_PINFUNC_FS3 (1<<19) +#define SYS_PINFUNC_P0A (3<<17) +#define SYS_PINFUNC_CS (1<<16) +#define SYS_PINFUNC_CIM (1<<15) +#define SYS_PINFUNC_P1C (1<<14) +#define SYS_PINFUNC_U1T (1<<12) +#define SYS_PINFUNC_U1R (1<<11) +#define SYS_PINFUNC_EX1 (1<<10) +#define SYS_PINFUNC_EX0 (1<<9) +#define SYS_PINFUNC_U0R (1<<8) +#define SYS_PINFUNC_MC (1<<7) +#define SYS_PINFUNC_S0B (1<<6) +#define SYS_PINFUNC_S0C (1<<5) +#define SYS_PINFUNC_P0B (1<<4) +#define SYS_PINFUNC_U0T (1<<3) +#define SYS_PINFUNC_S1B (1<<2) +#endif + #define SYS_TRIOUTRD 0xB1900100 #define SYS_TRIOUTCLR 0xB1900100 #define SYS_OUTPUTRD 0xB1900108 @@ -1239,6 +1561,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) #define SYS_CS_DI2 (1<<16) #define SYS_CS_CI2 (1<<15) +#ifdef CONFIG_SOC_AU1100 + #define SYS_CS_ML_BIT 7 + #define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT) + #define SYS_CS_DL (1<<6) + #define SYS_CS_CL (1<<5) +#else #define SYS_CS_MUH_BIT 12 #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) #define SYS_CS_DUH (1<<11) @@ -1247,6 +1575,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) #define SYS_CS_DUD (1<<6) #define SYS_CS_CUD (1<<5) +#endif #define SYS_CS_MIR_BIT 2 #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) #define SYS_CS_DIR (1<<1) @@ -1300,7 +1629,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define SD1_XMIT_FIFO 0xB0680000 #define SD1_RECV_FIFO 0xB0680004 - #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) /* Au1500 PCI Controller */ #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr @@ -1363,36 +1691,77 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; _ctl_; }) -#else /* Au1000 and Au1100 */ +#else /* Au1000 and Au1100 and Au1200 */ /* don't allow any legacy ports probing */ -#define IOPORT_RESOURCE_START 0x10000000; +#define IOPORT_RESOURCE_START 0x10000000 #define IOPORT_RESOURCE_END 0xffffffff #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xffffffff -#ifdef CONFIG_MIPS_PB1000 -#define PCI_IO_START 0x10000000 -#define PCI_IO_END 0x1000ffff -#define PCI_MEM_START 0x18000000 -#define PCI_MEM_END 0x18ffffff -#define PCI_FIRST_DEVFN 0 -#define PCI_LAST_DEVFN 1 -#else -/* no PCI bus controller */ #define PCI_IO_START 0 #define PCI_IO_END 0 #define PCI_MEM_START 0 #define PCI_MEM_END 0 #define PCI_FIRST_DEVFN 0 #define PCI_LAST_DEVFN 0 -#endif #endif +#ifndef _LANGUAGE_ASSEMBLY +typedef volatile struct +{ + /* 0x0000 */ u32 toytrim; + /* 0x0004 */ u32 toywrite; + /* 0x0008 */ u32 toymatch0; + /* 0x000C */ u32 toymatch1; + /* 0x0010 */ u32 toymatch2; + /* 0x0014 */ u32 cntrctrl; + /* 0x0018 */ u32 scratch0; + /* 0x001C */ u32 scratch1; + /* 0x0020 */ u32 freqctrl0; + /* 0x0024 */ u32 freqctrl1; + /* 0x0028 */ u32 clksrc; + /* 0x002C */ u32 pinfunc; + /* 0x0030 */ u32 reserved0; + /* 0x0034 */ u32 wakemsk; + /* 0x0038 */ u32 endian; + /* 0x003C */ u32 powerctrl; + /* 0x0040 */ u32 toyread; + /* 0x0044 */ u32 rtctrim; + /* 0x0048 */ u32 rtcwrite; + /* 0x004C */ u32 rtcmatch0; + /* 0x0050 */ u32 rtcmatch1; + /* 0x0054 */ u32 rtcmatch2; + /* 0x0058 */ u32 rtcread; + /* 0x005C */ u32 wakesrc; + /* 0x0060 */ u32 cpupll; + /* 0x0064 */ u32 auxpll; + /* 0x0068 */ u32 reserved1; + /* 0x006C */ u32 reserved2; + /* 0x0070 */ u32 reserved3; + /* 0x0074 */ u32 reserved4; + /* 0x0078 */ u32 slppwr; + /* 0x007C */ u32 sleep; + /* 0x0080 */ u32 reserved5[32]; + /* 0x0100 */ u32 trioutrd; +#define trioutclr trioutrd + /* 0x0104 */ u32 reserved6; + /* 0x0108 */ u32 outputrd; +#define outputset outputrd + /* 0x010C */ u32 outputclr; + /* 0x0110 */ u32 pinstaterd; +#define pininputen pinstaterd + +} AU1X00_SYS; + +static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE; + +#endif /* Processor information base on prid. * Copied from PowerPC. */ +#ifndef _LANGUAGE_ASSEMBLY struct cpu_spec { /* CPU is matched via (PRID & prid_mask) == prid_value */ unsigned int prid_mask; @@ -1406,3 +1775,6 @@ struct cpu_spec { extern struct cpu_spec cpu_specs[]; extern struct cpu_spec *cur_cpu_spec[]; #endif + +#endif + diff --git a/include/asm-mips/mach-au1x00/au1xxx.h b/include/asm-mips/mach-au1x00/au1xxx.h new file mode 100644 index 000000000000..b7b46dd9b929 --- /dev/null +++ b/include/asm-mips/mach-au1x00/au1xxx.h @@ -0,0 +1,44 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _AU1XXX_H_ +#define _AU1XXX_H_ + +#include <linux/config.h> + +#include <asm/mach-au1x00/au1000.h> + +#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) +#include <asm/mach-db1x00/db1x00.h> + +#elif defined(CONFIG_MIPS_PB1550) +#include <asm/mach-pb1x00/pb1550.h> + +#elif defined(CONFIG_MIPS_PB1200) +#include <asm/mach-pb1x00/pb1200.h> + +#elif defined(CONFIG_MIPS_DB1200) +#include <asm/mach-db1x00/db1200.h> + +#endif + +#endif /* _AU1XXX_H_ */ diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h index d5eb88cd7d51..b327bcd3fee1 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h +++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h @@ -45,7 +45,7 @@ #define DDMA_GLOBAL_BASE 0xb4003000 #define DDMA_CHANNEL_BASE 0xb4002000 -typedef struct dbdma_global { +typedef volatile struct dbdma_global { u32 ddma_config; u32 ddma_intstat; u32 ddma_throttle; @@ -62,7 +62,7 @@ typedef struct dbdma_global { /* The structure of a DMA Channel. */ -typedef struct au1xxx_dma_channel { +typedef volatile struct au1xxx_dma_channel { u32 ddma_cfg; /* See below */ u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */ u32 ddma_statptr; /* word aligned pointer to status word */ @@ -98,7 +98,7 @@ typedef struct au1xxx_dma_channel { /* "Standard" DDMA Descriptor. * Must be 32-byte aligned. */ -typedef struct au1xxx_ddma_desc { +typedef volatile struct au1xxx_ddma_desc { u32 dscr_cmd0; /* See below */ u32 dscr_cmd1; /* See below */ u32 dscr_source0; /* source phys address */ @@ -107,6 +107,12 @@ typedef struct au1xxx_ddma_desc { u32 dscr_dest1; /* See below */ u32 dscr_stat; /* completion status */ u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */ + /* First 32bytes are HW specific!!! + Lets have some SW data following.. make sure its 32bytes + */ + u32 sw_status; + u32 sw_context; + u32 sw_reserved[6]; } au1x_ddma_desc_t; #define DSCR_CMD0_V (1 << 31) /* Descriptor valid */ @@ -125,8 +131,11 @@ typedef struct au1xxx_ddma_desc { #define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */ #define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */ +#define SW_STATUS_INUSE (1<<0) + /* Command 0 device IDs. */ +#ifdef CONFIG_SOC_AU1550 #define DSCR_CMD0_UART0_TX 0 #define DSCR_CMD0_UART0_RX 1 #define DSCR_CMD0_UART3_TX 2 @@ -155,9 +164,45 @@ typedef struct au1xxx_ddma_desc { #define DSCR_CMD0_MAC0_TX 25 #define DSCR_CMD0_MAC1_RX 26 #define DSCR_CMD0_MAC1_TX 27 +#endif /* CONFIG_SOC_AU1550 */ + +#ifdef CONFIG_SOC_AU1200 +#define DSCR_CMD0_UART0_TX 0 +#define DSCR_CMD0_UART0_RX 1 +#define DSCR_CMD0_UART1_TX 2 +#define DSCR_CMD0_UART1_RX 3 +#define DSCR_CMD0_DMA_REQ0 4 +#define DSCR_CMD0_DMA_REQ1 5 +#define DSCR_CMD0_MAE_BE 6 +#define DSCR_CMD0_MAE_FE 7 +#define DSCR_CMD0_SDMS_TX0 8 +#define DSCR_CMD0_SDMS_RX0 9 +#define DSCR_CMD0_SDMS_TX1 10 +#define DSCR_CMD0_SDMS_RX1 11 +#define DSCR_CMD0_AES_TX 13 +#define DSCR_CMD0_AES_RX 12 +#define DSCR_CMD0_PSC0_TX 14 +#define DSCR_CMD0_PSC0_RX 15 +#define DSCR_CMD0_PSC1_TX 16 +#define DSCR_CMD0_PSC1_RX 17 +#define DSCR_CMD0_CIM_RXA 18 +#define DSCR_CMD0_CIM_RXB 19 +#define DSCR_CMD0_CIM_RXC 20 +#define DSCR_CMD0_MAE_BOTH 21 +#define DSCR_CMD0_LCD 22 +#define DSCR_CMD0_NAND_FLASH 23 +#define DSCR_CMD0_PSC0_SYNC 24 +#define DSCR_CMD0_PSC1_SYNC 25 +#define DSCR_CMD0_CIM_SYNC 26 +#endif /* CONFIG_SOC_AU1200 */ + #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 +/* THis macro is used to find/create custom device types */ +#define DSCR_DEV2CUSTOM_ID(x,d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF)) +#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF) + #define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25) #define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20) @@ -246,6 +291,43 @@ typedef struct au1xxx_ddma_desc { */ #define NUM_DBDMA_CHANS 16 +/* + * Ddma API definitions + * FIXME: may not fit to this header file + */ +typedef struct dbdma_device_table { + u32 dev_id; + u32 dev_flags; + u32 dev_tsize; + u32 dev_devwidth; + u32 dev_physaddr; /* If FIFO */ + u32 dev_intlevel; + u32 dev_intpolarity; +} dbdev_tab_t; + + +typedef struct dbdma_chan_config { + spinlock_t lock; + + u32 chan_flags; + u32 chan_index; + dbdev_tab_t *chan_src; + dbdev_tab_t *chan_dest; + au1x_dma_chan_t *chan_ptr; + au1x_ddma_desc_t *chan_desc_base; + au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr; + void *chan_callparam; + void (*chan_callback)(int, void *, struct pt_regs *); +} chan_tab_t; + +#define DEV_FLAGS_INUSE (1 << 0) +#define DEV_FLAGS_ANYUSE (1 << 1) +#define DEV_FLAGS_OUT (1 << 2) +#define DEV_FLAGS_IN (1 << 3) +#define DEV_FLAGS_BURSTABLE (1 << 4) +#define DEV_FLAGS_SYNC (1 << 5) +/* end Ddma API definitions */ + /* External functions for drivers to use. */ /* Use this to allocate a dbdma channel. The device ids are one of the @@ -258,18 +340,6 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, #define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS -/* ACK! These should be in a board specific description file. -*/ -#ifdef CONFIG_MIPS_PB1550 -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#endif -#ifdef CONFIG_MIPS_DB1550 -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#endif - - /* Set the device width of a in/out fifo. */ u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits); @@ -280,8 +350,8 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries); /* Put buffers on source/destination descriptors. */ -u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes); -u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes); +u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags); +u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags); /* Get a buffer from the destination descriptor. */ @@ -295,5 +365,29 @@ u32 au1xxx_get_dma_residue(u32 chanid); void au1xxx_dbdma_chan_free(u32 chanid); void au1xxx_dbdma_dump(u32 chanid); +u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr ); + +u32 au1xxx_ddma_add_device( dbdev_tab_t *dev ); +void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); + +/* + Some compatibilty macros -- + Needed to make changes to API without breaking existing drivers +*/ +#define au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) +#define au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) +#define put_source_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) + + +#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) +#define au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) +#define put_dest_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) + +/* + * Flags for the put_source/put_dest functions. + */ +#define DDMA_FLAGS_IE (1<<0) +#define DDMA_FLAGS_NOIE (1<<1) + #endif /* _LANGUAGE_ASSEMBLY */ #endif /* _AU1000_DBDMA_H_ */ diff --git a/include/asm-mips/mach-au1x00/au1xxx_gpio.h b/include/asm-mips/mach-au1x00/au1xxx_gpio.h new file mode 100644 index 000000000000..27911e054ffc --- /dev/null +++ b/include/asm-mips/mach-au1x00/au1xxx_gpio.h @@ -0,0 +1,20 @@ +#ifndef __AU1XXX_GPIO_H +#define __AU1XXX_GPIO_H + +void au1xxx_gpio1_set_inputs(void); +void au1xxx_gpio_tristate(int signal); +void au1xxx_gpio_write(int signal, int value); +int au1xxx_gpio_read(int signal); + +typedef volatile struct +{ + u32 dir; + u32 reserved; + u32 output; + u32 pinstate; + u32 inten; + u32 enable; + +} AU1X00_GPIO2; + +#endif //__AU1XXX_GPIO_H diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h new file mode 100644 index 000000000000..33d275c3b84c --- /dev/null +++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h @@ -0,0 +1,301 @@ +/* + * include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005 + * + * BRIEF MODULE DESCRIPTION + * AMD Alchemy Au1xxx IDE interface routines over the Static Bus + * + * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any later + * version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE + * Interface and Linux Device Driver" Application Note. + */ +#include <linux/config.h> + +#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA + #define DMA_WAIT_TIMEOUT 100 + #define NUM_DESCRIPTORS PRD_ENTRIES +#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */ + #define NUM_DESCRIPTORS 2 +#endif + +#ifndef AU1XXX_ATA_RQSIZE + #define AU1XXX_ATA_RQSIZE 128 +#endif + +/* Disable Burstable-Support for DBDMA */ +#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON + #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0 +#endif + +#ifdef CONFIG_PM +/* +* This will enable the device to be powered up when write() or read() +* is called. If this is not defined, the driver will return -EBUSY. +*/ +#define WAKE_ON_ACCESS 1 + +typedef struct +{ + spinlock_t lock; /* Used to block on state transitions */ + au1xxx_power_dev_t *dev; /* Power Managers device structure */ + unsigned stopped; /* USed to signaling device is stopped */ +} pm_state; +#endif + + +typedef struct +{ + u32 tx_dev_id, rx_dev_id, target_dev_id; + u32 tx_chan, rx_chan; + void *tx_desc_head, *rx_desc_head; + ide_hwif_t *hwif; +#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA + ide_drive_t *drive; + u8 white_list, black_list; + struct dbdma_cmd *dma_table_cpu; + dma_addr_t dma_table_dma; + struct scatterlist *sg_table; + int sg_nents; + int sg_dma_direction; +#endif + struct device *dev; + int irq; + u32 regbase; +#ifdef CONFIG_PM + pm_state pm; +#endif +} _auide_hwif; + +#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA +struct drive_list_entry { + const char * id_model; + const char * id_firmware; +}; + +/* HD white list */ +static const struct drive_list_entry dma_white_list [] = { +/* + * Hitachi + */ + { "HITACHI_DK14FA-20" , "ALL" }, + { "HTS726060M9AT00" , "ALL" }, +/* + * Maxtor + */ + { "Maxtor 6E040L0" , "ALL" }, + { "Maxtor 6Y080P0" , "ALL" }, + { "Maxtor 6Y160P0" , "ALL" }, +/* + * Seagate + */ + { "ST3120026A" , "ALL" }, + { "ST320014A" , "ALL" }, + { "ST94011A" , "ALL" }, + { "ST340016A" , "ALL" }, +/* + * Western Digital + */ + { "WDC WD400UE-00HCT0" , "ALL" }, + { "WDC WD400JB-00JJC0" , "ALL" }, + { NULL , NULL } +}; + +/* HD black list */ +static const struct drive_list_entry dma_black_list [] = { +/* + * Western Digital + */ + { "WDC WD100EB-00CGH0" , "ALL" }, + { "WDC WD200BB-00AUA1" , "ALL" }, + { "WDC AC24300L" , "ALL" }, + { NULL , NULL } +}; +#endif + +/* function prototyping */ +u8 auide_inb(unsigned long port); +u16 auide_inw(unsigned long port); +u32 auide_inl(unsigned long port); +void auide_insw(unsigned long port, void *addr, u32 count); +void auide_insl(unsigned long port, void *addr, u32 count); +void auide_outb(u8 addr, unsigned long port); +void auide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port); +void auide_outw(u16 addr, unsigned long port); +void auide_outl(u32 addr, unsigned long port); +void auide_outsw(unsigned long port, void *addr, u32 count); +void auide_outsl(unsigned long port, void *addr, u32 count); +static void auide_tune_drive(ide_drive_t *drive, byte pio); +static int auide_tune_chipset (ide_drive_t *drive, u8 speed); +static int auide_ddma_init( _auide_hwif *auide ); +static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif); +int __init auide_probe(void); + +#ifdef CONFIG_PM + int au1200ide_pm_callback( au1xxx_power_dev_t *dev, + au1xxx_request_t request, void *data); + static int au1xxxide_pm_standby( au1xxx_power_dev_t *dev ); + static int au1xxxide_pm_sleep( au1xxx_power_dev_t *dev ); + static int au1xxxide_pm_resume( au1xxx_power_dev_t *dev ); + static int au1xxxide_pm_getstatus( au1xxx_power_dev_t *dev ); + static int au1xxxide_pm_access( au1xxx_power_dev_t *dev ); + static int au1xxxide_pm_idle( au1xxx_power_dev_t *dev ); + static int au1xxxide_pm_cleanup( au1xxx_power_dev_t *dev ); +#endif + + +/* + * Multi-Word DMA + DbDMA functions + */ +#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA + + static int in_drive_list(struct hd_driveid *id, + const struct drive_list_entry *drive_table); + static int auide_build_sglist(ide_drive_t *drive, struct request *rq); + static int auide_build_dmatable(ide_drive_t *drive); + static int auide_dma_end(ide_drive_t *drive); + static void auide_dma_start(ide_drive_t *drive ); + ide_startstop_t auide_dma_intr (ide_drive_t *drive); + static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command); + static int auide_dma_setup(ide_drive_t *drive); + static int auide_dma_check(ide_drive_t *drive); + static int auide_dma_test_irq(ide_drive_t *drive); + static int auide_dma_host_off(ide_drive_t *drive); + static int auide_dma_host_on(ide_drive_t *drive); + static int auide_dma_lostirq(ide_drive_t *drive); + static int auide_dma_on(ide_drive_t *drive); + static void auide_ddma_tx_callback(int irq, void *param, + struct pt_regs *regs); + static void auide_ddma_rx_callback(int irq, void *param, + struct pt_regs *regs); + static int auide_dma_off_quietly(ide_drive_t *drive); + static int auide_dma_timeout(ide_drive_t *drive); + +#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ + +/******************************************************************************* +* PIO Mode timing calculation : * +* * +* Static Bus Spec ATA Spec * +* Tcsoe = t1 * +* Toecs = t9 * +* Twcs = t9 * +* Tcsh = t2i | t2 * +* Tcsoff = t2i | t2 * +* Twp = t2 * +* Tcsw = t1 * +* Tpm = 0 * +* Ta = t1+t2 * +*******************************************************************************/ + +#define TCSOE_MASK (0x07<<29) +#define TOECS_MASK (0x07<<26) +#define TWCS_MASK (0x07<<28) +#define TCSH_MASK (0x0F<<24) +#define TCSOFF_MASK (0x07<<20) +#define TWP_MASK (0x3F<<14) +#define TCSW_MASK (0x0F<<10) +#define TPM_MASK (0x0F<<6) +#define TA_MASK (0x3F<<0) +#define TS_MASK (1<<8) + +/* Timing parameters PIO mode 0 */ +#define SBC_IDE_PIO0_TCSOE (0x04<<29) +#define SBC_IDE_PIO0_TOECS (0x01<<26) +#define SBC_IDE_PIO0_TWCS (0x02<<28) +#define SBC_IDE_PIO0_TCSH (0x08<<24) +#define SBC_IDE_PIO0_TCSOFF (0x07<<20) +#define SBC_IDE_PIO0_TWP (0x10<<14) +#define SBC_IDE_PIO0_TCSW (0x04<<10) +#define SBC_IDE_PIO0_TPM (0x0<<6) +#define SBC_IDE_PIO0_TA (0x15<<0) +/* Timing parameters PIO mode 1 */ +#define SBC_IDE_PIO1_TCSOE (0x03<<29) +#define SBC_IDE_PIO1_TOECS (0x01<<26) +#define SBC_IDE_PIO1_TWCS (0x01<<28) +#define SBC_IDE_PIO1_TCSH (0x06<<24) +#define SBC_IDE_PIO1_TCSOFF (0x06<<20) +#define SBC_IDE_PIO1_TWP (0x08<<14) +#define SBC_IDE_PIO1_TCSW (0x03<<10) +#define SBC_IDE_PIO1_TPM (0x00<<6) +#define SBC_IDE_PIO1_TA (0x0B<<0) +/* Timing parameters PIO mode 2 */ +#define SBC_IDE_PIO2_TCSOE (0x05<<29) +#define SBC_IDE_PIO2_TOECS (0x01<<26) +#define SBC_IDE_PIO2_TWCS (0x01<<28) +#define SBC_IDE_PIO2_TCSH (0x07<<24) +#define SBC_IDE_PIO2_TCSOFF (0x07<<20) +#define SBC_IDE_PIO2_TWP (0x1F<<14) +#define SBC_IDE_PIO2_TCSW (0x05<<10) +#define SBC_IDE_PIO2_TPM (0x00<<6) +#define SBC_IDE_PIO2_TA (0x22<<0) +/* Timing parameters PIO mode 3 */ +#define SBC_IDE_PIO3_TCSOE (0x05<<29) +#define SBC_IDE_PIO3_TOECS (0x01<<26) +#define SBC_IDE_PIO3_TWCS (0x01<<28) +#define SBC_IDE_PIO3_TCSH (0x0D<<24) +#define SBC_IDE_PIO3_TCSOFF (0x0D<<20) +#define SBC_IDE_PIO3_TWP (0x15<<14) +#define SBC_IDE_PIO3_TCSW (0x05<<10) +#define SBC_IDE_PIO3_TPM (0x00<<6) +#define SBC_IDE_PIO3_TA (0x1A<<0) +/* Timing parameters PIO mode 4 */ +#define SBC_IDE_PIO4_TCSOE (0x04<<29) +#define SBC_IDE_PIO4_TOECS (0x01<<26) +#define SBC_IDE_PIO4_TWCS (0x01<<28) +#define SBC_IDE_PIO4_TCSH (0x04<<24) +#define SBC_IDE_PIO4_TCSOFF (0x04<<20) +#define SBC_IDE_PIO4_TWP (0x0D<<14) +#define SBC_IDE_PIO4_TCSW (0x03<<10) +#define SBC_IDE_PIO4_TPM (0x00<<6) +#define SBC_IDE_PIO4_TA (0x12<<0) +/* Timing parameters MDMA mode 0 */ +#define SBC_IDE_MDMA0_TCSOE (0x03<<29) +#define SBC_IDE_MDMA0_TOECS (0x01<<26) +#define SBC_IDE_MDMA0_TWCS (0x01<<28) +#define SBC_IDE_MDMA0_TCSH (0x07<<24) +#define SBC_IDE_MDMA0_TCSOFF (0x07<<20) +#define SBC_IDE_MDMA0_TWP (0x0C<<14) +#define SBC_IDE_MDMA0_TCSW (0x03<<10) +#define SBC_IDE_MDMA0_TPM (0x00<<6) +#define SBC_IDE_MDMA0_TA (0x0F<<0) +/* Timing parameters MDMA mode 1 */ +#define SBC_IDE_MDMA1_TCSOE (0x05<<29) +#define SBC_IDE_MDMA1_TOECS (0x01<<26) +#define SBC_IDE_MDMA1_TWCS (0x01<<28) +#define SBC_IDE_MDMA1_TCSH (0x05<<24) +#define SBC_IDE_MDMA1_TCSOFF (0x05<<20) +#define SBC_IDE_MDMA1_TWP (0x0F<<14) +#define SBC_IDE_MDMA1_TCSW (0x05<<10) +#define SBC_IDE_MDMA1_TPM (0x00<<6) +#define SBC_IDE_MDMA1_TA (0x15<<0) +/* Timing parameters MDMA mode 2 */ +#define SBC_IDE_MDMA2_TCSOE (0x04<<29) +#define SBC_IDE_MDMA2_TOECS (0x01<<26) +#define SBC_IDE_MDMA2_TWCS (0x01<<28) +#define SBC_IDE_MDMA2_TCSH (0x04<<24) +#define SBC_IDE_MDMA2_TCSOFF (0x04<<20) +#define SBC_IDE_MDMA2_TWP (0x0D<<14) +#define SBC_IDE_MDMA2_TCSW (0x04<<10) +#define SBC_IDE_MDMA2_TPM (0x00<<6) +#define SBC_IDE_MDMA2_TA (0x12<<0) + diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h index 283519dfdec4..8e5fb3c7da4d 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_psc.h +++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h @@ -33,6 +33,8 @@ #ifndef _AU1000_PSC_H_ #define _AU1000_PSC_H_ +#include <linux/config.h> + /* The PSC base addresses. */ #ifdef CONFIG_SOC_AU1550 #define PSC0_BASE_ADDR 0xb1a00000 diff --git a/include/asm-mips/mach-au1x00/ioremap.h b/include/asm-mips/mach-au1x00/ioremap.h new file mode 100644 index 000000000000..d3ec6274575a --- /dev/null +++ b/include/asm-mips/mach-au1x00/ioremap.h @@ -0,0 +1,32 @@ +/* + * include/asm-mips/mach-au1x00/ioremap.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef __ASM_MACH_AU1X00_IOREMAP_H +#define __ASM_MACH_AU1X00_IOREMAP_H + +#include <linux/config.h> +#include <linux/types.h> + +#ifdef CONFIG_64BIT_PHYS_ADDR +extern phys_t __fixup_bigphys_addr(phys_t, phys_t); +#else +static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) +{ + return phys_addr; +} +#endif + +/* + * Allow physical addresses to be fixed up to help 36-bit peripherals. + */ +static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) +{ + return __fixup_bigphys_addr(phys_addr, size); +} + +#endif /* __ASM_MACH_AU1X00_IOREMAP_H */ diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h new file mode 100644 index 000000000000..5d894376fc1a --- /dev/null +++ b/include/asm-mips/mach-db1x00/db1200.h @@ -0,0 +1,224 @@ +/* + * AMD Alchemy DB1200 Referrence Board + * Board Registers defines. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * + */ +#ifndef __ASM_DB1200_H +#define __ASM_DB1200_H + +#include <linux/types.h> + +// This is defined in au1000.h with bogus value +#undef AU1X00_EXTERNAL_INT + +#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX +#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX +#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX +#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX + +/* SPI and SMB are muxed on the Pb1200 board. + Refer to board documentation. + */ +#define SPI_PSC_BASE PSC0_BASE_ADDR +#define SMBUS_PSC_BASE PSC0_BASE_ADDR +/* AC97 and I2S are muxed on the Pb1200 board. + Refer to board documentation. + */ +#define AC97_PSC_BASE PSC1_BASE_ADDR +#define I2S_PSC_BASE PSC1_BASE_ADDR + +#define BCSR_KSEG1_ADDR 0xB9800000 + +typedef volatile struct +{ + /*00*/ u16 whoami; + u16 reserved0; + /*04*/ u16 status; + u16 reserved1; + /*08*/ u16 switches; + u16 reserved2; + /*0C*/ u16 resets; + u16 reserved3; + + /*10*/ u16 pcmcia; + u16 reserved4; + /*14*/ u16 board; + u16 reserved5; + /*18*/ u16 disk_leds; + u16 reserved6; + /*1C*/ u16 system; + u16 reserved7; + + /*20*/ u16 intclr; + u16 reserved8; + /*24*/ u16 intset; + u16 reserved9; + /*28*/ u16 intclr_mask; + u16 reserved10; + /*2C*/ u16 intset_mask; + u16 reserved11; + + /*30*/ u16 sig_status; + u16 reserved12; + /*34*/ u16 int_status; + u16 reserved13; + /*38*/ u16 reserved14; + u16 reserved15; + /*3C*/ u16 reserved16; + u16 reserved17; + +} BCSR; + +static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; + +/* + * Register bit definitions for the BCSRs + */ +#define BCSR_WHOAMI_DCID 0x000F +#define BCSR_WHOAMI_CPLD 0x00F0 +#define BCSR_WHOAMI_BOARD 0x0F00 + +#define BCSR_STATUS_PCMCIA0VS 0x0003 +#define BCSR_STATUS_PCMCIA1VS 0x000C +#define BCSR_STATUS_SWAPBOOT 0x0040 +#define BCSR_STATUS_FLASHBUSY 0x0100 +#define BCSR_STATUS_IDECBLID 0x0200 +#define BCSR_STATUS_SD0WP 0x0400 +#define BCSR_STATUS_U0RXD 0x1000 +#define BCSR_STATUS_U1RXD 0x2000 + +#define BCSR_SWITCHES_OCTAL 0x00FF +#define BCSR_SWITCHES_DIP_1 0x0080 +#define BCSR_SWITCHES_DIP_2 0x0040 +#define BCSR_SWITCHES_DIP_3 0x0020 +#define BCSR_SWITCHES_DIP_4 0x0010 +#define BCSR_SWITCHES_DIP_5 0x0008 +#define BCSR_SWITCHES_DIP_6 0x0004 +#define BCSR_SWITCHES_DIP_7 0x0002 +#define BCSR_SWITCHES_DIP_8 0x0001 +#define BCSR_SWITCHES_ROTARY 0x0F00 + +#define BCSR_RESETS_ETH 0x0001 +#define BCSR_RESETS_CAMERA 0x0002 +#define BCSR_RESETS_DC 0x0004 +#define BCSR_RESETS_IDE 0x0008 +#define BCSR_RESETS_TV 0x0010 +/* not resets but in the same register */ +#define BCSR_RESETS_PWMR1mUX 0x0800 +#define BCSR_RESETS_PCS0MUX 0x1000 +#define BCSR_RESETS_PCS1MUX 0x2000 +#define BCSR_RESETS_SPISEL 0x4000 + +#define BCSR_PCMCIA_PC0VPP 0x0003 +#define BCSR_PCMCIA_PC0VCC 0x000C +#define BCSR_PCMCIA_PC0DRVEN 0x0010 +#define BCSR_PCMCIA_PC0RST 0x0080 +#define BCSR_PCMCIA_PC1VPP 0x0300 +#define BCSR_PCMCIA_PC1VCC 0x0C00 +#define BCSR_PCMCIA_PC1DRVEN 0x1000 +#define BCSR_PCMCIA_PC1RST 0x8000 + +#define BCSR_BOARD_LCDVEE 0x0001 +#define BCSR_BOARD_LCDVDD 0x0002 +#define BCSR_BOARD_LCDBL 0x0004 +#define BCSR_BOARD_CAMSNAP 0x0010 +#define BCSR_BOARD_CAMPWR 0x0020 +#define BCSR_BOARD_SD0PWR 0x0040 + +#define BCSR_LEDS_DECIMALS 0x0003 +#define BCSR_LEDS_LED0 0x0100 +#define BCSR_LEDS_LED1 0x0200 +#define BCSR_LEDS_LED2 0x0400 +#define BCSR_LEDS_LED3 0x0800 + +#define BCSR_SYSTEM_POWEROFF 0x4000 +#define BCSR_SYSTEM_RESET 0x8000 + +/* Bit positions for the different interrupt sources */ +#define BCSR_INT_IDE 0x0001 +#define BCSR_INT_ETH 0x0002 +#define BCSR_INT_PC0 0x0004 +#define BCSR_INT_PC0STSCHG 0x0008 +#define BCSR_INT_PC1 0x0010 +#define BCSR_INT_PC1STSCHG 0x0020 +#define BCSR_INT_DC 0x0040 +#define BCSR_INT_FLASHBUSY 0x0080 +#define BCSR_INT_PC0INSERT 0x0100 +#define BCSR_INT_PC0EJECT 0x0200 +#define BCSR_INT_PC1INSERT 0x0400 +#define BCSR_INT_PC1EJECT 0x0800 +#define BCSR_INT_SD0INSERT 0x1000 +#define BCSR_INT_SD0EJECT 0x2000 + +#define AU1XXX_SMC91111_PHYS_ADDR (0x19000300) +#define AU1XXX_SMC91111_IRQ DB1200_ETH_INT + +#define AU1XXX_ATA_PHYS_ADDR (0x18800000) +#define AU1XXX_ATA_PHYS_LEN (0x100) +#define AU1XXX_ATA_REG_OFFSET (5) +#define AU1XXX_ATA_INT DB1200_IDE_INT +#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1; +#define AU1XXX_ATA_RQSIZE 128 + +#define NAND_PHYS_ADDR 0x20000000 + +/* + * External Interrupts for Pb1200 as of 8/6/2004. + * Bit positions in the CPLD registers can be calculated by taking + * the interrupt define and subtracting the DB1200_INT_BEGIN value. + * *example: IDE bis pos is = 64 - 64 + ETH bit pos is = 65 - 64 + */ +#define DB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1) +#define DB1200_IDE_INT (DB1200_INT_BEGIN + 0) +#define DB1200_ETH_INT (DB1200_INT_BEGIN + 1) +#define DB1200_PC0_INT (DB1200_INT_BEGIN + 2) +#define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3) +#define DB1200_PC1_INT (DB1200_INT_BEGIN + 4) +#define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5) +#define DB1200_DC_INT (DB1200_INT_BEGIN + 6) +#define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7) +#define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8) +#define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9) +#define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10) +#define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11) +#define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12) +#define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13) + +#define DB1200_INT_END (DB1200_INT_BEGIN + 15) + +/* For drivers/pcmcia/au1000_db1x00.c */ + +/* PCMCIA Db1x00 specific defines */ + +#define PCMCIA_MAX_SOCK 1 +#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) + +/* VPP/VCC */ +#define SET_VCC_VPP(VCC, VPP, SLOT)\ + ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) + +#define BOARD_PC0_INT DB1200_PC0_INT +#define BOARD_PC1_INT DB1200_PC1_INT +#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) + +#endif /* __ASM_DB1200_H */ + diff --git a/include/asm-mips/mach-dec/mc146818rtc.h b/include/asm-mips/mach-dec/mc146818rtc.h index a326f451253b..6d37a5675803 100644 --- a/include/asm-mips/mach-dec/mc146818rtc.h +++ b/include/asm-mips/mach-dec/mc146818rtc.h @@ -3,7 +3,7 @@ * * Copyright (C) 1998, 2001 by Ralf Baechle * Copyright (C) 1998 by Harald Koerfgen - * Copyright (C) 2002 Maciej W. Rozycki + * Copyright (C) 2002, 2005 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -14,23 +14,18 @@ #define __ASM_MIPS_DEC_RTC_DEC_H #include <linux/types.h> - #include <asm/addrspace.h> +#include <asm/dec/system.h> extern volatile u8 *dec_rtc_base; -extern unsigned long dec_kn_slot_size; -#define RTC_PORT(x) CPHYSADDR(dec_rtc_base) +#define RTC_PORT(x) CPHYSADDR((long)dec_rtc_base) #define RTC_IO_EXTENT dec_kn_slot_size #define RTC_IOMAPPED 0 #undef RTC_IRQ #define RTC_DEC_YEAR 0x3f /* Where we store the real year on DECs. */ -#include <linux/mc146818rtc.h> -#include <linux/module.h> -#include <linux/types.h> - static inline unsigned char CMOS_READ(unsigned long addr) { return dec_rtc_base[addr * 4]; diff --git a/include/asm-mips/mach-generic/cpu-feature-overrides.h b/include/asm-mips/mach-generic/cpu-feature-overrides.h index 0aecfd08e39a..7c185bb06f13 100644 --- a/include/asm-mips/mach-generic/cpu-feature-overrides.h +++ b/include/asm-mips/mach-generic/cpu-feature-overrides.h @@ -8,6 +8,6 @@ #ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H -/* Intensionally empty file ... */ +/* Intentionally empty file ... */ #endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h index cb2edd018ad6..961006948c7c 100644 --- a/include/asm-mips/mach-generic/ide.h +++ b/include/asm-mips/mach-generic/ide.h @@ -18,6 +18,7 @@ #include <linux/config.h> #include <linux/pci.h> #include <linux/stddef.h> +#include <asm/processor.h> #ifndef MAX_HWIFS # ifdef CONFIG_BLK_DEV_IDEPCI @@ -104,15 +105,71 @@ static __inline__ unsigned long ide_default_io_base(int index) /* MIPS port and memory-mapped I/O string operations. */ -#define __ide_insw insw -#define __ide_insl insl -#define __ide_outsw outsw -#define __ide_outsl outsl +static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size) +{ + if (cpu_has_dc_aliases) { + unsigned long end = addr + size; + for (; addr < end; addr += PAGE_SIZE) + flush_dcache_page(virt_to_page(addr)); + } +} + +static inline void __ide_insw(unsigned long port, void *addr, + unsigned int count) +{ + insw(port, addr, count); + __ide_flush_dcache_range((unsigned long)addr, count * 2); +} + +static inline void __ide_insl(unsigned long port, void *addr, unsigned int count) +{ + insl(port, addr, count); + __ide_flush_dcache_range((unsigned long)addr, count * 4); +} + +static inline void __ide_outsw(unsigned long port, const void *addr, + unsigned long count) +{ + outsw(port, addr, count); + __ide_flush_dcache_range((unsigned long)addr, count * 2); +} + +static inline void __ide_outsl(unsigned long port, const void *addr, + unsigned long count) +{ + outsl(port, addr, count); + __ide_flush_dcache_range((unsigned long)addr, count * 4); +} + +static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count) +{ + readsw(port, addr, count); + __ide_flush_dcache_range((unsigned long)addr, count * 2); +} + +static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count) +{ + readsl(port, addr, count); + __ide_flush_dcache_range((unsigned long)addr, count * 4); +} + +static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count) +{ + writesw(port, addr, count); + __ide_flush_dcache_range((unsigned long)addr, count * 2); +} + +static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count) +{ + writesl(port, addr, count); + __ide_flush_dcache_range((unsigned long)addr, count * 4); +} -#define __ide_mm_insw readsw -#define __ide_mm_insl readsl -#define __ide_mm_outsw writesw -#define __ide_mm_outsl writesl +/* ide_insw calls insw, not __ide_insw. Why? */ +#undef insw +#undef insl +#define insw(port, addr, count) __ide_insw(port, addr, count) +#define insl(port, addr, count) __ide_insl(port, addr, count) #endif /* __KERNEL__ */ diff --git a/include/asm-mips/mach-generic/ioremap.h b/include/asm-mips/mach-generic/ioremap.h new file mode 100644 index 000000000000..9b64ff6e485d --- /dev/null +++ b/include/asm-mips/mach-generic/ioremap.h @@ -0,0 +1,23 @@ +/* + * include/asm-mips/mach-generic/ioremap.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef __ASM_MACH_GENERIC_IOREMAP_H +#define __ASM_MACH_GENERIC_IOREMAP_H + +#include <linux/types.h> + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) +{ + return phys_addr; +} + +#endif /* __ASM_MACH_GENERIC_IOREMAP_H */ diff --git a/include/asm-mips/mach-generic/kernel-entry-init.h b/include/asm-mips/mach-generic/kernel-entry-init.h new file mode 100644 index 000000000000..7e66505fa574 --- /dev/null +++ b/include/asm-mips/mach-generic/kernel-entry-init.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005 Embedded Alley Solutions, Inc + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H +#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H + +/* Intentionally empty macro, used in head.S. Override in + * arch/mips/mach-xxx/kernel-entry-init.h when necessary. + */ +.macro kernel_entry_setup +.endm + +/* + * Do SMP slave processor setup necessary before we can savely execute C code. + */ + .macro smp_slave_setup + .endm + + +#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */ diff --git a/include/asm-mips/mach-generic/kmalloc.h b/include/asm-mips/mach-generic/kmalloc.h new file mode 100644 index 000000000000..373d66dee9d7 --- /dev/null +++ b/include/asm-mips/mach-generic/kmalloc.h @@ -0,0 +1,13 @@ +#ifndef __ASM_MACH_GENERIC_KMALLOC_H +#define __ASM_MACH_GENERIC_KMALLOC_H + +#include <linux/config.h> + +#ifndef CONFIG_DMA_COHERENT +/* + * Total overkill for most systems but need as a safe default. + */ +#define ARCH_KMALLOC_MINALIGN 128 +#endif + +#endif /* __ASM_MACH_GENERIC_KMALLOC_H */ diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h index 5a2c1efb4eb7..b849d8dd7e78 100644 --- a/include/asm-mips/mach-generic/spaces.h +++ b/include/asm-mips/mach-generic/spaces.h @@ -55,13 +55,13 @@ #endif #ifdef CONFIG_DMA_NONCOHERENT -#define CAC_BASE 0x9800000000000000 +#define CAC_BASE 0x9800000000000000UL #else -#define CAC_BASE 0xa800000000000000 +#define CAC_BASE 0xa800000000000000UL #endif -#define IO_BASE 0x9000000000000000 -#define UNCAC_BASE 0x9000000000000000 -#define MAP_BASE 0xc000000000000000 +#define IO_BASE 0x9000000000000000UL +#define UNCAC_BASE 0x9000000000000000UL +#define MAP_BASE 0xc000000000000000UL #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h index 3c8896d9b133..ab9714668177 100644 --- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip22/cpu-feature-overrides.h @@ -11,6 +11,12 @@ /* * IP22 with a variety of processors so we can't use defaults for everything. */ +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4kcache 1 +#define cpu_has_fpu 1 +#define cpu_has_32fpr 1 +#define cpu_has_counter 1 #define cpu_has_mips16 0 #define cpu_has_divec 0 #define cpu_has_cache_cdex_p 1 @@ -23,6 +29,8 @@ #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) #define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 + #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h index e96166f27c49..8385f716798d 100644 --- a/include/asm-mips/mach-ip22/spaces.h +++ b/include/asm-mips/mach-ip22/spaces.h @@ -44,7 +44,7 @@ #define CAC_BASE 0xffffffff80000000 #define IO_BASE 0xffffffffa0000000 #define UNCAC_BASE 0xffffffffa0000000 -#define MAP_BASE 0xffffffffc0000000 +#define MAP_BASE 0xc000000000000000 #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h index fe96d7358517..4c8a90051fd0 100644 --- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h @@ -25,6 +25,7 @@ #define cpu_has_vtag_icache 0 #define cpu_has_dc_aliases 0 #define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 #define cpu_icache_snoops_remote_store 1 #define cpu_has_nofpuex 0 diff --git a/include/asm-mips/mach-ip27/kernel-entry-init.h b/include/asm-mips/mach-ip27/kernel-entry-init.h new file mode 100644 index 000000000000..c1a10314b317 --- /dev/null +++ b/include/asm-mips/mach-ip27/kernel-entry-init.h @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 Silicon Graphics, Inc. + * Copyright (C) 2005 Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MACH_IP27_KERNEL_ENTRY_H +#define __ASM_MACH_IP27_KERNEL_ENTRY_H + +#include <asm/sn/addrs.h> +#include <asm/sn/sn0/hubni.h> +#include <asm/sn/klkernvars.h> + +/* + * Returns the local nasid into res. + */ + .macro GET_NASID_ASM res + dli \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID) + ld \res, (\res) + and \res, NSRI_NODEID_MASK + dsrl \res, NSRI_NODEID_SHFT + .endm + +/* + * Intentionally empty macro, used in head.S. Override in + * arch/mips/mach-xxx/kernel-entry-init.h when necessary. + */ + .macro kernel_entry_setup + GET_NASID_ASM t1 + move t2, t1 # text and data are here + MAPPED_KERNEL_SETUP_TLB + .endm + +/* + * Do SMP slave processor setup necessary before we can savely execute C code. + */ + .macro smp_slave_setup + GET_NASID_ASM t1 + dli t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \ + KLDIR_OFF_POINTER + CAC_BASE + dsll t1, NASID_SHFT + or t0, t0, t1 + ld t0, 0(t0) # t0 points to kern_vars struct + lh t1, KV_RO_NASID_OFFSET(t0) + lh t2, KV_RW_NASID_OFFSET(t0) + MAPPED_KERNEL_SETUP_TLB + ARC64_TWIDDLE_PC + .endm + +#endif /* __ASM_MACH_IP27_KERNEL_ENTRY_H */ diff --git a/include/asm-mips/mach-ip27/kmalloc.h b/include/asm-mips/mach-ip27/kmalloc.h new file mode 100644 index 000000000000..426bd049b2d7 --- /dev/null +++ b/include/asm-mips/mach-ip27/kmalloc.h @@ -0,0 +1,8 @@ +#ifndef __ASM_MACH_IP27_KMALLOC_H +#define __ASM_MACH_IP27_KMALLOC_H + +/* + * All happy, no need to define ARCH_KMALLOC_MINALIGN + */ + +#endif /* __ASM_MACH_IP27_KMALLOC_H */ diff --git a/include/asm-mips/mach-ip27/mmzone.h b/include/asm-mips/mach-ip27/mmzone.h index d3f566362e9d..986a3b9b59a7 100644 --- a/include/asm-mips/mach-ip27/mmzone.h +++ b/include/asm-mips/mach-ip27/mmzone.h @@ -10,7 +10,6 @@ #define LEVELS_PER_SLICE 128 struct slice_data { - unsigned long irq_alloc_mask[2]; unsigned long irq_enable_mask[2]; int level_to_irq[LEVELS_PER_SLICE]; }; @@ -20,6 +19,7 @@ struct hub_data { DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW); cpumask_t h_cpus; unsigned long slice_map; + unsigned long irq_alloc_mask[2]; struct slice_data slice[2]; }; diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h index e3b3fe32eeb1..45e61785ef42 100644 --- a/include/asm-mips/mach-ip27/spaces.h +++ b/include/asm-mips/mach-ip27/spaces.h @@ -20,6 +20,7 @@ #define IO_BASE 0x9200000000000000 #define MSPEC_BASE 0x9400000000000000 #define UNCAC_BASE 0x9600000000000000 +#define MAP_BASE 0xc000000000000000 #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h index a70a81257c3d..82141c711c33 100644 --- a/include/asm-mips/mach-ip27/topology.h +++ b/include/asm-mips/mach-ip27/topology.h @@ -9,6 +9,9 @@ #define parent_node(node) (node) #define node_to_cpumask(node) (hub_data(node)->h_cpus) #define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node))) +struct pci_bus; +extern int pcibus_to_node(struct pci_bus *); + #define pcibus_to_cpumask(bus) (cpu_online_map) extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES]; diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h index 04713973c6c3..ab37fc1842ba 100644 --- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h @@ -37,5 +37,6 @@ #define cpu_has_ejtag 0 #define cpu_has_vtag_icache 0 #define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 #endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-ip32/kmalloc.h b/include/asm-mips/mach-ip32/kmalloc.h new file mode 100644 index 000000000000..9d2d4d9ac036 --- /dev/null +++ b/include/asm-mips/mach-ip32/kmalloc.h @@ -0,0 +1,12 @@ +#ifndef __ASM_MACH_IP32_KMALLOC_H +#define __ASM_MACH_IP32_KMALLOC_H + +#include <linux/config.h> + +#if defined(CONFIG_CPU_R5000) || defined (CONFIG_CPU_RM7000) +#define ARCH_KMALLOC_MINALIGN 32 +#else +#define ARCH_KMALLOC_MINALIGN 128 +#endif + +#endif /* __ASM_MACH_IP32_KMALLOC_H */ diff --git a/include/asm-mips/mach-ip32/spaces.h b/include/asm-mips/mach-ip32/spaces.h index c7839f85c68d..44abe5c02389 100644 --- a/include/asm-mips/mach-ip32/spaces.h +++ b/include/asm-mips/mach-ip32/spaces.h @@ -19,10 +19,10 @@ #define HIGHMEM_START (1UL << 59UL) #endif -#define CAC_BASE 0x9800000000000000 -#define IO_BASE 0x9000000000000000 -#define UNCAC_BASE 0x9000000000000000 -#define MAP_BASE 0xc000000000000000 +#define CAC_BASE 0x9800000000000000UL +#define IO_BASE 0x9000000000000000UL +#define UNCAC_BASE 0x9000000000000000UL +#define MAP_BASE 0xc000000000000000UL #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) diff --git a/include/asm-mips/mach-ja/cpu-feature-overrides.h b/include/asm-mips/mach-ja/cpu-feature-overrides.h index ca57e7db98bb..a0fde405d4c4 100644 --- a/include/asm-mips/mach-ja/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ja/cpu-feature-overrides.h @@ -25,6 +25,7 @@ #define cpu_has_vtag_icache 0 #define cpu_has_dc_aliases 0 #define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 #define cpu_icache_snoops_remote_store 0 #define cpu_has_nofpuex 0 @@ -36,10 +37,4 @@ #define cpu_icache_line_size() 32 #define cpu_scache_line_size() 32 -/* - * On the RM9000 we need to ensure that I-cache lines being fetches only - * contain valid instructions are funny things will happen. - */ -#define PLAT_TRAMPOLINE_STUFF_LINE 32UL - #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-mips/cpu-feature-overrides.h index 6f51be571bf0..9f92aed17754 100644 --- a/include/asm-mips/mach-mips/cpu-feature-overrides.h +++ b/include/asm-mips/mach-mips/cpu-feature-overrides.h @@ -17,7 +17,7 @@ #ifdef CONFIG_CPU_MIPS32 #define cpu_has_tlb 1 #define cpu_has_4kex 1 -#define cpu_has_4ktlb 1 +#define cpu_has_4kcache 1 /* #define cpu_has_fpu ? */ /* #define cpu_has_32fpr ? */ #define cpu_has_counter 1 @@ -37,12 +37,13 @@ /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ /* #define cpu_has_subset_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 #endif #ifdef CONFIG_CPU_MIPS64 #define cpu_has_tlb 1 #define cpu_has_4kex 1 -#define cpu_has_4ktlb 1 +#define cpu_has_4kcache 1 /* #define cpu_has_fpu ? */ /* #define cpu_has_32fpr ? */ #define cpu_has_counter 1 @@ -62,6 +63,7 @@ /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ /* #define cpu_has_subset_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 #endif #endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-mips/irq.h b/include/asm-mips/mach-mips/irq.h new file mode 100644 index 000000000000..f8579696ca54 --- /dev/null +++ b/include/asm-mips/mach-mips/irq.h @@ -0,0 +1,14 @@ +#ifndef __ASM_MACH_MIPS_IRQ_H +#define __ASM_MACH_MIPS_IRQ_H + +#include <linux/config.h> + +#define NR_IRQS 256 + +#ifdef CONFIG_SMP + +#define ARCH_HAS_IRQ_PER_CPU + +#endif + +#endif /* __ASM_MACH_MIPS_IRQ_H */ diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h index 7473512384bc..825c5f674dfc 100644 --- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h @@ -28,6 +28,7 @@ #define cpu_has_vtag_icache 0 #define cpu_has_dc_aliases 0 #define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 #define cpu_icache_snoops_remote_store 0 #define cpu_has_nofpuex 0 @@ -39,10 +40,4 @@ #define cpu_icache_line_size() 32 #define cpu_scache_line_size() 32 -/* - * On the RM9000 we need to ensure that I-cache lines being fetches only - * contain valid instructions are funny things will happen. - */ -#define PLAT_TRAMPOLINE_STUFF_LINE 32UL - #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h new file mode 100644 index 000000000000..9a3088b19bf3 --- /dev/null +++ b/include/asm-mips/mach-pb1x00/pb1200.h @@ -0,0 +1,252 @@ +/* + * AMD Alchemy PB1200 Referrence Board + * Board Registers defines. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * + */ +#ifndef __ASM_PB1200_H +#define __ASM_PB1200_H + +#include <linux/types.h> + +// This is defined in au1000.h with bogus value +#undef AU1X00_EXTERNAL_INT + +#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX +#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX +#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX +#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX + +/* SPI and SMB are muxed on the Pb1200 board. + Refer to board documentation. + */ +#define SPI_PSC_BASE PSC0_BASE_ADDR +#define SMBUS_PSC_BASE PSC0_BASE_ADDR +/* AC97 and I2S are muxed on the Pb1200 board. + Refer to board documentation. + */ +#define AC97_PSC_BASE PSC1_BASE_ADDR +#define I2S_PSC_BASE PSC1_BASE_ADDR + +#define BCSR_KSEG1_ADDR 0xAD800000 + +typedef volatile struct +{ + /*00*/ u16 whoami; + u16 reserved0; + /*04*/ u16 status; + u16 reserved1; + /*08*/ u16 switches; + u16 reserved2; + /*0C*/ u16 resets; + u16 reserved3; + + /*10*/ u16 pcmcia; + u16 reserved4; + /*14*/ u16 board; + u16 reserved5; + /*18*/ u16 disk_leds; + u16 reserved6; + /*1C*/ u16 system; + u16 reserved7; + + /*20*/ u16 intclr; + u16 reserved8; + /*24*/ u16 intset; + u16 reserved9; + /*28*/ u16 intclr_mask; + u16 reserved10; + /*2C*/ u16 intset_mask; + u16 reserved11; + + /*30*/ u16 sig_status; + u16 reserved12; + /*34*/ u16 int_status; + u16 reserved13; + /*38*/ u16 reserved14; + u16 reserved15; + /*3C*/ u16 reserved16; + u16 reserved17; + +} BCSR; + +static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; + +/* + * Register bit definitions for the BCSRs + */ +#define BCSR_WHOAMI_DCID 0x000F +#define BCSR_WHOAMI_CPLD 0x00F0 +#define BCSR_WHOAMI_BOARD 0x0F00 + +#define BCSR_STATUS_PCMCIA0VS 0x0003 +#define BCSR_STATUS_PCMCIA1VS 0x000C +#define BCSR_STATUS_SWAPBOOT 0x0040 +#define BCSR_STATUS_FLASHBUSY 0x0100 +#define BCSR_STATUS_IDECBLID 0x0200 +#define BCSR_STATUS_SD0WP 0x0400 +#define BCSR_STATUS_SD1WP 0x0800 +#define BCSR_STATUS_U0RXD 0x1000 +#define BCSR_STATUS_U1RXD 0x2000 + +#define BCSR_SWITCHES_OCTAL 0x00FF +#define BCSR_SWITCHES_DIP_1 0x0080 +#define BCSR_SWITCHES_DIP_2 0x0040 +#define BCSR_SWITCHES_DIP_3 0x0020 +#define BCSR_SWITCHES_DIP_4 0x0010 +#define BCSR_SWITCHES_DIP_5 0x0008 +#define BCSR_SWITCHES_DIP_6 0x0004 +#define BCSR_SWITCHES_DIP_7 0x0002 +#define BCSR_SWITCHES_DIP_8 0x0001 +#define BCSR_SWITCHES_ROTARY 0x0F00 + +#define BCSR_RESETS_ETH 0x0001 +#define BCSR_RESETS_CAMERA 0x0002 +#define BCSR_RESETS_DC 0x0004 +#define BCSR_RESETS_IDE 0x0008 +/* not resets but in the same register */ +#define BCSR_RESETS_WSCFSM 0x0800 +#define BCSR_RESETS_PCS0MUX 0x1000 +#define BCSR_RESETS_PCS1MUX 0x2000 +#define BCSR_RESETS_SPISEL 0x4000 +#define BCSR_RESETS_SD1MUX 0x8000 + +#define BCSR_PCMCIA_PC0VPP 0x0003 +#define BCSR_PCMCIA_PC0VCC 0x000C +#define BCSR_PCMCIA_PC0DRVEN 0x0010 +#define BCSR_PCMCIA_PC0RST 0x0080 +#define BCSR_PCMCIA_PC1VPP 0x0300 +#define BCSR_PCMCIA_PC1VCC 0x0C00 +#define BCSR_PCMCIA_PC1DRVEN 0x1000 +#define BCSR_PCMCIA_PC1RST 0x8000 + +#define BCSR_BOARD_LCDVEE 0x0001 +#define BCSR_BOARD_LCDVDD 0x0002 +#define BCSR_BOARD_LCDBL 0x0004 +#define BCSR_BOARD_CAMSNAP 0x0010 +#define BCSR_BOARD_CAMPWR 0x0020 +#define BCSR_BOARD_SD0PWR 0x0040 +#define BCSR_BOARD_SD1PWR 0x0080 + +#define BCSR_LEDS_DECIMALS 0x00FF +#define BCSR_LEDS_LED0 0x0100 +#define BCSR_LEDS_LED1 0x0200 +#define BCSR_LEDS_LED2 0x0400 +#define BCSR_LEDS_LED3 0x0800 + +#define BCSR_SYSTEM_VDDI 0x001F +#define BCSR_SYSTEM_POWEROFF 0x4000 +#define BCSR_SYSTEM_RESET 0x8000 + +/* Bit positions for the different interrupt sources */ +#define BCSR_INT_IDE 0x0001 +#define BCSR_INT_ETH 0x0002 +#define BCSR_INT_PC0 0x0004 +#define BCSR_INT_PC0STSCHG 0x0008 +#define BCSR_INT_PC1 0x0010 +#define BCSR_INT_PC1STSCHG 0x0020 +#define BCSR_INT_DC 0x0040 +#define BCSR_INT_FLASHBUSY 0x0080 +#define BCSR_INT_PC0INSERT 0x0100 +#define BCSR_INT_PC0EJECT 0x0200 +#define BCSR_INT_PC1INSERT 0x0400 +#define BCSR_INT_PC1EJECT 0x0800 +#define BCSR_INT_SD0INSERT 0x1000 +#define BCSR_INT_SD0EJECT 0x2000 +#define BCSR_INT_SD1INSERT 0x4000 +#define BCSR_INT_SD1EJECT 0x8000 + +/* PCMCIA Db1x00 specific defines */ +#define PCMCIA_MAX_SOCK 1 +#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) + +/* VPP/VCC */ +#define SET_VCC_VPP(VCC, VPP, SLOT)\ + ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) + +#define AU1XXX_SMC91111_PHYS_ADDR (0x0D000300) +#define AU1XXX_SMC91111_IRQ PB1200_ETH_INT + +#define AU1XXX_ATA_PHYS_ADDR (0x0C800000) +#define AU1XXX_ATA_PHYS_LEN (0x100) +#define AU1XXX_ATA_REG_OFFSET (5) +#define AU1XXX_ATA_INT PB1200_IDE_INT +#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1; +#define AU1XXX_ATA_RQSIZE 128 + +#define NAND_PHYS_ADDR 0x1C000000 + +/* Timing values as described in databook, * ns value stripped of + * lower 2 bits. + * These defines are here rather than an SOC1200 generic file because + * the parts chosen on another board may be different and may require + * different timings. + */ +#define NAND_T_H (18 >> 2) +#define NAND_T_PUL (30 >> 2) +#define NAND_T_SU (30 >> 2) +#define NAND_T_WH (30 >> 2) + +/* Bitfield shift amounts */ +#define NAND_T_H_SHIFT 0 +#define NAND_T_PUL_SHIFT 4 +#define NAND_T_SU_SHIFT 8 +#define NAND_T_WH_SHIFT 12 + +#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ + ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ + ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ + ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) + + +/* + * External Interrupts for Pb1200 as of 8/6/2004. + * Bit positions in the CPLD registers can be calculated by taking + * the interrupt define and subtracting the PB1200_INT_BEGIN value. + * *example: IDE bis pos is = 64 - 64 + ETH bit pos is = 65 - 64 + */ +#define PB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1) +#define PB1200_IDE_INT (PB1200_INT_BEGIN + 0) +#define PB1200_ETH_INT (PB1200_INT_BEGIN + 1) +#define PB1200_PC0_INT (PB1200_INT_BEGIN + 2) +#define PB1200_PC0_STSCHG_INT (PB1200_INT_BEGIN + 3) +#define PB1200_PC1_INT (PB1200_INT_BEGIN + 4) +#define PB1200_PC1_STSCHG_INT (PB1200_INT_BEGIN + 5) +#define PB1200_DC_INT (PB1200_INT_BEGIN + 6) +#define PB1200_FLASHBUSY_INT (PB1200_INT_BEGIN + 7) +#define PB1200_PC0_INSERT_INT (PB1200_INT_BEGIN + 8) +#define PB1200_PC0_EJECT_INT (PB1200_INT_BEGIN + 9) +#define PB1200_PC1_INSERT_INT (PB1200_INT_BEGIN + 10) +#define PB1200_PC1_EJECT_INT (PB1200_INT_BEGIN + 11) +#define PB1200_SD0_INSERT_INT (PB1200_INT_BEGIN + 12) +#define PB1200_SD0_EJECT_INT (PB1200_INT_BEGIN + 13) +#define PB1200_SD1_INSERT_INT (PB1200_INT_BEGIN + 14) +#define PB1200_SD1_EJECT_INT (PB1200_INT_BEGIN + 15) + +#define PB1200_INT_END (PB1200_INT_BEGIN + 15) + +/* For drivers/pcmcia/au1000_db1x00.c */ +#define BOARD_PC0_INT PB1200_PC0_INT +#define BOARD_PC1_INT PB1200_PC1_INT +#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) + +#endif /* __ASM_PB1200_H */ + diff --git a/include/asm-mips/mach-pnx8550/cm.h b/include/asm-mips/mach-pnx8550/cm.h new file mode 100644 index 000000000000..bb0a56c7d011 --- /dev/null +++ b/include/asm-mips/mach-pnx8550/cm.h @@ -0,0 +1,43 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Clock module specific definitions + * + * Author: source@mvista.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ + +#ifndef __PNX8550_CM_H +#define __PNX8550_CM_H + +#define PNX8550_CM_BASE 0xBBE47000 + +#define PNX8550_CM_PLL0_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000) +#define PNX8550_CM_PLL1_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004) +#define PNX8550_CM_PLL2_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008) +#define PNX8550_CM_PLL3_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C) + +// Table not complete..... + +#define PNX8550_CM_PLL_BLOCKED_MASK 0x80000000 +#define PNX8550_CM_PLL_LOCK_MASK 0x40000000 +#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000 +#define PNX8550_CM_PLL_N_MASK 0x01ff0000 +#define PNX8550_CM_PLL_M_MASK 0x00003f00 +#define PNX8550_CM_PLL_P_MASK 0x0000000c +#define PNX8550_CM_PLL_PD_MASK 0x00000002 + + +#endif diff --git a/include/asm-mips/mach-pnx8550/glb.h b/include/asm-mips/mach-pnx8550/glb.h new file mode 100644 index 000000000000..07aa85e609bc --- /dev/null +++ b/include/asm-mips/mach-pnx8550/glb.h @@ -0,0 +1,86 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * PNX8550 global definitions + * + * Author: source@mvista.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ + +#ifndef __PNX8550_GLB_H +#define __PNX8550_GLB_H + +#define PNX8550_GLB1_BASE 0xBBE63000 +#define PNX8550_GLB2_BASE 0xBBE4d000 +#define PNX8550_RESET_BASE 0xBBE60000 + +/* PCI Inta Output Enable Registers */ +#define PNX8550_GLB2_ENAB_INTA_O *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050) + +/* Bit 1:Enable DAC Powerdown + 0:DACs are enabled and are working normally + 1:DACs are powerdown +*/ +#define PNX8550_GLB_DAC_PD 0x2 +/* Bit 0:Enable of PCI inta output + 0 = Disable PCI inta output + 1 = Enable PCI inta output +*/ +#define PNX8550_GLB_ENABLE_INTA_O 0x1 + +/* PCI Direct Mappings */ +#define PNX8550_PCIMEM 0x12000000 +#define PNX8550_PCIMEM_SIZE 0x08000000 +#define PNX8550_PCIIO 0x1c000000 +#define PNX8550_PCIIO_SIZE 0x02000000 /* 32M */ + +#define PNX8550_PORT_BASE KSEG1 + +// GPIO def +#define PNX8550_GPIO_BASE 0x1Be00000 + +#define PNX8550_GPIO_DIRQ0 (PNX8550_GPIO_BASE + 0x104500) +#define PNX8550_GPIO_MC1 (PNX8550_GPIO_BASE + 0x104004) +#define PNX8550_GPIO_MC_31_BIT 30 +#define PNX8550_GPIO_MC_30_BIT 28 +#define PNX8550_GPIO_MC_29_BIT 26 +#define PNX8550_GPIO_MC_28_BIT 24 +#define PNX8550_GPIO_MC_27_BIT 22 +#define PNX8550_GPIO_MC_26_BIT 20 +#define PNX8550_GPIO_MC_25_BIT 18 +#define PNX8550_GPIO_MC_24_BIT 16 +#define PNX8550_GPIO_MC_23_BIT 14 +#define PNX8550_GPIO_MC_22_BIT 12 +#define PNX8550_GPIO_MC_21_BIT 10 +#define PNX8550_GPIO_MC_20_BIT 8 +#define PNX8550_GPIO_MC_19_BIT 6 +#define PNX8550_GPIO_MC_18_BIT 4 +#define PNX8550_GPIO_MC_17_BIT 2 +#define PNX8550_GPIO_MC_16_BIT 0 + +#define PNX8550_GPIO_MODE_PRIMOP 0x1 +#define PNX8550_GPIO_MODE_NO_OPENDR 0x2 +#define PNX8550_GPIO_MODE_OPENDR 0x3 + +// RESET module +#define PNX8550_RST_CTL *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0) +#define PNX8550_RST_CAUSE *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4) +#define PNX8550_RST_EN_WATCHDOG *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8) + +#define PNX8550_RST_REL_MIPS_RST_N 0x8 +#define PNX8550_RST_DO_SW_RST 0x4 +#define PNX8550_RST_REL_SYS_RST_OUT 0x2 +#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1 +#endif diff --git a/include/asm-mips/mach-pnx8550/int.h b/include/asm-mips/mach-pnx8550/int.h new file mode 100644 index 000000000000..0e0668b524f4 --- /dev/null +++ b/include/asm-mips/mach-pnx8550/int.h @@ -0,0 +1,140 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Interrupt specific definitions + * + * Author: source@mvista.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ + +#ifndef __PNX8550_INT_H +#define __PNX8550_INT_H + +#define PNX8550_GIC_BASE 0xBBE3E000 + +#define PNX8550_GIC_PRIMASK_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000) +#define PNX8550_GIC_PRIMASK_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004) +#define PNX8550_GIC_VECTOR_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100) +#define PNX8550_GIC_VECTOR_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104) +#define PNX8550_GIC_PEND_1_31 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200) +#define PNX8550_GIC_PEND_32_63 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204) +#define PNX8550_GIC_PEND_64_70 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208) +#define PNX8550_GIC_FEATURES *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300) +#define PNX8550_GIC_REQ(x) *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4) +#define PNX8550_GIC_MOD_ID *(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC) + +// cp0 is two software + six hw exceptions +#define PNX8550_INT_CP0_TOTINT 8 +#define PNX8550_INT_CP0_MIN 0 +#define PNX8550_INT_CP0_MAX (PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1) + +#define MIPS_CPU_GIC_IRQ 2 +#define MIPS_CPU_TIMER_IRQ 7 + +// GIC are 71 exceptions connected to cp0's first hardware exception +#define PNX8550_INT_GIC_TOTINT 71 +#define PNX8550_INT_GIC_MIN (PNX8550_INT_CP0_MAX+1) +#define PNX8550_INT_GIC_MAX (PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1) + +#define PNX8550_INT_UNDEF (PNX8550_INT_GIC_MIN+0) +#define PNX8550_INT_IPC_TARGET0_MIPS (PNX8550_INT_GIC_MIN+1) +#define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2) +#define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3) +#define PNX8550_INT_RESERVED_4 (PNX8550_INT_GIC_MIN+4) +#define PNX8550_INT_USB (PNX8550_INT_GIC_MIN+5) +#define PNX8550_INT_GPIO_EQ1 (PNX8550_INT_GIC_MIN+6) +#define PNX8550_INT_GPIO_EQ2 (PNX8550_INT_GIC_MIN+7) +#define PNX8550_INT_GPIO_EQ3 (PNX8550_INT_GIC_MIN+8) +#define PNX8550_INT_GPIO_EQ4 (PNX8550_INT_GIC_MIN+9) + +#define PNX8550_INT_GPIO_EQ5 (PNX8550_INT_GIC_MIN+10) +#define PNX8550_INT_GPIO_EQ6 (PNX8550_INT_GIC_MIN+11) +#define PNX8550_INT_RESERVED_12 (PNX8550_INT_GIC_MIN+12) +#define PNX8550_INT_QVCP1 (PNX8550_INT_GIC_MIN+13) +#define PNX8550_INT_QVCP2 (PNX8550_INT_GIC_MIN+14) +#define PNX8550_INT_I2C1 (PNX8550_INT_GIC_MIN+15) +#define PNX8550_INT_I2C2 (PNX8550_INT_GIC_MIN+16) +#define PNX8550_INT_ISO_UART1 (PNX8550_INT_GIC_MIN+17) +#define PNX8550_INT_ISO_UART2 (PNX8550_INT_GIC_MIN+18) +#define PNX8550_INT_UART1 (PNX8550_INT_GIC_MIN+19) + +#define PNX8550_INT_UART2 (PNX8550_INT_GIC_MIN+20) +#define PNX8550_INT_QNTR (PNX8550_INT_GIC_MIN+21) +#define PNX8550_INT_RESERVED22 (PNX8550_INT_GIC_MIN+22) +#define PNX8550_INT_T_DSC (PNX8550_INT_GIC_MIN+23) +#define PNX8550_INT_M_DSC (PNX8550_INT_GIC_MIN+24) +#define PNX8550_INT_RESERVED25 (PNX8550_INT_GIC_MIN+25) +#define PNX8550_INT_2D_DRAW_ENG (PNX8550_INT_GIC_MIN+26) +#define PNX8550_INT_MEM_BASED_SCALAR1 (PNX8550_INT_GIC_MIN+27) +#define PNX8550_INT_VIDEO_MPEG (PNX8550_INT_GIC_MIN+28) +#define PNX8550_INT_VIDEO_INPUT_P1 (PNX8550_INT_GIC_MIN+29) + +#define PNX8550_INT_VIDEO_INPUT_P2 (PNX8550_INT_GIC_MIN+30) +#define PNX8550_INT_SPDI1 (PNX8550_INT_GIC_MIN+31) +#define PNX8550_INT_SPDO (PNX8550_INT_GIC_MIN+32) +#define PNX8550_INT_AUDIO_INPUT1 (PNX8550_INT_GIC_MIN+33) +#define PNX8550_INT_AUDIO_OUTPUT1 (PNX8550_INT_GIC_MIN+34) +#define PNX8550_INT_AUDIO_INPUT2 (PNX8550_INT_GIC_MIN+35) +#define PNX8550_INT_AUDIO_OUTPUT2 (PNX8550_INT_GIC_MIN+36) +#define PNX8550_INT_MEMBASED_SCALAR2 (PNX8550_INT_GIC_MIN+37) +#define PNX8550_INT_VPK (PNX8550_INT_GIC_MIN+38) +#define PNX8550_INT_MPEG1_MIPS (PNX8550_INT_GIC_MIN+39) + +#define PNX8550_INT_MPEG1_TM (PNX8550_INT_GIC_MIN+40) +#define PNX8550_INT_MPEG2_MIPS (PNX8550_INT_GIC_MIN+41) +#define PNX8550_INT_MPEG2_TM (PNX8550_INT_GIC_MIN+42) +#define PNX8550_INT_TS_DMA (PNX8550_INT_GIC_MIN+43) +#define PNX8550_INT_EDMA (PNX8550_INT_GIC_MIN+44) +#define PNX8550_INT_TM_DEBUG1 (PNX8550_INT_GIC_MIN+45) +#define PNX8550_INT_TM_DEBUG2 (PNX8550_INT_GIC_MIN+46) +#define PNX8550_INT_PCI_INTA (PNX8550_INT_GIC_MIN+47) +#define PNX8550_INT_CLOCK_MODULE (PNX8550_INT_GIC_MIN+48) +#define PNX8550_INT_PCI_XIO_INTA_PCI (PNX8550_INT_GIC_MIN+49) + +#define PNX8550_INT_PCI_XIO_INTB_DMA (PNX8550_INT_GIC_MIN+50) +#define PNX8550_INT_PCI_XIO_INTC_GPPM (PNX8550_INT_GIC_MIN+51) +#define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52) +#define PNX8550_INT_DVD_CSS (PNX8550_INT_GIC_MIN+53) +#define PNX8550_INT_VLD (PNX8550_INT_GIC_MIN+54) +#define PNX8550_INT_GPIO_TSU_7_0 (PNX8550_INT_GIC_MIN+55) +#define PNX8550_INT_GPIO_TSU_15_8 (PNX8550_INT_GIC_MIN+56) +#define PNX8550_INT_GPIO_CTU_IR (PNX8550_INT_GIC_MIN+57) +#define PNX8550_INT_GPIO0 (PNX8550_INT_GIC_MIN+58) +#define PNX8550_INT_GPIO1 (PNX8550_INT_GIC_MIN+59) + +#define PNX8550_INT_GPIO2 (PNX8550_INT_GIC_MIN+60) +#define PNX8550_INT_GPIO3 (PNX8550_INT_GIC_MIN+61) +#define PNX8550_INT_GPIO4 (PNX8550_INT_GIC_MIN+62) +#define PNX8550_INT_GPIO5 (PNX8550_INT_GIC_MIN+63) +#define PNX8550_INT_GPIO6 (PNX8550_INT_GIC_MIN+64) +#define PNX8550_INT_GPIO7 (PNX8550_INT_GIC_MIN+65) +#define PNX8550_INT_PMAN_SECURITY (PNX8550_INT_GIC_MIN+66) +#define PNX8550_INT_I2C3 (PNX8550_INT_GIC_MIN+67) +#define PNX8550_INT_RESERVED_68 (PNX8550_INT_GIC_MIN+68) +#define PNX8550_INT_SPDI2 (PNX8550_INT_GIC_MIN+69) + +#define PNX8550_INT_I2C4 (PNX8550_INT_GIC_MIN+70) + +// Timer are 3 exceptions connected to cp0's 7th hardware exception +#define PNX8550_INT_TIMER_TOTINT 3 +#define PNX8550_INT_TIMER_MIN (PNX8550_INT_GIC_MAX+1) +#define PNX8550_INT_TIMER_MAX (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1) + +#define PNX8550_INT_TIMER1 (PNX8550_INT_TIMER_MIN+0) +#define PNX8550_INT_TIMER2 (PNX8550_INT_TIMER_MIN+1) +#define PNX8550_INT_TIMER3 (PNX8550_INT_TIMER_MIN+2) +#define PNX8550_INT_WATCHDOG PNX8550_INT_TIMER3 + +#endif diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h new file mode 100644 index 000000000000..57102fa9da51 --- /dev/null +++ b/include/asm-mips/mach-pnx8550/kernel-entry-init.h @@ -0,0 +1,262 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005 Embedded Alley Solutions, Inc + */ +#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H +#define __ASM_MACH_KERNEL_ENTRY_INIT_H + +#include <asm/cacheops.h> +#include <asm/addrspace.h> + +#define CO_CONFIGPR_VALID 0x3F1F41FF /* valid bits to write to ConfigPR */ +#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; +#define CACHE_OPC 0xBC000000 /* MIPS cache instruction opcode */ +#define ICACHE_LINE_SIZE 32 /* Instruction cache line size bytes */ +#define DCACHE_LINE_SIZE 32 /* Data cache line size in bytes */ + +#define ICACHE_SET_COUNT 256 /* Instruction cache set count */ +#define DCACHE_SET_COUNT 128 /* Data cache set count */ + +#define ICACHE_SET_SIZE (ICACHE_SET_COUNT * ICACHE_LINE_SIZE) +#define DCACHE_SET_SIZE (DCACHE_SET_COUNT * DCACHE_LINE_SIZE) + + .macro kernel_entry_setup + .set push + .set noreorder + /* + * PNX8550 entry point, when running a non compressed + * kernel. When loading a zImage, the head.S code in + * arch/mips/zboot/pnx8550 will init the caches and, + * decompress the kernel, and branch to kernel_entry. + */ +cache_begin: li t0, (1<<28) + mtc0 t0, CP0_STATUS /* cp0 usable */ + HAZARD_CP0 + + mtc0 zero, CP0_CAUSE + HAZARD_CP0 + + + /* Set static virtual to phys address translation and TLB disabled */ + mfc0 t0, CP0_CONFIG, 7 + HAZARD_CP0 + + and t0,~((1<<19) | (1<<20)) /* TLB/MAP cleared */ + mtc0 t0, CP0_CONFIG, 7 + HAZARD_CP0 + + /* CPU boots with kseg0 cache algo set to 0x2 -- uncached */ + + init_icache + nop + init_dcache + nop + + cachePr4450ICReset + nop + + cachePr4450DCReset + nop + + /* read ConfigPR into t0 */ + mfc0 t0, CP0_CONFIG, 7 + HAZARD_CP0 + + /* enable the TLB */ + or t0, (1<<19) + + /* disable the ICACHE: at least 10x slower */ + /* or t0, (1<<26) */ + + /* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set */ + /* or t0, (1<<27) */ + + and t0, CO_CONFIGPR_VALID + + /* enable TLB. */ + mtc0 t0, CP0_CONFIG, 7 + HAZARD_CP0 +cache_end: + /* Setup CMEM_0 to MMIO address space, 2MB */ + lui t0, 0x1BE0 + addi t0, t0, 0x3 + mtc0 $8, $22, 4 + nop + + /* Setup CMEM_1, 128MB */ + lui t0, 0x1000 + addi t0, t0, 0xf + mtc0 $8, $22, 5 + nop + + + /* Setup CMEM_2, 32MB */ + lui t0, 0x1C00 + addi t0, t0, 0xb + mtc0 $8, $22, 6 + nop + + /* Setup CMEM_3, 0MB */ + lui t0, 0x0 + addi t0, t0, 0x0 + mtc0 $8, $22, 7 + nop + + /* Enable cache */ + mfc0 t0, CP0_CONFIG + HAZARD_CP0 + and t0, t0, 0xFFFFFFF8 + or t0, t0, 3 + mtc0 t0, CP0_CONFIG + HAZARD_CP0 + .set pop + .endm + + .macro init_icache + .set push + .set noreorder + + /* Get Cache Configuration */ + mfc0 t3, CP0_CONFIG, 1 + HAZARD_CP0 + + /* get cache Line size */ + + srl t1, t3, 19 /* C0_CONFIGPR_IL_SHIFT */ + andi t1, t1, 0x7 /* C0_CONFIGPR_IL_MASK */ + beq t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */ + nop + addiu t0, t1, 1 + ori t1, zero, 1 + sllv t1, t1, t0 + + /* get max cache Index */ + srl t2, t3, 22 /* C0_CONFIGPR_IS_SHIFT */ + andi t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */ + addiu t0, t2, 6 + ori t2, zero, 1 + sllv t2, t2, t0 + + /* get max cache way */ + srl t3, t3, 16 /* C0_CONFIGPR_IA_SHIFT */ + andi t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */ + addiu t3, t3, 1 + + /* total no of cache lines */ + multu t2, t3 /* max index * max way */ + mflo t2 + addiu t2, t2, -1 + + move t0, zero +pr4450_next_instruction_cache_set: + cache Index_Invalidate_I, 0(t0) + addu t0, t0, t1 /* add bytes in a line */ + bne t2, zero, pr4450_next_instruction_cache_set + addiu t2, t2, -1 /* reduce no of lines to invalidate by one */ +pr4450_instr_cache_invalidated: + .set pop + .endm + + .macro init_dcache + .set push + .set noreorder + move t1, zero + + /* Store Tag Information */ + mtc0 zero, CP0_TAGLO, 0 + HAZARD_CP0 + + mtc0 zero, CP0_TAGHI, 0 + HAZARD_CP0 + + /* Cache size is 16384 = 512 lines x 32 bytes per line */ + or t2, zero, (128*4)-1 /* 512 lines */ + /* Invalidate all lines */ +2: + cache Index_Store_Tag_D, 0(t1) + addiu t2, t2, -1 + bne t2, zero, 2b + addiu t1, t1, 32 /* 32 bytes in a line */ + .set pop + .endm + + .macro cachePr4450ICReset + .set push + .set noreorder + + /* Save CP0 status reg on entry; */ + /* disable interrupts during cache reset */ + mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */ + HAZARD_CP0 + + mtc0 zero, CP0_STATUS /* disable CPU interrupts */ + HAZARD_CP0 + + or t1, zero, zero /* T1 = starting cache index (0) */ + ori t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */ + + icache_invd_loop: + /* 9 == register t1 */ + .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ + (0 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY0 */ + .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ + (1 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY1 */ + + addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */ + bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */ + addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */ + + /* Initialize the latches in the instruction cache tag */ + /* that drive the way selection tri-state bus drivers, by doing a */ + /* dummy load while the instruction cache is still disabled. */ + /* TODO: Is this needed ? */ + la t1, KSEG0 /* T1 = cached memory base address */ + lw zero, 0x0000(t1) /* (dummy read of first memory word) */ + + mtc0 t0, CP0_STATUS /* restore interrupt status on entry */ + HAZARD_CP0 + .set pop + .endm + + .macro cachePr4450DCReset + .set push + .set noreorder + mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */ + HAZARD_CP0 + mtc0 zero, CP0_STATUS /* disable CPU interrupts */ + HAZARD_CP0 + + /* Writeback/invalidate entire data cache sets/ways/lines */ + or t1, zero, zero /* T1 = starting cache index (0) */ + ori t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */ + + dcache_wbinvd_loop: + /* 9 == register t1 */ + .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ + (0 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY0 */ + .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ + (1 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY1 */ + .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ + (2 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY2 */ + .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ + (3 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY3 */ + + addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */ + bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */ + addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */ + + /* Initialize the latches in the data cache tag that drive the way + selection tri-state bus drivers, by doing a dummy load while the + data cache is still in the disabled mode. TODO: Is this needed ? */ + la t1, KSEG0 /* T1 = cached memory base address */ + lw zero, 0x0000(t1) /* (dummy read of first memory word) */ + + mtc0 t0, CP0_STATUS /* restore interrupt status on entry */ + HAZARD_CP0 + .set pop + .endm + +#endif /* __ASM_MACH_KERNEL_ENTRY_INIT_H */ diff --git a/include/asm-mips/mach-pnx8550/nand.h b/include/asm-mips/mach-pnx8550/nand.h new file mode 100644 index 000000000000..aefbc514ab09 --- /dev/null +++ b/include/asm-mips/mach-pnx8550/nand.h @@ -0,0 +1,121 @@ +#ifndef __PNX8550_NAND_H +#define __PNX8550_NAND_H + +#define PNX8550_NAND_BASE_ADDR 0x10000000 +#define PNX8550_PCIXIO_BASE 0xBBE40000 + +#define PNX8550_DMA_EXT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800) +#define PNX8550_DMA_INT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804) +#define PNX8550_DMA_TRANS_SIZE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808) +#define PNX8550_DMA_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c) +#define PNX8550_XIO_SEL0 *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814) +#define PNX8550_GPXIO_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820) +#define PNX8550_GPXIO_WR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824) +#define PNX8550_GPXIO_RD *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x828) +#define PNX8550_GPXIO_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x82C) +#define PNX8550_XIO_FLASH_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x830) +#define PNX8550_GPXIO_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb0) +#define PNX8550_GPXIO_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb4) +#define PNX8550_GPXIO_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb8) +#define PNX8550_DMA_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd0) +#define PNX8550_DMA_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4) +#define PNX8550_DMA_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8) + +#define PNX8550_XIO_SEL0_EN_16BIT 0x00800000 +#define PNX8550_XIO_SEL0_USE_ACK 0x00400000 +#define PNX8550_XIO_SEL0_REN_HIGH 0x00100000 +#define PNX8550_XIO_SEL0_REN_LOW 0x00040000 +#define PNX8550_XIO_SEL0_WEN_HIGH 0x00010000 +#define PNX8550_XIO_SEL0_WEN_LOW 0x00004000 +#define PNX8550_XIO_SEL0_WAIT 0x00000200 +#define PNX8550_XIO_SEL0_OFFSET 0x00000020 +#define PNX8550_XIO_SEL0_TYPE_68360 0x00000000 +#define PNX8550_XIO_SEL0_TYPE_NOR 0x00000008 +#define PNX8550_XIO_SEL0_TYPE_NAND 0x00000010 +#define PNX8550_XIO_SEL0_TYPE_IDE 0x00000018 +#define PNX8550_XIO_SEL0_SIZE_8MB 0x00000000 +#define PNX8550_XIO_SEL0_SIZE_16MB 0x00000002 +#define PNX8550_XIO_SEL0_SIZE_32MB 0x00000004 +#define PNX8550_XIO_SEL0_SIZE_64MB 0x00000006 +#define PNX8550_XIO_SEL0_ENAB 0x00000001 + +#define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT) | \ + (PNX8550_XIO_SEL0_REN_HIGH*0)| \ + (PNX8550_XIO_SEL0_REN_LOW*2) | \ + (PNX8550_XIO_SEL0_WEN_HIGH*0)| \ + (PNX8550_XIO_SEL0_WEN_LOW*2) | \ + (PNX8550_XIO_SEL0_WAIT*4) | \ + (PNX8550_XIO_SEL0_OFFSET*0) | \ + (PNX8550_XIO_SEL0_TYPE_NAND) | \ + (PNX8550_XIO_SEL0_SIZE_32MB) | \ + (PNX8550_XIO_SEL0_ENAB)) + +#define PNX8550_GPXIO_PENDING 0x00000200 +#define PNX8550_GPXIO_DONE 0x00000100 +#define PNX8550_GPXIO_CLR_DONE 0x00000080 +#define PNX8550_GPXIO_INIT 0x00000040 +#define PNX8550_GPXIO_READ_CMD 0x00000010 +#define PNX8550_GPXIO_BEN 0x0000000F + +#define PNX8550_XIO_FLASH_64MB 0x00200000 +#define PNX8550_XIO_FLASH_INC_DATA 0x00100000 +#define PNX8550_XIO_FLASH_CMD_PH 0x000C0000 +#define PNX8550_XIO_FLASH_CMD_PH2 0x00080000 +#define PNX8550_XIO_FLASH_CMD_PH1 0x00040000 +#define PNX8550_XIO_FLASH_CMD_PH0 0x00000000 +#define PNX8550_XIO_FLASH_ADR_PH 0x00030000 +#define PNX8550_XIO_FLASH_ADR_PH3 0x00030000 +#define PNX8550_XIO_FLASH_ADR_PH2 0x00020000 +#define PNX8550_XIO_FLASH_ADR_PH1 0x00010000 +#define PNX8550_XIO_FLASH_ADR_PH0 0x00000000 +#define PNX8550_XIO_FLASH_CMD_B(x) ((x<<8) & 0x0000FF00) +#define PNX8550_XIO_FLASH_CMD_A(x) (x & 0x000000FF) + +#define PNX8550_XIO_INT_ACK 0x00004000 +#define PNX8550_XIO_INT_COMPL 0x00002000 +#define PNX8550_XIO_INT_NONSUP 0x00000200 +#define PNX8550_XIO_INT_ABORT 0x00000004 + +#define PNX8550_DMA_CTRL_SINGLE_DATA 0x00000400 +#define PNX8550_DMA_CTRL_SND2XIO 0x00000200 +#define PNX8550_DMA_CTRL_FIX_ADDR 0x00000100 +#define PNX8550_DMA_CTRL_BURST_8 0x00000000 +#define PNX8550_DMA_CTRL_BURST_16 0x00000020 +#define PNX8550_DMA_CTRL_BURST_32 0x00000040 +#define PNX8550_DMA_CTRL_BURST_64 0x00000060 +#define PNX8550_DMA_CTRL_BURST_128 0x00000080 +#define PNX8550_DMA_CTRL_BURST_256 0x000000A0 +#define PNX8550_DMA_CTRL_BURST_512 0x000000C0 +#define PNX8550_DMA_CTRL_BURST_NORES 0x000000E0 +#define PNX8550_DMA_CTRL_INIT_DMA 0x00000010 +#define PNX8550_DMA_CTRL_CMD_TYPE 0x0000000F + +/* see PCI system arch, page 100 for the full list: */ +#define PNX8550_DMA_CTRL_PCI_CMD_READ 0x00000006 +#define PNX8550_DMA_CTRL_PCI_CMD_WRITE 0x00000007 + +#define PNX8550_DMA_INT_STAT_ACK_DONE (1<<14) +#define PNX8550_DMA_INT_STAT_DMA_DONE (1<<12) +#define PNX8550_DMA_INT_STAT_DMA_ERR (1<<9) +#define PNX8550_DMA_INT_STAT_PERR5 (1<<5) +#define PNX8550_DMA_INT_STAT_PERR4 (1<<4) +#define PNX8550_DMA_INT_STAT_M_ABORT (1<<2) +#define PNX8550_DMA_INT_STAT_T_ABORT (1<<1) + +#define PNX8550_DMA_INT_EN_ACK_DONE (1<<14) +#define PNX8550_DMA_INT_EN_DMA_DONE (1<<12) +#define PNX8550_DMA_INT_EN_DMA_ERR (1<<9) +#define PNX8550_DMA_INT_EN_PERR5 (1<<5) +#define PNX8550_DMA_INT_EN_PERR4 (1<<4) +#define PNX8550_DMA_INT_EN_M_ABORT (1<<2) +#define PNX8550_DMA_INT_EN_T_ABORT (1<<1) + +#define PNX8550_DMA_INT_CLR_ACK_DONE (1<<14) +#define PNX8550_DMA_INT_CLR_DMA_DONE (1<<12) +#define PNX8550_DMA_INT_CLR_DMA_ERR (1<<9) +#define PNX8550_DMA_INT_CLR_PERR5 (1<<5) +#define PNX8550_DMA_INT_CLR_PERR4 (1<<4) +#define PNX8550_DMA_INT_CLR_M_ABORT (1<<2) +#define PNX8550_DMA_INT_CLR_T_ABORT (1<<1) + +#endif diff --git a/include/asm-mips/mach-pnx8550/pci.h b/include/asm-mips/mach-pnx8550/pci.h new file mode 100644 index 000000000000..b921508d701b --- /dev/null +++ b/include/asm-mips/mach-pnx8550/pci.h @@ -0,0 +1,185 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * PCI specific definitions + * + * Author: source@mvista.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ + +#ifndef __PNX8550_PCI_H +#define __PNX8550_PCI_H + +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/init.h> + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#define PCI_CMD_IOR 0x20 +#define PCI_CMD_IOW 0x30 +#define PCI_CMD_CONFIG_READ 0xa0 +#define PCI_CMD_CONFIG_WRITE 0xb0 + +#define PCI_IO_TIMEOUT 1000 +#define PCI_IO_RETRY 5 +/* Timeout for IO and CFG accesses. + This is in 1/1024 th of a jiffie(=10ms) + i.e. approx 10us */ +#define PCI_IO_JIFFIES_TIMEOUT 40 +#define PCI_IO_JIFFIES_SHIFT 10 + +#define PCI_BYTE_ENABLE_MASK 0x0000000f +#define PCI_CFG_BUS_SHIFT 16 +#define PCI_CFG_FUNC_SHIFT 8 +#define PCI_CFG_REG_SHIFT 2 + +#define PCI_BASE 0x1be00000 +#define PCI_SETUP 0x00040010 +#define PCI_DIS_REQGNT (1<<30) +#define PCI_DIS_REQGNTA (1<<29) +#define PCI_DIS_REQGNTB (1<<28) +#define PCI_D2_SUPPORT (1<<27) +#define PCI_D1_SUPPORT (1<<26) +#define PCI_EN_TA (1<<24) +#define PCI_EN_PCI2MMI (1<<23) +#define PCI_EN_XIO (1<<22) +#define PCI_BASE18_PREF (1<<21) +#define SIZE_16M 0x3 +#define SIZE_32M 0x4 +#define SIZE_64M 0x5 +#define SIZE_128M 0x6 +#define PCI_SETUP_BASE18_SIZE(X) (X<<18) +#define PCI_SETUP_BASE18_EN (1<<17) +#define PCI_SETUP_BASE14_PREF (1<<16) +#define PCI_SETUP_BASE14_SIZE(X) (X<<12) +#define PCI_SETUP_BASE14_EN (1<<11) +#define PCI_SETUP_BASE10_PREF (1<<10) +#define PCI_SETUP_BASE10_SIZE(X) (X<<7) +#define PCI_SETUP_CFGMANAGE_EN (1<<1) +#define PCI_SETUP_PCIARB_EN (1<<0) + +#define PCI_CTRL 0x040014 +#define PCI_SWPB_DCS_PCI (1<<16) +#define PCI_SWPB_PCI_PCI (1<<15) +#define PCI_SWPB_PCI_DCS (1<<14) +#define PCI_REG_WR_POST (1<<13) +#define PCI_XIO_WR_POST (1<<12) +#define PCI_PCI2_WR_POST (1<<13) +#define PCI_PCI1_WR_POST (1<<12) +#define PCI_SERR_SEEN (1<<11) +#define PCI_B10_SPEC_RD (1<<6) +#define PCI_B14_SPEC_RD (1<<5) +#define PCI_B18_SPEC_RD (1<<4) +#define PCI_B10_NOSUBWORD (1<<3) +#define PCI_B14_NOSUBWORD (1<<2) +#define PCI_B18_NOSUBWORD (1<<1) +#define PCI_RETRY_TMREN (1<<0) + +#define PCI_BASE1_LO 0x040018 +#define PCI_BASE1_HI 0x04001C +#define PCI_BASE2_LO 0x040020 +#define PCI_BASE2_HI 0x040024 +#define PCI_RDLIFETIM 0x040028 +#define PCI_GPPM_ADDR 0x04002C +#define PCI_GPPM_WDAT 0x040030 +#define PCI_GPPM_RDAT 0x040034 +#define PCI_GPPM_CTRL 0x040038 +#define GPPM_DONE (1<<10) +#define INIT_PCI_CYCLE (1<<9) +#define GPPM_CMD(X) (((X)&0xf)<<4) +#define GPPM_BYTEEN(X) ((X)&0xf) +#define PCI_UNLOCKREG 0x04003C +#define UNLOCK_SSID(X) (((X)&0xff)<<8) +#define UNLOCK_SETUP(X) (((X)&0xff)<<0) +#define UNLOCK_MAGIC 0xCA +#define PCI_DEV_VEND_ID 0x040040 +#define DEVICE_ID(X) (((X)>>16)&0xffff) +#define VENDOR_ID(X) (((X)&0xffff)) +#define PCI_CFG_CMDSTAT 0x040044 +#define PCI_CFG_STATUS(X) (((X)>>16)&0xffff) +#define PCI_CFG_COMMAND(X) ((X)&0xffff) +#define PCI_CLASS_REV 0x040048 +#define PCI_CLASSCODE(X) (((X)>>8)&0xffffff) +#define PCI_REVID(X) ((X)&0xff) +#define PCI_LAT_TMR 0x04004c +#define PCI_BASE10 0x040050 +#define PCI_BASE14 0x040054 +#define PCI_BASE18 0x040058 +#define PCI_SUBSYS_ID 0x04006c +#define PCI_CAP_PTR 0x040074 +#define PCI_CFG_MISC 0x04007c +#define PCI_PMC 0x040080 +#define PCI_PWR_STATE 0x040084 +#define PCI_IO 0x040088 +#define PCI_SLVTUNING 0x04008C +#define PCI_DMATUNING 0x040090 +#define PCI_DMAEADDR 0x040800 +#define PCI_DMAIADDR 0x040804 +#define PCI_DMALEN 0x040808 +#define PCI_DMACTRL 0x04080C +#define PCI_XIOCTRL 0x040810 +#define PCI_SEL0PROF 0x040814 +#define PCI_SEL1PROF 0x040818 +#define PCI_SEL2PROF 0x04081C +#define PCI_GPXIOADDR 0x040820 +#define PCI_NANDCTRLS 0x400830 +#define PCI_SEL3PROF 0x040834 +#define PCI_SEL4PROF 0x040838 +#define PCI_GPXIO_STAT 0x040FB0 +#define PCI_GPXIO_IMASK 0x040FB4 +#define PCI_GPXIO_ICLR 0x040FB8 +#define PCI_GPXIO_ISET 0x040FBC +#define PCI_GPPM_STATUS 0x040FC0 +#define GPPM_DONE (1<<10) +#define GPPM_ERR (1<<9) +#define GPPM_MPAR_ERR (1<<8) +#define GPPM_PAR_ERR (1<<7) +#define GPPM_R_MABORT (1<<2) +#define GPPM_R_TABORT (1<<1) +#define PCI_GPPM_IMASK 0x040FC4 +#define PCI_GPPM_ICLR 0x040FC8 +#define PCI_GPPM_ISET 0x040FCC +#define PCI_DMA_STATUS 0x040FD0 +#define PCI_DMA_IMASK 0x040FD4 +#define PCI_DMA_ICLR 0x040FD8 +#define PCI_DMA_ISET 0x040FDC +#define PCI_ISTATUS 0x040FE0 +#define PCI_IMASK 0x040FE4 +#define PCI_ICLR 0x040FE8 +#define PCI_ISET 0x040FEC +#define PCI_MOD_ID 0x040FFC + +/* + * PCI configuration cycle AD bus definition + */ +/* Type 0 */ +#define PCI_CFG_TYPE0_REG_SHF 0 +#define PCI_CFG_TYPE0_FUNC_SHF 8 + +/* Type 1 */ +#define PCI_CFG_TYPE1_REG_SHF 0 +#define PCI_CFG_TYPE1_FUNC_SHF 8 +#define PCI_CFG_TYPE1_DEV_SHF 11 +#define PCI_CFG_TYPE1_BUS_SHF 16 + +/* + * Ethernet device DP83816 definition + */ +#define DP83816_IRQ_ETHER 66 + +#endif diff --git a/include/asm-mips/mach-pnx8550/uart.h b/include/asm-mips/mach-pnx8550/uart.h new file mode 100644 index 000000000000..e32b9a23d70e --- /dev/null +++ b/include/asm-mips/mach-pnx8550/uart.h @@ -0,0 +1,16 @@ +#ifndef __IP3106_UART_H +#define __IP3106_UART_H + +#include <int.h> + +/* early macros for kgdb use. fixme: clean this up */ + +#define UART_BASE 0xbbe4a000 /* PNX8550 */ + +#define PNX8550_UART_PORT0 (UART_BASE) +#define PNX8550_UART_PORT1 (UART_BASE + 0x1000) + +#define PNX8550_UART_INT(x) (PNX8550_INT_GIC_MIN+19+x) +#define IRQ_TO_UART(x) (x-PNX8550_INT_GIC_MIN-19) + +#endif diff --git a/include/asm-mips/mach-pnx8550/usb.h b/include/asm-mips/mach-pnx8550/usb.h new file mode 100644 index 000000000000..483b7fc65d41 --- /dev/null +++ b/include/asm-mips/mach-pnx8550/usb.h @@ -0,0 +1,32 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * USB specific definitions + * + * Author: source@mvista.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ + +#ifndef __PNX8550_USB_H +#define __PNX8550_USB_H + +/* + * USB Host controller + */ + +#define PNX8550_USB_OHCI_OP_BASE 0x1be48000 +#define PNX8550_USB_OHCI_OP_LEN 0x1000 + +#endif diff --git a/include/asm-mips/mach-rm200/cpu-feature-overrides.h b/include/asm-mips/mach-rm200/cpu-feature-overrides.h index f48736032b2a..79f9b064c864 100644 --- a/include/asm-mips/mach-rm200/cpu-feature-overrides.h +++ b/include/asm-mips/mach-rm200/cpu-feature-overrides.h @@ -14,7 +14,7 @@ #define cpu_has_tlb 1 #define cpu_has_4kex 1 -#define cpu_has_4ktlb 1 +#define cpu_has_4kcache 1 #define cpu_has_fpu 1 #define cpu_has_32fpr 1 #define cpu_has_counter 1 @@ -31,6 +31,7 @@ #define cpu_has_vtag_icache 0 #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) #define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h index a3a2cc6014b2..193a666cd131 100644 --- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h +++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h @@ -25,6 +25,7 @@ #define cpu_has_vtag_icache 1 #define cpu_has_dc_aliases 0 #define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 #define cpu_icache_snoops_remote_store 0 #define cpu_has_nofpuex 0 diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-sim/cpu-feature-overrides.h new file mode 100644 index 000000000000..cadbe8eda79c --- /dev/null +++ b/include/asm-mips/mach-sim/cpu-feature-overrides.h @@ -0,0 +1,66 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Chris Dearman + */ +#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H + +#include <linux/config.h> + +/* + * CPU feature overrides for MIPS boards + */ +#ifdef CONFIG_CPU_MIPS32 +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4kcache 1 +#define cpu_has_fpu 0 +/* #define cpu_has_32fpr ? */ +#define cpu_has_counter 1 +/* #define cpu_has_watch ? */ +#define cpu_has_divec 1 +#define cpu_has_vce 0 +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_prefetch ? */ +#define cpu_has_mcheck 1 +/* #define cpu_has_ejtag ? */ +#define cpu_has_llsc 1 +/* #define cpu_has_vtag_icache ? */ +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_nofpuex 0 +/* #define cpu_has_64bits ? */ +/* #define cpu_has_64bit_zero_reg ? */ +/* #define cpu_has_subset_pcaches ? */ +#endif + +#ifdef CONFIG_CPU_MIPS64 +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4kcache 1 +/* #define cpu_has_fpu ? */ +/* #define cpu_has_32fpr ? */ +#define cpu_has_counter 1 +/* #define cpu_has_watch ? */ +#define cpu_has_divec 1 +#define cpu_has_vce 0 +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_prefetch ? */ +#define cpu_has_mcheck 1 +/* #define cpu_has_ejtag ? */ +#define cpu_has_llsc 1 +/* #define cpu_has_vtag_icache ? */ +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_nofpuex 0 +/* #define cpu_has_64bits ? */ +/* #define cpu_has_64bit_zero_reg ? */ +/* #define cpu_has_subset_pcaches ? */ +#endif + +#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h index 58603e3daca6..463d051f4683 100644 --- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h +++ b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h @@ -25,6 +25,7 @@ #define cpu_has_vtag_icache 0 #define cpu_has_dc_aliases 0 #define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 #define cpu_icache_snoops_remote_store 0 #define cpu_has_nofpuex 0 @@ -36,10 +37,4 @@ #define cpu_icache_line_size() 32 #define cpu_scache_line_size() 32 -/* - * On the RM9000 we need to ensure that I-cache lines being fetches only - * contain valid instructions are funny things will happen. - */ -#define PLAT_TRAMPOLINE_STUFF_LINE 32UL - #endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h index 65d1d16eab16..25b6ffc26623 100644 --- a/include/asm-mips/mips-boards/generic.h +++ b/include/asm-mips/mips-boards/generic.h @@ -66,6 +66,7 @@ #define MIPS_REVISION_CORID_CORE_EMUL 6 #define MIPS_REVISION_CORID_CORE_FPGA2 7 #define MIPS_REVISION_CORID_CORE_FPGAR2 8 +#define MIPS_REVISION_CORID_CORE_FPGA3 9 /**** Artificial corid defines ****/ /* @@ -79,4 +80,10 @@ extern unsigned int mips_revision_corid; +#ifdef CONFIG_PCI +extern void mips_pcibios_init(void); +#else +#define mips_pcibios_init() do { } while (0) +#endif + #endif /* __ASM_MIPS_BOARDS_GENERIC_H */ diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h index 376181882e81..da6cc2fbbc78 100644 --- a/include/asm-mips/mips-boards/maltaint.h +++ b/include/asm-mips/mips-boards/maltaint.h @@ -25,9 +25,63 @@ #ifndef _MIPS_MALTAINT_H #define _MIPS_MALTAINT_H -/* Number of IRQ supported on hw interrupt 0. */ -#define MALTAINT_END 16 +/* + * Interrupts 0..15 are used for Malta ISA compatible interrupts + */ +#define MALTA_INT_BASE 0 + +/* + * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode) + */ +#define MIPSCPU_INT_BASE 16 + +/* CPU interrupt offsets */ +#define MIPSCPU_INT_SW0 0 +#define MIPSCPU_INT_SW1 1 +#define MIPSCPU_INT_MB0 2 +#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 +#define MIPSCPU_INT_MB1 3 +#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 +#define MIPSCPU_INT_MB2 4 +#define MIPSCPU_INT_MB3 5 +#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 +#define MIPSCPU_INT_MB4 6 +#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 +#define MIPSCPU_INT_CPUCTR 7 + +/* + * Interrupts 64..127 are used for Soc-it Classic interrupts + */ +#define MSC01C_INT_BASE 64 + +/* SOC-it Classic interrupt offsets */ +#define MSC01C_INT_TMR 0 +#define MSC01C_INT_PCI 1 + +/* + * Interrupts 64..127 are used for Soc-it EIC interrupts + */ +#define MSC01E_INT_BASE 64 + +/* SOC-it EIC interrupt offsets */ +#define MSC01E_INT_SW0 1 +#define MSC01E_INT_SW1 2 +#define MSC01E_INT_MB0 3 +#define MSC01E_INT_I8259A MSC01E_INT_MB0 +#define MSC01E_INT_MB1 4 +#define MSC01E_INT_SMI MSC01E_INT_MB1 +#define MSC01E_INT_MB2 5 +#define MSC01E_INT_MB3 6 +#define MSC01E_INT_COREHI MSC01E_INT_MB3 +#define MSC01E_INT_MB4 7 +#define MSC01E_INT_CORELO MSC01E_INT_MB4 +#define MSC01E_INT_TMR 8 +#define MSC01E_INT_PCI 9 +#define MSC01E_INT_PERFCTR 10 +#define MSC01E_INT_CPUCTR 11 +#ifndef __ASSEMBLY__ extern void maltaint_init(void); +#endif #endif /* !(_MIPS_MALTAINT_H) */ diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h index 6b2a87a38f4b..8eaefb837b9d 100644 --- a/include/asm-mips/mips-boards/msc01_pci.h +++ b/include/asm-mips/mips-boards/msc01_pci.h @@ -1,8 +1,9 @@ /* * PCI Register definitions for the MIPS System Controller. * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2002, 2005 MIPS Technologies, Inc. All rights reserved. + * Authors: Carsten Langgaard <carstenl@mips.com> + * Maciej W. Rozycki <macro@mips.com> * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -29,22 +30,22 @@ #define MSC01_PCI_CFGADDR_OFS 0x0610 #define MSC01_PCI_CFGDATA_OFS 0x0618 #define MSC01_PCI_IACK_OFS 0x0620 -#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */ -#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */ -#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */ -#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */ -#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */ -#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */ -#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */ -#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */ -#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */ -#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */ -#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */ -#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */ -#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */ -#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */ -#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */ -#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */ +#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */ +#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */ +#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */ +#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */ +#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */ +#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */ +#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */ +#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */ +#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */ +#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */ +#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */ +#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */ +#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */ +#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */ +#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */ +#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */ #define MSC01_PCI_BAR0_OFS 0x2220 #define MSC01_PCI_CFG_OFS 0x2380 #define MSC01_PCI_SWAP_OFS 0x2388 @@ -86,73 +87,73 @@ #define MSC01_PCI_P2SCMAPL_MAP_SHF 24 #define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000 -#define MSC01_PCI_INTCFG_RST_SHF 10 -#define MSC01_PCI_INTCFG_RST_MSK 0x00000400 -#define MSC01_PCI_INTCFG_RST_BIT 0x00000400 -#define MSC01_PCI_INTCFG_MWE_SHF 9 -#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200 -#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200 -#define MSC01_PCI_INTCFG_DTO_SHF 8 -#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100 -#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100 -#define MSC01_PCI_INTCFG_MA_SHF 7 -#define MSC01_PCI_INTCFG_MA_MSK 0x00000080 -#define MSC01_PCI_INTCFG_MA_BIT 0x00000080 -#define MSC01_PCI_INTCFG_TA_SHF 6 -#define MSC01_PCI_INTCFG_TA_MSK 0x00000040 -#define MSC01_PCI_INTCFG_TA_BIT 0x00000040 -#define MSC01_PCI_INTCFG_RTY_SHF 5 -#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020 -#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020 -#define MSC01_PCI_INTCFG_MWP_SHF 4 -#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010 -#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010 -#define MSC01_PCI_INTCFG_MRP_SHF 3 -#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008 -#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008 -#define MSC01_PCI_INTCFG_SWP_SHF 2 -#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004 -#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004 -#define MSC01_PCI_INTCFG_SRP_SHF 1 -#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002 -#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002 -#define MSC01_PCI_INTCFG_SE_SHF 0 -#define MSC01_PCI_INTCFG_SE_MSK 0x00000001 -#define MSC01_PCI_INTCFG_SE_BIT 0x00000001 +#define MSC01_PCI_INTCFG_RST_SHF 10 +#define MSC01_PCI_INTCFG_RST_MSK 0x00000400 +#define MSC01_PCI_INTCFG_RST_BIT 0x00000400 +#define MSC01_PCI_INTCFG_MWE_SHF 9 +#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200 +#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200 +#define MSC01_PCI_INTCFG_DTO_SHF 8 +#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100 +#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100 +#define MSC01_PCI_INTCFG_MA_SHF 7 +#define MSC01_PCI_INTCFG_MA_MSK 0x00000080 +#define MSC01_PCI_INTCFG_MA_BIT 0x00000080 +#define MSC01_PCI_INTCFG_TA_SHF 6 +#define MSC01_PCI_INTCFG_TA_MSK 0x00000040 +#define MSC01_PCI_INTCFG_TA_BIT 0x00000040 +#define MSC01_PCI_INTCFG_RTY_SHF 5 +#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020 +#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020 +#define MSC01_PCI_INTCFG_MWP_SHF 4 +#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010 +#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010 +#define MSC01_PCI_INTCFG_MRP_SHF 3 +#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008 +#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008 +#define MSC01_PCI_INTCFG_SWP_SHF 2 +#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004 +#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004 +#define MSC01_PCI_INTCFG_SRP_SHF 1 +#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002 +#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002 +#define MSC01_PCI_INTCFG_SE_SHF 0 +#define MSC01_PCI_INTCFG_SE_MSK 0x00000001 +#define MSC01_PCI_INTCFG_SE_BIT 0x00000001 -#define MSC01_PCI_INTSTAT_RST_SHF 10 -#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400 -#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400 -#define MSC01_PCI_INTSTAT_MWE_SHF 9 -#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200 -#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200 -#define MSC01_PCI_INTSTAT_DTO_SHF 8 -#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100 -#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100 -#define MSC01_PCI_INTSTAT_MA_SHF 7 -#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080 -#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080 -#define MSC01_PCI_INTSTAT_TA_SHF 6 -#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040 -#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040 -#define MSC01_PCI_INTSTAT_RTY_SHF 5 -#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020 -#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020 -#define MSC01_PCI_INTSTAT_MWP_SHF 4 -#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010 -#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010 -#define MSC01_PCI_INTSTAT_MRP_SHF 3 -#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008 -#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008 -#define MSC01_PCI_INTSTAT_SWP_SHF 2 -#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004 -#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004 -#define MSC01_PCI_INTSTAT_SRP_SHF 1 -#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002 -#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002 -#define MSC01_PCI_INTSTAT_SE_SHF 0 -#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001 -#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001 +#define MSC01_PCI_INTSTAT_RST_SHF 10 +#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400 +#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400 +#define MSC01_PCI_INTSTAT_MWE_SHF 9 +#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200 +#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200 +#define MSC01_PCI_INTSTAT_DTO_SHF 8 +#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100 +#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100 +#define MSC01_PCI_INTSTAT_MA_SHF 7 +#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080 +#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080 +#define MSC01_PCI_INTSTAT_TA_SHF 6 +#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040 +#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040 +#define MSC01_PCI_INTSTAT_RTY_SHF 5 +#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020 +#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020 +#define MSC01_PCI_INTSTAT_MWP_SHF 4 +#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010 +#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010 +#define MSC01_PCI_INTSTAT_MRP_SHF 3 +#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008 +#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008 +#define MSC01_PCI_INTSTAT_SWP_SHF 2 +#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004 +#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004 +#define MSC01_PCI_INTSTAT_SRP_SHF 1 +#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002 +#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002 +#define MSC01_PCI_INTSTAT_SE_SHF 0 +#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001 +#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001 #define MSC01_PCI_CFGADDR_BNUM_SHF 16 #define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000 @@ -167,29 +168,29 @@ #define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff /* The defines below are ONLY valid for a MEM bar! */ -#define MSC01_PCI_BAR0_SIZE_SHF 4 -#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0 -#define MSC01_PCI_BAR0_P_SHF 3 -#define MSC01_PCI_BAR0_P_MSK 0x00000008 -#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK -#define MSC01_PCI_BAR0_D_SHF 1 -#define MSC01_PCI_BAR0_D_MSK 0x00000006 -#define MSC01_PCI_BAR0_T_SHF 0 -#define MSC01_PCI_BAR0_T_MSK 0x00000001 -#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK +#define MSC01_PCI_BAR0_SIZE_SHF 4 +#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0 +#define MSC01_PCI_BAR0_P_SHF 3 +#define MSC01_PCI_BAR0_P_MSK 0x00000008 +#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK +#define MSC01_PCI_BAR0_D_SHF 1 +#define MSC01_PCI_BAR0_D_MSK 0x00000006 +#define MSC01_PCI_BAR0_T_SHF 0 +#define MSC01_PCI_BAR0_T_MSK 0x00000001 +#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK -#define MSC01_PCI_CFG_RA_SHF 17 -#define MSC01_PCI_CFG_RA_MSK 0x00020000 -#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK -#define MSC01_PCI_CFG_G_SHF 16 -#define MSC01_PCI_CFG_G_MSK 0x00010000 -#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK -#define MSC01_PCI_CFG_EN_SHF 15 -#define MSC01_PCI_CFG_EN_MSK 0x00008000 -#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK -#define MSC01_PCI_CFG_MAXRTRY_SHF 0 -#define MSC01_PCI_CFG_MAXRTRY_MSK 0x000000ff +#define MSC01_PCI_CFG_RA_SHF 17 +#define MSC01_PCI_CFG_RA_MSK 0x00020000 +#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK +#define MSC01_PCI_CFG_G_SHF 16 +#define MSC01_PCI_CFG_G_MSK 0x00010000 +#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK +#define MSC01_PCI_CFG_EN_SHF 15 +#define MSC01_PCI_CFG_EN_MSK 0x00008000 +#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK +#define MSC01_PCI_CFG_MAXRTRY_SHF 0 +#define MSC01_PCI_CFG_MAXRTRY_MSK 0x00000fff #define MSC01_PCI_SWAP_IO_SHF 18 #define MSC01_PCI_SWAP_IO_MSK 0x000c0000 @@ -206,7 +207,7 @@ * FIXME - are these macros specific to Malta and co or to the MSC? If the * latter, they should be moved elsewhere. */ -#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000 +#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000 extern unsigned long _pcictrl_msc; @@ -219,19 +220,19 @@ extern unsigned long _pcictrl_msc; * Registers absolute addresses */ -#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS) -#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS) -#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS) -#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS) -#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS) -#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS) -#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS) -#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS) -#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS) -#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS) -#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS) -#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS) -#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS) +#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS) +#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS) +#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS) +#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS) +#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS) +#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS) +#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS) +#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS) +#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS) +#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS) +#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS) +#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS) +#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS) #define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS) #define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS) #define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS) @@ -248,7 +249,7 @@ extern unsigned long _pcictrl_msc; #define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) #define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) #define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) -#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) +#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) #define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS) #define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS) #define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS) diff --git a/include/asm-mips/mips-boards/sim.h b/include/asm-mips/mips-boards/sim.h new file mode 100644 index 000000000000..acb7c2331d98 --- /dev/null +++ b/include/asm-mips/mips-boards/sim.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#ifndef _ASM_MIPS_BOARDS_SIM_H +#define _ASM_MIPS_BOARDS_SIM_H + +#define STATS_ON 1 +#define STATS_OFF 2 +#define STATS_CLEAR 3 +#define STATS_DUMP 4 +#define TRACE_ON 5 +#define TRACE_OFF 6 + + +#define simcfg(code) \ +({ \ + __asm__ __volatile__( \ + "sltiu $0,$0, %0" \ + ::"i"(code) \ + ); \ +}) + + + +#endif diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h new file mode 100644 index 000000000000..4952e0b3bf11 --- /dev/null +++ b/include/asm-mips/mips-boards/simint.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#ifndef _MIPS_SIMINT_H +#define _MIPS_SIMINT_H + + +#define SIM_INT_BASE 0 +#define MIPSCPU_INT_MB0 2 +#define MIPSCPU_INT_BASE 16 +#define MIPS_CPU_TIMER_IRQ 7 + + +#define MIPSCPU_INT_CPUCTR 7 + +#define MSC01E_INT_BASE 64 + +#define MIPSCPU_INT_CPUCTR 7 +#define MSC01E_INT_CPUCTR 11 + +#endif diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h new file mode 100644 index 000000000000..a669c0702c66 --- /dev/null +++ b/include/asm-mips/mipsmtregs.h @@ -0,0 +1,391 @@ +/* + * MT regs definitions, follows on from mipsregs.h + * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved. + * Elizabeth Clarke et. al. + * + */ +#ifndef _ASM_MIPSMTREGS_H +#define _ASM_MIPSMTREGS_H + +#include <asm/mipsregs.h> +#include <asm/war.h> + +#ifndef __ASSEMBLY__ + +/* + * C macros + */ + +#define read_c0_mvpcontrol() __read_32bit_c0_register($0, 1) +#define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val) + +#define read_c0_mvpconf0() __read_32bit_c0_register($0, 2) +#define read_c0_mvpconf1() __read_32bit_c0_register($0, 3) + +#define read_c0_vpecontrol() __read_32bit_c0_register($1, 1) +#define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val) + +#define read_c0_vpeconf0() __read_32bit_c0_register($1, 2) +#define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val) + +#define read_c0_tcstatus() __read_32bit_c0_register($2, 1) +#define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) + +#define read_c0_tcbind() __read_32bit_c0_register($2, 2) + +#define read_c0_tccontext() __read_32bit_c0_register($2, 5) +#define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val) + +#else /* Assembly */ +/* + * Macros for use in assembly language code + */ + +#define CP0_MVPCONTROL $0,1 +#define CP0_MVPCONF0 $0,2 +#define CP0_MVPCONF1 $0,3 +#define CP0_VPECONTROL $1,1 +#define CP0_VPECONF0 $1,2 +#define CP0_VPECONF1 $1,3 +#define CP0_YQMASK $1,4 +#define CP0_VPESCHEDULE $1,5 +#define CP0_VPESCHEFBK $1,6 +#define CP0_TCSTATUS $2,1 +#define CP0_TCBIND $2,2 +#define CP0_TCRESTART $2,3 +#define CP0_TCHALT $2,4 +#define CP0_TCCONTEXT $2,5 +#define CP0_TCSCHEDULE $2,6 +#define CP0_TCSCHEFBK $2,7 +#define CP0_SRSCONF0 $6,1 +#define CP0_SRSCONF1 $6,2 +#define CP0_SRSCONF2 $6,3 +#define CP0_SRSCONF3 $6,4 +#define CP0_SRSCONF4 $6,5 + +#endif + +/* MVPControl fields */ +#define MVPCONTROL_EVP (_ULCAST_(1)) + +#define MVPCONTROL_VPC_SHIFT 1 +#define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT) + +#define MVPCONTROL_STLB_SHIFT 2 +#define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT) + + +/* MVPConf0 fields */ +#define MVPCONF0_PTC_SHIFT 0 +#define MVPCONF0_PTC ( _ULCAST_(0xff)) +#define MVPCONF0_PVPE_SHIFT 10 +#define MVPCONF0_PVPE ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT) +#define MVPCONF0_TCA_SHIFT 15 +#define MVPCONF0_TCA ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT) +#define MVPCONF0_PTLBE_SHIFT 16 +#define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT) +#define MVPCONF0_TLBS_SHIFT 29 +#define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT) +#define MVPCONF0_M_SHIFT 31 +#define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT) + + +/* config3 fields */ +#define CONFIG3_MT_SHIFT 2 +#define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT) + + +/* VPEControl fields (per VPE) */ +#define VPECONTROL_TARGTC (_ULCAST_(0xff)) + +#define VPECONTROL_TE_SHIFT 15 +#define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT) +#define VPECONTROL_EXCPT_SHIFT 16 +#define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT) + +/* Thread Exception Codes for EXCPT field */ +#define THREX_TU 0 +#define THREX_TO 1 +#define THREX_IYQ 2 +#define THREX_GSX 3 +#define THREX_YSCH 4 +#define THREX_GSSCH 5 + +#define VPECONTROL_GSI_SHIFT 20 +#define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT) +#define VPECONTROL_YSI_SHIFT 21 +#define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT) + +/* VPEConf0 fields (per VPE) */ +#define VPECONF0_VPA_SHIFT 0 +#define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT) +#define VPECONF0_MVP_SHIFT 1 +#define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT) +#define VPECONF0_XTC_SHIFT 21 +#define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT) + +/* TCStatus fields (per TC) */ +#define TCSTATUS_TASID (_ULCAST_(0xff)) +#define TCSTATUS_IXMT_SHIFT 10 +#define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT) +#define TCSTATUS_TKSU_SHIFT 11 +#define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT) +#define TCSTATUS_A_SHIFT 13 +#define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT) +#define TCSTATUS_DA_SHIFT 15 +#define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT) +#define TCSTATUS_DT_SHIFT 20 +#define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT) +#define TCSTATUS_TDS_SHIFT 21 +#define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT) +#define TCSTATUS_TSST_SHIFT 22 +#define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT) +#define TCSTATUS_RNST_SHIFT 23 +#define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT) +/* Codes for RNST */ +#define TC_RUNNING 0 +#define TC_WAITING 1 +#define TC_YIELDING 2 +#define TC_GATED 3 + +#define TCSTATUS_TMX_SHIFT 27 +#define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT) +/* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */ + +/* TCBind */ +#define TCBIND_CURVPE_SHIFT 0 +#define TCBIND_CURVPE (_ULCAST_(0xf)) + +#define TCBIND_CURTC_SHIFT 21 + +#define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT) + +/* TCHalt */ +#define TCHALT_H (_ULCAST_(1)) + +#ifndef __ASSEMBLY__ + +extern void mips_mt_regdump(void); + +static inline unsigned int dvpe(void) +{ + int res = 0; + + __asm__ __volatile__( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips32r2 \n" + " .word 0x41610001 # dvpe $1 \n" + " move %0, $1 \n" + " ehb \n" + " .set pop \n" + : "=r" (res)); + + instruction_hazard(); + + return res; +} + +static inline void __raw_evpe(void) +{ + __asm__ __volatile__( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips32r2 \n" + " .word 0x41600021 # evpe \n" + " ehb \n" + " .set pop \n"); +} + +/* Enable multiMT if previous suggested it should be. + EMT_ENABLE to force */ + +#define EVPE_ENABLE MVPCONTROL_EVP + +static inline void evpe(int previous) +{ + if ((previous & MVPCONTROL_EVP)) + __raw_evpe(); +} + +static inline unsigned int dmt(void) +{ + int res; + + __asm__ __volatile__( + " .set push \n" + " .set mips32r2 \n" + " .set noat \n" + " .word 0x41610BC1 # dmt $1 \n" + " ehb \n" + " move %0, $1 \n" + " .set pop \n" + : "=r" (res)); + + instruction_hazard(); + + return res; +} + +static inline void __raw_emt(void) +{ + __asm__ __volatile__( + " .set noreorder \n" + " .set mips32r2 \n" + " emt \n" + " ehb \n" + " .set mips0 \n" + " .set reorder"); +} + +/* enable multiVPE if previous suggested it should be. + EVPE_ENABLE to force */ + +#define EMT_ENABLE VPECONTROL_TE + +static inline void emt(int previous) +{ + if ((previous & EMT_ENABLE)) + __raw_emt(); +} + +static inline void ehb(void) +{ + __asm__ __volatile__( + " .set mips32r2 \n" + " ehb \n" + " .set mips0 \n"); +} + +#define mftc0(rt,sel) \ +({ \ + unsigned long __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set mips32r2 \n" \ + " .set noat \n" \ + " # mftc0 $1, $" #rt ", " #sel " \n" \ + " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__res)); \ + \ + __res; \ +}) + +#define mftgpr(rt) \ +({ \ + unsigned long __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set mips32r2 \n" \ + " mftgpr %0," #rt " \n" \ + " .set pop \n" \ + : "=r" (__res)); \ + \ + __res; \ +}) + +#define mftr(rt,u,sel) \ +({ \ + unsigned long __res; \ + \ + __asm__ __volatile__( \ + ".set noat\n\t" \ + "mftr\t%0, " #rt ", " #u ", " #sel "\n\t" \ + ".set at\n\t" \ + : "=r" (__res)); \ + \ + __res; \ +}) + +#define mttgpr(rd,v) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set mips32r2 \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mttgpr $1, " #rd " \n" \ + " .word 0x41810020 | (" #rd " << 11) \n" \ + " .set pop \n" \ + : : "r" (v)); \ +} while (0) + +#define mttc0(rd,sel,v) \ +({ \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set mips32r2 \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mttc0 %0," #rd ", " #sel " \n" \ + " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \ + " .set pop \n" \ + : \ + : "r" (v)); \ +}) + + +#define mttr(rd,u,sel,v) \ +({ \ + __asm__ __volatile__( \ + "mttr %0," #rd ", " #u ", " #sel \ + : : "r" (v)); \ +}) + + +#define settc(tc) \ +do { \ + write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \ + ehb(); \ +} while (0) + + +/* you *must* set the target tc (settc) before trying to use these */ +#define read_vpe_c0_vpecontrol() mftc0(1, 1) +#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) +#define read_vpe_c0_vpeconf0() mftc0(1, 2) +#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) +#define read_vpe_c0_status() mftc0(12, 0) +#define write_vpe_c0_status(val) mttc0(12, 0, val) +#define read_vpe_c0_cause() mftc0(13, 0) +#define write_vpe_c0_cause(val) mttc0(13, 0, val) +#define read_vpe_c0_config() mftc0(16, 0) +#define write_vpe_c0_config(val) mttc0(16, 0, val) +#define read_vpe_c0_config1() mftc0(16, 1) +#define write_vpe_c0_config1(val) mttc0(16, 1, val) +#define read_vpe_c0_config7() mftc0(16, 7) +#define write_vpe_c0_config7(val) mttc0(16, 7, val) +#define read_vpe_c0_ebase() mftc0(15,1) +#define write_vpe_c0_ebase(val) mttc0(15, 1, val) +#define write_vpe_c0_compare(val) mttc0(11, 0, val) + + +/* TC */ +#define read_tc_c0_tcstatus() mftc0(2, 1) +#define write_tc_c0_tcstatus(val) mttc0(2,1,val) +#define read_tc_c0_tcbind() mftc0(2, 2) +#define write_tc_c0_tcbind(val) mttc0(2,2,val) +#define read_tc_c0_tcrestart() mftc0(2, 3) +#define write_tc_c0_tcrestart(val) mttc0(2,3,val) +#define read_tc_c0_tchalt() mftc0(2, 4) +#define write_tc_c0_tchalt(val) mttc0(2,4,val) +#define read_tc_c0_tccontext() mftc0(2, 5) +#define write_tc_c0_tccontext(val) mttc0(2,5,val) + +/* GPR */ +#define read_tc_gpr_sp() mftgpr(29) +#define write_tc_gpr_sp(val) mttgpr(29, val) +#define read_tc_gpr_gp() mftgpr(28) +#define write_tc_gpr_gp(val) mttgpr(28, val) + +__BUILD_SET_C0(mvpcontrol) + +#endif /* Not __ASSEMBLY__ */ + +#endif diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 2197aa4ce456..80370e0a5589 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -8,7 +8,7 @@ * Modified for further R[236]000 support by Paul M. Antoine, 1996. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2003 Maciej W. Rozycki + * Copyright (C) 2003, 2004 Maciej W. Rozycki */ #ifndef _ASM_MIPSREGS_H #define _ASM_MIPSREGS_H @@ -96,6 +96,16 @@ #define CP0_S1_INTCONTROL $20 /* + * Coprocessor 0 Set 2 register names + */ +#define CP0_S2_SRSCTL $12 /* MIPSR2 */ + +/* + * Coprocessor 0 Set 3 register names + */ +#define CP0_S3_SRSMAP $12 /* MIPSR2 */ + +/* * TX39 Series */ #define CP0_TX39_CACHE $7 @@ -281,6 +291,11 @@ #define ST0_DL (_ULCAST_(1) << 24) /* + * Enable the MIPS DSP ASE + */ +#define ST0_MX 0x01000000 + +/* * Bitfields in the TX39 family CP0 Configuration Register 3 */ #define TX39_CONF_ICS_SHIFT 19 @@ -433,6 +448,14 @@ #define R5K_CONF_SE (_ULCAST_(1) << 12) #define R5K_CONF_SS (_ULCAST_(3) << 20) +/* Bits specific to the RM7000. */ +#define RM7K_CONF_SE (_ULCAST_(1) << 3) +#define RM7K_CONF_TE (_ULCAST_(1) << 12) +#define RM7K_CONF_CLK (_ULCAST_(1) << 16) +#define RM7K_CONF_TC (_ULCAST_(1) << 17) +#define RM7K_CONF_SI (_ULCAST_(3) << 20) +#define RM7K_CONF_SC (_ULCAST_(1) << 31) + /* Bits specific to the R10000. */ #define R10K_CONF_DN (_ULCAST_(3) << 3) #define R10K_CONF_CT (_ULCAST_(1) << 5) @@ -475,6 +498,53 @@ #define MIPS_CONF_M (_ULCAST_(1) << 31) /* + * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. + */ +#define MIPS_CONF1_FP (_ULCAST_(1) << 0) +#define MIPS_CONF1_EP (_ULCAST_(1) << 1) +#define MIPS_CONF1_CA (_ULCAST_(1) << 2) +#define MIPS_CONF1_WR (_ULCAST_(1) << 3) +#define MIPS_CONF1_PC (_ULCAST_(1) << 4) +#define MIPS_CONF1_MD (_ULCAST_(1) << 5) +#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) +#define MIPS_CONF1_DA (_ULCAST_(7) << 7) +#define MIPS_CONF1_DL (_ULCAST_(7) << 10) +#define MIPS_CONF1_DS (_ULCAST_(7) << 13) +#define MIPS_CONF1_IA (_ULCAST_(7) << 16) +#define MIPS_CONF1_IL (_ULCAST_(7) << 19) +#define MIPS_CONF1_IS (_ULCAST_(7) << 22) +#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) + +#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) +#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) +#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) +#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) +#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) +#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) +#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) +#define MIPS_CONF2_TU (_ULCAST_(7) << 28) + +#define MIPS_CONF3_TL (_ULCAST_(1) << 0) +#define MIPS_CONF3_SM (_ULCAST_(1) << 1) +#define MIPS_CONF3_MT (_ULCAST_(1) << 2) +#define MIPS_CONF3_SP (_ULCAST_(1) << 4) +#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) +#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) +#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) +#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) + +/* + * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. + */ +#define MIPS_FPIR_S (_ULCAST_(1) << 16) +#define MIPS_FPIR_D (_ULCAST_(1) << 17) +#define MIPS_FPIR_PS (_ULCAST_(1) << 18) +#define MIPS_FPIR_3D (_ULCAST_(1) << 19) +#define MIPS_FPIR_W (_ULCAST_(1) << 20) +#define MIPS_FPIR_L (_ULCAST_(1) << 21) +#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) + +/* * R10000 performance counter definitions. * * FIXME: The R10000 performance counter opens a nice way to implement CPU @@ -621,13 +691,13 @@ do { \ if (sel == 0) \ __asm__ __volatile__( \ "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" ((unsigned int)value)); \ + : : "Jr" ((unsigned int)(value))); \ else \ __asm__ __volatile__( \ ".set\tmips32\n\t" \ "mtc0\t%z0, " #register ", " #sel "\n\t" \ ".set\tmips0" \ - : : "Jr" ((unsigned int)value)); \ + : : "Jr" ((unsigned int)(value))); \ } while (0) #define __write_64bit_c0_register(register, sel, value) \ @@ -676,7 +746,7 @@ do { \ do { \ __asm__ __volatile__( \ "ctc0\t%z0, " #register "\n\t" \ - : : "Jr" ((unsigned int)value)); \ + : : "Jr" ((unsigned int)(value))); \ } while (0) /* @@ -769,12 +839,24 @@ do { \ #define read_c0_count() __read_32bit_c0_register($9, 0) #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) +#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ +#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) + +#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ +#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) + #define read_c0_entryhi() __read_ulong_c0_register($10, 0) #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) #define read_c0_compare() __read_32bit_c0_register($11, 0) #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) +#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ +#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) + +#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ +#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) + #define read_c0_status() __read_32bit_c0_register($12, 0) #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) @@ -790,10 +872,18 @@ do { \ #define read_c0_config1() __read_32bit_c0_register($16, 1) #define read_c0_config2() __read_32bit_c0_register($16, 2) #define read_c0_config3() __read_32bit_c0_register($16, 3) +#define read_c0_config4() __read_32bit_c0_register($16, 4) +#define read_c0_config5() __read_32bit_c0_register($16, 5) +#define read_c0_config6() __read_32bit_c0_register($16, 6) +#define read_c0_config7() __read_32bit_c0_register($16, 7) #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) +#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) +#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) +#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) +#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) /* * The WatchLo register. There may be upto 8 of them. @@ -917,6 +1007,22 @@ do { \ #define read_c0_errorepc() __read_ulong_c0_register($30, 0) #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) +/* MIPSR2 */ +#define read_c0_hwrena() __read_32bit_c0_register($7,0) +#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) + +#define read_c0_intctl() __read_32bit_c0_register($12, 1) +#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) + +#define read_c0_srsctl() __read_32bit_c0_register($12, 2) +#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) + +#define read_c0_srsmap() __read_32bit_c0_register($12, 3) +#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) + +#define read_c0_ebase() __read_32bit_c0_register($15,1) +#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) + /* * Macros to access the floating point coprocessor control registers */ @@ -930,6 +1036,284 @@ do { \ : "=r" (__res)); \ __res;}) +#define rddsp(mask) \ +({ \ + unsigned int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # rddsp $1, %x1 \n" \ + " .word 0x7c000cb8 | (%x1 << 16) \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) + +#define wrdsp(val, mask) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # wrdsp $1, %x1 \n" \ + " .word 0x7c2004f8 | (%x1 << 15) \n" \ + " .set pop \n" \ + : \ + : "r" (val), "i" (mask)); \ +} while (0) + +#if 0 /* Need DSP ASE capable assembler ... */ +#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) +#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) +#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) +#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;}) + +#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;}) +#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;}) +#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;}) +#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;}) + +#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x)) +#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x)) +#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x)) +#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x)) + +#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x)) +#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x)) +#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x)) +#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x)) + +#else + +#define mfhi0() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mfhi %0, $ac0 \n" \ + " .word 0x00000810 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mfhi1() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mfhi %0, $ac1 \n" \ + " .word 0x00200810 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mfhi2() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mfhi %0, $ac2 \n" \ + " .word 0x00400810 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mfhi3() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mfhi %0, $ac3 \n" \ + " .word 0x00600810 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mflo0() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mflo %0, $ac0 \n" \ + " .word 0x00000812 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mflo1() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mflo %0, $ac1 \n" \ + " .word 0x00200812 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mflo2() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mflo %0, $ac2 \n" \ + " .word 0x00400812 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mflo3() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mflo %0, $ac3 \n" \ + " .word 0x00600812 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mthi0(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mthi $1, $ac0 \n" \ + " .word 0x00200011 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mthi1(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mthi $1, $ac1 \n" \ + " .word 0x00200811 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mthi2(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mthi $1, $ac2 \n" \ + " .word 0x00201011 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mthi3(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mthi $1, $ac3 \n" \ + " .word 0x00201811 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mtlo0(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mtlo $1, $ac0 \n" \ + " .word 0x00200013 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mtlo1(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mtlo $1, $ac1 \n" \ + " .word 0x00200813 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mtlo2(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mtlo $1, $ac2 \n" \ + " .word 0x00201013 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mtlo3(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mtlo $1, $ac3 \n" \ + " .word 0x00201813 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#endif + /* * TLB operations. * @@ -1012,6 +1396,8 @@ __BUILD_SET_C0(status) __BUILD_SET_C0(cause) __BUILD_SET_C0(config) __BUILD_SET_C0(intcontrol) +__BUILD_SET_C0(intctl) +__BUILD_SET_C0(srsmap) #endif /* !__ASSEMBLY__ */ diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h index 45cd72d172e8..19cdf7642e66 100644 --- a/include/asm-mips/mmu_context.h +++ b/include/asm-mips/mmu_context.h @@ -30,7 +30,7 @@ extern unsigned long pgd_current[]; #ifdef CONFIG_32BIT #define TLBMISS_HANDLER_SETUP() \ - write_c0_context((unsigned long) smp_processor_id() << 23); \ + write_c0_context((unsigned long) smp_processor_id() << 25); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) #endif #if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) @@ -40,7 +40,7 @@ extern unsigned long pgd_current[]; #endif #if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64) #define TLBMISS_HANDLER_SETUP() \ - write_c0_context((unsigned long) smp_processor_id() << 23); \ + write_c0_context((unsigned long) smp_processor_id() << 26); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) #endif diff --git a/include/asm-mips/mmzone.h b/include/asm-mips/mmzone.h index d721143dbd47..011caebac369 100644 --- a/include/asm-mips/mmzone.h +++ b/include/asm-mips/mmzone.h @@ -5,6 +5,7 @@ #ifndef _ASM_MMZONE_H_ #define _ASM_MMZONE_H_ +#include <linux/config.h> #include <asm/page.h> #include <mmzone.h> diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h index 0be58b2aeb9f..2be399311eec 100644 --- a/include/asm-mips/module.h +++ b/include/asm-mips/module.h @@ -14,15 +14,23 @@ struct mod_arch_specific { typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */ -typedef struct -{ - Elf64_Addr r_offset; /* Address of relocation. */ - Elf64_Word r_sym; /* Symbol index. */ - Elf64_Byte r_ssym; /* Special symbol. */ - Elf64_Byte r_type3; /* Third relocation. */ - Elf64_Byte r_type2; /* Second relocation. */ - Elf64_Byte r_type; /* First relocation. */ - Elf64_Sxword r_addend; /* Addend. */ +typedef struct { + Elf64_Addr r_offset; /* Address of relocation. */ + Elf64_Word r_sym; /* Symbol index. */ + Elf64_Byte r_ssym; /* Special symbol. */ + Elf64_Byte r_type3; /* Third relocation. */ + Elf64_Byte r_type2; /* Second relocation. */ + Elf64_Byte r_type; /* First relocation. */ +} Elf64_Mips_Rel; + +typedef struct { + Elf64_Addr r_offset; /* Address of relocation. */ + Elf64_Word r_sym; /* Symbol index. */ + Elf64_Byte r_ssym; /* Special symbol. */ + Elf64_Byte r_type3; /* Third relocation. */ + Elf64_Byte r_type2; /* Second relocation. */ + Elf64_Byte r_type; /* First relocation. */ + Elf64_Sxword r_addend; /* Addend. */ } Elf64_Mips_Rela; #ifdef CONFIG_32BIT @@ -30,6 +38,13 @@ typedef struct #define Elf_Shdr Elf32_Shdr #define Elf_Sym Elf32_Sym #define Elf_Ehdr Elf32_Ehdr +#define Elf_Addr Elf32_Addr + +#define Elf_Mips_Rel Elf32_Rel +#define Elf_Mips_Rela Elf32_Rela + +#define ELF_MIPS_R_SYM(rel) ELF32_R_SYM(rel.r_info) +#define ELF_MIPS_R_TYPE(rel) ELF32_R_TYPE(rel.r_info) #endif @@ -38,6 +53,13 @@ typedef struct #define Elf_Shdr Elf64_Shdr #define Elf_Sym Elf64_Sym #define Elf_Ehdr Elf64_Ehdr +#define Elf_Addr Elf64_Addr + +#define Elf_Mips_Rel Elf64_Mips_Rel +#define Elf_Mips_Rela Elf64_Mips_Rela + +#define ELF_MIPS_R_SYM(rel) (rel.r_sym) +#define ELF_MIPS_R_TYPE(rel) (rel.r_type) #endif @@ -53,4 +75,54 @@ search_module_dbetables(unsigned long addr) } #endif +#ifdef CONFIG_CPU_MIPS32_R1 +#define MODULE_PROC_FAMILY "MIPS32_R1" +#elif defined CONFIG_CPU_MIPS32_R2 +#define MODULE_PROC_FAMILY "MIPS32_R2" +#elif defined CONFIG_CPU_MIPS64_R1 +#define MODULE_PROC_FAMILY "MIPS64_R1" +#elif defined CONFIG_CPU_MIPS64_R2 +#define MODULE_PROC_FAMILY "MIPS64_R2" +#elif defined CONFIG_CPU_R3000 +#define MODULE_PROC_FAMILY "R3000" +#elif defined CONFIG_CPU_TX39XX +#define MODULE_PROC_FAMILY "TX39XX" +#elif defined CONFIG_CPU_VR41XX +#define MODULE_PROC_FAMILY "VR41XX" +#elif defined CONFIG_CPU_R4300 +#define MODULE_PROC_FAMILY "R4300" +#elif defined CONFIG_CPU_R4X00 +#define MODULE_PROC_FAMILY "R4X00" +#elif defined CONFIG_CPU_TX49XX +#define MODULE_PROC_FAMILY "TX49XX" +#elif defined CONFIG_CPU_R5000 +#define MODULE_PROC_FAMILY "R5000" +#elif defined CONFIG_CPU_R5432 +#define MODULE_PROC_FAMILY "R5432" +#elif defined CONFIG_CPU_R6000 +#define MODULE_PROC_FAMILY "R6000" +#elif defined CONFIG_CPU_NEVADA +#define MODULE_PROC_FAMILY "NEVADA" +#elif defined CONFIG_CPU_R8000 +#define MODULE_PROC_FAMILY "R8000" +#elif defined CONFIG_CPU_R10000 +#define MODULE_PROC_FAMILY "R10000" +#elif defined CONFIG_CPU_RM7000 +#define MODULE_PROC_FAMILY "RM7000" +#elif defined CONFIG_CPU_RM9000 +#define MODULE_PROC_FAMILY "RM9000" +#elif defined CONFIG_CPU_SB1 +#define MODULE_PROC_FAMILY "SB1" +#else +#error MODULE_PROC_FAMILY undefined for your processor configuration +#endif + +#ifdef CONFIG_32BIT +#define MODULE_KERNEL_TYPE "32BIT " +#elif defined CONFIG_64BIT +#define MODULE_KERNEL_TYPE "64BIT " +#endif + +#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY MODULE_KERNEL_TYPE + #endif /* _ASM_MODULE_H */ diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h index 309bc3099f68..46f2d23d2697 100644 --- a/include/asm-mips/paccess.h +++ b/include/asm-mips/paccess.h @@ -52,7 +52,7 @@ struct __large_pstruct { unsigned long buf[100]; }; }) #define __get_dbe_asm(insn) \ -({ \ +{ \ __asm__ __volatile__( \ "1:\t" insn "\t%1,%2\n\t" \ "move\t%0,$0\n" \ @@ -67,7 +67,7 @@ struct __large_pstruct { unsigned long buf[100]; }; ".previous" \ :"=r" (__gu_err), "=r" (__gu_val) \ :"o" (__mp(__gu_addr)), "i" (-EFAULT)); \ -}) +} extern void __get_dbe_unknown(void); @@ -90,7 +90,7 @@ extern void __get_dbe_unknown(void); }) #define __put_dbe_asm(insn) \ -({ \ +{ \ __asm__ __volatile__( \ "1:\t" insn "\t%1,%2\n\t" \ "move\t%0,$0\n" \ @@ -104,7 +104,7 @@ extern void __get_dbe_unknown(void); ".previous" \ : "=r" (__pu_err) \ : "r" (__pu_val), "o" (__mp(__pu_addr)), "i" (-EFAULT)); \ -}) +} extern void __put_dbe_unknown(void); diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index 652b6d67a571..ee25a779bf49 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -87,22 +87,48 @@ static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, typedef struct { unsigned long pte; } pte_t; #define pte_val(x) ((x).pte) #endif +#define __pte(x) ((pte_t) { (x) } ) -typedef struct { unsigned long pmd; } pmd_t; -typedef struct { unsigned long pgd; } pgd_t; -typedef struct { unsigned long pgprot; } pgprot_t; +/* + * For 3-level pagetables we defines these ourselves, for 2-level the + * definitions are supplied by <asm-generic/pgtable-nopmd.h>. + */ +#ifdef CONFIG_64BIT +typedef struct { unsigned long pmd; } pmd_t; #define pmd_val(x) ((x).pmd) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) +#define __pmd(x) ((pmd_t) { (x) } ) -#define ptep_buddy(x) ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t))) +#endif -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) +/* + * Right now we don't support 4-level pagetables, so all pud-related + * definitions come from <asm-generic/pgtable-nopud.h>. + */ + +/* + * Finall the top of the hierarchy, the pgd + */ +typedef struct { unsigned long pgd; } pgd_t; +#define pgd_val(x) ((x).pgd) #define __pgd(x) ((pgd_t) { (x) } ) + +/* + * Manipulate page protection bits + */ +typedef struct { unsigned long pgprot; } pgprot_t; +#define pgprot_val(x) ((x).pgprot) #define __pgprot(x) ((pgprot_t) { (x) } ) +/* + * On R4000-style MMUs where a TLB entry is mapping a adjacent even / odd + * pair of pages we only have a single global bit per pair of pages. When + * writing to the TLB make sure we always have the bit set for both pages + * or none. This macro is used to access the `buddy' of the pte we're just + * working on. + */ +#define ptep_buddy(x) ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t))) + #endif /* !__ASSEMBLY__ */ /* to align the pointer to the (next) page boundary */ diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index c9a00ca1c012..6c9ad8171a77 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -40,6 +40,11 @@ struct pci_controller { unsigned int need_domain_info; int iommu; + + /* Optional access methods for reading/writing the bus number + of the PCI controller */ + int (*get_busno)(void); + void (*set_busno)(int busno); }; /* @@ -142,8 +147,22 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, extern void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res); -extern void pcibios_bus_to_resource(struct pci_dev *dev, - struct resource *res, struct pci_bus_region *region); + +extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, + struct pci_bus_region *region); + +static inline struct resource * +pcibios_select_root(struct pci_dev *pdev, struct resource *res) +{ + struct resource *root = NULL; + + if (res->flags & IORESOURCE_IO) + root = &ioport_resource; + if (res->flags & IORESOURCE_MEM) + root = &iomem_resource; + + return root; +} #ifdef CONFIG_PCI_DOMAINS @@ -169,17 +188,4 @@ static inline void pcibios_add_platform_entries(struct pci_dev *dev) /* Do platform specific device initialization at pci_enable_device() time */ extern int pcibios_plat_dev_init(struct pci_dev *dev); -static inline struct resource * -pcibios_select_root(struct pci_dev *pdev, struct resource *res) -{ - struct resource *root = NULL; - - if (res->flags & IORESOURCE_IO) - root = &ioport_resource; - if (res->flags & IORESOURCE_MEM) - root = &iomem_resource; - - return root; -} - #endif /* _ASM_PCI_H */ diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h index ce57288d43bd..fe1df572318b 100644 --- a/include/asm-mips/pgalloc.h +++ b/include/asm-mips/pgalloc.h @@ -26,10 +26,22 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, } /* + * Initialize a new pmd table with invalid pointers. + */ +extern void pmd_init(unsigned long page, unsigned long pagetable); + +#ifdef CONFIG_64BIT + +static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) +{ + set_pud(pud, __pud((unsigned long)pmd)); +} +#endif + +/* * Initialize a new pgd / pmd table with invalid pointers. */ extern void pgd_init(unsigned long page); -extern void pmd_init(unsigned long page, unsigned long pagetable); static inline pgd_t *pgd_alloc(struct mm_struct *mm) { @@ -86,21 +98,18 @@ static inline void pte_free(struct page *pte) #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) #ifdef CONFIG_32BIT -#define pgd_populate(mm, pmd, pte) BUG() /* * allocating and freeing a pmd is trivial: the 1-entry pmd is * inside the pgd, so has no extra memory associated with it. */ -#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); }) #define pmd_free(x) do { } while (0) #define __pmd_free_tlb(tlb,x) do { } while (0) + #endif #ifdef CONFIG_64BIT -#define pgd_populate(mm, pgd, pmd) set_pgd(pgd, __pgd(pmd)) - static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) { pmd_t *pmd; diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h index 7fec93b76da9..0cff64ce0fb8 100644 --- a/include/asm-mips/pgtable-32.h +++ b/include/asm-mips/pgtable-32.h @@ -17,6 +17,8 @@ #include <asm/cachectl.h> #include <asm/fixmap.h> +#include <asm-generic/pgtable-nopmd.h> + /* * - add_wired_entry() add a fixed TLB entry, and move wired register */ @@ -41,42 +43,38 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, * works even with the cache aliasing problem the R4k and above have. */ -/* PMD_SHIFT determines the size of the area a second-level page table can map */ +/* PGDIR_SHIFT determines what a third-level page table entry can map */ #ifdef CONFIG_64BIT_PHYS_ADDR -#define PMD_SHIFT 21 +#define PGDIR_SHIFT 21 #else -#define PMD_SHIFT 22 +#define PGDIR_SHIFT 22 #endif -#define PMD_SIZE (1UL << PMD_SHIFT) -#define PMD_MASK (~(PMD_SIZE-1)) - -/* PGDIR_SHIFT determines what a third-level page table entry can map */ -#define PGDIR_SHIFT PMD_SHIFT #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) /* * Entries per page directory level: we use two-level, so - * we don't really have any PMD directory physically. + * we don't really have any PUD/PMD directory physically. */ #ifdef CONFIG_64BIT_PHYS_ADDR #define PGD_ORDER 1 -#define PMD_ORDER 0 +#define PUD_ORDER aieeee_attempt_to_allocate_pud +#define PMD_ORDER 1 #define PTE_ORDER 0 #else #define PGD_ORDER 0 -#define PMD_ORDER 0 +#define PUD_ORDER aieeee_attempt_to_allocate_pud +#define PMD_ORDER 1 #define PTE_ORDER 0 #endif #define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) -#define PTRS_PER_PMD 1 #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) #define FIRST_USER_ADDRESS 0 -#define VMALLOC_START KSEG2 +#define VMALLOC_START MAP_BASE #ifdef CONFIG_HIGHMEM # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE) @@ -91,8 +89,6 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, #define pte_ERROR(e) \ printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) #endif -#define pmd_ERROR(e) \ - printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) #define pgd_ERROR(e) \ printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) @@ -120,17 +116,7 @@ static inline void pmd_clear(pmd_t *pmdp) pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); } -/* - * The "pgd_xxx()" functions here are trivial for a folded two-level - * setup: the pgd is never bad, and a pmd always exists (as it's folded - * into the pgd entry) - */ -static inline int pgd_none(pgd_t pgd) { return 0; } -static inline int pgd_bad(pgd_t pgd) { return 0; } -static inline int pgd_present(pgd_t pgd) { return 1; } -static inline void pgd_clear(pgd_t *pgdp) { } - -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) #define pte_page(x) pfn_to_page(pte_pfn(x)) #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) static inline pte_t @@ -151,27 +137,22 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) #else #define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) -#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) +#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) #endif -#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ +#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */ #define __pgd_offset(address) pgd_index(address) +#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) #define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) /* to find an entry in a kernel page-table-directory */ #define pgd_offset_k(address) pgd_offset(&init_mm, address) -#define pgd_index(address) ((address) >> PGDIR_SHIFT) +#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) /* to find an entry in a page-table-directory */ #define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) -/* Find an entry in the second-level page table.. */ -static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address) -{ - return (pmd_t *) dir; -} - /* Find an entry in the third-level page table.. */ #define __pte_offset(address) \ (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) @@ -221,7 +202,7 @@ static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address) */ #define PTE_FILE_MAX_BITS 27 -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) /* fixme */ #define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f)) #define pgoff_to_pte(off) \ diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h index 1011e0635f56..3e0a522c0f0e 100644 --- a/include/asm-mips/pgtable-64.h +++ b/include/asm-mips/pgtable-64.h @@ -16,13 +16,15 @@ #include <asm/page.h> #include <asm/cachectl.h> +#include <asm-generic/pgtable-nopud.h> + /* * Each address space has 2 4K pages as its page directory, giving 1024 * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a - * pair of 4K pages, giving 1024 (== PTRS_PER_PMD) 8 byte pointers to - * page tables. Each page table is a single 4K page, giving 512 (== - * PTRS_PER_PTE) 8 byte ptes. Each pgde is initialized to point to - * invalid_pmd_table, each pmde is initialized to point to + * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page + * tables. Each page table is also a single 4K page, giving 512 (== + * PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to + * invalid_pmd_table, each pmd entry is initialized to point to * invalid_pte_table, each pte is initialized to 0. When memory is low, * and a pmd table or a page table allocation fails, empty_bad_pmd_table * and empty_bad_page_table is returned back to higher layer code, so @@ -36,17 +38,17 @@ */ /* PMD_SHIFT determines the size of the area a second-level page table can map */ -#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3)) +#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3)) #define PMD_SIZE (1UL << PMD_SHIFT) #define PMD_MASK (~(PMD_SIZE-1)) /* PGDIR_SHIFT determines what a third-level page table entry can map */ -#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + 1 - 3)) +#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3)) #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) /* - * For 4kB page size we use a 3 level page tree and a 8kB pmd and pgds which + * For 4kB page size we use a 3 level page tree and an 8kB pud, which * permits us mapping 40 bits of virtual address space. * * We used to implement 41 bits by having an order 1 pmd level but that seemed @@ -57,7 +59,7 @@ * two levels would be easy to implement. * * For 16kB page size we use a 2 level page tree which permits a total of - * 36 bits of virtual address space. We could add a third leve. but it seems + * 36 bits of virtual address space. We could add a third level but it seems * like at the moment there's no need for this. * * For 64kB page size we use a 2 level page table tree for a total of 42 bits @@ -65,21 +67,25 @@ */ #ifdef CONFIG_PAGE_SIZE_4KB #define PGD_ORDER 1 +#define PUD_ORDER aieeee_attempt_to_allocate_pud #define PMD_ORDER 0 #define PTE_ORDER 0 #endif #ifdef CONFIG_PAGE_SIZE_8KB #define PGD_ORDER 0 +#define PUD_ORDER aieeee_attempt_to_allocate_pud #define PMD_ORDER 0 #define PTE_ORDER 0 #endif #ifdef CONFIG_PAGE_SIZE_16KB #define PGD_ORDER 0 +#define PUD_ORDER aieeee_attempt_to_allocate_pud #define PMD_ORDER 0 #define PTE_ORDER 0 #endif #ifdef CONFIG_PAGE_SIZE_64KB #define PGD_ORDER 0 +#define PUD_ORDER aieeee_attempt_to_allocate_pud #define PMD_ORDER 0 #define PTE_ORDER 0 #endif @@ -91,7 +97,7 @@ #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) #define FIRST_USER_ADDRESS 0 -#define VMALLOC_START XKSEG +#define VMALLOC_START MAP_BASE #define VMALLOC_END \ (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE) @@ -102,13 +108,13 @@ #define pgd_ERROR(e) \ printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) -extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)]; -extern pte_t empty_bad_page_table[PAGE_SIZE/sizeof(pte_t)]; -extern pmd_t invalid_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)]; -extern pmd_t empty_bad_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)]; +extern pte_t invalid_pte_table[PTRS_PER_PTE]; +extern pte_t empty_bad_page_table[PTRS_PER_PTE]; +extern pmd_t invalid_pmd_table[PTRS_PER_PMD]; +extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD]; /* - * Empty pmd entries point to the invalid_pte_table. + * Empty pgd/pmd entries point to the invalid_pte_table. */ static inline int pmd_none(pmd_t pmd) { @@ -128,26 +134,30 @@ static inline void pmd_clear(pmd_t *pmdp) } /* - * Empty pgd entries point to the invalid_pmd_table. + * Empty pud entries point to the invalid_pmd_table. */ -static inline int pgd_none(pgd_t pgd) +static inline int pud_none(pud_t pud) { - return pgd_val(pgd) == (unsigned long) invalid_pmd_table; + return pud_val(pud) == (unsigned long) invalid_pmd_table; } -#define pgd_bad(pgd) (pgd_val(pgd) &~ PAGE_MASK) +static inline int pud_bad(pud_t pud) +{ + return pud_val(pud) & ~PAGE_MASK; +} -static inline int pgd_present(pgd_t pgd) +static inline int pud_present(pud_t pud) { - return pgd_val(pgd) != (unsigned long) invalid_pmd_table; + return pud_val(pud) != (unsigned long) invalid_pmd_table; } -static inline void pgd_clear(pgd_t *pgdp) +static inline void pud_clear(pud_t *pudp) { - pgd_val(*pgdp) = ((unsigned long) invalid_pmd_table); + pud_val(*pudp) = ((unsigned long) invalid_pmd_table); } -#define pte_page(x) pfn_to_page((unsigned long)((pte_val(x) >> PAGE_SHIFT))) +#define pte_page(x) pfn_to_page(pte_pfn(x)) + #ifdef CONFIG_CPU_VR41XX #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) @@ -157,26 +167,28 @@ static inline void pgd_clear(pgd_t *pgdp) #endif #define __pgd_offset(address) pgd_index(address) +#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) +#define __pmd_offset(address) pmd_index(address) #define page_pte(page) page_pte_prot(page, __pgprot(0)) /* to find an entry in a kernel page-table-directory */ #define pgd_offset_k(address) pgd_offset(&init_mm, 0) -#define pgd_index(address) ((address) >> PGDIR_SHIFT) +#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) +#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) /* to find an entry in a page-table-directory */ #define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) -static inline unsigned long pgd_page(pgd_t pgd) +static inline unsigned long pud_page(pud_t pud) { - return pgd_val(pgd); + return pud_val(pud); } /* Find an entry in the second-level page table.. */ -static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address) +static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address) { - return (pmd_t *) pgd_page(*dir) + - ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1)); + return (pmd_t *) pud_page(*pud) + pmd_index(address); } /* Find an entry in the third-level page table.. */ diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h index 3aad751ccd5f..01e76e932e3f 100644 --- a/include/asm-mips/pgtable-bits.h +++ b/include/asm-mips/pgtable-bits.h @@ -33,7 +33,7 @@ * unpredictable things. The code (when it is written) to deal with * this problem will be in the update_mmu_cache() code for the r4k. */ -#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) +#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) #define _PAGE_PRESENT (1<<6) /* implemented in software */ #define _PAGE_READ (1<<7) /* implemented in software */ @@ -123,7 +123,7 @@ #endif #endif -#endif /* defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) */ +#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */ #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) @@ -140,7 +140,7 @@ #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW #endif -#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) +#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3) #else #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9) diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index eaf5d9b3a0e1..1e8ae2723be4 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -8,8 +8,6 @@ #ifndef _ASM_PGTABLE_H #define _ASM_PGTABLE_H -#include <asm-generic/4level-fixup.h> - #include <linux/config.h> #ifdef CONFIG_32BIT #include <asm/pgtable-32.h> @@ -18,6 +16,7 @@ #include <asm/pgtable-64.h> #endif +#include <asm/io.h> #include <asm/pgtable-bits.h> #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) @@ -84,7 +83,7 @@ extern void paging_init(void); #define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL)) #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) static inline void set_pte(pte_t *ptep, pte_t pte) { ptep->pte_high = pte.pte_high; @@ -148,11 +147,18 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt #endif /* - * (pmds are folded into pgds so this doesn't get actually called, + * (pmds are folded into puds so this doesn't get actually called, * but the define is needed for a generic inline function.) */ #define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0) -#define set_pgd(pgdptr, pgdval) do { *(pgdptr) = (pgdval); } while(0) + +#ifdef CONFIG_64BIT +/* + * (puds are folded into pgds so this doesn't get actually called, + * but the define is needed for a generic inline function.) + */ +#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0) +#endif #define PGD_T_LOG2 ffz(~sizeof(pgd_t)) #define PMD_T_LOG2 ffz(~sizeof(pmd_t)) @@ -165,7 +171,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; * Undefined behaviour if not.. */ static inline int pte_user(pte_t pte) { BUG(); return 0; } -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_READ; } static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_WRITE; } static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_MODIFIED; } @@ -324,7 +330,7 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot) */ #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) { pte.pte_low &= _PAGE_CHG_MASK; @@ -357,7 +363,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, #endif #ifdef CONFIG_64BIT_PHYS_ADDR -extern phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size); extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot); static inline int io_remap_pfn_range(struct vm_area_struct *vma, @@ -367,7 +372,7 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma, pgprot_t prot) { phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size); - return remap_pfn_range(vma, vaddr, pfn, size, prot); + return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot); } #else #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index d6466aa09fb7..f1980c6c3bcc 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -96,12 +96,26 @@ union mips_fpu_union { {{0,},} \ } +#define NUM_DSP_REGS 6 + +typedef __u32 dspreg_t; + +struct mips_dsp_state { + dspreg_t dspr[NUM_DSP_REGS]; + unsigned int dspcontrol; + unsigned short used_dsp; +}; + +#define INIT_DSP {{0,},} + typedef struct { unsigned long seg; } mm_segment_t; #define ARCH_MIN_TASKALIGN 8 +struct mips_abi; + /* * If you change thread_struct remember to change the #defines below too! */ @@ -117,6 +131,9 @@ struct thread_struct { /* Saved fpu/fpu emulator stuff. */ union mips_fpu_union fpu; + /* Saved state of the DSP ASE, if available. */ + struct mips_dsp_state dsp; + /* Other stuff associated with the thread. */ unsigned long cp0_badvaddr; /* Last user fault */ unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ @@ -129,6 +146,7 @@ struct thread_struct { unsigned long mflags; unsigned long irix_trampoline; /* Wheee... */ unsigned long irix_oldctx; + struct mips_abi *abi; }; #define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR) @@ -151,6 +169,10 @@ struct thread_struct { */ \ INIT_FPU, \ /* \ + * saved dsp/dsp emulator stuff \ + */ \ + INIT_DSP, \ + /* \ * Other stuff associated with the process \ */ \ 0, 0, 0, 0, \ diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h index 2b5c624c3d4f..95c5839ac465 100644 --- a/include/asm-mips/ptrace.h +++ b/include/asm-mips/ptrace.h @@ -22,6 +22,8 @@ #define MMLO 68 #define FPC_CSR 69 #define FPC_EIR 70 +#define DSP_BASE 71 /* 3 more hi / lo register pairs */ +#define DSP_CONTROL 77 /* * This struct defines the way the registers are stored on the stack during a @@ -38,18 +40,18 @@ struct pt_regs { /* Saved special registers. */ unsigned long cp0_status; - unsigned long lo; unsigned long hi; + unsigned long lo; unsigned long cp0_badvaddr; unsigned long cp0_cause; unsigned long cp0_epc; }; /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -/* #define PTRACE_GETREGS 12 */ -/* #define PTRACE_SETREGS 13 */ -/* #define PTRACE_GETFPREGS 14 */ -/* #define PTRACE_SETFPREGS 15 */ +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 +#define PTRACE_GETFPREGS 14 +#define PTRACE_SETFPREGS 15 /* #define PTRACE_GETFPXREGS 18 */ /* #define PTRACE_SETFPXREGS 19 */ @@ -58,6 +60,13 @@ struct pt_regs { #define PTRACE_GET_THREAD_AREA 25 #define PTRACE_SET_THREAD_AREA 26 +/* Calls to trace a 64bit program from a 32bit program. */ +#define PTRACE_PEEKTEXT_3264 0xc0 +#define PTRACE_PEEKDATA_3264 0xc1 +#define PTRACE_POKETEXT_3264 0xc2 +#define PTRACE_POKEDATA_3264 0xc3 +#define PTRACE_GET_THREAD_AREA_3264 0xc4 + #ifdef __KERNEL__ #include <linux/linkage.h> diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index 5bea49feec66..a5ea9d828aee 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -21,7 +21,7 @@ * * - The MIPS32 and MIPS64 specs permit an implementation to directly derive * the index bits from the virtual address. This breaks with tradition - * set by the R4000. To keep unpleassant surprises from happening we pick + * set by the R4000. To keep unpleasant surprises from happening we pick * an address in KSEG0 / CKSEG0. * - We need a properly sign extended address for 64-bit code. To get away * without ifdefs we let the compiler do it by a type cast. @@ -30,11 +30,11 @@ #define cache_op(op,addr) \ __asm__ __volatile__( \ + " .set push \n" \ " .set noreorder \n" \ " .set mips3\n\t \n" \ " cache %0, %1 \n" \ - " .set mips0 \n" \ - " .set reorder" \ + " .set pop \n" \ : \ : "i" (op), "m" (*(unsigned char *)(addr))) @@ -84,14 +84,14 @@ static inline void flush_scache_line(unsigned long addr) static inline void protected_flush_icache_line(unsigned long addr) { __asm__ __volatile__( - ".set noreorder\n\t" - ".set mips3\n" - "1:\tcache %0,(%1)\n" - "2:\t.set mips0\n\t" - ".set reorder\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,2b\n\t" - ".previous" + " .set push \n" + " .set noreorder \n" + " .set mips3 \n" + "1: cache %0, (%1) \n" + "2: .set pop \n" + " .section __ex_table,\"a\" \n" + " "STR(PTR)" 1b, 2b \n" + " .previous" : : "i" (Hit_Invalidate_I), "r" (addr)); } @@ -100,19 +100,19 @@ static inline void protected_flush_icache_line(unsigned long addr) * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style * caches. We're talking about one cacheline unnecessarily getting invalidated - * here so the penaltiy isn't overly hard. + * here so the penalty isn't overly hard. */ static inline void protected_writeback_dcache_line(unsigned long addr) { __asm__ __volatile__( - ".set noreorder\n\t" - ".set mips3\n" - "1:\tcache %0,(%1)\n" - "2:\t.set mips0\n\t" - ".set reorder\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,2b\n\t" - ".previous" + " .set push \n" + " .set noreorder \n" + " .set mips3 \n" + "1: cache %0, (%1) \n" + "2: .set pop \n" + " .section __ex_table,\"a\" \n" + " "STR(PTR)" 1b, 2b \n" + " .previous" : : "i" (Hit_Writeback_Inv_D), "r" (addr)); } @@ -120,14 +120,14 @@ static inline void protected_writeback_dcache_line(unsigned long addr) static inline void protected_writeback_scache_line(unsigned long addr) { __asm__ __volatile__( - ".set noreorder\n\t" - ".set mips3\n" - "1:\tcache %0,(%1)\n" - "2:\t.set mips0\n\t" - ".set reorder\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,2b\n\t" - ".previous" + " .set push \n" + " .set noreorder \n" + " .set mips3 \n" + "1: cache %0, (%1) \n" + "2: .set pop \n" + " .section __ex_table,\"a\" \n" + " "STR(PTR)" 1b, 2b \n" + " .previous" : : "i" (Hit_Writeback_Inv_SD), "r" (addr)); } @@ -142,6 +142,7 @@ static inline void invalidate_tcache_page(unsigned long addr) #define cache16_unroll32(base,op) \ __asm__ __volatile__( \ + " .set push \n" \ " .set noreorder \n" \ " .set mips3 \n" \ " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ @@ -160,8 +161,7 @@ static inline void invalidate_tcache_page(unsigned long addr) " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ - " .set mips0 \n" \ - " .set reorder \n" \ + " .set pop \n" \ : \ : "r" (base), \ "i" (op)); @@ -285,6 +285,7 @@ static inline void blast_scache16_page_indexed(unsigned long page) #define cache32_unroll32(base,op) \ __asm__ __volatile__( \ + " .set push \n" \ " .set noreorder \n" \ " .set mips3 \n" \ " cache %1, 0x000(%0); cache %1, 0x020(%0) \n" \ @@ -303,8 +304,7 @@ static inline void blast_scache16_page_indexed(unsigned long page) " cache %1, 0x340(%0); cache %1, 0x360(%0) \n" \ " cache %1, 0x380(%0); cache %1, 0x3a0(%0) \n" \ " cache %1, 0x3c0(%0); cache %1, 0x3e0(%0) \n" \ - " .set mips0 \n" \ - " .set reorder \n" \ + " .set pop \n" \ : \ : "r" (base), \ "i" (op)); @@ -428,6 +428,7 @@ static inline void blast_scache32_page_indexed(unsigned long page) #define cache64_unroll32(base,op) \ __asm__ __volatile__( \ + " .set push \n" \ " .set noreorder \n" \ " .set mips3 \n" \ " cache %1, 0x000(%0); cache %1, 0x040(%0) \n" \ @@ -446,8 +447,7 @@ static inline void blast_scache32_page_indexed(unsigned long page) " cache %1, 0x680(%0); cache %1, 0x6c0(%0) \n" \ " cache %1, 0x700(%0); cache %1, 0x740(%0) \n" \ " cache %1, 0x780(%0); cache %1, 0x7c0(%0) \n" \ - " .set mips0 \n" \ - " .set reorder \n" \ + " .set pop \n" \ : \ : "r" (base), \ "i" (op)); @@ -532,6 +532,7 @@ static inline void blast_scache64_page_indexed(unsigned long page) #define cache128_unroll32(base,op) \ __asm__ __volatile__( \ + " .set push \n" \ " .set noreorder \n" \ " .set mips3 \n" \ " cache %1, 0x000(%0); cache %1, 0x080(%0) \n" \ @@ -550,8 +551,7 @@ static inline void blast_scache64_page_indexed(unsigned long page) " cache %1, 0xd00(%0); cache %1, 0xd80(%0) \n" \ " cache %1, 0xe00(%0); cache %1, 0xe80(%0) \n" \ " cache %1, 0xf00(%0); cache %1, 0xf80(%0) \n" \ - " .set mips0 \n" \ - " .set reorder \n" \ + " .set pop \n" \ : \ : "r" (base), \ "i" (op)); diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h index 3c4b637fd925..a60e0dc7c9b9 100644 --- a/include/asm-mips/rtc.h +++ b/include/asm-mips/rtc.h @@ -14,7 +14,9 @@ #ifdef __KERNEL__ +#include <linux/spinlock.h> #include <linux/rtc.h> +#include <asm/time.h> #define RTC_PIE 0x40 /* periodic interrupt enable */ #define RTC_AIE 0x20 /* alarm interrupt enable */ @@ -27,11 +29,52 @@ #define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ #define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ -unsigned int get_rtc_time(struct rtc_time *time); -int set_rtc_time(struct rtc_time *time); -unsigned int get_rtc_ss(void); -int get_rtc_pll(struct rtc_pll_info *pll); -int set_rtc_pll(struct rtc_pll_info *pll); +static DEFINE_SPINLOCK(mips_rtc_lock); +static inline unsigned int get_rtc_time(struct rtc_time *time) +{ + unsigned long nowtime; + + spin_lock(&mips_rtc_lock); + nowtime = rtc_get_time(); + to_tm(nowtime, time); + time->tm_year -= 1900; + spin_unlock(&mips_rtc_lock); + + return RTC_24H; +} + +static inline int set_rtc_time(struct rtc_time *time) +{ + unsigned long nowtime; + int ret; + + spin_lock(&mips_rtc_lock); + nowtime = mktime(time->tm_year+1900, time->tm_mon+1, + time->tm_mday, time->tm_hour, time->tm_min, + time->tm_sec); + ret = rtc_set_time(nowtime); + spin_unlock(&mips_rtc_lock); + + return ret; +} + +static inline unsigned int get_rtc_ss(void) +{ + struct rtc_time h; + + get_rtc_time(&h); + return h.tm_sec; +} + +static inline int get_rtc_pll(struct rtc_pll_info *pll) +{ + return -EINVAL; +} + +static inline int set_rtc_pll(struct rtc_pll_info *pll) +{ + return -EINVAL; +} #endif #endif diff --git a/include/asm-mips/rtlx.h b/include/asm-mips/rtlx.h new file mode 100644 index 000000000000..83cdf6ab0d1f --- /dev/null +++ b/include/asm-mips/rtlx.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. + * + */ + +#ifndef _RTLX_H +#define _RTLX_H_ + +#define LX_NODE_BASE 10 + +#define MIPSCPU_INT_BASE 16 +#define MIPS_CPU_RTLX_IRQ 0 + +#define RTLX_VERSION 1 +#define RTLX_xID 0x12345600 +#define RTLX_ID (RTLX_xID | RTLX_VERSION) +#define RTLX_CHANNELS 8 + +enum rtlx_state { + RTLX_STATE_UNUSED = 0, + RTLX_STATE_INITIALISED, + RTLX_STATE_REMOTE_READY, + RTLX_STATE_OPENED +}; + +#define RTLX_BUFFER_SIZE 1024 +/* each channel supports read and write. + linux (vpe0) reads lx_buffer and writes rt_buffer + SP (vpe1) reads rt_buffer and writes lx_buffer +*/ +typedef struct rtlx_channel { + enum rtlx_state rt_state; + enum rtlx_state lx_state; + + int buffer_size; + + /* read and write indexes per buffer */ + int rt_write, rt_read; + char *rt_buffer; + + int lx_write, lx_read; + char *lx_buffer; + + void *queues; + +} rtlx_channel_t; + +typedef struct rtlx_info { + unsigned long id; + enum rtlx_state state; + + struct rtlx_channel channel[RTLX_CHANNELS]; + +} rtlx_info_t; + +#endif diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h index 4eed8e2acdc3..e796d75f027e 100644 --- a/include/asm-mips/serial.h +++ b/include/asm-mips/serial.h @@ -52,16 +52,6 @@ #define JAZZ_SERIAL_PORT_DEFNS #endif -#ifdef CONFIG_MIPS_COBALT -#include <asm/cobalt/cobalt.h> -#define COBALT_BASE_BAUD (18432000 / 16) -#define COBALT_SERIAL_PORT_DEFNS \ - /* UART CLK PORT IRQ FLAGS */ \ - { 0, COBALT_BASE_BAUD, 0xc800000, COBALT_SERIAL_IRQ, STD_COM_FLAGS }, /* ttyS0 */ -#else -#define COBALT_SERIAL_PORT_DEFNS -#endif - /* * Both Galileo boards have the same UART mappings. */ @@ -113,17 +103,6 @@ #define IVR_SERIAL_PORT_DEFNS #endif -#ifdef CONFIG_TOSHIBA_JMR3927 -#include <asm/jmr3927/jmr3927.h> -#define TXX927_SERIAL_PORT_DEFNS \ - { .baud_base = JMR3927_BASE_BAUD, .port = UART0_ADDR, .irq = UART0_INT, \ - .flags = UART0_FLAGS, .type = 1 }, \ - { .baud_base = JMR3927_BASE_BAUD, .port = UART1_ADDR, .irq = UART1_INT, \ - .flags = UART1_FLAGS, .type = 1 }, -#else -#define TXX927_SERIAL_PORT_DEFNS -#endif - #ifdef CONFIG_SERIAL_AU1X00 #include <asm/mach-au1x00/au1000.h> #ifdef CONFIG_SOC_AU1000 @@ -227,9 +206,9 @@ #define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L #define _JAGUAR_ATX_SERIAL_INIT(int, base) \ - { baud_base: JAGUAR_ATX_BASE_BAUD, irq: int, \ - flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - iomem_base: (u8 *) base, iomem_reg_shift: 2, \ + { .baud_base = JAGUAR_ATX_BASE_BAUD, irq: int, \ + .flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ + .iomem_base = (u8 *) base, iomem_reg_shift: 2, \ io_type: SERIAL_IO_MEM } #define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \ _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE) @@ -243,9 +222,9 @@ #define OCELOT_3_SERIAL_BASE (signed)0xfd000020 #define _OCELOT_3_SERIAL_INIT(int, base) \ - { baud_base: OCELOT_3_BASE_BAUD, irq: int, \ - flags: STD_COM_FLAGS, \ - iomem_base: (u8 *) base, iomem_reg_shift: 2, \ + { .baud_base = OCELOT_3_BASE_BAUD, irq: int, \ + .flags = STD_COM_FLAGS, \ + .iomem_base = (u8 *) base, iomem_reg_shift: 2, \ io_type: SERIAL_IO_MEM } #define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ @@ -342,7 +321,6 @@ #endif /* CONFIG_SGI_IP32 */ #define SERIAL_PORT_DFNS \ - COBALT_SERIAL_PORT_DEFNS \ DDB5477_SERIAL_PORT_DEFNS \ EV96100_SERIAL_PORT_DEFNS \ IP32_SERIAL_PORT_DEFNS \ @@ -354,7 +332,6 @@ MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ - TXX927_SERIAL_PORT_DEFNS \ AU1000_SERIAL_PORT_DEFNS #endif /* _ASM_SERIAL_H */ diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h new file mode 100644 index 000000000000..42d4cf00efd3 --- /dev/null +++ b/include/asm-mips/sibyte/bcm1480_int.h @@ -0,0 +1,310 @@ +/* ********************************************************************* + * BCM1280/BCM1480 Board Support Package + * + * Interrupt Mapper definitions File: bcm1480_int.h + * + * This module contains constants for manipulating the + * BCM1255/BCM1280/BCM1455/BCM1480's interrupt mapper and + * definitions for the interrupt sources. + * + * BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03) + * + ********************************************************************* + * + * Copyright 2000,2001,2002,2003 + * Broadcom Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + ********************************************************************* */ + + +#ifndef _BCM1480_INT_H +#define _BCM1480_INT_H + +#include "sb1250_defs.h" + +/* ********************************************************************* + * Interrupt Mapper Constants + ********************************************************************* */ + +/* + * The interrupt mapper deals with 128-bit logical registers that are + * implemented as pairs of 64-bit registers, with the "low" 64 bits in + * a register that has an address 0x1000 higher(!) than the + * corresponding "high" register. + * + * For appropriate registers, bit 0 of the "high" register is a + * cascade bit that summarizes (as a bit-OR) the 64 bits of the "low" + * register. + */ + +/* + * This entire file uses _BCM1480_ in all the symbols because it is + * entirely BCM1480 specific. + */ + +/* + * Interrupt sources (Table 22) + */ + +#define K_BCM1480_INT_SOURCES 128 + +#define _BCM1480_INT_HIGH(k) (k) +#define _BCM1480_INT_LOW(k) ((k)+64) + +#define K_BCM1480_INT_ADDR_TRAP _BCM1480_INT_HIGH(1) +#define K_BCM1480_INT_GPIO_0 _BCM1480_INT_HIGH(4) +#define K_BCM1480_INT_GPIO_1 _BCM1480_INT_HIGH(5) +#define K_BCM1480_INT_GPIO_2 _BCM1480_INT_HIGH(6) +#define K_BCM1480_INT_GPIO_3 _BCM1480_INT_HIGH(7) +#define K_BCM1480_INT_PCI_INTA _BCM1480_INT_HIGH(8) +#define K_BCM1480_INT_PCI_INTB _BCM1480_INT_HIGH(9) +#define K_BCM1480_INT_PCI_INTC _BCM1480_INT_HIGH(10) +#define K_BCM1480_INT_PCI_INTD _BCM1480_INT_HIGH(11) +#define K_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_HIGH(12) +#define K_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_HIGH(13) +#define K_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_HIGH(14) +#define K_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_HIGH(15) +#define K_BCM1480_INT_TIMER_0 _BCM1480_INT_HIGH(20) +#define K_BCM1480_INT_TIMER_1 _BCM1480_INT_HIGH(21) +#define K_BCM1480_INT_TIMER_2 _BCM1480_INT_HIGH(22) +#define K_BCM1480_INT_TIMER_3 _BCM1480_INT_HIGH(23) +#define K_BCM1480_INT_DM_CH_0 _BCM1480_INT_HIGH(28) +#define K_BCM1480_INT_DM_CH_1 _BCM1480_INT_HIGH(29) +#define K_BCM1480_INT_DM_CH_2 _BCM1480_INT_HIGH(30) +#define K_BCM1480_INT_DM_CH_3 _BCM1480_INT_HIGH(31) +#define K_BCM1480_INT_MAC_0 _BCM1480_INT_HIGH(36) +#define K_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_HIGH(37) +#define K_BCM1480_INT_MAC_1 _BCM1480_INT_HIGH(38) +#define K_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_HIGH(39) +#define K_BCM1480_INT_MAC_2 _BCM1480_INT_HIGH(40) +#define K_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_HIGH(41) +#define K_BCM1480_INT_MAC_3 _BCM1480_INT_HIGH(42) +#define K_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_HIGH(43) +#define K_BCM1480_INT_PMI_LOW _BCM1480_INT_HIGH(52) +#define K_BCM1480_INT_PMI_HIGH _BCM1480_INT_HIGH(53) +#define K_BCM1480_INT_PMO_LOW _BCM1480_INT_HIGH(54) +#define K_BCM1480_INT_PMO_HIGH _BCM1480_INT_HIGH(55) +#define K_BCM1480_INT_MBOX_0_0 _BCM1480_INT_HIGH(56) +#define K_BCM1480_INT_MBOX_0_1 _BCM1480_INT_HIGH(57) +#define K_BCM1480_INT_MBOX_0_2 _BCM1480_INT_HIGH(58) +#define K_BCM1480_INT_MBOX_0_3 _BCM1480_INT_HIGH(59) +#define K_BCM1480_INT_MBOX_1_0 _BCM1480_INT_HIGH(60) +#define K_BCM1480_INT_MBOX_1_1 _BCM1480_INT_HIGH(61) +#define K_BCM1480_INT_MBOX_1_2 _BCM1480_INT_HIGH(62) +#define K_BCM1480_INT_MBOX_1_3 _BCM1480_INT_HIGH(63) + +#define K_BCM1480_INT_BAD_ECC _BCM1480_INT_LOW(1) +#define K_BCM1480_INT_COR_ECC _BCM1480_INT_LOW(2) +#define K_BCM1480_INT_IO_BUS _BCM1480_INT_LOW(3) +#define K_BCM1480_INT_PERF_CNT _BCM1480_INT_LOW(4) +#define K_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_LOW(5) +#define K_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_LOW(6) +#define K_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_LOW(7) +#define K_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_LOW(8) +#define K_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_LOW(9) +#define K_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_LOW(10) +#define K_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_LOW(11) +#define K_BCM1480_INT_PCI_ERROR _BCM1480_INT_LOW(16) +#define K_BCM1480_INT_PCI_RESET _BCM1480_INT_LOW(17) +#define K_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_LOW(18) +#define K_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_LOW(19) +#define K_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_LOW(20) +#define K_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_LOW(21) +#define K_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_LOW(22) +#define K_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_LOW(23) +#define K_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_LOW(24) +#define K_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_LOW(25) +#define K_BCM1480_INT_LDT_SMI _BCM1480_INT_LOW(32) +#define K_BCM1480_INT_LDT_NMI _BCM1480_INT_LOW(33) +#define K_BCM1480_INT_LDT_INIT _BCM1480_INT_LOW(34) +#define K_BCM1480_INT_LDT_STARTUP _BCM1480_INT_LOW(35) +#define K_BCM1480_INT_LDT_EXT _BCM1480_INT_LOW(36) +#define K_BCM1480_INT_SMB_0 _BCM1480_INT_LOW(40) +#define K_BCM1480_INT_SMB_1 _BCM1480_INT_LOW(41) +#define K_BCM1480_INT_PCMCIA _BCM1480_INT_LOW(42) +#define K_BCM1480_INT_UART_0 _BCM1480_INT_LOW(44) +#define K_BCM1480_INT_UART_1 _BCM1480_INT_LOW(45) +#define K_BCM1480_INT_UART_2 _BCM1480_INT_LOW(46) +#define K_BCM1480_INT_UART_3 _BCM1480_INT_LOW(47) +#define K_BCM1480_INT_GPIO_4 _BCM1480_INT_LOW(52) +#define K_BCM1480_INT_GPIO_5 _BCM1480_INT_LOW(53) +#define K_BCM1480_INT_GPIO_6 _BCM1480_INT_LOW(54) +#define K_BCM1480_INT_GPIO_7 _BCM1480_INT_LOW(55) +#define K_BCM1480_INT_GPIO_8 _BCM1480_INT_LOW(56) +#define K_BCM1480_INT_GPIO_9 _BCM1480_INT_LOW(57) +#define K_BCM1480_INT_GPIO_10 _BCM1480_INT_LOW(58) +#define K_BCM1480_INT_GPIO_11 _BCM1480_INT_LOW(59) +#define K_BCM1480_INT_GPIO_12 _BCM1480_INT_LOW(60) +#define K_BCM1480_INT_GPIO_13 _BCM1480_INT_LOW(61) +#define K_BCM1480_INT_GPIO_14 _BCM1480_INT_LOW(62) +#define K_BCM1480_INT_GPIO_15 _BCM1480_INT_LOW(63) + +/* + * Mask values for each interrupt + */ + +#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F)) +#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6) + +#define M_BCM1480_INT_CASCADE _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0)) + +#define M_BCM1480_INT_ADDR_TRAP _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP) +#define M_BCM1480_INT_GPIO_0 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0) +#define M_BCM1480_INT_GPIO_1 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1) +#define M_BCM1480_INT_GPIO_2 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2) +#define M_BCM1480_INT_GPIO_3 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3) +#define M_BCM1480_INT_PCI_INTA _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA) +#define M_BCM1480_INT_PCI_INTB _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB) +#define M_BCM1480_INT_PCI_INTC _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC) +#define M_BCM1480_INT_PCI_INTD _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD) +#define M_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0) +#define M_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1) +#define M_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2) +#define M_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3) +#define M_BCM1480_INT_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0) +#define M_BCM1480_INT_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1) +#define M_BCM1480_INT_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2) +#define M_BCM1480_INT_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3) +#define M_BCM1480_INT_DM_CH_0 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0) +#define M_BCM1480_INT_DM_CH_1 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1) +#define M_BCM1480_INT_DM_CH_2 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2) +#define M_BCM1480_INT_DM_CH_3 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3) +#define M_BCM1480_INT_MAC_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0) +#define M_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1) +#define M_BCM1480_INT_MAC_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1) +#define M_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1) +#define M_BCM1480_INT_MAC_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2) +#define M_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1) +#define M_BCM1480_INT_MAC_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3) +#define M_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1) +#define M_BCM1480_INT_PMI_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW) +#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH) +#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW) +#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH) +#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0) +#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1) +#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2) +#define M_BCM1480_INT_MBOX_0_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3) +#define M_BCM1480_INT_MBOX_1_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0) +#define M_BCM1480_INT_MBOX_1_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1) +#define M_BCM1480_INT_MBOX_1_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2) +#define M_BCM1480_INT_MBOX_1_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3) +#define M_BCM1480_INT_BAD_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC) +#define M_BCM1480_INT_COR_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC) +#define M_BCM1480_INT_IO_BUS _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS) +#define M_BCM1480_INT_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT) +#define M_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT) +#define M_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE) +#define M_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE) +#define M_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0) +#define M_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1) +#define M_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2) +#define M_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3) +#define M_BCM1480_INT_PCI_ERROR _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR) +#define M_BCM1480_INT_PCI_RESET _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET) +#define M_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER) +#define M_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE) +#define M_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL) +#define M_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL) +#define M_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL) +#define M_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL) +#define M_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL) +#define M_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL) +#define M_BCM1480_INT_LDT_SMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI) +#define M_BCM1480_INT_LDT_NMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI) +#define M_BCM1480_INT_LDT_INIT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT) +#define M_BCM1480_INT_LDT_STARTUP _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP) +#define M_BCM1480_INT_LDT_EXT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT) +#define M_BCM1480_INT_SMB_0 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0) +#define M_BCM1480_INT_SMB_1 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1) +#define M_BCM1480_INT_PCMCIA _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA) +#define M_BCM1480_INT_UART_0 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0) +#define M_BCM1480_INT_UART_1 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1) +#define M_BCM1480_INT_UART_2 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2) +#define M_BCM1480_INT_UART_3 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3) +#define M_BCM1480_INT_GPIO_4 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4) +#define M_BCM1480_INT_GPIO_5 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5) +#define M_BCM1480_INT_GPIO_6 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6) +#define M_BCM1480_INT_GPIO_7 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7) +#define M_BCM1480_INT_GPIO_8 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8) +#define M_BCM1480_INT_GPIO_9 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9) +#define M_BCM1480_INT_GPIO_10 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10) +#define M_BCM1480_INT_GPIO_11 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11) +#define M_BCM1480_INT_GPIO_12 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12) +#define M_BCM1480_INT_GPIO_13 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13) +#define M_BCM1480_INT_GPIO_14 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14) +#define M_BCM1480_INT_GPIO_15 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15) + +/* + * Interrupt mappings (Table 18) + */ + +#define K_BCM1480_INT_MAP_I0 0 /* interrupt pins on processor */ +#define K_BCM1480_INT_MAP_I1 1 +#define K_BCM1480_INT_MAP_I2 2 +#define K_BCM1480_INT_MAP_I3 3 +#define K_BCM1480_INT_MAP_I4 4 +#define K_BCM1480_INT_MAP_I5 5 +#define K_BCM1480_INT_MAP_NMI 6 /* nonmaskable */ +#define K_BCM1480_INT_MAP_DINT 7 /* debug interrupt */ + +/* + * Interrupt LDT Set Register (Table 19) + */ + +#define S_BCM1480_INT_HT_INTMSG 0 +#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3,S_BCM1480_INT_HT_INTMSG) +#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTMSG) +#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTMSG,M_BCM1480_INT_HT_INTMSG) + +#define K_BCM1480_INT_HT_INTMSG_FIXED 0 +#define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1 +#define K_BCM1480_INT_HT_INTMSG_SMI 2 +#define K_BCM1480_INT_HT_INTMSG_NMI 3 +#define K_BCM1480_INT_HT_INTMSG_INIT 4 +#define K_BCM1480_INT_HT_INTMSG_STARTUP 5 +#define K_BCM1480_INT_HT_INTMSG_EXTINT 6 +#define K_BCM1480_INT_HT_INTMSG_RESERVED 7 + +#define M_BCM1480_INT_HT_TRIGGERMODE _SB_MAKEMASK1(3) +#define V_BCM1480_INT_HT_EDGETRIGGER 0 +#define V_BCM1480_INT_HT_LEVELTRIGGER M_BCM1480_INT_HT_TRIGGERMODE + +#define M_BCM1480_INT_HT_DESTMODE _SB_MAKEMASK1(4) +#define V_BCM1480_INT_HT_PHYSICALDEST 0 +#define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE + +#define S_BCM1480_INT_HT_INTDEST 5 +#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8,S_BCM1480_INT_HT_INTDEST) +#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTDEST) +#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTDEST,M_BCM1480_INT_HT_INTDEST) + +#define S_BCM1480_INT_HT_VECTOR 13 +#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8,S_BCM1480_INT_HT_VECTOR) +#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_VECTOR) +#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_VECTOR,M_BCM1480_INT_HT_VECTOR) + +/* + * Vector prefix (Table 4-7) + */ + +#define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH 0x00 +#define M_BCM1480_HTVECT_RAISE_MBOX_0 0x40 +#define M_BCM1480_HTVECT_RAISE_INTLDT_LO 0x80 +#define M_BCM1480_HTVECT_RAISE_MBOX_1 0xC0 + +#endif /* _BCM1480_INT_H */ diff --git a/include/asm-mips/sibyte/bcm1480_l2c.h b/include/asm-mips/sibyte/bcm1480_l2c.h new file mode 100644 index 000000000000..886b099565e6 --- /dev/null +++ b/include/asm-mips/sibyte/bcm1480_l2c.h @@ -0,0 +1,176 @@ +/* ********************************************************************* + * BCM1280/BCM1480 Board Support Package + * + * L2 Cache constants and macros File: bcm1480_l2c.h + * + * This module contains constants useful for manipulating the + * level 2 cache. + * + * BCM1400 specification level: 1280-UM100-D2 (11/14/03) + * + ********************************************************************* + * + * Copyright 2000,2001,2002,2003 + * Broadcom Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + ********************************************************************* */ + + +#ifndef _BCM1480_L2C_H +#define _BCM1480_L2C_H + +#include "sb1250_defs.h" + +/* + * Format of level 2 cache management address (Table 55) + */ + +#define S_BCM1480_L2C_MGMT_INDEX 5 +#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_MGMT_INDEX) +#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_INDEX) +#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_INDEX,M_BCM1480_L2C_MGMT_INDEX) + +#define S_BCM1480_L2C_MGMT_WAY 17 +#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_MGMT_WAY) +#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_WAY) +#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_WAY,M_BCM1480_L2C_MGMT_WAY) + +#define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20) +#define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21) + +#define S_BCM1480_L2C_MGMT_ECC_DIAG 22 +#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_BCM1480_L2C_MGMT_ECC_DIAG) +#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG) +#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG,M_BCM1480_L2C_MGMT_ECC_DIAG) + +#define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000 + +#define BCM1480_L2C_ENTRIES_PER_WAY 4096 +#define BCM1480_L2C_NUM_WAYS 8 + + +/* + * Level 2 Cache Tag register (Table 59) + */ + +#define S_BCM1480_L2C_TAG_MBZ 0 +#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5,S_BCM1480_L2C_TAG_MBZ) + +#define S_BCM1480_L2C_TAG_INDEX 5 +#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_TAG_INDEX) +#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_INDEX) +#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_INDEX,M_BCM1480_L2C_TAG_INDEX) + +/* Note that index bit 16 is also tag bit 40 */ +#define S_BCM1480_L2C_TAG_TAG 17 +#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23,S_BCM1480_L2C_TAG_TAG) +#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_TAG) +#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_TAG,M_BCM1480_L2C_TAG_TAG) + +#define S_BCM1480_L2C_TAG_ECC 40 +#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6,S_BCM1480_L2C_TAG_ECC) +#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_ECC) +#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_ECC,M_BCM1480_L2C_TAG_ECC) + +#define S_BCM1480_L2C_TAG_WAY 46 +#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_TAG_WAY) +#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_WAY) +#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_WAY,M_BCM1480_L2C_TAG_WAY) + +#define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49) +#define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50) + +#define S_BCM1480_L2C_DATA_ECC 51 +#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10,S_BCM1480_L2C_DATA_ECC) +#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_DATA_ECC) +#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_DATA_ECC,M_BCM1480_L2C_DATA_ECC) + + +/* + * L2 Misc0 Value Register (Table 60) + */ + +#define S_BCM1480_L2C_MISC0_WAY_REMOTE 0 +#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_REMOTE) +#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_REMOTE,M_BCM1480_L2C_MISC0_WAY_REMOTE) + +#define S_BCM1480_L2C_MISC0_WAY_LOCAL 8 +#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_LOCAL) +#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_LOCAL,M_BCM1480_L2C_MISC0_WAY_LOCAL) + +#define S_BCM1480_L2C_MISC0_WAY_ENABLE 16 +#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_ENABLE) +#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_ENABLE,M_BCM1480_L2C_MISC0_WAY_ENABLE) + +#define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24 +#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_DISABLE) +#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_DISABLE,M_BCM1480_L2C_MISC0_CACHE_DISABLE) + +#define S_BCM1480_L2C_MISC0_CACHE_QUAD 26 +#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_QUAD) +#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_QUAD,M_BCM1480_L2C_MISC0_CACHE_QUAD) + +#define S_BCM1480_L2C_MISC0_MC_PRIORITY 30 +#define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY) + +#define S_BCM1480_L2C_MISC0_ECC_CLEANUP 31 +#define M_BCM1480_L2C_MISC0_ECC_CLEANUP _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP) + + +/* + * L2 Misc1 Value Register (Table 60) + */ + +#define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0 +#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_0) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_0,M_BCM1480_L2C_MISC1_WAY_AGENT_0) + +#define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8 +#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_1) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_1,M_BCM1480_L2C_MISC1_WAY_AGENT_1) + +#define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16 +#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_2) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_2,M_BCM1480_L2C_MISC1_WAY_AGENT_2) + +#define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24 +#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_3) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_3,M_BCM1480_L2C_MISC1_WAY_AGENT_3) + +#define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32 +#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_4) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_4,M_BCM1480_L2C_MISC1_WAY_AGENT_4) + + +/* + * L2 Misc2 Value Register (Table 60) + */ + +#define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0 +#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_8) +#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_8,M_BCM1480_L2C_MISC2_WAY_AGENT_8) + +#define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8 +#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_9) +#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_9,M_BCM1480_L2C_MISC2_WAY_AGENT_9) + +#define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16 +#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_A) +#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_A,M_BCM1480_L2C_MISC2_WAY_AGENT_A) + + +#endif /* _BCM1480_L2C_H */ diff --git a/include/asm-mips/sibyte/bcm1480_mc.h b/include/asm-mips/sibyte/bcm1480_mc.h new file mode 100644 index 000000000000..6bdc941afc91 --- /dev/null +++ b/include/asm-mips/sibyte/bcm1480_mc.h @@ -0,0 +1,962 @@ +/* ********************************************************************* + * BCM1280/BCM1480 Board Support Package + * + * Memory Controller constants File: bcm1480_mc.h + * + * This module contains constants and macros useful for + * programming the memory controller. + * + * BCM1400 specification level: 1280-UM100-D1 (11/14/03 Review Copy) + * + ********************************************************************* + * + * Copyright 2000,2001,2002,2003 + * Broadcom Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + ********************************************************************* */ + + +#ifndef _BCM1480_MC_H +#define _BCM1480_MC_H + +#include "sb1250_defs.h" + +/* + * Memory Channel Configuration Register (Table 81) + */ + +#define S_BCM1480_MC_INTLV0 0 +#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) +#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) +#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) +#define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) + +#define S_BCM1480_MC_INTLV1 8 +#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) +#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) +#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) +#define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) + +#define S_BCM1480_MC_INTLV2 16 +#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV2) +#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV2) +#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV2,M_BCM1480_MC_INTLV2) +#define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) + +#define S_BCM1480_MC_CS_MODE 32 +#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8,S_BCM1480_MC_CS_MODE) +#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS_MODE) +#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_CS_MODE,M_BCM1480_MC_CS_MODE) +#define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) + +#define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ + V_BCM1480_MC_INTLV1_DEFAULT | \ + V_BCM1480_MC_INTLV2_DEFAULT | \ + V_BCM1480_MC_CS_MODE_DEFAULT) + +#define K_BCM1480_MC_CS01_MODE 0x03 +#define K_BCM1480_MC_CS02_MODE 0x05 +#define K_BCM1480_MC_CS0123_MODE 0x0F +#define K_BCM1480_MC_CS0246_MODE 0x55 +#define K_BCM1480_MC_CS0145_MODE 0x33 +#define K_BCM1480_MC_CS0167_MODE 0xC3 +#define K_BCM1480_MC_CSFULL_MODE 0xFF + +/* + * Chip Select Start Address Register (Table 82) + */ + +#define S_BCM1480_MC_CS0_START 0 +#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12,S_BCM1480_MC_CS0_START) +#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_START) +#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_START,M_BCM1480_MC_CS0_START) + +#define S_BCM1480_MC_CS1_START 16 +#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12,S_BCM1480_MC_CS1_START) +#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_START) +#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_START,M_BCM1480_MC_CS1_START) + +#define S_BCM1480_MC_CS2_START 32 +#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12,S_BCM1480_MC_CS2_START) +#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_START) +#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_START,M_BCM1480_MC_CS2_START) + +#define S_BCM1480_MC_CS3_START 48 +#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12,S_BCM1480_MC_CS3_START) +#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_START) +#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_START,M_BCM1480_MC_CS3_START) + +/* + * Chip Select End Address Register (Table 83) + */ + +#define S_BCM1480_MC_CS0_END 0 +#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12,S_BCM1480_MC_CS0_END) +#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_END) +#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_END,M_BCM1480_MC_CS0_END) + +#define S_BCM1480_MC_CS1_END 16 +#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12,S_BCM1480_MC_CS1_END) +#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_END) +#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_END,M_BCM1480_MC_CS1_END) + +#define S_BCM1480_MC_CS2_END 32 +#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12,S_BCM1480_MC_CS2_END) +#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_END) +#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_END,M_BCM1480_MC_CS2_END) + +#define S_BCM1480_MC_CS3_END 48 +#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12,S_BCM1480_MC_CS3_END) +#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_END) +#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_END,M_BCM1480_MC_CS3_END) + +/* + * Row Address Bit Select Register 0 (Table 84) + */ + +#define S_BCM1480_MC_ROW00 0 +#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6,S_BCM1480_MC_ROW00) +#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW00) +#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW00,M_BCM1480_MC_ROW00) + +#define S_BCM1480_MC_ROW01 8 +#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6,S_BCM1480_MC_ROW01) +#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW01) +#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW01,M_BCM1480_MC_ROW01) + +#define S_BCM1480_MC_ROW02 16 +#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6,S_BCM1480_MC_ROW02) +#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW02) +#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW02,M_BCM1480_MC_ROW02) + +#define S_BCM1480_MC_ROW03 24 +#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6,S_BCM1480_MC_ROW03) +#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW03) +#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW03,M_BCM1480_MC_ROW03) + +#define S_BCM1480_MC_ROW04 32 +#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6,S_BCM1480_MC_ROW04) +#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW04) +#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW04,M_BCM1480_MC_ROW04) + +#define S_BCM1480_MC_ROW05 40 +#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6,S_BCM1480_MC_ROW05) +#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW05) +#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW05,M_BCM1480_MC_ROW05) + +#define S_BCM1480_MC_ROW06 48 +#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6,S_BCM1480_MC_ROW06) +#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW06) +#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW06,M_BCM1480_MC_ROW06) + +#define S_BCM1480_MC_ROW07 56 +#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6,S_BCM1480_MC_ROW07) +#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW07) +#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW07,M_BCM1480_MC_ROW07) + +/* + * Row Address Bit Select Register 1 (Table 85) + */ + +#define S_BCM1480_MC_ROW08 0 +#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6,S_BCM1480_MC_ROW08) +#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW08) +#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW08,M_BCM1480_MC_ROW08) + +#define S_BCM1480_MC_ROW09 8 +#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6,S_BCM1480_MC_ROW09) +#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW09) +#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW09,M_BCM1480_MC_ROW09) + +#define S_BCM1480_MC_ROW10 16 +#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6,S_BCM1480_MC_ROW10) +#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW10) +#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW10,M_BCM1480_MC_ROW10) + +#define S_BCM1480_MC_ROW11 24 +#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6,S_BCM1480_MC_ROW11) +#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW11) +#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW11,M_BCM1480_MC_ROW11) + +#define S_BCM1480_MC_ROW12 32 +#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6,S_BCM1480_MC_ROW12) +#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW12) +#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW12,M_BCM1480_MC_ROW12) + +#define S_BCM1480_MC_ROW13 40 +#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6,S_BCM1480_MC_ROW13) +#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW13) +#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW13,M_BCM1480_MC_ROW13) + +#define S_BCM1480_MC_ROW14 48 +#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6,S_BCM1480_MC_ROW14) +#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW14) +#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW14,M_BCM1480_MC_ROW14) + +#define K_BCM1480_MC_ROWX_BIT_SPACING 8 + +/* + * Column Address Bit Select Register 0 (Table 86) + */ + +#define S_BCM1480_MC_COL00 0 +#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6,S_BCM1480_MC_COL00) +#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL00) +#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x,S_BCM1480_MC_COL00,M_BCM1480_MC_COL00) + +#define S_BCM1480_MC_COL01 8 +#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6,S_BCM1480_MC_COL01) +#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL01) +#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x,S_BCM1480_MC_COL01,M_BCM1480_MC_COL01) + +#define S_BCM1480_MC_COL02 16 +#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6,S_BCM1480_MC_COL02) +#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL02) +#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x,S_BCM1480_MC_COL02,M_BCM1480_MC_COL02) + +#define S_BCM1480_MC_COL03 24 +#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6,S_BCM1480_MC_COL03) +#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL03) +#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x,S_BCM1480_MC_COL03,M_BCM1480_MC_COL03) + +#define S_BCM1480_MC_COL04 32 +#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6,S_BCM1480_MC_COL04) +#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL04) +#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x,S_BCM1480_MC_COL04,M_BCM1480_MC_COL04) + +#define S_BCM1480_MC_COL05 40 +#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6,S_BCM1480_MC_COL05) +#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL05) +#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x,S_BCM1480_MC_COL05,M_BCM1480_MC_COL05) + +#define S_BCM1480_MC_COL06 48 +#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6,S_BCM1480_MC_COL06) +#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL06) +#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x,S_BCM1480_MC_COL06,M_BCM1480_MC_COL06) + +#define S_BCM1480_MC_COL07 56 +#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6,S_BCM1480_MC_COL07) +#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL07) +#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x,S_BCM1480_MC_COL07,M_BCM1480_MC_COL07) + +/* + * Column Address Bit Select Register 1 (Table 87) + */ + +#define S_BCM1480_MC_COL08 0 +#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6,S_BCM1480_MC_COL08) +#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL08) +#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x,S_BCM1480_MC_COL08,M_BCM1480_MC_COL08) + +#define S_BCM1480_MC_COL09 8 +#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6,S_BCM1480_MC_COL09) +#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL09) +#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x,S_BCM1480_MC_COL09,M_BCM1480_MC_COL09) + +#define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ + +#define S_BCM1480_MC_COL11 24 +#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6,S_BCM1480_MC_COL11) +#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL11) +#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x,S_BCM1480_MC_COL11,M_BCM1480_MC_COL11) + +#define S_BCM1480_MC_COL12 32 +#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6,S_BCM1480_MC_COL12) +#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL12) +#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x,S_BCM1480_MC_COL12,M_BCM1480_MC_COL12) + +#define S_BCM1480_MC_COL13 40 +#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6,S_BCM1480_MC_COL13) +#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL13) +#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x,S_BCM1480_MC_COL13,M_BCM1480_MC_COL13) + +#define S_BCM1480_MC_COL14 48 +#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6,S_BCM1480_MC_COL14) +#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL14) +#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x,S_BCM1480_MC_COL14,M_BCM1480_MC_COL14) + +#define K_BCM1480_MC_COLX_BIT_SPACING 8 + +/* + * CS0 and CS1 Bank Address Bit Select Register (Table 88) + */ + +#define S_BCM1480_MC_CS01_BANK0 0 +#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK0) +#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK0) +#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK0,M_BCM1480_MC_CS01_BANK0) + +#define S_BCM1480_MC_CS01_BANK1 8 +#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK1) +#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK1) +#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK1,M_BCM1480_MC_CS01_BANK1) + +#define S_BCM1480_MC_CS01_BANK2 16 +#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK2) +#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK2) +#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK2,M_BCM1480_MC_CS01_BANK2) + +/* + * CS2 and CS3 Bank Address Bit Select Register (Table 89) + */ + +#define S_BCM1480_MC_CS23_BANK0 0 +#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK0) +#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK0) +#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK0,M_BCM1480_MC_CS23_BANK0) + +#define S_BCM1480_MC_CS23_BANK1 8 +#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK1) +#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK1) +#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK1,M_BCM1480_MC_CS23_BANK1) + +#define S_BCM1480_MC_CS23_BANK2 16 +#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK2) +#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK2) +#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK2,M_BCM1480_MC_CS23_BANK2) + +#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8 + +/* + * DRAM Command Register (Table 90) + */ + +#define S_BCM1480_MC_COMMAND 0 +#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4,S_BCM1480_MC_COMMAND) +#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COMMAND) +#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x,S_BCM1480_MC_COMMAND,M_BCM1480_MC_COMMAND) + +#define K_BCM1480_MC_COMMAND_EMRS 0 +#define K_BCM1480_MC_COMMAND_MRS 1 +#define K_BCM1480_MC_COMMAND_PRE 2 +#define K_BCM1480_MC_COMMAND_AR 3 +#define K_BCM1480_MC_COMMAND_SETRFSH 4 +#define K_BCM1480_MC_COMMAND_CLRRFSH 5 +#define K_BCM1480_MC_COMMAND_SETPWRDN 6 +#define K_BCM1480_MC_COMMAND_CLRPWRDN 7 + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define K_BCM1480_MC_COMMAND_EMRS2 8 +#define K_BCM1480_MC_COMMAND_EMRS3 9 +#define K_BCM1480_MC_COMMAND_ENABLE_MCLK 10 +#define K_BCM1480_MC_COMMAND_DISABLE_MCLK 11 +#endif + +#define V_BCM1480_MC_COMMAND_EMRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS) +#define V_BCM1480_MC_COMMAND_MRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS) +#define V_BCM1480_MC_COMMAND_PRE V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE) +#define V_BCM1480_MC_COMMAND_AR V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR) +#define V_BCM1480_MC_COMMAND_SETRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH) +#define V_BCM1480_MC_COMMAND_CLRRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH) +#define V_BCM1480_MC_COMMAND_SETPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN) +#define V_BCM1480_MC_COMMAND_CLRPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN) + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define V_BCM1480_MC_COMMAND_EMRS2 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2) +#define V_BCM1480_MC_COMMAND_EMRS3 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3) +#define V_BCM1480_MC_COMMAND_ENABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK) +#define V_BCM1480_MC_COMMAND_DISABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK) +#endif + +#define S_BCM1480_MC_CS0 4 +#define M_BCM1480_MC_CS0 _SB_MAKEMASK1(4) +#define M_BCM1480_MC_CS1 _SB_MAKEMASK1(5) +#define M_BCM1480_MC_CS2 _SB_MAKEMASK1(6) +#define M_BCM1480_MC_CS3 _SB_MAKEMASK1(7) +#define M_BCM1480_MC_CS4 _SB_MAKEMASK1(8) +#define M_BCM1480_MC_CS5 _SB_MAKEMASK1(9) +#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) +#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) + +#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) + +/* + * DRAM Mode Register (Table 91) + */ + +#define S_BCM1480_MC_EMODE 0 +#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15,S_BCM1480_MC_EMODE) +#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_EMODE) +#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x,S_BCM1480_MC_EMODE,M_BCM1480_MC_EMODE) +#define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) + +#define S_BCM1480_MC_MODE 16 +#define M_BCM1480_MC_MODE _SB_MAKEMASK(15,S_BCM1480_MC_MODE) +#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MODE) +#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_MODE,M_BCM1480_MC_MODE) +#define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) + +#define S_BCM1480_MC_DRAM_TYPE 32 +#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4,S_BCM1480_MC_DRAM_TYPE) +#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DRAM_TYPE) +#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_BCM1480_MC_DRAM_TYPE,M_BCM1480_MC_DRAM_TYPE) + +#define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 +#define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define K_BCM1480_MC_DRAM_TYPE_DDR2 2 +#endif + +#define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC) +#define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM) + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define V_BCM1480_MC_DRAM_TYPE_DDR2 V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2) +#endif + +#define M_BCM1480_MC_GANGED _SB_MAKEMASK1(36) +#define M_BCM1480_MC_BY9_INTF _SB_MAKEMASK1(37) +#define M_BCM1480_MC_FORCE_ECC64 _SB_MAKEMASK1(38) +#define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) + +#define S_BCM1480_MC_PG_POLICY 40 +#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2,S_BCM1480_MC_PG_POLICY) +#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PG_POLICY) +#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x,S_BCM1480_MC_PG_POLICY,M_BCM1480_MC_PG_POLICY) + +#define K_BCM1480_MC_PG_POLICY_CLOSED 0 +#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1 + +#define V_BCM1480_MC_PG_POLICY_CLOSED V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED) +#define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define M_BCM1480_MC_2T_CMD _SB_MAKEMASK1(42) +#define M_BCM1480_MC_ECC_COR_DIS _SB_MAKEMASK1(43) +#endif + +#define V_BCM1480_MC_DRAMMODE_DEFAULT V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \ + V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) + +/* + * Memory Clock Configuration Register (Table 92) + */ + +#define S_BCM1480_MC_CLK_RATIO 0 +#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6,S_BCM1480_MC_CLK_RATIO) +#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CLK_RATIO) +#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_BCM1480_MC_CLK_RATIO,M_BCM1480_MC_CLK_RATIO) + +#define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10) + +#define S_BCM1480_MC_REF_RATE 8 +#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8,S_BCM1480_MC_REF_RATE) +#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_REF_RATE) +#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x,S_BCM1480_MC_REF_RATE,M_BCM1480_MC_REF_RATE) + +#define K_BCM1480_MC_REF_RATE_100MHz 0x31 +#define K_BCM1480_MC_REF_RATE_200MHz 0x62 +#define K_BCM1480_MC_REF_RATE_400MHz 0xC4 + +#define V_BCM1480_MC_REF_RATE_100MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz) +#define V_BCM1480_MC_REF_RATE_200MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz) +#define V_BCM1480_MC_REF_RATE_400MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz) +#define V_BCM1480_MC_REF_RATE_DEFAULT V_BCM1480_MC_REF_RATE_400MHz + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define M_BCM1480_MC_AUTO_REF_DIS _SB_MAKEMASK1(16) +#endif + +/* + * ODT Register (Table 99) + */ + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define M_BCM1480_MC_RD_ODT0_CS0 _SB_MAKEMASK1(0) +#define M_BCM1480_MC_RD_ODT0_CS2 _SB_MAKEMASK1(1) +#define M_BCM1480_MC_RD_ODT0_CS4 _SB_MAKEMASK1(2) +#define M_BCM1480_MC_RD_ODT0_CS6 _SB_MAKEMASK1(3) +#define M_BCM1480_MC_WR_ODT0_CS0 _SB_MAKEMASK1(4) +#define M_BCM1480_MC_WR_ODT0_CS2 _SB_MAKEMASK1(5) +#define M_BCM1480_MC_WR_ODT0_CS4 _SB_MAKEMASK1(6) +#define M_BCM1480_MC_WR_ODT0_CS6 _SB_MAKEMASK1(7) +#define M_BCM1480_MC_RD_ODT2_CS0 _SB_MAKEMASK1(8) +#define M_BCM1480_MC_RD_ODT2_CS2 _SB_MAKEMASK1(9) +#define M_BCM1480_MC_RD_ODT2_CS4 _SB_MAKEMASK1(10) +#define M_BCM1480_MC_RD_ODT2_CS6 _SB_MAKEMASK1(11) +#define M_BCM1480_MC_WR_ODT2_CS0 _SB_MAKEMASK1(12) +#define M_BCM1480_MC_WR_ODT2_CS2 _SB_MAKEMASK1(13) +#define M_BCM1480_MC_WR_ODT2_CS4 _SB_MAKEMASK1(14) +#define M_BCM1480_MC_WR_ODT2_CS6 _SB_MAKEMASK1(15) +#define M_BCM1480_MC_RD_ODT4_CS0 _SB_MAKEMASK1(16) +#define M_BCM1480_MC_RD_ODT4_CS2 _SB_MAKEMASK1(17) +#define M_BCM1480_MC_RD_ODT4_CS4 _SB_MAKEMASK1(18) +#define M_BCM1480_MC_RD_ODT4_CS6 _SB_MAKEMASK1(19) +#define M_BCM1480_MC_WR_ODT4_CS0 _SB_MAKEMASK1(20) +#define M_BCM1480_MC_WR_ODT4_CS2 _SB_MAKEMASK1(21) +#define M_BCM1480_MC_WR_ODT4_CS4 _SB_MAKEMASK1(22) +#define M_BCM1480_MC_WR_ODT4_CS6 _SB_MAKEMASK1(23) +#define M_BCM1480_MC_RD_ODT6_CS0 _SB_MAKEMASK1(24) +#define M_BCM1480_MC_RD_ODT6_CS2 _SB_MAKEMASK1(25) +#define M_BCM1480_MC_RD_ODT6_CS4 _SB_MAKEMASK1(26) +#define M_BCM1480_MC_RD_ODT6_CS6 _SB_MAKEMASK1(27) +#define M_BCM1480_MC_WR_ODT6_CS0 _SB_MAKEMASK1(28) +#define M_BCM1480_MC_WR_ODT6_CS2 _SB_MAKEMASK1(29) +#define M_BCM1480_MC_WR_ODT6_CS4 _SB_MAKEMASK1(30) +#define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31) + +#define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) +#endif + +/* + * Memory DLL Configuration Register (Table 93) + */ + +#define S_BCM1480_MC_ADDR_COARSE_ADJ 0 +#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_ADDR_COARSE_ADJ) +#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ) +#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ,M_BCM1480_MC_ADDR_COARSE_ADJ) +#define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0) + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define S_BCM1480_MC_ADDR_FREQ_RANGE 8 +#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FREQ_RANGE) +#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE) +#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE,M_BCM1480_MC_ADDR_FREQ_RANGE) +#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4) +#endif + +#define S_BCM1480_MC_ADDR_FINE_ADJ 8 +#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FINE_ADJ) +#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ) +#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ,M_BCM1480_MC_ADDR_FINE_ADJ) +#define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8) + +#define S_BCM1480_MC_DQI_COARSE_ADJ 16 +#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQI_COARSE_ADJ) +#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ) +#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ,M_BCM1480_MC_DQI_COARSE_ADJ) +#define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0) + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define S_BCM1480_MC_DQI_FREQ_RANGE 24 +#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FREQ_RANGE) +#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE) +#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE,M_BCM1480_MC_DQI_FREQ_RANGE) +#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4) +#endif + +#define S_BCM1480_MC_DQI_FINE_ADJ 24 +#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FINE_ADJ) +#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ) +#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ,M_BCM1480_MC_DQI_FINE_ADJ) +#define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8) + +#define S_BCM1480_MC_DQO_COARSE_ADJ 32 +#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQO_COARSE_ADJ) +#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ) +#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ,M_BCM1480_MC_DQO_COARSE_ADJ) +#define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0) + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define S_BCM1480_MC_DQO_FREQ_RANGE 40 +#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FREQ_RANGE) +#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE) +#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE,M_BCM1480_MC_DQO_FREQ_RANGE) +#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4) +#endif + +#define S_BCM1480_MC_DQO_FINE_ADJ 40 +#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FINE_ADJ) +#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ) +#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ,M_BCM1480_MC_DQO_FINE_ADJ) +#define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8) + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define S_BCM1480_MC_DLL_PDSEL 44 +#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_PDSEL) +#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_PDSEL) +#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_PDSEL,M_BCM1480_MC_DLL_PDSEL) +#define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0) + +#define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46) +#define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47) +#endif + +#define S_BCM1480_MC_DLL_DEFAULT 48 +#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT) +#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT) +#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT) +#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define S_BCM1480_MC_DLL_REGCTRL 54 +#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_REGCTRL) +#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_REGCTRL) +#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_REGCTRL,M_BCM1480_MC_DLL_REGCTRL) +#define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0) +#endif + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define S_BCM1480_MC_DLL_FREQ_RANGE 56 +#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_FREQ_RANGE) +#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE) +#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE,M_BCM1480_MC_DLL_FREQ_RANGE) +#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4) +#endif + +#define S_BCM1480_MC_DLL_STEP_SIZE 56 +#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_STEP_SIZE) +#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE) +#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE,M_BCM1480_MC_DLL_STEP_SIZE) +#define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8) + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define S_BCM1480_MC_DLL_BGCTRL 60 +#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_BGCTRL) +#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_BGCTRL) +#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_BGCTRL,M_BCM1480_MC_DLL_BGCTRL) +#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0) +#endif + +#define M_BCM1480_MC_DLL_BYPASS _SB_MAKEMASK1(63) + +/* + * Memory Drive Configuration Register (Table 94) + */ + +#define S_BCM1480_MC_RTT_BYP_PULLDOWN 0 +#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLDOWN) +#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN) +#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN,M_BCM1480_MC_RTT_BYP_PULLDOWN) + +#define S_BCM1480_MC_RTT_BYP_PULLUP 6 +#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLUP) +#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP) +#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP,M_BCM1480_MC_RTT_BYP_PULLUP) + +#define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8) +#define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9) + +#define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10 +#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) +#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) +#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN,M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) + +#define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15 +#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLUP) +#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP) +#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP,M_BCM1480_MC_PVT_BYP_C1_PULLUP) + +#define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20 +#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) +#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) +#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN,M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) + +#define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25 +#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLUP) +#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP) +#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP,M_BCM1480_MC_PVT_BYP_C2_PULLUP) + +#define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30) +#define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31) + +#define M_BCM1480_MC_CLK_CLASS _SB_MAKEMASK1(34) +#define M_BCM1480_MC_DATA_CLASS _SB_MAKEMASK1(35) +#define M_BCM1480_MC_ADDR_CLASS _SB_MAKEMASK1(36) + +#define M_BCM1480_MC_DQ_ODT_75 _SB_MAKEMASK1(37) +#define M_BCM1480_MC_DQ_ODT_150 _SB_MAKEMASK1(38) +#define M_BCM1480_MC_DQS_ODT_75 _SB_MAKEMASK1(39) +#define M_BCM1480_MC_DQS_ODT_150 _SB_MAKEMASK1(40) +#define M_BCM1480_MC_DQS_DIFF _SB_MAKEMASK1(41) + +/* + * ECC Test Data Register (Table 95) + */ + +#define S_BCM1480_MC_DATA_INVERT 0 +#define M_DATA_ECC_INVERT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_INVERT) + +/* + * ECC Test ECC Register (Table 96) + */ + +#define S_BCM1480_MC_ECC_INVERT 0 +#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8,S_BCM1480_MC_ECC_INVERT) + +/* + * SDRAM Timing Register (Table 97) + */ + +#define S_BCM1480_MC_tRCD 0 +#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4,S_BCM1480_MC_tRCD) +#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCD) +#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCD,M_BCM1480_MC_tRCD) +#define K_BCM1480_MC_tRCD_DEFAULT 3 +#define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT) + +#define S_BCM1480_MC_tCL 4 +#define M_BCM1480_MC_tCL _SB_MAKEMASK(4,S_BCM1480_MC_tCL) +#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCL) +#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x,S_BCM1480_MC_tCL,M_BCM1480_MC_tCL) +#define K_BCM1480_MC_tCL_DEFAULT 2 +#define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT) + +#define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8) + +#define S_BCM1480_MC_tWR 9 +#define M_BCM1480_MC_tWR _SB_MAKEMASK(3,S_BCM1480_MC_tWR) +#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tWR) +#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x,S_BCM1480_MC_tWR,M_BCM1480_MC_tWR) +#define K_BCM1480_MC_tWR_DEFAULT 2 +#define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT) + +#define S_BCM1480_MC_tCwD 12 +#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4,S_BCM1480_MC_tCwD) +#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCwD) +#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x,S_BCM1480_MC_tCwD,M_BCM1480_MC_tCwD) +#define K_BCM1480_MC_tCwD_DEFAULT 1 +#define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT) + +#define S_BCM1480_MC_tRP 16 +#define M_BCM1480_MC_tRP _SB_MAKEMASK(4,S_BCM1480_MC_tRP) +#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRP) +#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRP,M_BCM1480_MC_tRP) +#define K_BCM1480_MC_tRP_DEFAULT 4 +#define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT) + +#define S_BCM1480_MC_tRRD 20 +#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4,S_BCM1480_MC_tRRD) +#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRRD) +#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRRD,M_BCM1480_MC_tRRD) +#define K_BCM1480_MC_tRRD_DEFAULT 2 +#define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT) + +#define S_BCM1480_MC_tRCw 24 +#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5,S_BCM1480_MC_tRCw) +#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCw) +#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCw,M_BCM1480_MC_tRCw) +#define K_BCM1480_MC_tRCw_DEFAULT 10 +#define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT) + +#define S_BCM1480_MC_tRCr 32 +#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5,S_BCM1480_MC_tRCr) +#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCr) +#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCr,M_BCM1480_MC_tRCr) +#define K_BCM1480_MC_tRCr_DEFAULT 9 +#define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT) + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define S_BCM1480_MC_tFAW 40 +#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6,S_BCM1480_MC_tFAW) +#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFAW) +#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x,S_BCM1480_MC_tFAW,M_BCM1480_MC_tFAW) +#define K_BCM1480_MC_tFAW_DEFAULT 0 +#define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT) +#endif + +#define S_BCM1480_MC_tRFC 48 +#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7,S_BCM1480_MC_tRFC) +#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRFC) +#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x,S_BCM1480_MC_tRFC,M_BCM1480_MC_tRFC) +#define K_BCM1480_MC_tRFC_DEFAULT 12 +#define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT) + +#define S_BCM1480_MC_tFIFO 56 +#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2,S_BCM1480_MC_tFIFO) +#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFIFO) +#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x,S_BCM1480_MC_tFIFO,M_BCM1480_MC_tFIFO) +#define K_BCM1480_MC_tFIFO_DEFAULT 0 +#define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT) + +#define S_BCM1480_MC_tW2R 58 +#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2,S_BCM1480_MC_tW2R) +#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2R) +#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2R,M_BCM1480_MC_tW2R) +#define K_BCM1480_MC_tW2R_DEFAULT 1 +#define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT) + +#define S_BCM1480_MC_tR2W 60 +#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2,S_BCM1480_MC_tR2W) +#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tR2W) +#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tR2W,M_BCM1480_MC_tR2W) +#define K_BCM1480_MC_tR2W_DEFAULT 0 +#define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT) + +#define M_BCM1480_MC_tR2R _SB_MAKEMASK1(62) + +#define V_BCM1480_MC_TIMING_DEFAULT (M_BCM1480_MC_tR2R | \ + V_BCM1480_MC_tFIFO_DEFAULT | \ + V_BCM1480_MC_tR2W_DEFAULT | \ + V_BCM1480_MC_tW2R_DEFAULT | \ + V_BCM1480_MC_tRFC_DEFAULT | \ + V_BCM1480_MC_tRCr_DEFAULT | \ + V_BCM1480_MC_tRCw_DEFAULT | \ + V_BCM1480_MC_tRRD_DEFAULT | \ + V_BCM1480_MC_tRP_DEFAULT | \ + V_BCM1480_MC_tCwD_DEFAULT | \ + V_BCM1480_MC_tWR_DEFAULT | \ + M_BCM1480_MC_tCrDh | \ + V_BCM1480_MC_tCL_DEFAULT | \ + V_BCM1480_MC_tRCD_DEFAULT) + +/* + * SDRAM Timing Register 2 + */ + +#if SIBYTE_HDR_FEATURE(1480, PASS2) + +#define S_BCM1480_MC_tAL 0 +#define M_BCM1480_MC_tAL _SB_MAKEMASK(4,S_BCM1480_MC_tAL) +#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tAL) +#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x,S_BCM1480_MC_tAL,M_BCM1480_MC_tAL) +#define K_BCM1480_MC_tAL_DEFAULT 0 +#define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT) + +#define S_BCM1480_MC_tRTP 4 +#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3,S_BCM1480_MC_tRTP) +#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRTP) +#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRTP,M_BCM1480_MC_tRTP) +#define K_BCM1480_MC_tRTP_DEFAULT 2 +#define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT) + +#define S_BCM1480_MC_tW2W 8 +#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2,S_BCM1480_MC_tW2W) +#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2W) +#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2W,M_BCM1480_MC_tW2W) +#define K_BCM1480_MC_tW2W_DEFAULT 0 +#define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT) + +#define S_BCM1480_MC_tRAP 12 +#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4,S_BCM1480_MC_tRAP) +#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRAP) +#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRAP,M_BCM1480_MC_tRAP) +#define K_BCM1480_MC_tRAP_DEFAULT 0 +#define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT) + +#endif + + + +/* + * Global Registers: single instances per BCM1480 + */ + +/* + * Global Configuration Register (Table 99) + */ + +#define S_BCM1480_MC_BLK_SET_MARK 8 +#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_SET_MARK) +#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_SET_MARK) +#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_SET_MARK,M_BCM1480_MC_BLK_SET_MARK) + +#define S_BCM1480_MC_BLK_CLR_MARK 12 +#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_CLR_MARK) +#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_CLR_MARK) +#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_CLR_MARK,M_BCM1480_MC_BLK_CLR_MARK) + +#define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16) + +#define S_BCM1480_MC_MAX_AGE 20 +#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4,S_BCM1480_MC_MAX_AGE) +#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MAX_AGE) +#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x,S_BCM1480_MC_MAX_AGE,M_BCM1480_MC_MAX_AGE) + +#define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29) +#define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30) +#define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32) + +#define S_BCM1480_MC_SLEW 33 +#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2,S_BCM1480_MC_SLEW) +#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_SLEW) +#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x,S_BCM1480_MC_SLEW,M_BCM1480_MC_SLEW) + +#define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35) + +/* + * Global Channel Interleave Register (Table 100) + */ + +#define S_BCM1480_MC_INTLV0 0 +#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) +#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) +#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) + +#define S_BCM1480_MC_INTLV1 8 +#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) +#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) +#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) + +#define S_BCM1480_MC_INTLV_MODE 16 +#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3,S_BCM1480_MC_INTLV_MODE) +#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV_MODE) +#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV_MODE,M_BCM1480_MC_INTLV_MODE) + +#define K_BCM1480_MC_INTLV_MODE_NONE 0x0 +#define K_BCM1480_MC_INTLV_MODE_01 0x1 +#define K_BCM1480_MC_INTLV_MODE_23 0x2 +#define K_BCM1480_MC_INTLV_MODE_01_23 0x3 +#define K_BCM1480_MC_INTLV_MODE_0123 0x4 + +#define V_BCM1480_MC_INTLV_MODE_NONE V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE) +#define V_BCM1480_MC_INTLV_MODE_01 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01) +#define V_BCM1480_MC_INTLV_MODE_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23) +#define V_BCM1480_MC_INTLV_MODE_01_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23) +#define V_BCM1480_MC_INTLV_MODE_0123 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123) + +/* + * ECC Status Register + */ + +#define S_BCM1480_MC_ECC_ERR_ADDR 0 +#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_ERR_ADDR) +#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR) +#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR,M_BCM1480_MC_ECC_ERR_ADDR) + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60) +#endif + +#define M_BCM1480_MC_ECC_MULT_ERR_DET _SB_MAKEMASK1(61) +#define M_BCM1480_MC_ECC_UERR_DET _SB_MAKEMASK1(62) +#define M_BCM1480_MC_ECC_CERR_DET _SB_MAKEMASK1(63) + +/* + * Global ECC Address Register (Table 102) + */ + +#define S_BCM1480_MC_ECC_CORR_ADDR 0 +#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_CORR_ADDR) +#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR) +#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR,M_BCM1480_MC_ECC_CORR_ADDR) + +/* + * Global ECC Correction Register (Table 103) + */ + +#define S_BCM1480_MC_ECC_CORRECT 0 +#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_CORRECT) +#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORRECT) +#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORRECT,M_BCM1480_MC_ECC_CORRECT) + +/* + * Global ECC Performance Counters Control Register (Table 104) + */ + +#define S_BCM1480_MC_CHANNEL_SELECT 0 +#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4,S_BCM1480_MC_CHANNEL_SELECT) +#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CHANNEL_SELECT) +#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x,S_BCM1480_MC_CHANNEL_SELECT,M_BCM1480_MC_CHANNEL_SELECT) +#define K_BCM1480_MC_CHANNEL_SELECT_0 0x1 +#define K_BCM1480_MC_CHANNEL_SELECT_1 0x2 +#define K_BCM1480_MC_CHANNEL_SELECT_2 0x4 +#define K_BCM1480_MC_CHANNEL_SELECT_3 0x8 + +#endif /* _BCM1480_MC_H */ diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h new file mode 100644 index 000000000000..c2dd2fe3047c --- /dev/null +++ b/include/asm-mips/sibyte/bcm1480_regs.h @@ -0,0 +1,869 @@ +/* ********************************************************************* + * BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package + * + * Register Definitions File: bcm1480_regs.h + * + * This module contains the addresses of the on-chip peripherals + * on the BCM1280 and BCM1480. + * + * BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03) + * + ********************************************************************* + * + * Copyright 2000,2001,2002,2003 + * Broadcom Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + ********************************************************************* */ + +#ifndef _BCM1480_REGS_H +#define _BCM1480_REGS_H + +#include "sb1250_defs.h" + +/* ********************************************************************* + * Pull in the BCM1250's registers since a great deal of the 1480's + * functions are the same as the BCM1250. + ********************************************************************* */ + +#include "sb1250_regs.h" + + +/* ********************************************************************* + * Some general notes: + * + * Register addresses are grouped by function and follow the order + * of the User Manual. + * + * For the most part, when there is more than one peripheral + * of the same type on the SOC, the constants below will be + * offsets from the base of each peripheral. For example, + * the MAC registers are described as offsets from the first + * MAC register, and there will be a MAC_REGISTER() macro + * to calculate the base address of a given MAC. + * + * The information in this file is based on the BCM1X55/BCM1X80 + * User Manual, Document 1X55_1X80-UM100-R, 22/12/03. + * + * This file is basically a "what's new" header file. Since the + * BCM1250 and the new BCM1480 (and derivatives) share many common + * features, this file contains only what's new or changed from + * the 1250. (above, you can see that we include the 1250 symbols + * to get the base functionality). + * + * In software, be sure to use the correct symbols, particularly + * for blocks that are different between the two chip families. + * All BCM1480-specific symbols have _BCM1480_ in their names, + * and all BCM1250-specific and "base" functions that are common in + * both chips have no special names (this is for compatibility with + * older include files). Therefore, if you're working with the + * SCD, which is very different on each chip, A_SCD_xxx implies + * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480 + * version. + ********************************************************************* */ + + +/* ********************************************************************* + * Memory Controller Registers (Section 6) + ********************************************************************* */ + +#define A_BCM1480_MC_BASE_0 0x0010050000 +#define A_BCM1480_MC_BASE_1 0x0010051000 +#define A_BCM1480_MC_BASE_2 0x0010052000 +#define A_BCM1480_MC_BASE_3 0x0010053000 +#define BCM1480_MC_REGISTER_SPACING 0x1000 + +#define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING) +#define A_BCM1480_MC_REGISTER(ctlid,reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) + +#define R_BCM1480_MC_CONFIG 0x0000000100 +#define R_BCM1480_MC_CS_START 0x0000000120 +#define R_BCM1480_MC_CS_END 0x0000000140 +#define S_BCM1480_MC_CS_STARTEND 24 + +#define R_BCM1480_MC_CS01_ROW0 0x0000000180 +#define R_BCM1480_MC_CS01_ROW1 0x00000001A0 +#define R_BCM1480_MC_CS23_ROW0 0x0000000200 +#define R_BCM1480_MC_CS23_ROW1 0x0000000220 +#define R_BCM1480_MC_CS01_COL0 0x0000000280 +#define R_BCM1480_MC_CS01_COL1 0x00000002A0 +#define R_BCM1480_MC_CS23_COL0 0x0000000300 +#define R_BCM1480_MC_CS23_COL1 0x0000000320 + +#define R_BCM1480_MC_CSX_BASE 0x0000000180 +#define R_BCM1480_MC_CSX_ROW0 0x0000000000 /* relative to CSX_BASE */ +#define R_BCM1480_MC_CSX_ROW1 0x0000000020 /* relative to CSX_BASE */ +#define R_BCM1480_MC_CSX_COL0 0x0000000100 /* relative to CSX_BASE */ +#define R_BCM1480_MC_CSX_COL1 0x0000000120 /* relative to CSX_BASE */ +#define BCM1480_MC_CSX_SPACING 0x0000000080 /* CS23 relative to CS01 */ + +#define R_BCM1480_MC_CS01_BA 0x0000000380 +#define R_BCM1480_MC_CS23_BA 0x00000003A0 +#define R_BCM1480_MC_DRAMCMD 0x0000000400 +#define R_BCM1480_MC_DRAMMODE 0x0000000420 +#define R_BCM1480_MC_CLOCK_CFG 0x0000000440 +#define R_BCM1480_MC_MCLK_CFG R_BCM1480_MC_CLOCK_CFG +#define R_BCM1480_MC_TEST_DATA 0x0000000480 +#define R_BCM1480_MC_TEST_ECC 0x00000004A0 +#define R_BCM1480_MC_TIMING1 0x00000004C0 +#define R_BCM1480_MC_TIMING2 0x00000004E0 +#define R_BCM1480_MC_DLL_CFG 0x0000000500 +#define R_BCM1480_MC_DRIVE_CFG 0x0000000520 + +#if SIBYTE_HDR_FEATURE(1480, PASS2) +#define R_BCM1480_MC_ODT 0x0000000460 +#define R_BCM1480_MC_ECC_STATUS 0x0000000540 +#endif + +/* Global registers (single instance) */ +#define A_BCM1480_MC_GLB_CONFIG 0x0010054100 +#define A_BCM1480_MC_GLB_INTLV 0x0010054120 +#define A_BCM1480_MC_GLB_ECC_STATUS 0x0010054140 +#define A_BCM1480_MC_GLB_ECC_ADDR 0x0010054160 +#define A_BCM1480_MC_GLB_ECC_CORRECT 0x0010054180 +#define A_BCM1480_MC_GLB_PERF_CNT_CONTROL 0x00100541A0 + +/* ********************************************************************* + * L2 Cache Control Registers (Section 5) + ********************************************************************* */ + +#define A_BCM1480_L2_BASE 0x0010040000 + +#define A_BCM1480_L2_READ_TAG 0x0010040018 +#define A_BCM1480_L2_ECC_TAG 0x0010040038 +#define A_BCM1480_L2_MISC0_VALUE 0x0010040058 +#define A_BCM1480_L2_MISC1_VALUE 0x0010040078 +#define A_BCM1480_L2_MISC2_VALUE 0x0010040098 +#define A_BCM1480_L2_MISC_CONFIG 0x0010040040 /* x040 */ +#define A_BCM1480_L2_CACHE_DISABLE 0x0010040060 /* x060 */ +#define A_BCM1480_L2_MAKECACHEDISABLE(x) (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12)) +#define A_BCM1480_L2_WAY_ENABLE_3_0 0x0010040080 /* x080 */ +#define A_BCM1480_L2_WAY_ENABLE_7_4 0x00100400A0 /* x0A0 */ +#define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12)) +#define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12)) +#define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12)) +#define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12)) +#define A_BCM1480_L2_WAY_LOCAL_3_0 0x0010040100 /* x100 */ +#define A_BCM1480_L2_WAY_LOCAL_7_4 0x0010040120 /* x120 */ +#define A_BCM1480_L2_WAY_REMOTE_3_0 0x0010040140 /* x140 */ +#define A_BCM1480_L2_WAY_REMOTE_7_4 0x0010040160 /* x160 */ +#define A_BCM1480_L2_WAY_AGENT_3_0 0x00100400C0 /* xxC0 */ +#define A_BCM1480_L2_WAY_AGENT_7_4 0x00100400E0 /* xxE0 */ +#define A_BCM1480_L2_WAY_ENABLE(A, banks) (A | (((~(banks))&0x0F) << 8)) +#define A_BCM1480_L2_BANK_BASE 0x00D0300000 +#define A_BCM1480_L2_BANK_ADDRESS(b) (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17)) +#define A_BCM1480_L2_MGMT_TAG_BASE 0x00D0000000 + + +/* ********************************************************************* + * PCI-X Interface Registers (Section 7) + ********************************************************************* */ + +#define A_BCM1480_PCI_BASE 0x0010061400 + +#define A_BCM1480_PCI_RESET 0x0010061400 +#define A_BCM1480_PCI_DLL 0x0010061500 + +#define A_BCM1480_PCI_TYPE00_HEADER 0x002E000000 + +/* ********************************************************************* + * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6) + ********************************************************************* */ + +/* No register changes with Rev.C BCM1250, but one additional MAC */ + +#define A_BCM1480_MAC_BASE_2 0x0010066000 + +#ifndef A_MAC_BASE_2 +#define A_MAC_BASE_2 A_BCM1480_MAC_BASE_2 +#endif + +#define A_BCM1480_MAC_BASE_3 0x0010067000 +#define A_MAC_BASE_3 A_BCM1480_MAC_BASE_3 + +#define R_BCM1480_MAC_DMA_OODPKTLOST 0x00000038 + +#ifndef R_MAC_DMA_OODPKTLOST +#define R_MAC_DMA_OODPKTLOST R_BCM1480_MAC_DMA_OODPKTLOST +#endif + + +/* ********************************************************************* + * DUART Registers (Section 14) + ********************************************************************* */ + +/* No significant differences from BCM1250, two DUARTs */ + +/* Conventions, per user manual: + * DUART generic, channels A,B,C,D + * DUART0 implementing channels A,B + * DUART1 inplementing channels C,D + */ + +#define BCM1480_DUART_NUM_PORTS 4 + +#define A_BCM1480_DUART0 0x0010060000 +#define A_BCM1480_DUART1 0x0010060400 +#define A_BCM1480_DUART(chan) ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1) + +#define BCM1480_DUART_CHANREG_SPACING 0x100 +#define A_BCM1480_DUART_CHANREG(chan,reg) (A_BCM1480_DUART(chan) \ + + BCM1480_DUART_CHANREG_SPACING*((chan)&1) \ + + (reg)) +#define R_BCM1480_DUART_CHANREG(chan,reg) (BCM1480_DUART_CHANREG_SPACING*((chan)&1) + (reg)) + +#define R_BCM1480_DUART_IMRREG(chan) (R_DUART_IMR_A + ((chan)&1)*DUART_IMRISR_SPACING) +#define R_BCM1480_DUART_ISRREG(chan) (R_DUART_ISR_A + ((chan)&1)*DUART_IMRISR_SPACING) + +#define A_BCM1480_DUART_IMRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan)) +#define A_BCM1480_DUART_ISRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan)) + +/* + * These constants are the absolute addresses. + */ + +#define A_BCM1480_DUART_MODE_REG_1_C 0x0010060400 +#define A_BCM1480_DUART_MODE_REG_2_C 0x0010060410 +#define A_BCM1480_DUART_STATUS_C 0x0010060420 +#define A_BCM1480_DUART_CLK_SEL_C 0x0010060430 +#define A_BCM1480_DUART_FULL_CTL_C 0x0010060440 +#define A_BCM1480_DUART_CMD_C 0x0010060450 +#define A_BCM1480_DUART_RX_HOLD_C 0x0010060460 +#define A_BCM1480_DUART_TX_HOLD_C 0x0010060470 +#define A_BCM1480_DUART_OPCR_C 0x0010060480 +#define A_BCM1480_DUART_AUX_CTRL_C 0x0010060490 + +#define A_BCM1480_DUART_MODE_REG_1_D 0x0010060500 +#define A_BCM1480_DUART_MODE_REG_2_D 0x0010060510 +#define A_BCM1480_DUART_STATUS_D 0x0010060520 +#define A_BCM1480_DUART_CLK_SEL_D 0x0010060530 +#define A_BCM1480_DUART_FULL_CTL_D 0x0010060540 +#define A_BCM1480_DUART_CMD_D 0x0010060550 +#define A_BCM1480_DUART_RX_HOLD_D 0x0010060560 +#define A_BCM1480_DUART_TX_HOLD_D 0x0010060570 +#define A_BCM1480_DUART_OPCR_D 0x0010060580 +#define A_BCM1480_DUART_AUX_CTRL_D 0x0010060590 + +#define A_BCM1480_DUART_INPORT_CHNG_CD 0x0010060600 +#define A_BCM1480_DUART_AUX_CTRL_CD 0x0010060610 +#define A_BCM1480_DUART_ISR_C 0x0010060620 +#define A_BCM1480_DUART_IMR_C 0x0010060630 +#define A_BCM1480_DUART_ISR_D 0x0010060640 +#define A_BCM1480_DUART_IMR_D 0x0010060650 +#define A_BCM1480_DUART_OUT_PORT_CD 0x0010060660 +#define A_BCM1480_DUART_OPCR_CD 0x0010060670 +#define A_BCM1480_DUART_IN_PORT_CD 0x0010060680 +#define A_BCM1480_DUART_ISR_CD 0x0010060690 +#define A_BCM1480_DUART_IMR_CD 0x00100606A0 +#define A_BCM1480_DUART_SET_OPR_CD 0x00100606B0 +#define A_BCM1480_DUART_CLEAR_OPR_CD 0x00100606C0 +#define A_BCM1480_DUART_INPORT_CHNG_C 0x00100606D0 +#define A_BCM1480_DUART_INPORT_CHNG_D 0x00100606E0 + + +/* ********************************************************************* + * Generic Bus Registers (Section 15) and PCMCIA Registers (Section 16) + ********************************************************************* */ + +#define A_BCM1480_IO_PCMCIA_CFG_B 0x0010061A58 +#define A_BCM1480_IO_PCMCIA_STATUS_B 0x0010061A68 + +/* ********************************************************************* + * GPIO Registers (Section 17) + ********************************************************************* */ + +/* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */ + +#define A_BCM1480_GPIO_INT_ADD_TYPE 0x0010061A78 +#define R_BCM1480_GPIO_INT_ADD_TYPE (-8) + +#define A_GPIO_INT_ADD_TYPE A_BCM1480_GPIO_INT_ADD_TYPE +#define R_GPIO_INT_ADD_TYPE R_BCM1480_GPIO_INT_ADD_TYPE + +/* ********************************************************************* + * SMBus Registers (Section 18) + ********************************************************************* */ + +/* No changes from BCM1250 */ + +/* ********************************************************************* + * Timer Registers (Sections 4.6) + ********************************************************************* */ + +/* BCM1480 has two additional watchdogs */ + +/* Watchdog timers */ + +#define A_BCM1480_SCD_WDOG_2 0x0010022050 +#define A_BCM1480_SCD_WDOG_3 0x0010022150 + +#define BCM1480_SCD_NUM_WDOGS 4 + +#define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100) +#define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) + +#define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050 +#define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058 +#define A_BCM1480_SCD_WDOG_CFG_2 0x0010022060 + +#define A_BCM1480_SCD_WDOG_INIT_3 0x0010022150 +#define A_BCM1480_SCD_WDOG_CNT_3 0x0010022158 +#define A_BCM1480_SCD_WDOG_CFG_3 0x0010022160 + +/* BCM1480 has two additional compare registers */ + +#define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT A_SCD_ZBBUS_CYCLE_COUNT +#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE 0x0010020C00 +#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0 A_SCD_ZBBUS_CYCLE_CP0 +#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1 A_SCD_ZBBUS_CYCLE_CP1 +#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2 0x0010020C10 +#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3 0x0010020C18 + +/* ********************************************************************* + * System Control Registers (Section 4.2) + ********************************************************************* */ + +/* Scratch register in different place */ + +#define A_BCM1480_SCD_SCRATCH 0x100200A0 + +/* ********************************************************************* + * System Address Trap Registers (Section 4.9) + ********************************************************************* */ + +/* No changes from BCM1250 */ + +/* ********************************************************************* + * System Interrupt Mapper Registers (Sections 4.3-4.5) + ********************************************************************* */ + +#define A_BCM1480_IMR_CPU0_BASE 0x0010020000 +#define A_BCM1480_IMR_CPU1_BASE 0x0010022000 +#define A_BCM1480_IMR_CPU2_BASE 0x0010024000 +#define A_BCM1480_IMR_CPU3_BASE 0x0010026000 +#define BCM1480_IMR_REGISTER_SPACING 0x2000 +#define BCM1480_IMR_REGISTER_SPACING_SHIFT 13 + +#define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING) +#define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) + +/* Most IMR registers are 128 bits, implemented as non-contiguous + 64-bit registers high (_H) and low (_L) */ +#define BCM1480_IMR_HL_SPACING 0x1000 + +#define R_BCM1480_IMR_INTERRUPT_DIAG_H 0x0010 +#define R_BCM1480_IMR_LDT_INTERRUPT_H 0x0018 +#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H 0x0020 +#define R_BCM1480_IMR_INTERRUPT_MASK_H 0x0028 +#define R_BCM1480_IMR_INTERRUPT_TRACE_H 0x0038 +#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040 +#define R_BCM1480_IMR_LDT_INTERRUPT_SET 0x0048 +#define R_BCM1480_IMR_MAILBOX_0_CPU 0x00C0 +#define R_BCM1480_IMR_MAILBOX_0_SET_CPU 0x00C8 +#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU 0x00D0 +#define R_BCM1480_IMR_MAILBOX_1_CPU 0x00E0 +#define R_BCM1480_IMR_MAILBOX_1_SET_CPU 0x00E8 +#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU 0x00F0 +#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H 0x0100 +#define BCM1480_IMR_INTERRUPT_STATUS_COUNT 8 +#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H 0x0200 +#define BCM1480_IMR_INTERRUPT_MAP_COUNT 64 + +#define R_BCM1480_IMR_INTERRUPT_DIAG_L 0x1010 +#define R_BCM1480_IMR_LDT_INTERRUPT_L 0x1018 +#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L 0x1020 +#define R_BCM1480_IMR_INTERRUPT_MASK_L 0x1028 +#define R_BCM1480_IMR_INTERRUPT_TRACE_L 0x1038 +#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040 +#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L 0x1100 +#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L 0x1200 + +#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE 0x0010028000 +#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE 0x0010028100 +#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE 0x0010028200 +#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE 0x0010028300 +#define BCM1480_IMR_ALIAS_MAILBOX_SPACING 0100 + +#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \ + (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING) +#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) + +#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ +#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ + +/* ********************************************************************* + * System Performance Counter Registers (Section 4.7) + ********************************************************************* */ + +/* BCM1480 has four more performance counter registers, and two control + registers. */ + +#define A_BCM1480_SCD_PERF_CNT_BASE 0x00100204C0 + +#define A_BCM1480_SCD_PERF_CNT_CFG0 0x00100204C0 +#define A_BCM1480_SCD_PERF_CNT_CFG_0 A_BCM1480_SCD_PERF_CNT_CFG0 +#define A_BCM1480_SCD_PERF_CNT_CFG1 0x00100204C8 +#define A_BCM1480_SCD_PERF_CNT_CFG_1 A_BCM1480_SCD_PERF_CNT_CFG1 + +#define A_BCM1480_SCD_PERF_CNT_0 A_SCD_PERF_CNT_0 +#define A_BCM1480_SCD_PERF_CNT_1 A_SCD_PERF_CNT_1 +#define A_BCM1480_SCD_PERF_CNT_2 A_SCD_PERF_CNT_2 +#define A_BCM1480_SCD_PERF_CNT_3 A_SCD_PERF_CNT_3 + +#define A_BCM1480_SCD_PERF_CNT_4 0x00100204F0 +#define A_BCM1480_SCD_PERF_CNT_5 0x00100204F8 +#define A_BCM1480_SCD_PERF_CNT_6 0x0010020500 +#define A_BCM1480_SCD_PERF_CNT_7 0x0010020508 + +/* ********************************************************************* + * System Bus Watcher Registers (Section 4.8) + ********************************************************************* */ + + +/* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */ + +#define A_BCM1480_BUS_ERR_STATUS_DEBUG 0x00100208D8 + +/* ********************************************************************* + * System Debug Controller Registers (Section 19) + ********************************************************************* */ + +/* Same as 1250 */ + +/* ********************************************************************* + * System Trace Unit Registers (Sections 4.10) + ********************************************************************* */ + +/* Same as 1250 */ + +/* ********************************************************************* + * Data Mover DMA Registers (Section 10.7) + ********************************************************************* */ + +/* Same as 1250 */ + + +/* ********************************************************************* + * HyperTransport Interface Registers (Section 8) + ********************************************************************* */ + +#define BCM1480_HT_NUM_PORTS 3 +#define BCM1480_HT_PORT_SPACING 0x800 +#define A_BCM1480_HT_PORT_HEADER(x) (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING)) + +#define A_BCM1480_HT_PORT0_HEADER 0x00FE000000 +#define A_BCM1480_HT_PORT1_HEADER 0x00FE000800 +#define A_BCM1480_HT_PORT2_HEADER 0x00FE001000 +#define A_BCM1480_HT_TYPE00_HEADER 0x00FE002000 + + +/* ********************************************************************* + * Node Controller Registers (Section 9) + ********************************************************************* */ + +#define A_BCM1480_NC_BASE 0x00DFBD0000 + +#define A_BCM1480_NC_RLD_FIELD 0x00DFBD0000 +#define A_BCM1480_NC_RLD_TRIGGER 0x00DFBD0020 +#define A_BCM1480_NC_RLD_BAD_ERROR 0x00DFBD0040 +#define A_BCM1480_NC_RLD_COR_ERROR 0x00DFBD0060 +#define A_BCM1480_NC_RLD_ECC_STATUS 0x00DFBD0080 +#define A_BCM1480_NC_RLD_WAY_ENABLE 0x00DFBD00A0 +#define A_BCM1480_NC_RLD_RANDOM_LFSR 0x00DFBD00C0 + +#define A_BCM1480_NC_INTERRUPT_STATUS 0x00DFBD00E0 +#define A_BCM1480_NC_INTERRUPT_ENABLE 0x00DFBD0100 +#define A_BCM1480_NC_TIMEOUT_COUNTER 0x00DFBD0120 +#define A_BCM1480_NC_TIMEOUT_COUNTER_SEL 0x00DFBD0140 + +#define A_BCM1480_NC_CREDIT_STATUS_REG0 0x00DFBD0200 +#define A_BCM1480_NC_CREDIT_STATUS_REG1 0x00DFBD0220 +#define A_BCM1480_NC_CREDIT_STATUS_REG2 0x00DFBD0240 +#define A_BCM1480_NC_CREDIT_STATUS_REG3 0x00DFBD0260 +#define A_BCM1480_NC_CREDIT_STATUS_REG4 0x00DFBD0280 +#define A_BCM1480_NC_CREDIT_STATUS_REG5 0x00DFBD02A0 +#define A_BCM1480_NC_CREDIT_STATUS_REG6 0x00DFBD02C0 +#define A_BCM1480_NC_CREDIT_STATUS_REG7 0x00DFBD02E0 +#define A_BCM1480_NC_CREDIT_STATUS_REG8 0x00DFBD0300 +#define A_BCM1480_NC_CREDIT_STATUS_REG9 0x00DFBD0320 +#define A_BCM1480_NC_CREDIT_STATUS_REG10 0x00DFBE0000 +#define A_BCM1480_NC_CREDIT_STATUS_REG11 0x00DFBE0020 +#define A_BCM1480_NC_CREDIT_STATUS_REG12 0x00DFBE0040 + +#define A_BCM1480_NC_SR_TIMEOUT_COUNTER 0x00DFBE0060 +#define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080 + + +/* ********************************************************************* + * H&R Block Configuration Registers (Section 12.4) + ********************************************************************* */ + +#define A_BCM1480_HR_BASE_0 0x00DF820000 +#define A_BCM1480_HR_BASE_1 0x00DF8A0000 +#define A_BCM1480_HR_BASE_2 0x00DF920000 +#define BCM1480_HR_REGISTER_SPACING 0x80000 + +#define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) +#define A_BCM1480_HR_REGISTER(idx,reg) (A_BCM1480_HR_BASE(idx) + (reg)) + +#define R_BCM1480_HR_CFG 0x0000000000 + +#define R_BCM1480_HR_MAPPING 0x0000010010 + +#define BCM1480_HR_RULE_SPACING 0x0000000010 +#define BCM1480_HR_NUM_RULES 16 +#define BCM1480_HR_OP_OFFSET 0x0000000100 +#define BCM1480_HR_TYPE_OFFSET 0x0000000108 +#define R_BCM1480_HR_RULE_OP(idx) (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) +#define R_BCM1480_HR_RULE_TYPE(idx) (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) + +#define BCM1480_HR_LEAF_SPACING 0x0000000010 +#define BCM1480_HR_NUM_LEAVES 10 +#define BCM1480_HR_LEAF_OFFSET 0x0000000300 +#define R_BCM1480_HR_HA_LEAF0(idx) (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING)) + +#define R_BCM1480_HR_EX_LEAF0 0x00000003A0 + +#define BCM1480_HR_PATH_SPACING 0x0000000010 +#define BCM1480_HR_NUM_PATHS 16 +#define BCM1480_HR_PATH_OFFSET 0x0000000600 +#define R_BCM1480_HR_PATH(idx) (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING)) + +#define R_BCM1480_HR_PATH_DEFAULT 0x0000000700 + +#define BCM1480_HR_ROUTE_SPACING 8 +#define BCM1480_HR_NUM_ROUTES 512 +#define BCM1480_HR_ROUTE_OFFSET 0x0000001000 +#define R_BCM1480_HR_RT_WORD(idx) (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING)) + + +/* checked to here - ehs */ +/* ********************************************************************* + * Packet Manager DMA Registers (Section 12.5) + ********************************************************************* */ + +#define A_BCM1480_PM_BASE 0x0010056000 + +#define A_BCM1480_PMI_LCL_0 0x0010058000 +#define A_BCM1480_PMO_LCL_0 0x001005C000 +#define A_BCM1480_PMI_OFFSET_0 (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE) +#define A_BCM1480_PMO_OFFSET_0 (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE) + +#define BCM1480_PM_LCL_REGISTER_SPACING 0x100 +#define BCM1480_PM_NUM_CHANNELS 32 + +#define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) +#define A_BCM1480_PMI_LCL_REGISTER(idx,reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) +#define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) +#define A_BCM1480_PMO_LCL_REGISTER(idx,reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) + +#define BCM1480_PM_INT_PACKING 8 +#define BCM1480_PM_INT_FUNCTION_SPACING 0x40 +#define BCM1480_PM_INT_NUM_FUNCTIONS 3 + +/* + * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n) + */ + +#define R_BCM1480_PM_BASE_SIZE 0x0000000000 +#define R_BCM1480_PM_CNT 0x0000000008 +#define R_BCM1480_PM_PFCNT 0x0000000010 +#define R_BCM1480_PM_LAST 0x0000000018 +#define R_BCM1480_PM_PFINDX 0x0000000020 +#define R_BCM1480_PM_INT_WMK 0x0000000028 +#define R_BCM1480_PM_CONFIG0 0x0000000030 +#define R_BCM1480_PM_LOCALDEBUG 0x0000000078 +#define R_BCM1480_PM_CACHEABILITY 0x0000000080 /* PMI only */ +#define R_BCM1480_PM_INT_CNFG 0x0000000088 +#define R_BCM1480_PM_DESC_MERGE_TIMER 0x0000000090 +#define R_BCM1480_PM_LOCALDEBUG_PIB 0x00000000F8 /* PMI only */ +#define R_BCM1480_PM_LOCALDEBUG_POB 0x00000000F8 /* PMO only */ + +/* + * Global Registers (Not Channelized) + */ + +#define A_BCM1480_PMI_GLB_0 0x0010056000 +#define A_BCM1480_PMO_GLB_0 0x0010057000 + +/* + * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0 + */ + +#define R_BCM1480_PM_PMO_MAPPING 0x00000008C8 /* PMO only */ + +#define A_BCM1480_PM_PMO_MAPPING (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING) + +/* + * Interrupt mapping registers + */ + + +#define A_BCM1480_PMI_INT_0 0x0010056800 +#define A_BCM1480_PMI_INT(q) (A_BCM1480_PMI_INT_0 + ((q>>8)<<8)) +#define A_BCM1480_PMI_INT_OFFSET_0 (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE) +#define A_BCM1480_PMO_INT_0 0x0010057800 +#define A_BCM1480_PMO_INT(q) (A_BCM1480_PMO_INT_0 + ((q>>8)<<8)) +#define A_BCM1480_PMO_INT_OFFSET_0 (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE) + +/* + * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0 + */ + +#define R_BCM1480_PM_INT_ST 0x0000000000 +#define R_BCM1480_PM_INT_MSK 0x0000000040 +#define R_BCM1480_PM_INT_CLR 0x0000000080 +#define R_BCM1480_PM_MRGD_INT 0x00000000C0 + +/* + * Debug registers (global) + */ + +#define A_BCM1480_PM_GLOBALDEBUGMODE_PMI 0x0010056000 +#define A_BCM1480_PM_GLOBALDEBUG_PID 0x00100567F8 +#define A_BCM1480_PM_GLOBALDEBUG_PIB 0x0010056FF8 +#define A_BCM1480_PM_GLOBALDEBUGMODE_PMO 0x0010057000 +#define A_BCM1480_PM_GLOBALDEBUG_POD 0x00100577F8 +#define A_BCM1480_PM_GLOBALDEBUG_POB 0x0010057FF8 + +/* ********************************************************************* + * Switch performance counters + ********************************************************************* */ + +#define A_BCM1480_SWPERF_CFG 0xdfb91800 +#define A_BCM1480_SWPERF_CNT0 0xdfb91880 +#define A_BCM1480_SWPERF_CNT1 0xdfb91888 +#define A_BCM1480_SWPERF_CNT2 0xdfb91890 +#define A_BCM1480_SWPERF_CNT3 0xdfb91898 + + +/* ********************************************************************* + * Switch Trace Unit + ********************************************************************* */ + +#define A_BCM1480_SWTRC_MATCH_CONTROL_0 0xDFB91000 +#define A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 0xDFB91100 +#define A_BCM1480_SWTRC_MATCH_DATA_MASK_0 0xDFB91108 +#define A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 0xDFB91200 +#define A_BCM1480_SWTRC_MATCH_TAG_MAKS_0 0xDFB91208 +#define A_BCM1480_SWTRC_EVENT_0 0xDFB91300 +#define A_BCM1480_SWTRC_SEQUENCE_0 0xDFB91400 + +#define A_BCM1480_SWTRC_CFG 0xDFB91500 +#define A_BCM1480_SWTRC_READ 0xDFB91508 + +#define A_BCM1480_SWDEBUG_SCHEDSTOP 0xDFB92000 + +#define A_BCM1480_SWTRC_MATCH_CONTROL(x) (A_BCM1480_SWTRC_MATCH_CONTROL_0 + ((x)*8)) +#define A_BCM1480_SWTRC_EVENT(x) (A_BCM1480_SWTRC_EVENT_0 + ((x)*8)) +#define A_BCM1480_SWTRC_SEQUENCE(x) (A_BCM1480_SWTRC_SEQUENCE_0 + ((x)*8)) + +#define A_BCM1480_SWTRC_MATCH_DATA_VALUE(x) (A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 + ((x)*16)) +#define A_BCM1480_SWTRC_MATCH_DATA_MASK(x) (A_BCM1480_SWTRC_MATCH_DATA_MASK_0 + ((x)*16)) +#define A_BCM1480_SWTRC_MATCH_TAG_VALUE(x) (A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 + ((x)*16)) +#define A_BCM1480_SWTRC_MATCH_TAG_MASK(x) (A_BCM1480_SWTRC_MATCH_TAG_MASK_0 + ((x)*16)) + + + +/* ********************************************************************* + * High-Speed Port Registers (Section 13) + ********************************************************************* */ + +#define A_BCM1480_HSP_BASE_0 0x00DF810000 +#define A_BCM1480_HSP_BASE_1 0x00DF890000 +#define A_BCM1480_HSP_BASE_2 0x00DF910000 +#define BCM1480_HSP_REGISTER_SPACING 0x80000 + +#define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING)) +#define A_BCM1480_HSP_REGISTER(idx,reg) (A_BCM1480_HSP_BASE(idx) + (reg)) + +#define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000 +#define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008 +#define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010 +#define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018 +#define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN 0x0000000020 +#define R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS 0x0000000028 + +#define R_BCM1480_HSP_RX_SPI4_CALENDAR_0 0x0000000200 +#define R_BCM1480_HSP_RX_SPI4_CALENDAR_1 0x0000000208 + +#define R_BCM1480_HSP_RX_PLL_CNFG 0x0000000800 +#define R_BCM1480_HSP_RX_CALIBRATION 0x0000000808 +#define R_BCM1480_HSP_RX_TEST 0x0000000810 +#define R_BCM1480_HSP_RX_DIAG_DETAILS 0x0000000818 +#define R_BCM1480_HSP_RX_DIAG_CRC_0 0x0000000820 +#define R_BCM1480_HSP_RX_DIAG_CRC_1 0x0000000828 +#define R_BCM1480_HSP_RX_DIAG_HTCMD 0x0000000830 +#define R_BCM1480_HSP_RX_DIAG_PKTCTL 0x0000000838 + +#define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER 0x0000000870 + +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0 0x0000020020 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1 0x0000020028 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2 0x0000020030 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3 0x0000020038 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4 0x0000020040 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5 0x0000020048 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6 0x0000020050 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7 0x0000020058 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx)) + +/* XXX Following registers were shuffled. Renamed/renumbered per errata. */ +#define R_BCM1480_HSP_RX_HT_RAMALLOC_0 0x0000020078 +#define R_BCM1480_HSP_RX_HT_RAMALLOC_1 0x0000020080 +#define R_BCM1480_HSP_RX_HT_RAMALLOC_2 0x0000020088 +#define R_BCM1480_HSP_RX_HT_RAMALLOC_3 0x0000020090 +#define R_BCM1480_HSP_RX_HT_RAMALLOC_4 0x0000020098 +#define R_BCM1480_HSP_RX_HT_RAMALLOC_5 0x00000200A0 + +#define R_BCM1480_HSP_RX_SPI_WATERMARK_0 0x00000200B0 +#define R_BCM1480_HSP_RX_SPI_WATERMARK_1 0x00000200B8 +#define R_BCM1480_HSP_RX_SPI_WATERMARK_2 0x00000200C0 +#define R_BCM1480_HSP_RX_SPI_WATERMARK_3 0x00000200C8 +#define R_BCM1480_HSP_RX_SPI_WATERMARK_4 0x00000200D0 +#define R_BCM1480_HSP_RX_SPI_WATERMARK_5 0x00000200D8 +#define R_BCM1480_HSP_RX_SPI_WATERMARK_6 0x00000200E0 +#define R_BCM1480_HSP_RX_SPI_WATERMARK_7 0x00000200E8 +#define R_BCM1480_HSP_RX_SPI_WATERMARK(idx) (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx)) + +#define R_BCM1480_HSP_RX_VIS_CMDQ_0 0x00000200F0 +#define R_BCM1480_HSP_RX_VIS_CMDQ_1 0x00000200F8 +#define R_BCM1480_HSP_RX_VIS_CMDQ_2 0x0000020100 +#define R_BCM1480_HSP_RX_RAM_READCTL 0x0000020108 +#define R_BCM1480_HSP_RX_RAM_READWINDOW 0x0000020110 +#define R_BCM1480_HSP_RX_RF_READCTL 0x0000020118 +#define R_BCM1480_HSP_RX_RF_READWINDOW 0x0000020120 + +#define R_BCM1480_HSP_TX_SPI4_CFG_0 0x0000040000 +#define R_BCM1480_HSP_TX_SPI4_CFG_1 0x0000040008 +#define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT 0x0000040010 + +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0 0x0000040020 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1 0x0000040028 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2 0x0000040030 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3 0x0000040038 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4 0x0000040040 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5 0x0000040048 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6 0x0000040050 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7 0x0000040058 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx)) +#define R_BCM1480_HSP_TX_NPC_RAMALLOC 0x0000040078 +#define R_BCM1480_HSP_TX_RSP_RAMALLOC 0x0000040080 +#define R_BCM1480_HSP_TX_PC_RAMALLOC 0x0000040088 +#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0 0x0000040090 +#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1 0x0000040098 +#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2 0x00000400A0 + +#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 0x00000400B0 +#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_1 0x00000400B8 +#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2 0x00000400C0 +#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3 0x00000400C8 +#define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx)) +#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT 0x00000400D0 +#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT 0x00000400D8 + +#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 0x00000400E0 +#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1 0x00000400E8 +#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2 0x00000400F0 +#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3 0x00000400F8 +#define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx)) +#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT 0x0000040100 +#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT 0x0000040108 + +#define R_BCM1480_HSP_TX_SPI4_CALENDAR_0 0x0000040200 +#define R_BCM1480_HSP_TX_SPI4_CALENDAR_1 0x0000040208 + +#define R_BCM1480_HSP_TX_PLL_CNFG 0x0000040800 +#define R_BCM1480_HSP_TX_CALIBRATION 0x0000040808 +#define R_BCM1480_HSP_TX_TEST 0x0000040810 + +#define R_BCM1480_HSP_TX_VIS_CMDQ_0 0x0000040840 +#define R_BCM1480_HSP_TX_VIS_CMDQ_1 0x0000040848 +#define R_BCM1480_HSP_TX_VIS_CMDQ_2 0x0000040850 +#define R_BCM1480_HSP_TX_RAM_READCTL 0x0000040860 +#define R_BCM1480_HSP_TX_RAM_READWINDOW 0x0000040868 +#define R_BCM1480_HSP_TX_RF_READCTL 0x0000040870 +#define R_BCM1480_HSP_TX_RF_READWINDOW 0x0000040878 + +#define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880 +#define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN 0x0000040888 + +#define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400 +#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x) (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x)) + + + +/* ********************************************************************* + * Physical Address Map (Table 10 and Figure 7) + ********************************************************************* */ + +#define A_BCM1480_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) +#define A_BCM1480_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) +#define A_BCM1480_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) +#define A_BCM1480_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) +#define A_BCM1480_PHYS_GENBUS _SB_MAKE64(0x0010090000) +#define A_BCM1480_PHYS_GENBUS_END _SB_MAKE64(0x0028000000) +#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES _SB_MAKE64(0x0028000000) +#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES _SB_MAKE64(0x0029000000) +#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES _SB_MAKE64(0x002C000000) +#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES _SB_MAKE64(0x002E000000) +#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES _SB_MAKE64(0x002F000000) +#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES _SB_MAKE64(0x0030000000) +#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES _SB_MAKE64(0x0040000000) +#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS _SB_MAKE64(0x0060000000) +#define A_BCM1480_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) +#define A_BCM1480_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) +#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS _SB_MAKE64(0x00A8000000) +#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS _SB_MAKE64(0x00A9000000) +#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS _SB_MAKE64(0x00AC000000) +#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS _SB_MAKE64(0x00AE000000) +#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS _SB_MAKE64(0x00AF000000) +#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS _SB_MAKE64(0x00B0000000) +#define A_BCM1480_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) +#define A_BCM1480_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) +#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) +#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) +#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) +#define A_BCM1480_PHYS_HS_SUBSYS _SB_MAKE64(0x00DF000000) +#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) +#define A_BCM1480_PHYS_HT_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) +#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) +#define A_BCM1480_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) +#define A_BCM1480_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) +#define A_BCM1480_PHYS_PCI_UPPER _SB_MAKE64(0x1000000000) +#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES _SB_MAKE64(0x2000000000) +#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS _SB_MAKE64(0x3000000000) +#define A_BCM1480_PHYS_HT_NODE_ALIAS _SB_MAKE64(0x4000000000) +#define A_BCM1480_PHYS_HT_FULLACCESS _SB_MAKE64(0xF000000000) + + +/* ********************************************************************* + * L2 Cache as RAM (Table 54) + ********************************************************************* */ + +#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) +#define BCM1480_PHYS_L2CACHE_NUM_WAYS 8 +#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000100000) +#define A_BCM1480_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0300000) +#define A_BCM1480_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D0320000) +#define A_BCM1480_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D0340000) +#define A_BCM1480_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D0360000) +#define A_BCM1480_PHYS_L2CACHE_WAY4 _SB_MAKE64(0x00D0380000) +#define A_BCM1480_PHYS_L2CACHE_WAY5 _SB_MAKE64(0x00D03A0000) +#define A_BCM1480_PHYS_L2CACHE_WAY6 _SB_MAKE64(0x00D03C0000) +#define A_BCM1480_PHYS_L2CACHE_WAY7 _SB_MAKE64(0x00D03E0000) + +#endif /* _BCM1480_REGS_H */ diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/include/asm-mips/sibyte/bcm1480_scd.h new file mode 100644 index 000000000000..648bed96780f --- /dev/null +++ b/include/asm-mips/sibyte/bcm1480_scd.h @@ -0,0 +1,436 @@ +/* ********************************************************************* + * BCM1280/BCM1400 Board Support Package + * + * SCD Constants and Macros File: bcm1480_scd.h + * + * This module contains constants and macros useful for + * manipulating the System Control and Debug module. + * + * BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03) + * + ********************************************************************* + * + * Copyright 2000,2001,2002,2003 + * Broadcom Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + ********************************************************************* */ + +#ifndef _BCM1480_SCD_H +#define _BCM1480_SCD_H + +#include "sb1250_defs.h" + +/* ********************************************************************* + * Pull in the BCM1250's SCD since lots of stuff is the same. + ********************************************************************* */ + +#include "sb1250_scd.h" + +/* ********************************************************************* + * Some general notes: + * + * This file is basically a "what's new" header file. Since the + * BCM1250 and the new BCM1480 (and derivatives) share many common + * features, this file contains only what's new or changed from + * the 1250. (above, you can see that we include the 1250 symbols + * to get the base functionality). + * + * In software, be sure to use the correct symbols, particularly + * for blocks that are different between the two chip families. + * All BCM1480-specific symbols have _BCM1480_ in their names, + * and all BCM1250-specific and "base" functions that are common in + * both chips have no special names (this is for compatibility with + * older include files). Therefore, if you're working with the + * SCD, which is very different on each chip, A_SCD_xxx implies + * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480 + * version. + ********************************************************************* */ + +/* ********************************************************************* + * System control/debug registers + ********************************************************************* */ + +/* + * System Identification and Revision Register (Table 12) + * Register: SCD_SYSTEM_REVISION + * This register is field compatible with the 1250. + */ + +/* + * New part definitions + */ + +#define K_SYS_PART_BCM1480 0x1406 +#define K_SYS_PART_BCM1280 0x1206 +#define K_SYS_PART_BCM1455 0x1407 +#define K_SYS_PART_BCM1255 0x1257 + +/* + * Manufacturing Information Register (Table 14) + * Register: SCD_SYSTEM_MANUF + */ + +/* + * System Configuration Register (Table 15) + * Register: SCD_SYSTEM_CFG + * Entire register is different from 1250, all new constants below + */ + +#define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0) +#define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1) +#define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2) +#define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3) +#define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4) +#define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) + +#define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) +#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_PLL_DIV) +#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_PLL_DIV) +#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_PLL_DIV,M_BCM1480_SYS_PLL_DIV) + +#define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) +#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_SW_DIV) +#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_SW_DIV) +#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_SW_DIV,M_BCM1480_SYS_SW_DIV) + +#define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) +#define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) + +#define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) +#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2,S_BCM1480_SYS_BOOT_MODE) +#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_BOOT_MODE) +#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_BCM1480_SYS_BOOT_MODE,M_BCM1480_SYS_BOOT_MODE) +#define K_BCM1480_SYS_BOOT_MODE_ROM32 0 +#define K_BCM1480_SYS_BOOT_MODE_ROM8 1 +#define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 +#define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG 3 +#define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19) + +#define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20) +#define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21) +#define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) +#define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23) +#define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24) +#define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) + +#define S_BCM1480_SYS_CONFIG 26 +#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6,S_BCM1480_SYS_CONFIG) +#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_CONFIG) +#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x,S_BCM1480_SYS_CONFIG,M_BCM1480_SYS_CONFIG) + +#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32,15) + +#define S_BCM1480_SYS_NODEID 47 +#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4,S_BCM1480_SYS_NODEID) +#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_NODEID) +#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x,S_BCM1480_SYS_NODEID,M_BCM1480_SYS_NODEID) + +#define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) +#define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) +#define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53) +#define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54) +#define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55) +#define S_BCM1480_SYS_DISABLECPU0 56 +#define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0) +#define S_BCM1480_SYS_DISABLECPU1 57 +#define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1) +#define S_BCM1480_SYS_DISABLECPU2 58 +#define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2) +#define S_BCM1480_SYS_DISABLECPU3 59 +#define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3) + +#define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60) +#define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61) +#define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62) +#define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63) + +/* + * Scratch Register (Table 16) + * Register: SCD_SYSTEM_SCRATCH + * Same as BCM1250 + */ + + +/* + * Mailbox Registers (Table 17) + * Registers: SCD_MBOX_{0,1}_CPU_x + * Same as BCM1250 + */ + + +/* + * See bcm1480_int.h for interrupt mapper registers. + */ + + +/* + * Watchdog Timer Initial Count Registers (Table 23) + * Registers: SCD_WDOG_INIT_CNT_x + * + * The watchdogs are almost the same as the 1250, except + * the configuration register has more bits to control the + * other CPUs. + */ + + +/* + * Watchdog Timer Configuration Registers (Table 25) + * Registers: SCD_WDOG_CFG_x + */ + +#define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) + +#define S_BCM1480_SCD_WDOG_RESET_TYPE 2 +#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5,S_BCM1480_SCD_WDOG_RESET_TYPE) +#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE) +#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE,M_BCM1480_SCD_WDOG_RESET_TYPE) + +#define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ +#define K_BCM1480_SCD_WDOG_RESET_SOFT 1 +#define K_BCM1480_SCD_WDOG_RESET_CPU0 3 +#define K_BCM1480_SCD_WDOG_RESET_CPU1 5 +#define K_BCM1480_SCD_WDOG_RESET_CPU2 9 +#define K_BCM1480_SCD_WDOG_RESET_CPU3 17 +#define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS 31 + + +#define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8) + +/* + * General Timer Initial Count Registers (Table 26) + * Registers: SCD_TIMER_INIT_x + * + * The timer registers are the same as the BCM1250 + */ + + +/* + * ZBbus Count Register (Table 29) + * Register: ZBBUS_CYCLE_COUNT + * + * Same as BCM1250 + */ + +/* + * ZBbus Compare Registers (Table 30) + * Registers: ZBBUS_CYCLE_CPx + * + * Same as BCM1250 + */ + + +/* + * System Performance Counter Configuration Register (Table 31) + * Register: PERF_CNT_CFG_0 + * + * Since the clear/enable bits are moved compared to the + * 1250 and there are more fields, this register will be BCM1480 specific. + */ + +#define S_BCM1480_SPC_CFG_SRC0 0 +#define M_BCM1480_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC0) +#define V_BCM1480_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC0) +#define G_BCM1480_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC0,M_BCM1480_SPC_CFG_SRC0) + +#define S_BCM1480_SPC_CFG_SRC1 8 +#define M_BCM1480_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC1) +#define V_BCM1480_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC1) +#define G_BCM1480_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC1,M_BCM1480_SPC_CFG_SRC1) + +#define S_BCM1480_SPC_CFG_SRC2 16 +#define M_BCM1480_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC2) +#define V_BCM1480_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC2) +#define G_BCM1480_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC2,M_BCM1480_SPC_CFG_SRC2) + +#define S_BCM1480_SPC_CFG_SRC3 24 +#define M_BCM1480_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC3) +#define V_BCM1480_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC3) +#define G_BCM1480_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC3,M_BCM1480_SPC_CFG_SRC3) + +#define S_BCM1480_SPC_CFG_SRC4 32 +#define M_BCM1480_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC4) +#define V_BCM1480_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC4) +#define G_BCM1480_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC4,M_BCM1480_SPC_CFG_SRC4) + +#define S_BCM1480_SPC_CFG_SRC5 40 +#define M_BCM1480_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC5) +#define V_BCM1480_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC5) +#define G_BCM1480_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC5,M_BCM1480_SPC_CFG_SRC5) + +#define S_BCM1480_SPC_CFG_SRC6 48 +#define M_BCM1480_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC6) +#define V_BCM1480_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC6) +#define G_BCM1480_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC6,M_BCM1480_SPC_CFG_SRC6) + +#define S_BCM1480_SPC_CFG_SRC7 56 +#define M_BCM1480_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC7) +#define V_BCM1480_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC7) +#define G_BCM1480_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC7,M_BCM1480_SPC_CFG_SRC7) + +/* + * System Performance Counter Control Register (Table 32) + * Register: PERF_CNT_CFG_1 + * BCM1480 specific + */ + +#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) +#define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) + +/* + * System Performance Counters (Table 33) + * Registers: PERF_CNT_x + */ + +#define S_BCM1480_SPC_CNT_COUNT 0 +#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40,S_BCM1480_SPC_CNT_COUNT) +#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CNT_COUNT) +#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x,S_BCM1480_SPC_CNT_COUNT,M_BCM1480_SPC_CNT_COUNT) + +#define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) + + +/* + * Bus Watcher Error Status Register (Tables 36, 37) + * Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG + * Same as BCM1250. + */ + +/* + * Bus Watcher Error Data Registers (Table 38) + * Registers: BUS_ERR_DATA_x + * Same as BCM1250. + */ + +/* + * Bus Watcher L2 ECC Counter Register (Table 39) + * Register: BUS_L2_ERRORS + * Same as BCM1250. + */ + + +/* + * Bus Watcher Memory and I/O Error Counter Register (Table 40) + * Register: BUS_MEM_IO_ERRORS + * Same as BCM1250. + */ + + +/* + * Address Trap Registers + * + * Register layout same as BCM1250, almost. The bus agents + * are different, and the address trap configuration bits are + * slightly different. + */ + +#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4,0) +#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40,0) + +#define S_BCM1480_ATRAP_CFG_CNT 0 +#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_BCM1480_ATRAP_CFG_CNT) +#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CNT) +#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CNT,M_BCM1480_ATRAP_CFG_CNT) + +#define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) +#define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) +#define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5) +#define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) +#define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) + +#define S_BCM1480_ATRAP_CFG_AGENTID 8 +#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_BCM1480_ATRAP_CFG_AGENTID) +#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID) +#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID,M_BCM1480_ATRAP_CFG_AGENTID) + + +#define K_BCM1480_BUS_AGENT_CPU0 0 +#define K_BCM1480_BUS_AGENT_CPU1 1 +#define K_BCM1480_BUS_AGENT_NC 2 +#define K_BCM1480_BUS_AGENT_IOB 3 +#define K_BCM1480_BUS_AGENT_SCD 4 +#define K_BCM1480_BUS_AGENT_L2C 6 +#define K_BCM1480_BUS_AGENT_MC 7 +#define K_BCM1480_BUS_AGENT_CPU2 8 +#define K_BCM1480_BUS_AGENT_CPU3 9 +#define K_BCM1480_BUS_AGENT_PM 10 + +#define S_BCM1480_ATRAP_CFG_CATTR 12 +#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2,S_BCM1480_ATRAP_CFG_CATTR) +#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CATTR) +#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CATTR,M_BCM1480_ATRAP_CFG_CATTR) + +#define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 +#define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 +#define K_BCM1480_ATRAP_CFG_CATTR_NONCOH 2 +#define K_BCM1480_ATRAP_CFG_CATTR_COHERENT 3 + +#define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14) + + +/* + * Trace Event Registers (Table 47) + * Same as BCM1250. + */ + +/* + * Trace Sequence Control Registers (Table 48) + * Registers: TRACE_SEQUENCE_x + * + * Same as BCM1250 except for two new fields. + */ + + +#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) + +#define S_BCM1480_SCD_TRSEQ_SWFUNC 26 +#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2,S_BCM1480_SCD_TRSEQ_SWFUNC) +#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC) +#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC,M_BCM1480_SCD_TRSEQ_SWFUNC) + +/* + * Trace Control Register (Table 49) + * Register: TRACE_CFG + * + * Bits 0..8 are the same as the BCM1250, rest are different. + * Entire register is redefined below. + */ + +#define M_BCM1480_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) +#define M_BCM1480_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) +#define M_BCM1480_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) +#define M_BCM1480_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) +#define M_BCM1480_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) +#define M_BCM1480_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) +#define M_BCM1480_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) +#define M_BCM1480_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) +#define M_BCM1480_SCD_TRACE_CFG_FORCE_CNT _SB_MAKEMASK1(8) + +#define S_BCM1480_SCD_TRACE_CFG_MODE 16 +#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE) +#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE) +#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE,M_BCM1480_SCD_TRACE_CFG_MODE) + +#define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 +#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 +#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 + +#define S_BCM1480_SCD_TRACE_CFG_CUR_ADDR 24 +#define M_BCM1480_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR) +#define V_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR) +#define G_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR,M_BCM1480_SCD_TRACE_CFG_CUR_ADDR) + +#endif /* _BCM1480_SCD_H */ diff --git a/include/asm-mips/sibyte/bigsur.h b/include/asm-mips/sibyte/bigsur.h new file mode 100644 index 000000000000..ebefe797fc1d --- /dev/null +++ b/include/asm-mips/sibyte/bigsur.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#ifndef __ASM_SIBYTE_BIGSUR_H +#define __ASM_SIBYTE_BIGSUR_H + +#include <asm/sibyte/sb1250.h> +#include <asm/sibyte/bcm1480_int.h> + +#ifdef CONFIG_SIBYTE_BIGSUR +#define SIBYTE_BOARD_NAME "BCM91x80A/B (BigSur)" +#define SIBYTE_HAVE_PCMCIA 1 +#define SIBYTE_HAVE_IDE 1 +#endif + +/* Generic bus chip selects */ +#define LEDS_CS 3 +#define LEDS_PHYS 0x100a0000 + +#ifdef SIBYTE_HAVE_IDE +#define IDE_CS 4 +#define IDE_PHYS 0x100b0000 +#define K_GPIO_GB_IDE 4 +#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) +#endif + +#ifdef SIBYTE_HAVE_PCMCIA +#define PCMCIA_CS 6 +#define PCMCIA_PHYS 0x11000000 +#define K_GPIO_PC_READY 9 +#define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY) +#endif + +#endif /* __ASM_SIBYTE_BIGSUR_H */ + diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h index d7b11b6c7c32..900edcbeec37 100644 --- a/include/asm-mips/sibyte/board.h +++ b/include/asm-mips/sibyte/board.h @@ -21,8 +21,6 @@ #include <linux/config.h> -#ifdef CONFIG_SIBYTE_BOARD - #if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \ defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \ defined(CONFIG_SIBYTE_LITTLESUR) @@ -37,6 +35,10 @@ #include <asm/sibyte/carmel.h> #endif +#ifdef CONFIG_SIBYTE_BIGSUR +#include <asm/sibyte/bigsur.h> +#endif + #ifdef __ASSEMBLY__ #ifdef LEDS_PHYS @@ -54,16 +56,6 @@ #define setleds(t0,t1,c0,c1,c2,c3) #endif /* LEDS_PHYS */ -#else - -#ifdef LEDS_PHYS -extern void setleds(char *str); -#else -#define setleds(s) do { } while (0) -#endif /* LEDS_PHYS */ - #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_SIBYTE_BOARD */ - #endif /* _SIBYTE_BOARD_H */ diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h index d62da4e2dd36..a474c29cd701 100644 --- a/include/asm-mips/sibyte/sb1250.h +++ b/include/asm-mips/sibyte/sb1250.h @@ -27,6 +27,9 @@ #define SB1250_NR_IRQS 64 +#define BCM1480_NR_IRQS 128 +#define BCM1480_NR_IRQS_HALF 64 + #define SB1250_DUART_MINOR_BASE 64 #ifndef __ASSEMBLY__ @@ -35,6 +38,7 @@ /* For revision/pass information */ #include <asm/sibyte/sb1250_scd.h> +#include <asm/sibyte/bcm1480_scd.h> extern unsigned int sb1_pass; extern unsigned int soc_pass; extern unsigned int soc_type; @@ -46,6 +50,13 @@ extern unsigned long sb1250_gettimeoffset(void); extern void sb1250_mask_irq(int cpu, int irq); extern void sb1250_unmask_irq(int cpu, int irq); extern void sb1250_smp_finish(void); + +extern void bcm1480_time_init(void); +extern unsigned long bcm1480_gettimeoffset(void); +extern void bcm1480_mask_irq(int cpu, int irq); +extern void bcm1480_unmask_irq(int cpu, int irq); +extern void bcm1480_smp_finish(void); + extern void prom_printf(char *fmt, ...); #define AT_spin \ @@ -58,6 +69,6 @@ extern void prom_printf(char *fmt, ...); #endif -#define IOADDR(a) (IO_BASE + (a)) +#define IOADDR(a) ((volatile void __iomem *)(IO_BASE + (a))) #endif diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h index 40ef97c76c8b..335dbaf1d831 100644 --- a/include/asm-mips/sibyte/sb1250_defs.h +++ b/include/asm-mips/sibyte/sb1250_defs.h @@ -8,8 +8,6 @@ * * SB1250 specification level: User's manual 1/02/02 * - * Author: Mitch Lichtenberg - * ********************************************************************* * * Copyright 2000,2001,2002,2003 @@ -97,13 +95,17 @@ * ordering, so be careful when adding support for new minor revs. ********************************************************************* */ -#define SIBYTE_HDR_FMASK_1250_ALL 0x00000ff -#define SIBYTE_HDR_FMASK_1250_PASS1 0x0000001 -#define SIBYTE_HDR_FMASK_1250_PASS2 0x0000002 -#define SIBYTE_HDR_FMASK_1250_PASS3 0x0000004 +#define SIBYTE_HDR_FMASK_1250_ALL 0x000000ff +#define SIBYTE_HDR_FMASK_1250_PASS1 0x00000001 +#define SIBYTE_HDR_FMASK_1250_PASS2 0x00000002 +#define SIBYTE_HDR_FMASK_1250_PASS3 0x00000004 + +#define SIBYTE_HDR_FMASK_112x_ALL 0x00000f00 +#define SIBYTE_HDR_FMASK_112x_PASS1 0x00000100 -#define SIBYTE_HDR_FMASK_112x_ALL 0x0000f00 -#define SIBYTE_HDR_FMASK_112x_PASS1 0x0000100 +#define SIBYTE_HDR_FMASK_1480_ALL 0x0000f000 +#define SIBYTE_HDR_FMASK_1480_PASS1 0x00001000 +#define SIBYTE_HDR_FMASK_1480_PASS2 0x00002000 /* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ #define SIBYTE_HDR_FMASK(chip, pass) \ @@ -111,8 +113,17 @@ #define SIBYTE_HDR_FMASK_ALLREVS(chip) \ (SIBYTE_HDR_FMASK_ ## chip ## _ALL) +/* Default constant value for all chips, all revisions */ #define SIBYTE_HDR_FMASK_ALL \ + (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL \ + | SIBYTE_HDR_FMASK_1480_ALL) + +/* This one is used for the "original" BCM1250/BCM112x chips. We use this + to weed out constants and macros that do not exist on later chips like + the BCM1480 */ +#define SIBYTE_HDR_FMASK_1250_112x_ALL \ (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL) +#define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL #ifndef SIBYTE_HDR_FEATURES #define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL @@ -133,6 +144,12 @@ #define SIBYTE_HDR_FEATURE_CHIP(chip) \ (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES)) +/* True for all versions of the BCM1250 and BCM1125, but not true for + anything else */ +#define SIBYTE_HDR_FEATURE_1250_112x \ + (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x)) +/* (!! (SIBYTE_HDR_FEATURES & SIBYHTE_HDR_FMASK_1250_112x)) */ + /* True if header features enabled for that rev or later, inclusive. */ #define SIBYTE_HDR_FEATURE(chip, pass) \ (!! ((SIBYTE_HDR_FMASK(chip, pass) \ diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h index 3cdb48f50ed0..e6145f524fbd 100644 --- a/include/asm-mips/sibyte/sb1250_dma.h +++ b/include/asm-mips/sibyte/sb1250_dma.h @@ -7,9 +7,8 @@ * programming the SB1250's DMA controllers, both the data mover * and the Ethernet DMA. * - * SB1250 specification level: User's manual 1/02/02 - * - * Author: Mitch Lichtenberg + * SB1250 specification level: User's manual 10/21/02 + * BCM1280 specification level: User's manual 11/24/03 * ********************************************************************* * @@ -58,17 +57,17 @@ #define M_DMA_RESERVED1 _SB_MAKEMASK1(2) #define S_DMA_DESC_TYPE _SB_MAKE64(1) -#define M_DMA_DESC_TYPE _SB_MAKE64(2,S_DMA_DESC_TYPE) +#define M_DMA_DESC_TYPE _SB_MAKEMASK(2,S_DMA_DESC_TYPE) #define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE) #define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE) #define K_DMA_DESC_TYPE_RING_AL 0 #define K_DMA_DESC_TYPE_CHAIN_AL 1 -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define K_DMA_DESC_TYPE_RING_UAL_WI 2 #define K_DMA_DESC_TYPE_RING_UAL_RMW 3 -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3) #define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4) @@ -111,11 +110,11 @@ #define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4) #define M_DMA_L2CA _SB_MAKEMASK1(5) -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6) #define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6) #define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define M_DMA_MBZ1 _SB_MAKEMASK(6,15) @@ -165,14 +164,14 @@ #define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) #define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT) -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ /* * Receive Packet Drop Registers */ -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_OODLOST_RX _SB_MAKE64(0) #define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX) #define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX) @@ -180,7 +179,7 @@ #define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) #define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX) #define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ /* ********************************************************************* * DMA Descriptors @@ -201,21 +200,21 @@ #define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) #define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) #define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE) #define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE) #define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE) -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) #define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT) #define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) #define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) @@ -235,12 +234,12 @@ #define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS) #define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS) -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) #define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE) #define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE) #define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) @@ -255,12 +254,12 @@ #define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) #define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB) #define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB) #define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) #define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE) @@ -282,15 +281,16 @@ #define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) #define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -/* Note: BADTCPCS is actually in DSCR_B options field */ +#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) +/* Note: This bit is in the DSCR_B options field */ #define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) -#endif /* 1250 PASS2 || 112x PASS1 */ +#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) +/* Note: These bits are in the DSCR_B options field */ #define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1) #define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_DMA_ETHRX_RXCH 53 #define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH) @@ -438,7 +438,7 @@ M_DM_CUR_DSCR_DSCR_COUNT) -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) /* * Data Mover Channel Partial Result Registers * Register: DM_PARTIAL_0 @@ -459,10 +459,10 @@ M_DM_PARTIAL_TCPCS_PARTIAL) #define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) /* * Data Mover CRC Definition Registers * Register: CRC_DEF_0 @@ -479,10 +479,10 @@ #define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY) #define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\ M_CRC_DEF_CRC_POLY) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) /* * Data Mover CRC/Checksum Definition Registers * Register: CTCP_DEF_0 @@ -511,7 +511,7 @@ #define K_CTCP_DEF_CRC_WIDTH_1 2 #define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ /* @@ -560,12 +560,12 @@ #define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50) #define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52) #define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53) -#endif /* 1250 PASS2 || 112x PASS1 */ +#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54) #define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55) #define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56) @@ -574,7 +574,7 @@ #define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59) #define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60) #define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61) diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h index f1f509f295c4..1b5cbc5c6454 100644 --- a/include/asm-mips/sibyte/sb1250_genbus.h +++ b/include/asm-mips/sibyte/sb1250_genbus.h @@ -6,9 +6,8 @@ * This module contains constants and macros useful for * manipulating the SB1250's Generic Bus interface * - * SB1250 specification level: User's manual 1/02/02 - * - * Author: Mitch Lichtenberg + * SB1250 specification level: User's manual 10/21/02 + * BCM1280 specification level: User's Manual 11/14/03 * ********************************************************************* * @@ -51,19 +50,21 @@ #define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) #define K_IO_WIDTH_SEL_1 0 #define K_IO_WIDTH_SEL_2 1 -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ + || SIBYTE_HDR_FEATURE_CHIP(1480) #define K_IO_WIDTH_SEL_1L 2 -#endif /* 1250 PASS2 || 112x PASS1 */ +#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define K_IO_WIDTH_SEL_4 3 #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) #define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) #define S_IO_PARITY_ENA 4 #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ + || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_IO_BURST_EN 5 #define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN) -#endif /* 1250 PASS2 || 112x PASS1 */ +#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_PARITY_ODD 6 #define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD) #define S_IO_NONMUX 7 @@ -96,8 +97,11 @@ #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ +#define M_IO_BLK_CACHE _SB_MAKEMASK1(15) + + /* - * Generic Bus Region 0 Timing Registers (Table 11-7) + * Generic Bus Timing 0 Registers (Table 11-7) */ #define S_IO_ALE_WIDTH 0 @@ -105,21 +109,23 @@ #define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) #define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ + || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_IO_EARLY_CS _SB_MAKEMASK1(3) -#endif /* 1250 PASS2 || 112x PASS1 */ +#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_ALE_TO_CS 4 #define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) #define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) #define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ + || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_IO_BURST_WIDTH _SB_MAKE64(6) #define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) #define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) #define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) -#endif /* 1250 PASS2 || 112x PASS1 */ +#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_CS_WIDTH 8 #define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) @@ -141,9 +147,10 @@ #define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) #define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ + || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_IO_RDY_SYNC _SB_MAKEMASK1(3) -#endif /* 1250 PASS2 || 112x PASS1 */ +#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_WRITE_WIDTH 4 #define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) @@ -183,9 +190,127 @@ #define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10) #define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11) #define M_IO_MULT_CS_INT _SB_MAKEMASK1(12) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_IO_COH_ERR _SB_MAKEMASK1(14) -#endif /* 1250 PASS2 || 112x PASS1 */ +#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ + + +/* + * Generic Bus Output Drive Control Register 0 (Table 14-18) + */ + +#define S_IO_SLEW0 0 +#define M_IO_SLEW0 _SB_MAKEMASK(2,S_IO_SLEW0) +#define V_IO_SLEW0(x) _SB_MAKEVALUE(x,S_IO_SLEW0) +#define G_IO_SLEW0(x) _SB_GETVALUE(x,S_IO_SLEW0,M_IO_SLEW0) + +#define S_IO_DRV_A 2 +#define M_IO_DRV_A _SB_MAKEMASK(2,S_IO_DRV_A) +#define V_IO_DRV_A(x) _SB_MAKEVALUE(x,S_IO_DRV_A) +#define G_IO_DRV_A(x) _SB_GETVALUE(x,S_IO_DRV_A,M_IO_DRV_A) + +#define S_IO_DRV_B 6 +#define M_IO_DRV_B _SB_MAKEMASK(2,S_IO_DRV_B) +#define V_IO_DRV_B(x) _SB_MAKEVALUE(x,S_IO_DRV_B) +#define G_IO_DRV_B(x) _SB_GETVALUE(x,S_IO_DRV_B,M_IO_DRV_B) + +#define S_IO_DRV_C 10 +#define M_IO_DRV_C _SB_MAKEMASK(2,S_IO_DRV_C) +#define V_IO_DRV_C(x) _SB_MAKEVALUE(x,S_IO_DRV_C) +#define G_IO_DRV_C(x) _SB_GETVALUE(x,S_IO_DRV_C,M_IO_DRV_C) + +#define S_IO_DRV_D 14 +#define M_IO_DRV_D _SB_MAKEMASK(2,S_IO_DRV_D) +#define V_IO_DRV_D(x) _SB_MAKEVALUE(x,S_IO_DRV_D) +#define G_IO_DRV_D(x) _SB_GETVALUE(x,S_IO_DRV_D,M_IO_DRV_D) + +/* + * Generic Bus Output Drive Control Register 1 (Table 14-19) + */ + +#define S_IO_DRV_E 2 +#define M_IO_DRV_E _SB_MAKEMASK(2,S_IO_DRV_E) +#define V_IO_DRV_E(x) _SB_MAKEVALUE(x,S_IO_DRV_E) +#define G_IO_DRV_E(x) _SB_GETVALUE(x,S_IO_DRV_E,M_IO_DRV_E) + +#define S_IO_DRV_F 6 +#define M_IO_DRV_F _SB_MAKEMASK(2,S_IO_DRV_F) +#define V_IO_DRV_F(x) _SB_MAKEVALUE(x,S_IO_DRV_F) +#define G_IO_DRV_F(x) _SB_GETVALUE(x,S_IO_DRV_F,M_IO_DRV_F) + +#define S_IO_SLEW1 8 +#define M_IO_SLEW1 _SB_MAKEMASK(2,S_IO_SLEW1) +#define V_IO_SLEW1(x) _SB_MAKEVALUE(x,S_IO_SLEW1) +#define G_IO_SLEW1(x) _SB_GETVALUE(x,S_IO_SLEW1,M_IO_SLEW1) + +#define S_IO_DRV_G 10 +#define M_IO_DRV_G _SB_MAKEMASK(2,S_IO_DRV_G) +#define V_IO_DRV_G(x) _SB_MAKEVALUE(x,S_IO_DRV_G) +#define G_IO_DRV_G(x) _SB_GETVALUE(x,S_IO_DRV_G,M_IO_DRV_G) + +#define S_IO_SLEW2 12 +#define M_IO_SLEW2 _SB_MAKEMASK(2,S_IO_SLEW2) +#define V_IO_SLEW2(x) _SB_MAKEVALUE(x,S_IO_SLEW2) +#define G_IO_SLEW2(x) _SB_GETVALUE(x,S_IO_SLEW2,M_IO_SLEW2) + +#define S_IO_DRV_H 14 +#define M_IO_DRV_H _SB_MAKEMASK(2,S_IO_DRV_H) +#define V_IO_DRV_H(x) _SB_MAKEVALUE(x,S_IO_DRV_H) +#define G_IO_DRV_H(x) _SB_GETVALUE(x,S_IO_DRV_H,M_IO_DRV_H) + +/* + * Generic Bus Output Drive Control Register 2 (Table 14-20) + */ + +#define S_IO_DRV_J 2 +#define M_IO_DRV_J _SB_MAKEMASK(2,S_IO_DRV_J) +#define V_IO_DRV_J(x) _SB_MAKEVALUE(x,S_IO_DRV_J) +#define G_IO_DRV_J(x) _SB_GETVALUE(x,S_IO_DRV_J,M_IO_DRV_J) + +#define S_IO_DRV_K 6 +#define M_IO_DRV_K _SB_MAKEMASK(2,S_IO_DRV_K) +#define V_IO_DRV_K(x) _SB_MAKEVALUE(x,S_IO_DRV_K) +#define G_IO_DRV_K(x) _SB_GETVALUE(x,S_IO_DRV_K,M_IO_DRV_K) + +#define S_IO_DRV_L 10 +#define M_IO_DRV_L _SB_MAKEMASK(2,S_IO_DRV_L) +#define V_IO_DRV_L(x) _SB_MAKEVALUE(x,S_IO_DRV_L) +#define G_IO_DRV_L(x) _SB_GETVALUE(x,S_IO_DRV_L,M_IO_DRV_L) + +#define S_IO_DRV_M 14 +#define M_IO_DRV_M _SB_MAKEMASK(2,S_IO_DRV_M) +#define V_IO_DRV_M(x) _SB_MAKEVALUE(x,S_IO_DRV_M) +#define G_IO_DRV_M(x) _SB_GETVALUE(x,S_IO_DRV_M,M_IO_DRV_M) + +/* + * Generic Bus Output Drive Control Register 3 (Table 14-21) + */ + +#define S_IO_SLEW3 0 +#define M_IO_SLEW3 _SB_MAKEMASK(2,S_IO_SLEW3) +#define V_IO_SLEW3(x) _SB_MAKEVALUE(x,S_IO_SLEW3) +#define G_IO_SLEW3(x) _SB_GETVALUE(x,S_IO_SLEW3,M_IO_SLEW3) + +#define S_IO_DRV_N 2 +#define M_IO_DRV_N _SB_MAKEMASK(2,S_IO_DRV_N) +#define V_IO_DRV_N(x) _SB_MAKEVALUE(x,S_IO_DRV_N) +#define G_IO_DRV_N(x) _SB_GETVALUE(x,S_IO_DRV_N,M_IO_DRV_N) + +#define S_IO_DRV_P 6 +#define M_IO_DRV_P _SB_MAKEMASK(2,S_IO_DRV_P) +#define V_IO_DRV_P(x) _SB_MAKEVALUE(x,S_IO_DRV_P) +#define G_IO_DRV_P(x) _SB_GETVALUE(x,S_IO_DRV_P,M_IO_DRV_P) + +#define S_IO_DRV_Q 10 +#define M_IO_DRV_Q _SB_MAKEMASK(2,S_IO_DRV_Q) +#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x,S_IO_DRV_Q) +#define G_IO_DRV_Q(x) _SB_GETVALUE(x,S_IO_DRV_Q,M_IO_DRV_Q) + +#define S_IO_DRV_R 14 +#define M_IO_DRV_R _SB_MAKEMASK(2,S_IO_DRV_R) +#define V_IO_DRV_R(x) _SB_MAKEVALUE(x,S_IO_DRV_R) +#define G_IO_DRV_R(x) _SB_GETVALUE(x,S_IO_DRV_R,M_IO_DRV_R) + /* * PCMCIA configuration register (Table 12-6) @@ -202,6 +327,22 @@ #define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8) #define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9) +#if SIBYTE_HDR_FEATURE_CHIP(1480) +#define S_PCMCIA_MODE 16 +#define M_PCMCIA_MODE _SB_MAKEMASK(3,S_PCMCIA_MODE) +#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x,S_PCMCIA_MODE) +#define G_PCMCIA_MODE(x) _SB_GETVALUE(x,S_PCMCIA_MODE,M_PCMCIA_MODE) + +#define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */ +#define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */ +#define K_PCMCIA_MODE_PCMIOA_NOB 2 /* PCMCIA with I/O "A", no "B" */ +#define K_PCMCIA_MODE_PCMA_PCMB 4 /* standard PCMCIA "A", standard PCMCIA "B" */ +#define K_PCMCIA_MODE_IDEA_PCMB 5 /* IDE "A", standard PCMCIA "B" */ +#define K_PCMCIA_MODE_PCMA_IDEB 6 /* standard PCMCIA "A", IDE "B" */ +#define K_PCMCIA_MODE_IDEA_IDEB 7 /* IDE "A", IDE "B" */ +#endif + + /* * PCMCIA status register (Table 12-7) */ @@ -272,5 +413,62 @@ #define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) #define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) +#if SIBYTE_HDR_FEATURE_CHIP(1480) + +/* + * GPIO Interrupt Additional Type Register + */ + +#define K_GPIO_INTR_BOTHEDGE 0 +#define K_GPIO_INTR_RISEEDGE 1 +#define K_GPIO_INTR_UNPRED1 2 +#define K_GPIO_INTR_UNPRED2 3 + +#define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2) +#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_ATYPEX(n)) +#define V_GPIO_INTR_ATYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPEX(n)) +#define G_GPIO_INTR_ATYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPEX(n),M_GPIO_INTR_ATYPEX(n)) + +#define S_GPIO_INTR_ATYPE0 0 +#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE0) +#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE0) +#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE0,M_GPIO_INTR_ATYPE0) + +#define S_GPIO_INTR_ATYPE2 2 +#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE2) +#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE2) +#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE2,M_GPIO_INTR_ATYPE2) + +#define S_GPIO_INTR_ATYPE4 4 +#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE4) +#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE4) +#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE4,M_GPIO_INTR_ATYPE4) + +#define S_GPIO_INTR_ATYPE6 6 +#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE6) +#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE6) +#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE6,M_GPIO_INTR_ATYPE6) + +#define S_GPIO_INTR_ATYPE8 8 +#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE8) +#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE8) +#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE8,M_GPIO_INTR_ATYPE8) + +#define S_GPIO_INTR_ATYPE10 10 +#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE10) +#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE10) +#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE10,M_GPIO_INTR_ATYPE10) + +#define S_GPIO_INTR_ATYPE12 12 +#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE12) +#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE12) +#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE12,M_GPIO_INTR_ATYPE12) + +#define S_GPIO_INTR_ATYPE14 14 +#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE14) +#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE14) +#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE14,M_GPIO_INTR_ATYPE14) +#endif + #endif diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h index e173e2ea4c98..05c7b39f1b02 100644 --- a/include/asm-mips/sibyte/sb1250_int.h +++ b/include/asm-mips/sibyte/sb1250_int.h @@ -8,8 +8,6 @@ * * SB1250 specification level: User's manual 1/02/02 * - * Author: Mitch Lichtenberg - * ********************************************************************* * * Copyright 2000,2001,2002,2003 @@ -47,6 +45,10 @@ * First, the interrupt numbers. */ +#if SIBYTE_HDR_FEATURE_1250_112x + +#define K_INT_SOURCES 64 + #define K_INT_WATCHDOG_TIMER_0 0 #define K_INT_WATCHDOG_TIMER_1 1 #define K_INT_TIMER_0 2 @@ -244,4 +246,6 @@ #define M_LDTVECT_RAISEMBOX 0x40 +#endif /* 1250/112x */ + #endif diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h index 8afe8e01581b..842f205094af 100644 --- a/include/asm-mips/sibyte/sb1250_l2c.h +++ b/include/asm-mips/sibyte/sb1250_l2c.h @@ -8,8 +8,6 @@ * * SB1250 specification level: User's manual 1/02/02 * - * Author: Mitch Lichtenberg - * ********************************************************************* * * Copyright 2000,2001,2002,2003 @@ -89,8 +87,13 @@ #define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY) #define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY) -#define S_L2C_MGMT_TAG 21 -#define M_L2C_MGMT_TAG _SB_MAKEMASK(6,S_L2C_MGMT_TAG) +#define S_L2C_MGMT_ECC_DIAG 21 +#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_L2C_MGMT_ECC_DIAG) +#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_ECC_DIAG) +#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_L2C_MGMT_ECC_DIAG,M_L2C_MGMT_ECC_DIAG) + +#define S_L2C_MGMT_TAG 23 +#define M_L2C_MGMT_TAG _SB_MAKEMASK(4,S_L2C_MGMT_TAG) #define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG) #define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG) diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h index f2617ded0a8f..7092535d1108 100644 --- a/include/asm-mips/sibyte/sb1250_ldt.h +++ b/include/asm-mips/sibyte/sb1250_ldt.h @@ -8,8 +8,6 @@ * * SB1250 specification level: User's manual 1/02/02 * - * Author: Mitch Lichtenberg - * ********************************************************************* * * Copyright 2000,2001,2002,2003 diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h index 18e74e43f4a2..adfc688fa559 100644 --- a/include/asm-mips/sibyte/sb1250_mac.h +++ b/include/asm-mips/sibyte/sb1250_mac.h @@ -8,8 +8,6 @@ * * SB1250 specification level: User's manual 1/02/02 * - * Author: Mitch Lichtenberg - * ********************************************************************* * * Copyright 2000,2001,2002,2003 @@ -81,7 +79,10 @@ #define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) #define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) -#define M_MAC_RESERVED2 _SB_MAKEMASK1(18) + +#if SIBYTE_HDR_FEATURE_CHIP(1480) +#define M_MAC_TIMESTAMP _SB_MAKEMASK1(18) +#endif #define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) #define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) #define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) @@ -132,9 +133,9 @@ #define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) #endif /* 1250 PASS2 || 112x PASS1 */ -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_MAC_BYPASS_IFG _SB_MAKE64(46) #define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) @@ -176,10 +177,22 @@ #define M_MAC_PORT_RESET _SB_MAKEMASK1(8) +#if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x)) #define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) #define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) #define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) #define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) +#endif + +/* + * MAC reset information register (1280/1255) + */ +#if SIBYTE_HDR_FEATURE_CHIP(1480) +#define M_MAC_RX_CH0_PAUSE_ON _SB_MAKEMASK1(8) +#define M_MAC_RX_CH1_PAUSE_ON _SB_MAKEMASK1(16) +#define M_MAC_TX_CH0_PAUSE_ON _SB_MAKEMASK1(24) +#define M_MAC_TX_CH1_PAUSE_ON _SB_MAKEMASK1(32) +#endif /* * MAC DMA Control Register @@ -267,12 +280,12 @@ #define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) #define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_MAC_PRE_LEN _SB_MAKE64(0) #define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN) #define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN) #define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_MAC_IFG_TX _SB_MAKE64(6) #define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) @@ -458,9 +471,9 @@ #define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) #define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ /* * MAC Fifo Pointer Registers (Table 9-19) [Debug register] @@ -594,7 +607,7 @@ #define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) #define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) #define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET) #define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET) @@ -612,7 +625,7 @@ #define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL) #define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL) #define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL) -#endif /* 1250 PASS3 || 112x PASS1 */ +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ /* * MAC Receive Channel Select Registers (Table 9-25) diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h index 1dd41c927996..26e421498c97 100644 --- a/include/asm-mips/sibyte/sb1250_mc.h +++ b/include/asm-mips/sibyte/sb1250_mc.h @@ -8,8 +8,6 @@ * * SB1250 specification level: User's manual 1/02/02 * - * Author: Mitch Lichtenberg - * ********************************************************************* * * Copyright 2000,2001,2002,2003 @@ -324,6 +322,10 @@ #define K_MC_tRFC_DEFAULT 12 #define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) +#if SIBYTE_HDR_FEATURE(1250, PASS3) +#define M_MC_tRFC_PLUS16 _SB_MAKEMASK1(51) /* 1250C3 and later. */ +#endif + #define S_MC_tCwCr 40 #define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr) #define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr) diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h index 9db80cd13a79..bab3a4580a36 100644 --- a/include/asm-mips/sibyte/sb1250_regs.h +++ b/include/asm-mips/sibyte/sb1250_regs.h @@ -8,8 +8,6 @@ * * SB1250 specification level: 01/02/2002 * - * Author: Mitch Lichtenberg - * ********************************************************************* * * Copyright 2000,2001,2002,2003 @@ -61,6 +59,8 @@ * XXX: can't remove MC base 0 if 112x, since it's used by other macros, * since there is one reg there (but it could get its addr/offset constant). */ + +#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ #define A_MC_BASE_0 0x0010051000 #define A_MC_BASE_1 0x0010052000 #define MC_REGISTER_SPACING 0x1000 @@ -101,10 +101,14 @@ #define R_MC_TEST_ECC 0x0000000420 #define R_MC_MCLK_CFG 0x0000000500 +#endif /* 1250 & 112x */ + /* ********************************************************************* * L2 Cache Control Registers ********************************************************************* */ +#if SIBYTE_HDR_FEATURE_1250_112x /* This L2C only on 1250/112x */ + #define A_L2_READ_TAG 0x0010040018 #define A_L2_ECC_TAG 0x0010040038 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) @@ -125,13 +129,16 @@ #define A_L2_READ_ADDRESS A_L2_READ_TAG #define A_L2_EEC_ADDRESS A_L2_ECC_TAG +#endif /* ********************************************************************* * PCI Interface Registers ********************************************************************* */ +#if SIBYTE_HDR_FEATURE_1250_112x /* This PCI/HT only on 1250/112x */ #define A_PCI_TYPE00_HEADER 0x00DE000000 #define A_PCI_TYPE01_HEADER 0x00DE000800 +#endif /* ********************************************************************* @@ -264,15 +271,15 @@ ********************************************************************* */ +#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ #define R_DUART_NUM_PORTS 2 #define A_DUART 0x0010060000 -#define A_DUART_REG(r) - #define DUART_CHANREG_SPACING 0x100 #define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg)) #define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg)) +#endif /* 1250 & 112x */ #define R_DUART_MODE_REG_1 0x100 #define R_DUART_MODE_REG_2 0x110 @@ -307,11 +314,13 @@ #define DUART_IMRISR_SPACING 0x20 +#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ #define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING) #define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING) #define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan)) #define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan)) +#endif /* 1250 & 112x */ @@ -368,6 +377,8 @@ ********************************************************************* */ +#if SIBYTE_HDR_FEATURE_1250_112x /* sync serial only on 1250/112x */ + #define A_SER_BASE_0 0x0010060400 #define A_SER_BASE_1 0x0010060800 #define SER_SPACING 0x400 @@ -457,6 +468,8 @@ #define R_SER_RMON_RX_ERRORS 0x000001F0 #define R_SER_RMON_RX_BADADDR 0x000001F8 +#endif /* 1250/112x */ + /* ********************************************************************* * Generic Bus Registers ********************************************************************* */ @@ -634,12 +647,13 @@ #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) #define A_SCD_SCRATCH 0x0010020C10 +#endif /* 1250 PASS2 || 112x PASS1 */ +#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 #define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 #define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 -#endif /* 1250 PASS2 || 112x PASS1 */ - +#endif /* ********************************************************************* * System Control Registers @@ -667,15 +681,16 @@ #define A_ADDR_TRAP_CFG_1 0x0010020448 #define A_ADDR_TRAP_CFG_2 0x0010020450 #define A_ADDR_TRAP_CFG_3 0x0010020458 -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define A_ADDR_TRAP_REG_DEBUG 0x0010020460 -#endif /* 1250 PASS2 || 112x PASS1 */ +#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ /* ********************************************************************* * System Interrupt Mapper Registers ********************************************************************* */ +#if SIBYTE_HDR_FEATURE_1250_112x #define A_IMR_CPU0_BASE 0x0010020000 #define A_IMR_CPU1_BASE 0x0010022000 #define IMR_REGISTER_SPACING 0x2000 @@ -700,6 +715,7 @@ #define R_IMR_INTERRUPT_STATUS_COUNT 7 #define R_IMR_INTERRUPT_MAP_BASE 0x0200 #define R_IMR_INTERRUPT_MAP_COUNT 64 +#endif /* 1250/112x */ /* ********************************************************************* * System Performance Counter Registers @@ -718,6 +734,7 @@ #define A_SCD_BUS_ERR_STATUS 0x0010020880 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) #define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 +#define A_BUS_ERR_STATUS_DEBUG 0x00100208D0 #endif /* 1250 PASS2 || 112x PASS1 */ #define A_BUS_ERR_DATA_0 0x00100208A0 #define A_BUS_ERR_DATA_1 0x00100208A8 @@ -798,6 +815,7 @@ * Physical Address Map ********************************************************************* */ +#if SIBYTE_HDR_FEATURE_1250_112x #define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) #define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) #define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) @@ -831,6 +849,7 @@ #define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) #define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) #define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) +#endif #endif diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h index dbbd682fb47e..a667bc14a7cd 100644 --- a/include/asm-mips/sibyte/sb1250_scd.h +++ b/include/asm-mips/sibyte/sb1250_scd.h @@ -8,8 +8,6 @@ * * SB1250 specification level: User's manual 1/02/02 * - * Author: Mitch Lichtenberg - * ********************************************************************* * * Copyright 2000,2001,2002,2003 @@ -51,26 +49,70 @@ #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) -#if SIBYTE_HDR_FEATURE_CHIP(1250) -#define K_SYS_REVISION_BCM1250_PASS1 1 -#define K_SYS_REVISION_BCM1250_PASS2 3 -#define K_SYS_REVISION_BCM1250_A10 11 -#define K_SYS_REVISION_BCM1250_PASS2_2 16 -#define K_SYS_REVISION_BCM1250_B2 17 -#define K_SYS_REVISION_BCM1250_PASS3 32 -#define K_SYS_REVISION_BCM1250_C1 33 +#define K_SYS_REVISION_BCM1250_PASS1 0x01 + +#define K_SYS_REVISION_BCM1250_PASS2 0x03 +#define K_SYS_REVISION_BCM1250_A1 0x03 /* Pass 2.0 WB */ +#define K_SYS_REVISION_BCM1250_A2 0x04 /* Pass 2.0 FC */ +#define K_SYS_REVISION_BCM1250_A3 0x05 /* Pass 2.1 FC */ +#define K_SYS_REVISION_BCM1250_A4 0x06 /* Pass 2.1 WB */ +#define K_SYS_REVISION_BCM1250_A6 0x07 /* OR 0x04 (A2) w/WID != 0 */ +#define K_SYS_REVISION_BCM1250_A8 0x0b /* A8/A10 */ +#define K_SYS_REVISION_BCM1250_A9 0x08 +#define K_SYS_REVISION_BCM1250_A10 K_SYS_REVISION_BCM1250_A8 +#define K_SYS_REVISION_BCM1250_PASS2_2 0x10 +#define K_SYS_REVISION_BCM1250_B0 K_SYS_REVISION_BCM1250_B1 +#define K_SYS_REVISION_BCM1250_B1 0x10 +#define K_SYS_REVISION_BCM1250_B2 0x11 + +#define K_SYS_REVISION_BCM1250_C0 0x20 +#define K_SYS_REVISION_BCM1250_C1 0x21 +#define K_SYS_REVISION_BCM1250_C2 0x22 +#define K_SYS_REVISION_BCM1250_C3 0x23 + +#if SIBYTE_HDR_FEATURE_CHIP(1250) /* XXX: discourage people from using these constants. */ #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 +#define K_SYS_REVISION_BCM1250_PASS3 K_SYS_REVISION_BCM1250_C0 #endif /* 1250 */ -#if SIBYTE_HDR_FEATURE_CHIP(112x) -#define K_SYS_REVISION_BCM112x_A1 32 -#define K_SYS_REVISION_BCM112x_A2 33 -#endif /* 112x */ +#define K_SYS_REVISION_BCM112x_A1 0x20 +#define K_SYS_REVISION_BCM112x_A2 0x21 +#define K_SYS_REVISION_BCM112x_A3 0x22 +#define K_SYS_REVISION_BCM112x_A4 0x23 + +#define K_SYS_REVISION_BCM1480_S0 0x01 +#define K_SYS_REVISION_BCM1480_A1 0x02 +#define K_SYS_REVISION_BCM1480_A2 0x03 +#define K_SYS_REVISION_BCM1480_A3 0x04 +#define K_SYS_REVISION_BCM1480_B0 0x11 + +/*Cache size - 23:20 of revision register*/ +#define S_SYS_L2C_SIZE _SB_MAKE64(20) +#define M_SYS_L2C_SIZE _SB_MAKEMASK(4,S_SYS_L2C_SIZE) +#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x,S_SYS_L2C_SIZE) +#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x,S_SYS_L2C_SIZE,M_SYS_L2C_SIZE) + +#define K_SYS_L2C_SIZE_1MB 0 +#define K_SYS_L2C_SIZE_512KB 5 +#define K_SYS_L2C_SIZE_256KB 2 +#define K_SYS_L2C_SIZE_128KB 1 + +#define K_SYS_L2C_SIZE_BCM1250 K_SYS_L2C_SIZE_512KB +#define K_SYS_L2C_SIZE_BCM1125 K_SYS_L2C_SIZE_256KB +#define K_SYS_L2C_SIZE_BCM1122 K_SYS_L2C_SIZE_128KB + + +/* Number of CPU cores, bits 27:24 of revision register*/ +#define S_SYS_NUM_CPUS _SB_MAKE64(24) +#define M_SYS_NUM_CPUS _SB_MAKEMASK(4,S_SYS_NUM_CPUS) +#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x,S_SYS_NUM_CPUS) +#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x,S_SYS_NUM_CPUS,M_SYS_NUM_CPUS) + /* XXX: discourage people from using these constants. */ #define S_SYS_PART _SB_MAKE64(16) @@ -83,6 +125,8 @@ #define K_SYS_PART_BCM1120 0x1121 #define K_SYS_PART_BCM1125 0x1123 #define K_SYS_PART_BCM1125H 0x1124 +#define K_SYS_PART_BCM1122 0x1113 + /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ #define S_SYS_SOC_TYPE _SB_MAKE64(16) @@ -96,6 +140,8 @@ #define K_SYS_SOC_TYPE_BCM1125 0x3 #define K_SYS_SOC_TYPE_BCM1125H 0x4 #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ +#define K_SYS_SOC_TYPE_BCM1x80 0x6 +#define K_SYS_SOC_TYPE_BCM1x55 0x7 /* * Calculate correct SOC type given a copy of system revision register. @@ -127,10 +173,12 @@ #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) -/* System Manufacturing Register -* Register: SCD_SYSTEM_MANUF -*/ +/* + * System Manufacturing Register + * Register: SCD_SYSTEM_MANUF + */ +#if SIBYTE_HDR_FEATURE_1250_112x /* Wafer ID: bits 31:0 */ #define S_SYS_WAFERID1_200 _SB_MAKE64(0) #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) @@ -139,8 +187,8 @@ #define S_SYS_BIN _SB_MAKE64(32) #define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) -#define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN) -#define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) +#define V_SYS_BIN(x) _SB_MAKEVALUE(x,S_SYS_BIN) +#define G_SYS_BIN(x) _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) /* Wafer ID: bits 39:36 */ #define S_SYS_WAFERID2_200 _SB_MAKE64(36) @@ -163,12 +211,14 @@ #define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) #define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) #define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) +#endif /* * System Config Register (Table 4-2) * Register: SCD_SYSTEM_CFG */ +#if SIBYTE_HDR_FEATURE_1250_112x #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) @@ -253,6 +303,8 @@ #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) #endif /* 1250 PASS2 || 112x PASS1 */ +#endif + /* * Mailbox Registers (Table 4-3) @@ -326,6 +378,7 @@ * System Performance Counters */ +#if SIBYTE_HDR_FEATURE_1250_112x #define S_SPC_CFG_SRC0 0 #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) @@ -348,6 +401,7 @@ #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) +#endif /* @@ -412,6 +466,7 @@ * Address Trap Registers */ +#if SIBYTE_HDR_FEATURE_1250_112x #define M_ATRAP_INDEX _SB_MAKEMASK(4,0) #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) @@ -436,7 +491,6 @@ #define K_BUS_AGENT_IOB0 2 #define K_BUS_AGENT_IOB1 3 #define K_BUS_AGENT_SCD 4 -#define K_BUS_AGENT_RESERVED 5 #define K_BUS_AGENT_L2C 6 #define K_BUS_AGENT_MC 7 @@ -454,10 +508,14 @@ #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 +#endif /* 1250/112x */ + /* * Trace Buffer Config register */ +#if SIBYTE_HDR_FEATURE_1250_112x + #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) @@ -475,6 +533,8 @@ #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) +#endif /* 1250/112x */ + /* * Trace Event registers */ @@ -578,5 +638,7 @@ #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) +#define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23) +#define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24) #endif diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h index 335c53e92936..279a912213cd 100644 --- a/include/asm-mips/sibyte/sb1250_smbus.h +++ b/include/asm-mips/sibyte/sb1250_smbus.h @@ -6,9 +6,8 @@ * This module contains constants and macros useful for * manipulating the SB1250's SMbus devices. * - * SB1250 specification level: 01/02/2002 - * - * Author: Mitch Lichtenberg + * SB1250 specification level: 10/21/02 + * BCM1280 specification level: 11/24/03 * ********************************************************************* * @@ -47,6 +46,7 @@ #define K_SMB_FREQ_400KHZ 0x1F #define K_SMB_FREQ_100KHZ 0x7D +#define K_SMB_FREQ_10KHZ 1250 #define S_SMB_CMD 0 #define M_SMB_CMD _SB_MAKEMASK(8,S_SMB_CMD) @@ -58,7 +58,11 @@ #define M_SMB_ERR_INTR _SB_MAKEMASK1(0) #define M_SMB_FINISH_INTR _SB_MAKEMASK1(1) -#define M_SMB_DATA_OUT _SB_MAKEMASK1(4) + +#define S_SMB_DATA_OUT 4 +#define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT) +#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x,S_SMB_DATA_OUT) + #define M_SMB_DATA_DIR _SB_MAKEMASK1(5) #define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR #define M_SMB_CLK_OUT _SB_MAKEMASK1(6) @@ -71,8 +75,23 @@ #define M_SMB_BUSY _SB_MAKEMASK1(0) #define M_SMB_ERROR _SB_MAKEMASK1(1) #define M_SMB_ERROR_TYPE _SB_MAKEMASK1(2) -#define M_SMB_REF _SB_MAKEMASK1(6) -#define M_SMB_DATA_IN _SB_MAKEMASK1(7) + +#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) +#define S_SMB_SCL_IN 5 +#define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN) +#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x,S_SMB_SCL_IN) +#define G_SMB_SCL_IN(x) _SB_GETVALUE(x,S_SMB_SCL_IN,M_SMB_SCL_IN) +#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ + +#define S_SMB_REF 6 +#define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF) +#define V_SMB_REF(x) _SB_MAKEVALUE(x,S_SMB_REF) +#define G_SMB_REF(x) _SB_GETVALUE(x,S_SMB_REF,M_SMB_REF) + +#define S_SMB_DATA_IN 7 +#define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN) +#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x,S_SMB_DATA_IN) +#define G_SMB_DATA_IN(x) _SB_GETVALUE(x,S_SMB_DATA_IN,M_SMB_DATA_IN) /* * SMBus Start/Command registers (Table 14-9) @@ -132,16 +151,14 @@ #define V_SPEC_MB(x) _SB_MAKEVALUE(x,S_SPEC_PEC) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_SMB_CMDH 8 -#define M_SMB_CMDH _SB_MAKEMASK(8,S_SMBH_CMD) -#define V_SMB_CMDH(x) _SB_MAKEVALUE(x,S_SMBH_CMD) +#define M_SMB_CMDH _SB_MAKEMASK(8,S_SMB_CMDH) +#define V_SMB_CMDH(x) _SB_MAKEVALUE(x,S_SMB_CMDH) #define M_SMB_EXTEND _SB_MAKEMASK1(14) -#define M_SMB_DIR _SB_MAKEMASK1(13) - #define S_SMB_DFMT 8 #define M_SMB_DFMT _SB_MAKEMASK(3,S_SMB_DFMT) #define V_SMB_DFMT(x) _SB_MAKEVALUE(x,S_SMB_DFMT) @@ -165,6 +182,23 @@ #define V_SMB_DFMT_CMD5BYTE V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE) #define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED) -#endif /* 1250 PASS2 || 112x PASS1 */ +#define S_SMB_AFMT 11 +#define M_SMB_AFMT _SB_MAKEMASK(2,S_SMB_AFMT) +#define V_SMB_AFMT(x) _SB_MAKEVALUE(x,S_SMB_AFMT) +#define G_SMB_AFMT(x) _SB_GETVALUE(x,S_SMB_AFMT,M_SMB_AFMT) + +#define K_SMB_AFMT_NONE 0 +#define K_SMB_AFMT_ADDR 1 +#define K_SMB_AFMT_ADDR_CMD1BYTE 2 +#define K_SMB_AFMT_ADDR_CMD2BYTE 3 + +#define V_SMB_AFMT_NONE V_SMB_AFMT(K_SMB_AFMT_NONE) +#define V_SMB_AFMT_ADDR V_SMB_AFMT(K_SMB_AFMT_ADDR) +#define V_SMB_AFMT_ADDR_CMD1BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD1BYTE) +#define V_SMB_AFMT_ADDR_CMD2BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD2BYTE) + +#define M_SMB_DIR _SB_MAKEMASK1(13) + +#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #endif diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h index fa2760d38b8b..dd154ac505d8 100644 --- a/include/asm-mips/sibyte/sb1250_syncser.h +++ b/include/asm-mips/sibyte/sb1250_syncser.h @@ -8,8 +8,6 @@ * * SB1250 specification level: User's manual 1/02/02 * - * Author: Mitch Lichtenberg - * ********************************************************************* * * Copyright 2000,2001,2002,2003 diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h index 923ea4f44e0f..e87045e62bf0 100644 --- a/include/asm-mips/sibyte/sb1250_uart.h +++ b/include/asm-mips/sibyte/sb1250_uart.h @@ -8,8 +8,6 @@ * * SB1250 specification level: User's manual 1/02/02 * - * Author: Mitch Lichtenberg - * ********************************************************************* * * Copyright 2000,2001,2002,2003 @@ -240,7 +238,12 @@ */ #define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) -#define M_DUART_ISR_RX_A _SB_MAKEMASK1(1) + +#define S_DUART_ISR_RX_A 1 +#define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A) +#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x,S_DUART_ISR_RX_A) +#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x,S_DUART_ISR_RX_A,M_DUART_ISR_RX_A) + #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) @@ -331,7 +334,7 @@ #define M_DUART_OUT_PIN_CLR(chan) \ (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) /* * Full Interrupt Control Register */ @@ -345,7 +348,7 @@ #define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) #define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) #define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) -#endif /* 1250 PASS2 || 112x PASS1 */ +#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ /* ********************************************************************** */ diff --git a/include/asm-mips/sibyte/swarm.h b/include/asm-mips/sibyte/swarm.h index 97fa0494c30c..06e1d528e03a 100644 --- a/include/asm-mips/sibyte/swarm.h +++ b/include/asm-mips/sibyte/swarm.h @@ -34,7 +34,7 @@ #define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200" #endif #ifdef CONFIG_SIBYTE_LITTLESUR -#define SIBYTE_BOARD_NAME "BCM1250C2 (LittleSur)" +#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)" #define SIBYTE_HAVE_PCMCIA 0 #define SIBYTE_HAVE_IDE 1 #define SIBYTE_DEFAULT_CONSOLE "cfe0" diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h index f7fbebaa0744..8edabb0be23f 100644 --- a/include/asm-mips/sigcontext.h +++ b/include/asm-mips/sigcontext.h @@ -27,14 +27,15 @@ struct sigcontext { unsigned int sc_fpc_csr; unsigned int sc_fpc_eir; /* Unused */ unsigned int sc_used_math; - unsigned int sc_ssflags; /* Unused */ + unsigned int sc_dsp; /* dsp status, was sc_ssflags */ unsigned long long sc_mdhi; unsigned long long sc_mdlo; - - unsigned int sc_cause; /* Unused */ - unsigned int sc_badvaddr; /* Unused */ - - unsigned long sc_sigset[4]; /* kernel's sigset_t */ + unsigned long sc_hi1; /* Was sc_cause */ + unsigned long sc_lo1; /* Was sc_badvaddr */ + unsigned long sc_hi2; /* Was sc_sigset[4] */ + unsigned long sc_lo2; + unsigned long sc_hi3; + unsigned long sc_lo3; }; #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ @@ -48,19 +49,19 @@ struct sigcontext { * Warning: this structure illdefined with sc_badvaddr being just an unsigned * int so it was changed to unsigned long in 2.6.0-test1. This may break * binary compatibility - no prisoners. + * DSP ASE in 2.6.12-rc4. Turn sc_mdhi and sc_mdlo into an array of four + * entries, add sc_dsp and sc_reserved for padding. No prisoners. */ struct sigcontext { unsigned long sc_regs[32]; unsigned long sc_fpregs[32]; - unsigned long sc_mdhi; - unsigned long sc_mdlo; + unsigned long sc_hi[4]; + unsigned long sc_lo[4]; unsigned long sc_pc; - unsigned long sc_badvaddr; - unsigned int sc_status; unsigned int sc_fpc_csr; - unsigned int sc_fpc_eir; unsigned int sc_used_math; - unsigned int sc_cause; + unsigned int sc_dsp; + unsigned int sc_reserved; }; #ifdef __KERNEL__ @@ -68,23 +69,24 @@ struct sigcontext { #include <linux/posix_types.h> struct sigcontext32 { - __u32 sc_regmask; /* Unused */ - __u32 sc_status; - __u64 sc_pc; - __u64 sc_regs[32]; - __u64 sc_fpregs[32]; - __u32 sc_ownedfp; /* Unused */ - __u32 sc_fpc_csr; - __u32 sc_fpc_eir; /* Unused */ - __u32 sc_used_math; - __u32 sc_ssflags; /* Unused */ - __u64 sc_mdhi; - __u64 sc_mdlo; - - __u32 sc_cause; /* Unused */ - __u32 sc_badvaddr; /* Unused */ - - __u32 sc_sigset[4]; /* kernel's sigset_t */ + __u32 sc_regmask; /* Unused */ + __u32 sc_status; + __u64 sc_pc; + __u64 sc_regs[32]; + __u64 sc_fpregs[32]; + __u32 sc_ownedfp; /* Unused */ + __u32 sc_fpc_csr; + __u32 sc_fpc_eir; /* Unused */ + __u32 sc_used_math; + __u32 sc_dsp; /* dsp status, was sc_ssflags */ + __u64 sc_mdhi; + __u64 sc_mdlo; + __u32 sc_hi1; /* Was sc_cause */ + __u32 sc_lo1; /* Was sc_badvaddr */ + __u32 sc_hi2; /* Was sc_sigset[4] */ + __u32 sc_lo2; + __u32 sc_hi3; + __u32 sc_lo3; }; #endif /* __KERNEL__ */ diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h index 698becab5a9e..2ba313d94a78 100644 --- a/include/asm-mips/siginfo.h +++ b/include/asm-mips/siginfo.h @@ -11,6 +11,7 @@ #include <linux/config.h> +#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2*sizeof(int)) #undef __ARCH_SI_TRAPNO /* exception code needs to fill this ... */ #define HAVE_ARCH_SIGINFO_T diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h index f2c470f1d369..8ca539e80d87 100644 --- a/include/asm-mips/signal.h +++ b/include/asm-mips/signal.h @@ -98,12 +98,39 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */ #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 +#ifdef __KERNEL__ + +/* + * These values of sa_flags are used only by the kernel as part of the + * irq handling routines. + * + * SA_INTERRUPT is also used by the irq handling routines. + * SA_SHIRQ flag is for shared interrupt support on PCI and EISA. + */ +#define SA_SAMPLE_RANDOM SA_RESTART + +#ifdef CONFIG_TRAD_SIGNALS +#define sig_uses_siginfo(ka) ((ka)->sa.sa_flags & SA_SIGINFO) +#else +#define sig_uses_siginfo(ka) (1) +#endif + +#endif /* __KERNEL__ */ + #define SIG_BLOCK 1 /* for blocking signals */ #define SIG_UNBLOCK 2 /* for unblocking signals */ #define SIG_SETMASK 3 /* for setting the signal mask */ #define SIG_SETMASK32 256 /* Goodie from SGI for BSD compatibility: set only the low 32 bit of the sigset. */ -#include <asm-generic/signal.h> + +/* Type of a signal handler. */ +typedef void __signalfn_t(int); +typedef __signalfn_t __user *__sighandler_t; + +/* Fake signal functions */ +#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ +#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ +#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ struct sigaction { unsigned int sa_flags; diff --git a/include/asm-mips/sn/sn0/arch.h b/include/asm-mips/sn/sn0/arch.h index 0e00dd474afc..fb78773a5efe 100644 --- a/include/asm-mips/sn/sn0/arch.h +++ b/include/asm-mips/sn/sn0/arch.h @@ -74,13 +74,8 @@ #define MAX_MEM_SLOTS 32 /* max slots per node */ #endif /* defined(N_MODE) */ -#if SABLE_RTL -#define SLOT_SHIFT (28) -#define SLOT_MIN_MEM_SIZE (16*1024*1024) -#else #define SLOT_SHIFT (27) #define SLOT_MIN_MEM_SIZE (32*1024*1024) -#endif #define CPUS_PER_NODE 2 /* CPUs on a single hub */ #define CPUS_PER_NODE_SHFT 1 /* Bits to shift in the node number */ diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h index 753b6620e6fa..0bb31e5aaca6 100644 --- a/include/asm-mips/socket.h +++ b/include/asm-mips/socket.h @@ -37,8 +37,6 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ #define SO_ERROR 0x1007 /* get error status and clear */ #define SO_SNDBUF 0x1001 /* Send buffer size. */ #define SO_RCVBUF 0x1002 /* Receive buffer. */ -#define SO_SNDBUFFORCE 0x100a -#define SO_RCVBUFFORCE 0x100b #define SO_SNDLOWAT 0x1003 /* send low-water mark */ #define SO_RCVLOWAT 0x1004 /* receive low-water mark */ #define SO_SNDTIMEO 0x1005 /* send timeout */ @@ -69,6 +67,8 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ #define SCM_TIMESTAMP SO_TIMESTAMP #define SO_PEERSEC 30 +#define SO_SNDBUFFORCE 31 +#define SO_RCVBUFFORCE 33 #ifdef __KERNEL__ @@ -92,6 +92,7 @@ enum sock_type { SOCK_RAW = 3, SOCK_RDM = 4, SOCK_SEQPACKET = 5, + SOCK_DCCP = 6, SOCK_PACKET = 10, }; diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h index 4d0135b11156..669b8e349ff2 100644 --- a/include/asm-mips/spinlock.h +++ b/include/asm-mips/spinlock.h @@ -9,17 +9,16 @@ #ifndef _ASM_SPINLOCK_H #define _ASM_SPINLOCK_H -#include <linux/config.h> #include <asm/war.h> /* * Your basic SMP spinlocks, allowing only a single CPU anywhere */ -#define __raw_spin_is_locked(x) ((x)->lock != 0) +#define __raw_spin_is_locked(x) ((x)->lock != 0) #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) #define __raw_spin_unlock_wait(x) \ - do { cpu_relax(); } while ((x)->lock) + do { cpu_relax(); } while ((x)->lock) /* * Simple spin lock operations. There are two variants, one clears IRQ's @@ -119,6 +118,18 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock) * read-locks. */ +/* + * read_can_lock - would read_trylock() succeed? + * @lock: the rwlock in question. + */ +#define __raw_read_can_lock(rw) ((rw)->lock >= 0) + +/* + * write_can_lock - would write_trylock() succeed? + * @lock: the rwlock in question. + */ +#define __raw_write_can_lock(rw) (!(rw)->lock) + static inline void __raw_read_lock(raw_rwlock_t *rw) { unsigned int tmp; @@ -197,8 +208,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) " lui %1, 0x8000 \n" " sc %1, %0 \n" " beqzl %1, 1b \n" - " nop \n" - " sync \n" + " sync \n" " .set reorder \n" : "=m" (rw->lock), "=&r" (tmp) : "m" (rw->lock) @@ -211,8 +221,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) " lui %1, 0x8000 \n" " sc %1, %0 \n" " beqz %1, 1b \n" - " nop \n" - " sync \n" + " sync \n" " .set reorder \n" : "=m" (rw->lock), "=&r" (tmp) : "m" (rw->lock) @@ -246,8 +255,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) " lui %1, 0x8000 \n" " sc %1, %0 \n" " beqzl %1, 1b \n" - " nop \n" - " sync \n" + " sync \n" " li %2, 1 \n" " .set reorder \n" "2: \n" diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index 7b5e64600bc8..a8919dcc93c8 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -60,7 +60,6 @@ mfc0 k0, CP0_CONTEXT lui k1, %hi(kernelsp) srl k0, k0, 23 - sll k0, k0, 2 addu k1, k0 LONG_L k1, %lo(kernelsp)(k1) #endif @@ -76,9 +75,14 @@ #endif #if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64) MFC0 k1, CP0_CONTEXT + lui k0, %highest(kernelsp) dsrl k1, 23 - dsll k1, k1, 3 - LONG_L k1, kernelsp(k1) + daddiu k0, %higher(kernelsp) + dsll k0, k0, 16 + daddiu k0, %hi(kernelsp) + dsll k0, k0, 16 + daddu k1, k1, k0 + LONG_L k1, %lo(kernelsp)(k1) #endif .endm @@ -86,25 +90,28 @@ #ifdef CONFIG_32BIT mfc0 \temp, CP0_CONTEXT srl \temp, 23 - sll \temp, 2 - LONG_S \stackp, kernelsp(\temp) #endif #if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) lw \temp, TI_CPU(gp) dsll \temp, 3 - lui \temp2, %hi(kernelsp) - daddu \temp, \temp2 - LONG_S \stackp, %lo(kernelsp)(\temp) #endif #if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64) - lw \temp, TI_CPU(gp) - dsll \temp, 3 - LONG_S \stackp, kernelsp(\temp) + MFC0 \temp, CP0_CONTEXT + dsrl \temp, 23 #endif + LONG_S \stackp, kernelsp(\temp) .endm #else .macro get_saved_sp /* Uniprocessor variation */ +#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64) + lui k1, %highest(kernelsp) + daddiu k1, %higher(kernelsp) + dsll k1, k1, 16 + daddiu k1, %hi(kernelsp) + dsll k1, k1, 16 +#else lui k1, %hi(kernelsp) +#endif LONG_L k1, %lo(kernelsp)(k1) .endm diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 6663efd49b27..330c4e497af3 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -17,6 +17,7 @@ #include <asm/addrspace.h> #include <asm/cpu-features.h> +#include <asm/dsp.h> #include <asm/ptrace.h> #include <asm/war.h> #include <asm/interrupt.h> @@ -70,7 +71,7 @@ * does not enforce ordering, since there is no data dependency between * the read of "a" and the read of "b". Therefore, on some CPUs, such * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() - * in cases like thiswhere there are no data dependencies. + * in cases like this where there are no data dependencies. */ #define read_barrier_depends() do { } while(0) @@ -154,15 +155,15 @@ extern asmlinkage void *resume(void *last, void *next, void *next_ti); struct task_struct; -#define switch_to(prev,next,last) \ -do { \ - (last) = resume(prev, next, next->thread_info); \ +#define switch_to(prev,next,last) \ +do { \ + if (cpu_has_dsp) \ + __save_dsp(prev); \ + (last) = resume(prev, next, next->thread_info); \ + if (cpu_has_dsp) \ + __restore_dsp(current); \ } while(0) -#define ROT_IN_PIECES \ - " .set noreorder \n" \ - " .set reorder \n" - static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) { __u32 retval; @@ -171,14 +172,17 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) unsigned long dummy; __asm__ __volatile__( + " .set mips3 \n" "1: ll %0, %3 # xchg_u32 \n" + " .set mips0 \n" " move %2, %z4 \n" + " .set mips3 \n" " sc %2, %1 \n" " beqzl %2, 1b \n" - ROT_IN_PIECES #ifdef CONFIG_SMP " sync \n" #endif + " .set mips0 \n" : "=&r" (retval), "=m" (*m), "=&r" (dummy) : "R" (*m), "Jr" (val) : "memory"); @@ -186,13 +190,17 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) unsigned long dummy; __asm__ __volatile__( + " .set mips3 \n" "1: ll %0, %3 # xchg_u32 \n" + " .set mips0 \n" " move %2, %z4 \n" + " .set mips3 \n" " sc %2, %1 \n" " beqz %2, 1b \n" #ifdef CONFIG_SMP " sync \n" #endif + " .set mips0 \n" : "=&r" (retval), "=m" (*m), "=&r" (dummy) : "R" (*m), "Jr" (val) : "memory"); @@ -217,14 +225,15 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) unsigned long dummy; __asm__ __volatile__( + " .set mips3 \n" "1: lld %0, %3 # xchg_u64 \n" " move %2, %z4 \n" " scd %2, %1 \n" " beqzl %2, 1b \n" - ROT_IN_PIECES #ifdef CONFIG_SMP " sync \n" #endif + " .set mips0 \n" : "=&r" (retval), "=m" (*m), "=&r" (dummy) : "R" (*m), "Jr" (val) : "memory"); @@ -232,6 +241,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) unsigned long dummy; __asm__ __volatile__( + " .set mips3 \n" "1: lld %0, %3 # xchg_u64 \n" " move %2, %z4 \n" " scd %2, %1 \n" @@ -239,6 +249,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) #ifdef CONFIG_SMP " sync \n" #endif + " .set mips0 \n" : "=&r" (retval), "=m" (*m), "=&r" (dummy) : "R" (*m), "Jr" (val) : "memory"); @@ -286,34 +297,41 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( + " .set push \n" " .set noat \n" + " .set mips3 \n" "1: ll %0, %2 # __cmpxchg_u32 \n" " bne %0, %z3, 2f \n" + " .set mips0 \n" " move $1, %z4 \n" + " .set mips3 \n" " sc $1, %1 \n" " beqzl $1, 1b \n" - ROT_IN_PIECES #ifdef CONFIG_SMP " sync \n" #endif "2: \n" - " .set at \n" + " .set pop \n" : "=&r" (retval), "=m" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( + " .set push \n" " .set noat \n" + " .set mips3 \n" "1: ll %0, %2 # __cmpxchg_u32 \n" " bne %0, %z3, 2f \n" + " .set mips0 \n" " move $1, %z4 \n" + " .set mips3 \n" " sc $1, %1 \n" " beqz $1, 1b \n" #ifdef CONFIG_SMP " sync \n" #endif "2: \n" - " .set at \n" + " .set pop \n" : "=&r" (retval), "=m" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); @@ -338,24 +356,27 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, if (cpu_has_llsc) { __asm__ __volatile__( + " .set push \n" " .set noat \n" + " .set mips3 \n" "1: lld %0, %2 # __cmpxchg_u64 \n" " bne %0, %z3, 2f \n" " move $1, %z4 \n" " scd $1, %1 \n" " beqzl $1, 1b \n" - ROT_IN_PIECES #ifdef CONFIG_SMP " sync \n" #endif "2: \n" - " .set at \n" + " .set pop \n" : "=&r" (retval), "=m" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( + " .set push \n" " .set noat \n" + " .set mips3 \n" "1: lld %0, %2 # __cmpxchg_u64 \n" " bne %0, %z3, 2f \n" " move $1, %z4 \n" @@ -365,7 +386,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, " sync \n" #endif "2: \n" - " .set at \n" + " .set pop \n" : "=&r" (retval), "=m" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); @@ -406,18 +427,20 @@ static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old, #define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr)))) +extern void set_handler (unsigned long offset, void *addr, unsigned long len); +extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len); +extern void *set_vi_handler (int n, void *addr); +extern void *set_vi_srs_handler (int n, void *addr, int regset); extern void *set_except_vector(int n, void *addr); extern void per_cpu_trap_init(void); -extern NORET_TYPE void __die(const char *, struct pt_regs *, const char *file, - const char *func, unsigned long line); -extern void __die_if_kernel(const char *, struct pt_regs *, const char *file, - const char *func, unsigned long line); +extern NORET_TYPE void die(const char *, struct pt_regs *); -#define die(msg, regs) \ - __die(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__) -#define die_if_kernel(msg, regs) \ - __die_if_kernel(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__) +static inline void die_if_kernel(const char *str, struct pt_regs *regs) +{ + if (unlikely(!user_mode(regs))) + die(str, regs); +} extern int stop_a_enabled; diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h index a70cb0854c8a..e6c24472e03f 100644 --- a/include/asm-mips/thread_info.h +++ b/include/asm-mips/thread_info.h @@ -26,6 +26,7 @@ struct thread_info { struct task_struct *task; /* main task structure */ struct exec_domain *exec_domain; /* execution domain */ unsigned long flags; /* low level flags */ + unsigned long tp_value; /* thread pointer */ __u32 cpu; /* current CPU */ int preempt_count; /* 0 => preemptable, <0 => BUG */ @@ -114,6 +115,7 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define TIF_SIGPENDING 2 /* signal pending */ #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ #define TIF_SYSCALL_AUDIT 4 /* syscall auditing active */ +#define TIF_SECCOMP 5 /* secure computing */ #define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_MEMDIE 18 @@ -124,13 +126,14 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) +#define _TIF_SECCOMP (1<<TIF_SECCOMP) #define _TIF_USEDFPU (1<<TIF_USEDFPU) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) -#define _TIF_WORK_MASK 0x0000ffef /* work to do on - interrupt/exception return */ -#define _TIF_ALLWORK_MASK 0x8000ffff /* work to do on any return to - u-space */ +/* work to do on interrupt/exception return */ +#define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP) +/* work to do on any return to u-space */ +#define _TIF_ALLWORK_MASK (0x8000ffff & ~_TIF_SECCOMP) #endif /* __KERNEL__ */ diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h index 179012263007..d02e019b0127 100644 --- a/include/asm-mips/traps.h +++ b/include/asm-mips/traps.h @@ -21,4 +21,7 @@ extern void (*board_be_init)(void); extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup); +extern void (*board_nmi_handler_setup)(void); +extern void (*board_ejtag_handler_setup)(void); + #endif /* _ASM_TRAPS_H */ diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h new file mode 100644 index 000000000000..0fbedafdcea8 --- /dev/null +++ b/include/asm-mips/tx4938/rbtx4938.h @@ -0,0 +1,207 @@ +/* + * linux/include/asm-mips/tx4938/rbtx4938.h + * Definitions for TX4937/TX4938 + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#ifndef __ASM_TX_BOARDS_RBTX4938_H +#define __ASM_TX_BOARDS_RBTX4938_H + +#include <asm/addrspace.h> +#include <asm/tx4938/tx4938.h> + +/* CS */ +#define RBTX4938_CE0 0x1c000000 /* 64M */ +#define RBTX4938_CE2 0x17f00000 /* 1M */ + +/* Address map */ +#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000) +#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002) +#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004) +#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006) +#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008) +#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000) +#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002) +#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004) +#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000) +#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002) +#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004) +#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006) +#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008) +#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a) +#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c) +#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000) +#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000) +#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002) +#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008) +#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a) +#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000) +#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002) +#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004) +#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000) + +/* Ethernet port address (Jumperless Mode (W12:Open)) */ +#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280) + +/* bits for ISTAT/IMASK/IMSTAT */ +#define RBTX4938_INTB_PCID 0 +#define RBTX4938_INTB_PCIC 1 +#define RBTX4938_INTB_PCIB 2 +#define RBTX4938_INTB_PCIA 3 +#define RBTX4938_INTB_RTC 4 +#define RBTX4938_INTB_ATA 5 +#define RBTX4938_INTB_MODEM 6 +#define RBTX4938_INTB_SWINT 7 +#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID) +#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC) +#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB) +#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA) +#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC) +#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA) +#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM) +#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT) + +#define rbtx4938_fpga_rev_ptr \ + ((volatile unsigned char *)RBTX4938_FPGA_REV_ADDR) +#define rbtx4938_led_ptr \ + ((volatile unsigned char *)RBTX4938_LED_ADDR) +#define rbtx4938_dipsw_ptr \ + ((volatile unsigned char *)RBTX4938_DIPSW_ADDR) +#define rbtx4938_bdipsw_ptr \ + ((volatile unsigned char *)RBTX4938_BDIPSW_ADDR) +#define rbtx4938_imask_ptr \ + ((volatile unsigned char *)RBTX4938_IMASK_ADDR) +#define rbtx4938_imask2_ptr \ + ((volatile unsigned char *)RBTX4938_IMASK2_ADDR) +#define rbtx4938_intpol_ptr \ + ((volatile unsigned char *)RBTX4938_INTPOL_ADDR) +#define rbtx4938_istat_ptr \ + ((volatile unsigned char *)RBTX4938_ISTAT_ADDR) +#define rbtx4938_istat2_ptr \ + ((volatile unsigned char *)RBTX4938_ISTAT2_ADDR) +#define rbtx4938_imstat_ptr \ + ((volatile unsigned char *)RBTX4938_IMSTAT_ADDR) +#define rbtx4938_imstat2_ptr \ + ((volatile unsigned char *)RBTX4938_IMSTAT2_ADDR) +#define rbtx4938_softint_ptr \ + ((volatile unsigned char *)RBTX4938_SOFTINT_ADDR) +#define rbtx4938_piosel_ptr \ + ((volatile unsigned char *)RBTX4938_PIOSEL_ADDR) +#define rbtx4938_spics_ptr \ + ((volatile unsigned char *)RBTX4938_SPICS_ADDR) +#define rbtx4938_sfpwr_ptr \ + ((volatile unsigned char *)RBTX4938_SFPWR_ADDR) +#define rbtx4938_sfvol_ptr \ + ((volatile unsigned char *)RBTX4938_SFVOL_ADDR) +#define rbtx4938_softreset_ptr \ + ((volatile unsigned char *)RBTX4938_SOFTRESET_ADDR) +#define rbtx4938_softresetlock_ptr \ + ((volatile unsigned char *)RBTX4938_SOFTRESETLOCK_ADDR) +#define rbtx4938_pcireset_ptr \ + ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR) + +/* SPI */ +#define RBTX4938_SEEPROM1_CHIPID 0 +#define RBTX4938_SEEPROM2_CHIPID 1 +#define RBTX4938_SEEPROM3_CHIPID 2 +#define RBTX4938_SRTC_CHIPID 3 + +/* + * IRQ mappings + */ + +#define RBTX4938_SOFT_INT0 0 /* not used */ +#define RBTX4938_SOFT_INT1 1 /* not used */ +#define RBTX4938_IRC_INT 2 +#define RBTX4938_TIMER_INT 7 + +/* These are the virtual IRQ numbers, we divide all IRQ's into + * 'spaces', the 'space' determines where and how to enable/disable + * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new + * IRQ hardware is supported. + */ +#define RBTX4938_NR_IRQ_LOCAL 8 +#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ +#define RBTX4938_NR_IRQ_IOC 8 + +#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */ +#define MI8259_IRQ_ISA_RAW_END 15 +#define TX4938_IRQ_CP0_RAW_BEG 0 /* tx4938 cpu built-in cp0 */ +#define TX4938_IRQ_CP0_RAW_END 7 +#define TX4938_IRQ_PIC_RAW_BEG 0 /* tx4938 cpu build-in pic */ +#define TX4938_IRQ_PIC_RAW_END 31 + +#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */ +#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */ + +#define TX4938_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG) /* 16 */ +#define TX4938_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END) /* 23 */ + +#define TX4938_IRQ_PIC_BEG ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG) /* 24 */ +#define TX4938_IRQ_PIC_END ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END) /* 55 */ +#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) +#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) +#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) +#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1) +#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7) + +#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0 +#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7 + +#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */ +#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */ +#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG +#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL) +#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC) +#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC) + +#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0) +#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1) +#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT) +#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT) +#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) +#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) +#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) +#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) +#define RBTX4938_IRQ_IRC_DMA(ch,n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch,n)) +#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) +#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) +#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) +#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n)) +#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC) +#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR) +#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME) +#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC) +#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME) +#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1) +#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI) +#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID) +#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC) +#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB) +#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA) +#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC) +#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA) +#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM) +#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT) + + +/* IOC (PCI, etc) */ +#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC) +/* Onboard 10M Ether */ +#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1) + +#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) +#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) + +/* IRCR : Int. Control */ +#define TX4938_IRCR_LOW 0x00000000 +#define TX4938_IRCR_HIGH 0x00000001 +#define TX4938_IRCR_DOWN 0x00000002 +#define TX4938_IRCR_UP 0x00000003 + +#endif /* __ASM_TX_BOARDS_RBTX4938_H */ diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/tx4938/spi.h new file mode 100644 index 000000000000..0dbbab820a5a --- /dev/null +++ b/include/asm-mips/tx4938/spi.h @@ -0,0 +1,74 @@ +/* + * linux/include/asm-mips/tx4938/spi.h + * Definitions for TX4937/TX4938 SPI + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#ifndef __ASM_TX_BOARDS_TX4938_SPI_H +#define __ASM_TX_BOARDS_TX4938_SPI_H + +/* SPI */ +struct spi_dev_desc { + unsigned int baud; + unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */ + unsigned int byteorder:1; /* 0:LSB-First, 1:MSB-First */ + unsigned int polarity:1; /* 0:High-Active */ + unsigned int phase:1; /* 0:Sample-Then-Shift */ +}; + +extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init; +extern void txx9_spi_irqinit(int irc_irq) __init; +extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc, + unsigned char **inbufs, unsigned int *incounts, + unsigned char **outbufs, unsigned int *outcounts, + int cansleep); +extern int spi_eeprom_write_enable(int chipid, int enable); +extern int spi_eeprom_read_status(int chipid); +extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); +extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len); +extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init; + +#define TXX9_IMCLK (txx9_gbus_clock / 2) + +/* +* SPI +*/ + +/* SPMCR : SPI Master Control */ +#define TXx9_SPMCR_OPMODE 0xc0 +#define TXx9_SPMCR_CONFIG 0x40 +#define TXx9_SPMCR_ACTIVE 0x80 +#define TXx9_SPMCR_SPSTP 0x02 +#define TXx9_SPMCR_BCLR 0x01 + +/* SPCR0 : SPI Status */ +#define TXx9_SPCR0_TXIFL_MASK 0xc000 +#define TXx9_SPCR0_RXIFL_MASK 0x3000 +#define TXx9_SPCR0_SIDIE 0x0800 +#define TXx9_SPCR0_SOEIE 0x0400 +#define TXx9_SPCR0_RBSIE 0x0200 +#define TXx9_SPCR0_TBSIE 0x0100 +#define TXx9_SPCR0_IFSPSE 0x0010 +#define TXx9_SPCR0_SBOS 0x0004 +#define TXx9_SPCR0_SPHA 0x0002 +#define TXx9_SPCR0_SPOL 0x0001 + +/* SPSR : SPI Status */ +#define TXx9_SPSR_TBSI 0x8000 +#define TXx9_SPSR_RBSI 0x4000 +#define TXx9_SPSR_TBS_MASK 0x3800 +#define TXx9_SPSR_RBS_MASK 0x0700 +#define TXx9_SPSR_SPOE 0x0080 +#define TXx9_SPSR_IFSD 0x0008 +#define TXx9_SPSR_SIDLE 0x0004 +#define TXx9_SPSR_STRDY 0x0002 +#define TXx9_SPSR_SRRDY 0x0001 + +#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */ diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h new file mode 100644 index 000000000000..e25b1a0975cb --- /dev/null +++ b/include/asm-mips/tx4938/tx4938.h @@ -0,0 +1,706 @@ +/* + * linux/include/asm-mips/tx4938/tx4938.h + * Definitions for TX4937/TX4938 + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#ifndef __ASM_TX_BOARDS_TX4938_H +#define __ASM_TX_BOARDS_TX4938_H + +#include <asm/tx4938/tx4938_mips.h> + +#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) +#define tx4938_write_nfmc(b,addr) (*(volatile unsigned int *)(addr)) = (b) + +#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG + +#define TX4938_IRQ_IRC_PCIC (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC) +#define TX4938_IRQ_IRC_PCIERR (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR) + +#define TX4938_PCIIO_0 0x10000000 +#define TX4938_PCIIO_1 0x01010000 +#define TX4938_PCIMEM_0 0x08000000 +#define TX4938_PCIMEM_1 0x11000000 + +#define TX4938_PCIIO_SIZE_0 0x01000000 +#define TX4938_PCIIO_SIZE_1 0x00010000 +#define TX4938_PCIMEM_SIZE_0 0x08000000 +#define TX4938_PCIMEM_SIZE_1 0x00010000 + +#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */ +#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ + +/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */ +#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000) +#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000) +#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000) +#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000) +#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000) +#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800) +#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000) +#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000) +#define TX4938_NR_TMR 3 +#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100) +#define TX4938_NR_SIO 2 +#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100) +#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500) +#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600) +#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) +#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) + +#ifndef _LANGUAGE_ASSEMBLY +#include <asm/byteorder.h> + +#define TX4938_MKA(x) ((u32)( ((u32)(TX4938_REG_BASE)) | ((u32)(x)) )) + +#define TX4938_RD08( reg ) (*(vu08*)(reg)) +#define TX4938_WR08( reg, val ) ((*(vu08*)(reg))=(val)) + +#define TX4938_RD16( reg ) (*(vu16*)(reg)) +#define TX4938_WR16( reg, val ) ((*(vu16*)(reg))=(val)) + +#define TX4938_RD32( reg ) (*(vu32*)(reg)) +#define TX4938_WR32( reg, val ) ((*(vu32*)(reg))=(val)) + +#define TX4938_RD64( reg ) (*(vu64*)(reg)) +#define TX4938_WR64( reg, val ) ((*(vu64*)(reg))=(val)) + +#define TX4938_RD( reg ) TX4938_RD32( reg ) +#define TX4938_WR( reg, val ) TX4938_WR32( reg, val ) + +#endif /* !__ASSEMBLY__ */ + +#ifdef __ASSEMBLY__ +#define _CONST64(c) c +#else +#define _CONST64(c) c##ull + +#include <asm/byteorder.h> + +#ifdef __BIG_ENDIAN +#define endian_def_l2(e1,e2) \ + volatile unsigned long e1,e2 +#define endian_def_s2(e1,e2) \ + volatile unsigned short e1,e2 +#define endian_def_sb2(e1,e2,e3) \ + volatile unsigned short e1;volatile unsigned char e2,e3 +#define endian_def_b2s(e1,e2,e3) \ + volatile unsigned char e1,e2;volatile unsigned short e3 +#define endian_def_b4(e1,e2,e3,e4) \ + volatile unsigned char e1,e2,e3,e4 +#else +#define endian_def_l2(e1,e2) \ + volatile unsigned long e2,e1 +#define endian_def_s2(e1,e2) \ + volatile unsigned short e2,e1 +#define endian_def_sb2(e1,e2,e3) \ + volatile unsigned char e3,e2;volatile unsigned short e1 +#define endian_def_b2s(e1,e2,e3) \ + volatile unsigned short e3;volatile unsigned char e2,e1 +#define endian_def_b4(e1,e2,e3,e4) \ + volatile unsigned char e4,e3,e2,e1 +#endif + + +struct tx4938_sdramc_reg { + volatile unsigned long long cr[4]; + volatile unsigned long long unused0[4]; + volatile unsigned long long tr; + volatile unsigned long long unused1[2]; + volatile unsigned long long cmd; + volatile unsigned long long sfcmd; +}; + +struct tx4938_ebusc_reg { + volatile unsigned long long cr[8]; +}; + +struct tx4938_dma_reg { + struct tx4938_dma_ch_reg { + volatile unsigned long long cha; + volatile unsigned long long sar; + volatile unsigned long long dar; + endian_def_l2(unused0, cntr); + endian_def_l2(unused1, sair); + endian_def_l2(unused2, dair); + endian_def_l2(unused3, ccr); + endian_def_l2(unused4, csr); + } ch[4]; + volatile unsigned long long dbr[8]; + volatile unsigned long long tdhr; + volatile unsigned long long midr; + endian_def_l2(unused0, mcr); +}; + +struct tx4938_pcic_reg { + volatile unsigned long pciid; + volatile unsigned long pcistatus; + volatile unsigned long pciccrev; + volatile unsigned long pcicfg1; + volatile unsigned long p2gm0plbase; /* +10 */ + volatile unsigned long p2gm0pubase; + volatile unsigned long p2gm1plbase; + volatile unsigned long p2gm1pubase; + volatile unsigned long p2gm2pbase; /* +20 */ + volatile unsigned long p2giopbase; + volatile unsigned long unused0; + volatile unsigned long pcisid; + volatile unsigned long unused1; /* +30 */ + volatile unsigned long pcicapptr; + volatile unsigned long unused2; + volatile unsigned long pcicfg2; + volatile unsigned long g2ptocnt; /* +40 */ + volatile unsigned long unused3[15]; + volatile unsigned long g2pstatus; /* +80 */ + volatile unsigned long g2pmask; + volatile unsigned long pcisstatus; + volatile unsigned long pcimask; + volatile unsigned long p2gcfg; /* +90 */ + volatile unsigned long p2gstatus; + volatile unsigned long p2gmask; + volatile unsigned long p2gccmd; + volatile unsigned long unused4[24]; /* +a0 */ + volatile unsigned long pbareqport; /* +100 */ + volatile unsigned long pbacfg; + volatile unsigned long pbastatus; + volatile unsigned long pbamask; + volatile unsigned long pbabm; /* +110 */ + volatile unsigned long pbacreq; + volatile unsigned long pbacgnt; + volatile unsigned long pbacstate; + volatile unsigned long long g2pmgbase[3]; /* +120 */ + volatile unsigned long long g2piogbase; + volatile unsigned long g2pmmask[3]; /* +140 */ + volatile unsigned long g2piomask; + volatile unsigned long long g2pmpbase[3]; /* +150 */ + volatile unsigned long long g2piopbase; + volatile unsigned long pciccfg; /* +170 */ + volatile unsigned long pcicstatus; + volatile unsigned long pcicmask; + volatile unsigned long unused5; + volatile unsigned long long p2gmgbase[3]; /* +180 */ + volatile unsigned long long p2giogbase; + volatile unsigned long g2pcfgadrs; /* +1a0 */ + volatile unsigned long g2pcfgdata; + volatile unsigned long unused6[8]; + volatile unsigned long g2pintack; + volatile unsigned long g2pspc; + volatile unsigned long unused7[12]; /* +1d0 */ + volatile unsigned long long pdmca; /* +200 */ + volatile unsigned long long pdmga; + volatile unsigned long long pdmpa; + volatile unsigned long long pdmctr; + volatile unsigned long long pdmcfg; /* +220 */ + volatile unsigned long long pdmsts; +}; + +struct tx4938_aclc_reg { + volatile unsigned long acctlen; + volatile unsigned long acctldis; + volatile unsigned long acregacc; + volatile unsigned long unused0; + volatile unsigned long acintsts; + volatile unsigned long acintmsts; + volatile unsigned long acinten; + volatile unsigned long acintdis; + volatile unsigned long acsemaph; + volatile unsigned long unused1[7]; + volatile unsigned long acgpidat; + volatile unsigned long acgpodat; + volatile unsigned long acslten; + volatile unsigned long acsltdis; + volatile unsigned long acfifosts; + volatile unsigned long unused2[11]; + volatile unsigned long acdmasts; + volatile unsigned long acdmasel; + volatile unsigned long unused3[6]; + volatile unsigned long acaudodat; + volatile unsigned long acsurrdat; + volatile unsigned long accentdat; + volatile unsigned long aclfedat; + volatile unsigned long acaudiat; + volatile unsigned long unused4; + volatile unsigned long acmodoat; + volatile unsigned long acmodidat; + volatile unsigned long unused5[15]; + volatile unsigned long acrevid; +}; + + +struct tx4938_tmr_reg { + volatile unsigned long tcr; + volatile unsigned long tisr; + volatile unsigned long cpra; + volatile unsigned long cprb; + volatile unsigned long itmr; + volatile unsigned long unused0[3]; + volatile unsigned long ccdr; + volatile unsigned long unused1[3]; + volatile unsigned long pgmr; + volatile unsigned long unused2[3]; + volatile unsigned long wtmr; + volatile unsigned long unused3[43]; + volatile unsigned long trr; +}; + +struct tx4938_sio_reg { + volatile unsigned long lcr; + volatile unsigned long dicr; + volatile unsigned long disr; + volatile unsigned long cisr; + volatile unsigned long fcr; + volatile unsigned long flcr; + volatile unsigned long bgr; + volatile unsigned long tfifo; + volatile unsigned long rfifo; +}; + +struct tx4938_pio_reg { + volatile unsigned long dout; + volatile unsigned long din; + volatile unsigned long dir; + volatile unsigned long od; + volatile unsigned long flag[2]; + volatile unsigned long pol; + volatile unsigned long intc; + volatile unsigned long maskcpu; + volatile unsigned long maskext; +}; +struct tx4938_irc_reg { + volatile unsigned long cer; + volatile unsigned long cr[2]; + volatile unsigned long unused0; + volatile unsigned long ilr[8]; + volatile unsigned long unused1[4]; + volatile unsigned long imr; + volatile unsigned long unused2[7]; + volatile unsigned long scr; + volatile unsigned long unused3[7]; + volatile unsigned long ssr; + volatile unsigned long unused4[7]; + volatile unsigned long csr; +}; + +struct tx4938_ndfmc_reg { + endian_def_l2(unused0, dtr); + endian_def_l2(unused1, mcr); + endian_def_l2(unused2, sr); + endian_def_l2(unused3, isr); + endian_def_l2(unused4, imr); + endian_def_l2(unused5, spr); + endian_def_l2(unused6, rstr); +}; + +struct tx4938_spi_reg { + volatile unsigned long mcr; + volatile unsigned long cr0; + volatile unsigned long cr1; + volatile unsigned long fs; + volatile unsigned long unused1; + volatile unsigned long sr; + volatile unsigned long dr; + volatile unsigned long unused2; +}; + +struct tx4938_sramc_reg { + volatile unsigned long long cr; +}; + +struct tx4938_ccfg_reg { + volatile unsigned long long ccfg; + volatile unsigned long long crir; + volatile unsigned long long pcfg; + volatile unsigned long long tear; + volatile unsigned long long clkctr; + volatile unsigned long long unused0; + volatile unsigned long long garbc; + volatile unsigned long long unused1; + volatile unsigned long long unused2; + volatile unsigned long long ramp; + volatile unsigned long long unused3; + volatile unsigned long long jmpadr; +}; + +#undef endian_def_l2 +#undef endian_def_s2 +#undef endian_def_sb2 +#undef endian_def_b2s +#undef endian_def_b4 + +#endif /* __ASSEMBLY__ */ + +/* + * NDFMC + */ + +/* NDFMCR : NDFMC Mode Control */ +#define TX4938_NDFMCR_WE 0x80 +#define TX4938_NDFMCR_ECC_ALL 0x60 +#define TX4938_NDFMCR_ECC_RESET 0x60 +#define TX4938_NDFMCR_ECC_READ 0x40 +#define TX4938_NDFMCR_ECC_ON 0x20 +#define TX4938_NDFMCR_ECC_OFF 0x00 +#define TX4938_NDFMCR_CE 0x10 +#define TX4938_NDFMCR_BSPRT 0x04 +#define TX4938_NDFMCR_ALE 0x02 +#define TX4938_NDFMCR_CLE 0x01 + +/* NDFMCR : NDFMC Status */ +#define TX4938_NDFSR_BUSY 0x80 + +/* NDFMCR : NDFMC Reset */ +#define TX4938_NDFRSTR_RST 0x01 + +/* + * IRC + */ + +#define TX4938_IR_ECCERR 0 +#define TX4938_IR_WTOERR 1 +#define TX4938_NUM_IR_INT 6 +#define TX4938_IR_INT(n) (2 + (n)) +#define TX4938_NUM_IR_SIO 2 +#define TX4938_IR_SIO(n) (8 + (n)) +#define TX4938_NUM_IR_DMA 4 +#define TX4938_IR_DMA(ch,n) ((ch ? 27 : 10) + (n)) /* 10-13,27-30 */ +#define TX4938_IR_PIO 14 +#define TX4938_IR_PDMAC 15 +#define TX4938_IR_PCIC 16 +#define TX4938_NUM_IR_TMR 3 +#define TX4938_IR_TMR(n) (17 + (n)) +#define TX4938_IR_NDFMC 21 +#define TX4938_IR_PCIERR 22 +#define TX4938_IR_PCIPME 23 +#define TX4938_IR_ACLC 24 +#define TX4938_IR_ACLCPME 25 +#define TX4938_IR_PCIC1 26 +#define TX4938_IR_SPI 31 +#define TX4938_NUM_IR 32 +/* multiplex */ +#define TX4938_IR_ETH0 TX4938_IR_INT(4) +#define TX4938_IR_ETH1 TX4938_IR_INT(3) + +/* + * CCFG + */ +/* CCFG : Chip Configuration */ +#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000) +#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000) +#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000) +#define TX4938_CCFG_TINTDIS 0x01000000 +#define TX4938_CCFG_PCI66 0x00800000 +#define TX4938_CCFG_PCIMODE 0x00400000 +#define TX4938_CCFG_PCI1_66 0x00200000 +#define TX4938_CCFG_DIVMODE_MASK 0x001e0000 +#define TX4938_CCFG_DIVMODE_2 (0x4 << 17) +#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17) +#define TX4938_CCFG_DIVMODE_3 (0x5 << 17) +#define TX4938_CCFG_DIVMODE_4 (0x6 << 17) +#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17) +#define TX4938_CCFG_DIVMODE_8 (0x0 << 17) +#define TX4938_CCFG_DIVMODE_10 (0xb << 17) +#define TX4938_CCFG_DIVMODE_12 (0x1 << 17) +#define TX4938_CCFG_DIVMODE_16 (0x2 << 17) +#define TX4938_CCFG_DIVMODE_18 (0x9 << 17) +#define TX4938_CCFG_BEOW 0x00010000 +#define TX4938_CCFG_WR 0x00008000 +#define TX4938_CCFG_TOE 0x00004000 +#define TX4938_CCFG_PCIXARB 0x00002000 +#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00 +#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10) +#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10) +#define TX4938_CCFG_PCIDIVMODE_5 (0x5 << 10) +#define TX4938_CCFG_PCIDIVMODE_5_5 (0x7 << 10) +#define TX4938_CCFG_PCIDIVMODE_8 (0x0 << 10) +#define TX4938_CCFG_PCIDIVMODE_9 (0x2 << 10) +#define TX4938_CCFG_PCIDIVMODE_10 (0x4 << 10) +#define TX4938_CCFG_PCIDIVMODE_11 (0x6 << 10) +#define TX4938_CCFG_PCI1DMD 0x00000100 +#define TX4938_CCFG_SYSSP_MASK 0x000000c0 +#define TX4938_CCFG_ENDIAN 0x00000004 +#define TX4938_CCFG_HALT 0x00000002 +#define TX4938_CCFG_ACEHOLD 0x00000001 + +/* PCFG : Pin Configuration */ +#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000) +#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000) +#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000) +#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000) +#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000) +#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000) +#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000 +#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) +#define TX4938_PCFG_SYSCLKEN 0x08000000 +#define TX4938_PCFG_SDCLKEN_ALL 0x07800000 +#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) +#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000 +#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) +#define TX4938_PCFG_SEL2 0x00000200 +#define TX4938_PCFG_SEL1 0x00000100 +#define TX4938_PCFG_DMASEL_ALL 0x0000000f +#define TX4938_PCFG_DMASEL0_DRQ0 0x00000000 +#define TX4938_PCFG_DMASEL0_SIO1 0x00000001 +#define TX4938_PCFG_DMASEL1_DRQ1 0x00000000 +#define TX4938_PCFG_DMASEL1_SIO1 0x00000002 +#define TX4938_PCFG_DMASEL2_DRQ2 0x00000000 +#define TX4938_PCFG_DMASEL2_SIO0 0x00000004 +#define TX4938_PCFG_DMASEL3_DRQ3 0x00000000 +#define TX4938_PCFG_DMASEL3_SIO0 0x00000008 + +/* CLKCTR : Clock Control */ +#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000) +#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000) +#define TX4938_CLKCTR_ETH1CKD 0x80000000 +#define TX4938_CLKCTR_ETH0CKD 0x40000000 +#define TX4938_CLKCTR_SPICKD 0x20000000 +#define TX4938_CLKCTR_SRAMCKD 0x10000000 +#define TX4938_CLKCTR_PCIC1CKD 0x08000000 +#define TX4938_CLKCTR_DMA1CKD 0x04000000 +#define TX4938_CLKCTR_ACLCKD 0x02000000 +#define TX4938_CLKCTR_PIOCKD 0x01000000 +#define TX4938_CLKCTR_DMACKD 0x00800000 +#define TX4938_CLKCTR_PCICKD 0x00400000 +#define TX4938_CLKCTR_TM0CKD 0x00100000 +#define TX4938_CLKCTR_TM1CKD 0x00080000 +#define TX4938_CLKCTR_TM2CKD 0x00040000 +#define TX4938_CLKCTR_SIO0CKD 0x00020000 +#define TX4938_CLKCTR_SIO1CKD 0x00010000 +#define TX4938_CLKCTR_ETH1RST 0x00008000 +#define TX4938_CLKCTR_ETH0RST 0x00004000 +#define TX4938_CLKCTR_SPIRST 0x00002000 +#define TX4938_CLKCTR_SRAMRST 0x00001000 +#define TX4938_CLKCTR_PCIC1RST 0x00000800 +#define TX4938_CLKCTR_DMA1RST 0x00000400 +#define TX4938_CLKCTR_ACLRST 0x00000200 +#define TX4938_CLKCTR_PIORST 0x00000100 +#define TX4938_CLKCTR_DMARST 0x00000080 +#define TX4938_CLKCTR_PCIRST 0x00000040 +#define TX4938_CLKCTR_TM0RST 0x00000010 +#define TX4938_CLKCTR_TM1RST 0x00000008 +#define TX4938_CLKCTR_TM2RST 0x00000004 +#define TX4938_CLKCTR_SIO0RST 0x00000002 +#define TX4938_CLKCTR_SIO1RST 0x00000001 + +/* bits for G2PSTATUS/G2PMASK */ +#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003 +#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002 +#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001 + +/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ +#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900 + +/* bits for PBACFG */ +#define TX4938_PCIC_PBACFG_FIXPA 0x00000008 +#define TX4938_PCIC_PBACFG_RPBA 0x00000004 +#define TX4938_PCIC_PBACFG_PBAEN 0x00000002 +#define TX4938_PCIC_PBACFG_BMCEN 0x00000001 + +/* bits for G2PMnGBASE */ +#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for G2PIOGBASE */ +#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for PCICSTATUS/PCICMASK */ +#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8 +#define TX4938_PCIC_PCICSTATUS_PME 0x00000400 +#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200 +#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100 +#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080 +#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020 +#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010 +#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008 +#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002 +#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001 + +/* bits for PCICCFG */ +#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000 +#define TX4938_PCIC_PCICCFG_HRST 0x00000800 +#define TX4938_PCIC_PCICCFG_SRST 0x00000400 +#define TX4938_PCIC_PCICCFG_IRBER 0x00000200 +#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch)) +#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100 +#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080 +#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040 +#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020 +#define TX4938_PCIC_PCICCFG_TCAR 0x00000010 +#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008 + +/* bits for P2GMnGBASE */ +#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) +#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) + +/* bits for P2GIOGBASE */ +#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) +#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) + +#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) +#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32) + +/* bits for PDMCFG */ +#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000 +#define TX4938_PCIC_PDMCFG_EXFER 0x00100000 +#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800 +#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11) +#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400 +#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200 +#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100 +#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080 +#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040 +#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020 +#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c +#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000 +#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004 +#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008 +#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002 +#define TX4938_PCIC_PDMCFG_CHRST 0x00000001 + +/* bits for PDMSTS */ +#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000 +#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 +#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000 +#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000 +#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800 +#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400 +#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200 +#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100 +#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080 +#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040 +#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020 +#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008 +#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004 +#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002 +#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001 +#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0 +#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f + +/* + * DMA + */ +/* bits for MCR */ +#define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch)) +#define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch)) +#define TX4938_DMA_MCR_RSFIF 0x00000080 +#define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) +#define TX4938_DMA_MCR_RPRT 0x00000002 +#define TX4938_DMA_MCR_MSTEN 0x00000001 + +/* bits for CCRn */ +#define TX4938_DMA_CCR_IMMCHN 0x20000000 +#define TX4938_DMA_CCR_USEXFSZ 0x10000000 +#define TX4938_DMA_CCR_LE 0x08000000 +#define TX4938_DMA_CCR_DBINH 0x04000000 +#define TX4938_DMA_CCR_SBINH 0x02000000 +#define TX4938_DMA_CCR_CHRST 0x01000000 +#define TX4938_DMA_CCR_RVBYTE 0x00800000 +#define TX4938_DMA_CCR_ACKPOL 0x00400000 +#define TX4938_DMA_CCR_REQPL 0x00200000 +#define TX4938_DMA_CCR_EGREQ 0x00100000 +#define TX4938_DMA_CCR_CHDN 0x00080000 +#define TX4938_DMA_CCR_DNCTL 0x00060000 +#define TX4938_DMA_CCR_EXTRQ 0x00010000 +#define TX4938_DMA_CCR_INTRQD 0x0000e000 +#define TX4938_DMA_CCR_INTENE 0x00001000 +#define TX4938_DMA_CCR_INTENC 0x00000800 +#define TX4938_DMA_CCR_INTENT 0x00000400 +#define TX4938_DMA_CCR_CHNEN 0x00000200 +#define TX4938_DMA_CCR_XFACT 0x00000100 +#define TX4938_DMA_CCR_SMPCHN 0x00000020 +#define TX4938_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) +#define TX4938_DMA_CCR_XFSZ_1W TX4938_DMA_CCR_XFSZ(2) +#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3) +#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4) +#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5) +#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6) +#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7) +#define TX4938_DMA_CCR_MEMIO 0x00000002 +#define TX4938_DMA_CCR_SNGAD 0x00000001 + +/* bits for CSRn */ +#define TX4938_DMA_CSR_CHNEN 0x00000400 +#define TX4938_DMA_CSR_STLXFER 0x00000200 +#define TX4938_DMA_CSR_CHNACT 0x00000100 +#define TX4938_DMA_CSR_ABCHC 0x00000080 +#define TX4938_DMA_CSR_NCHNC 0x00000040 +#define TX4938_DMA_CSR_NTRNFC 0x00000020 +#define TX4938_DMA_CSR_EXTDN 0x00000010 +#define TX4938_DMA_CSR_CFERR 0x00000008 +#define TX4938_DMA_CSR_CHERR 0x00000004 +#define TX4938_DMA_CSR_DESERR 0x00000002 +#define TX4938_DMA_CSR_SORERR 0x00000001 + +/* TX4938 Interrupt Controller (32-bit registers) */ +#define TX4938_IRC_BASE 0xf510 +#define TX4938_IRC_IRFLAG0 0xf510 +#define TX4938_IRC_IRFLAG1 0xf514 +#define TX4938_IRC_IRPOL 0xf518 +#define TX4938_IRC_IRRCNT 0xf51c +#define TX4938_IRC_IRMASKINT 0xf520 +#define TX4938_IRC_IRMASKEXT 0xf524 +#define TX4938_IRC_IRDEN 0xf600 +#define TX4938_IRC_IRDM0 0xf604 +#define TX4938_IRC_IRDM1 0xf608 +#define TX4938_IRC_IRLVL0 0xf610 +#define TX4938_IRC_IRLVL1 0xf614 +#define TX4938_IRC_IRLVL2 0xf618 +#define TX4938_IRC_IRLVL3 0xf61c +#define TX4938_IRC_IRLVL4 0xf620 +#define TX4938_IRC_IRLVL5 0xf624 +#define TX4938_IRC_IRLVL6 0xf628 +#define TX4938_IRC_IRLVL7 0xf62c +#define TX4938_IRC_IRMSK 0xf640 +#define TX4938_IRC_IREDC 0xf660 +#define TX4938_IRC_IRPND 0xf680 +#define TX4938_IRC_IRCS 0xf6a0 +#define TX4938_IRC_LIMIT 0xf6ff + + +#ifndef __ASSEMBLY__ + +#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) +#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) +#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) +#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) +#define tx4938_ircptr ((struct tx4938_irc_reg *)TX4938_IRC_REG) +#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) +#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) +#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) +#define tx4938_tmrptr(ch) ((struct tx4938_tmr_reg *)TX4938_TMR_REG(ch)) +#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) +#define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG) +#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) +#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG) +#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG) + + +#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff) +#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16) + +#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) +#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) + +#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) +#define TX4938_EBUSC_SIZE(ch) \ + (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf)) + + +#endif /* !__ASSEMBLY__ */ + +#endif diff --git a/include/asm-mips/tx4938/tx4938_mips.h b/include/asm-mips/tx4938/tx4938_mips.h new file mode 100644 index 000000000000..cf89b205f103 --- /dev/null +++ b/include/asm-mips/tx4938/tx4938_mips.h @@ -0,0 +1,54 @@ +/* + * linux/include/asm-mips/tx4938/tx4938_bitmask.h + * Generic bitmask definitions + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#ifndef TX4938_TX4938_MIPS_H +#define TX4938_TX4938_MIPS_H +#ifndef __ASSEMBLY__ + +#define reg_rd08(r) ((u8 )(*((vu8 *)(r)))) +#define reg_rd16(r) ((u16)(*((vu16*)(r)))) +#define reg_rd32(r) ((u32)(*((vu32*)(r)))) +#define reg_rd64(r) ((u64)(*((vu64*)(r)))) + +#define reg_wr08(r,v) ((*((vu8 *)(r)))=((u8 )(v))) +#define reg_wr16(r,v) ((*((vu16*)(r)))=((u16)(v))) +#define reg_wr32(r,v) ((*((vu32*)(r)))=((u32)(v))) +#define reg_wr64(r,v) ((*((vu64*)(r)))=((u64)(v))) + +typedef volatile __signed char vs8; +typedef volatile unsigned char vu8; + +typedef volatile __signed short vs16; +typedef volatile unsigned short vu16; + +typedef volatile __signed int vs32; +typedef volatile unsigned int vu32; + +typedef s8 s08; +typedef vs8 vs08; + +typedef u8 u08; +typedef vu8 vu08; + +#if (_MIPS_SZLONG == 64) + +typedef volatile __signed__ long vs64; +typedef volatile unsigned long vu64; + +#else + +typedef volatile __signed__ long long vs64; +typedef volatile unsigned long long vu64; + +#endif +#endif +#endif diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h index 5c2c98329012..41bb96bb2120 100644 --- a/include/asm-mips/uaccess.h +++ b/include/asm-mips/uaccess.h @@ -196,63 +196,55 @@ __get_user_nocheck((x),(ptr),sizeof(*(ptr))) struct __large_struct { unsigned long buf[100]; }; -#define __m(x) (*(struct __large_struct *)(x)) +#define __m(x) (*(struct __large_struct __user *)(x)) /* * Yuck. We need two variants, one for 64bit operation and one * for 32 bit mode and old iron. */ #ifdef __mips64 -#define __GET_USER_DW(__gu_err) __get_user_asm("ld", __gu_err) +#define __GET_USER_DW(ptr) __get_user_asm("ld", ptr) #else -#define __GET_USER_DW(__gu_err) __get_user_asm_ll32(__gu_err) +#define __GET_USER_DW(ptr) __get_user_asm_ll32(ptr) #endif #define __get_user_nocheck(x,ptr,size) \ ({ \ - __typeof(*(ptr)) __gu_val = 0; \ - long __gu_addr; \ + __typeof(*(ptr)) __gu_val = (__typeof(*(ptr))) 0; \ long __gu_err = 0; \ \ - might_sleep(); \ - __gu_addr = (long) (ptr); \ switch (size) { \ - case 1: __get_user_asm("lb", __gu_err); break; \ - case 2: __get_user_asm("lh", __gu_err); break; \ - case 4: __get_user_asm("lw", __gu_err); break; \ - case 8: __GET_USER_DW(__gu_err); break; \ + case 1: __get_user_asm("lb", ptr); break; \ + case 2: __get_user_asm("lh", ptr); break; \ + case 4: __get_user_asm("lw", ptr); break; \ + case 8: __GET_USER_DW(ptr); break; \ default: __get_user_unknown(); break; \ } \ - x = (__typeof__(*(ptr))) __gu_val; \ + (x) = (__typeof__(*(ptr))) __gu_val; \ __gu_err; \ }) #define __get_user_check(x,ptr,size) \ ({ \ + const __typeof__(*(ptr)) __user * __gu_addr = (ptr); \ __typeof__(*(ptr)) __gu_val = 0; \ - long __gu_addr; \ - long __gu_err; \ - \ - might_sleep(); \ - __gu_addr = (long) (ptr); \ - __gu_err = access_ok(VERIFY_READ, (void *) __gu_addr, size) \ - ? 0 : -EFAULT; \ + long __gu_err = -EFAULT; \ \ - if (likely(!__gu_err)) { \ + if (likely(access_ok(VERIFY_READ, __gu_addr, size))) { \ switch (size) { \ - case 1: __get_user_asm("lb", __gu_err); break; \ - case 2: __get_user_asm("lh", __gu_err); break; \ - case 4: __get_user_asm("lw", __gu_err); break; \ - case 8: __GET_USER_DW(__gu_err); break; \ + case 1: __get_user_asm("lb", __gu_addr); break; \ + case 2: __get_user_asm("lh", __gu_addr); break; \ + case 4: __get_user_asm("lw", __gu_addr); break; \ + case 8: __GET_USER_DW(__gu_addr); break; \ default: __get_user_unknown(); break; \ } \ } \ - x = (__typeof__(*(ptr))) __gu_val; \ + (x) = (__typeof__(*(ptr))) __gu_val; \ __gu_err; \ }) -#define __get_user_asm(insn,__gu_err) \ -({ \ +#define __get_user_asm(insn, addr) \ +{ \ __asm__ __volatile__( \ "1: " insn " %1, %3 \n" \ "2: \n" \ @@ -264,20 +256,20 @@ struct __large_struct { unsigned long buf[100]; }; " "__UA_ADDR "\t1b, 3b \n" \ " .previous \n" \ : "=r" (__gu_err), "=r" (__gu_val) \ - : "0" (__gu_err), "o" (__m(__gu_addr)), "i" (-EFAULT)); \ -}) + : "0" (0), "o" (__m(addr)), "i" (-EFAULT)); \ +} /* * Get a long long 64 using 32 bit registers. */ -#define __get_user_asm_ll32(__gu_err) \ -({ \ +#define __get_user_asm_ll32(addr) \ +{ \ __asm__ __volatile__( \ - "1: lw %1, %3 \n" \ - "2: lw %D1, %4 \n" \ + "1: lw %1, (%3) \n" \ + "2: lw %D1, 4(%3) \n" \ " move %0, $0 \n" \ "3: .section .fixup,\"ax\" \n" \ - "4: li %0, %5 \n" \ + "4: li %0, %4 \n" \ " move %1, $0 \n" \ " move %D1, $0 \n" \ " j 3b \n" \ @@ -287,9 +279,8 @@ struct __large_struct { unsigned long buf[100]; }; " " __UA_ADDR " 2b, 4b \n" \ " .previous \n" \ : "=r" (__gu_err), "=&r" (__gu_val) \ - : "0" (__gu_err), "o" (__m(__gu_addr)), \ - "o" (__m(__gu_addr + 4)), "i" (-EFAULT)); \ -}) + : "0" (0), "r" (addr), "i" (-EFAULT)); \ +} extern void __get_user_unknown(void); @@ -298,25 +289,22 @@ extern void __get_user_unknown(void); * for 32 bit mode and old iron. */ #ifdef __mips64 -#define __PUT_USER_DW(__pu_val) __put_user_asm("sd", __pu_val) +#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr) #else -#define __PUT_USER_DW(__pu_val) __put_user_asm_ll32(__pu_val) +#define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr) #endif #define __put_user_nocheck(x,ptr,size) \ ({ \ __typeof__(*(ptr)) __pu_val; \ - long __pu_addr; \ long __pu_err = 0; \ \ - might_sleep(); \ __pu_val = (x); \ - __pu_addr = (long) (ptr); \ switch (size) { \ - case 1: __put_user_asm("sb", __pu_val); break; \ - case 2: __put_user_asm("sh", __pu_val); break; \ - case 4: __put_user_asm("sw", __pu_val); break; \ - case 8: __PUT_USER_DW(__pu_val); break; \ + case 1: __put_user_asm("sb", ptr); break; \ + case 2: __put_user_asm("sh", ptr); break; \ + case 4: __put_user_asm("sw", ptr); break; \ + case 8: __PUT_USER_DW(ptr); break; \ default: __put_user_unknown(); break; \ } \ __pu_err; \ @@ -324,30 +312,24 @@ extern void __get_user_unknown(void); #define __put_user_check(x,ptr,size) \ ({ \ - __typeof__(*(ptr)) __pu_val; \ - long __pu_addr; \ - long __pu_err; \ + __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ + __typeof__(*(ptr)) __pu_val = (x); \ + long __pu_err = -EFAULT; \ \ - might_sleep(); \ - __pu_val = (x); \ - __pu_addr = (long) (ptr); \ - __pu_err = access_ok(VERIFY_WRITE, (void *) __pu_addr, size) \ - ? 0 : -EFAULT; \ - \ - if (likely(!__pu_err)) { \ + if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \ switch (size) { \ - case 1: __put_user_asm("sb", __pu_val); break; \ - case 2: __put_user_asm("sh", __pu_val); break; \ - case 4: __put_user_asm("sw", __pu_val); break; \ - case 8: __PUT_USER_DW(__pu_val); break; \ + case 1: __put_user_asm("sb", __pu_addr); break; \ + case 2: __put_user_asm("sh", __pu_addr); break; \ + case 4: __put_user_asm("sw", __pu_addr); break; \ + case 8: __PUT_USER_DW(__pu_addr); break; \ default: __put_user_unknown(); break; \ } \ } \ __pu_err; \ }) -#define __put_user_asm(insn, __pu_val) \ -({ \ +#define __put_user_asm(insn, ptr) \ +{ \ __asm__ __volatile__( \ "1: " insn " %z2, %3 # __put_user_asm\n" \ "2: \n" \ @@ -359,18 +341,18 @@ extern void __get_user_unknown(void); " " __UA_ADDR " 1b, 3b \n" \ " .previous \n" \ : "=r" (__pu_err) \ - : "0" (__pu_err), "Jr" (__pu_val), "o" (__m(__pu_addr)), \ + : "0" (0), "Jr" (__pu_val), "o" (__m(ptr)), \ "i" (-EFAULT)); \ -}) +} -#define __put_user_asm_ll32(__pu_val) \ -({ \ +#define __put_user_asm_ll32(ptr) \ +{ \ __asm__ __volatile__( \ - "1: sw %2, %3 # __put_user_asm_ll32 \n" \ - "2: sw %D2, %4 \n" \ + "1: sw %2, (%3) # __put_user_asm_ll32 \n" \ + "2: sw %D2, 4(%3) \n" \ "3: \n" \ " .section .fixup,\"ax\" \n" \ - "4: li %0, %5 \n" \ + "4: li %0, %4 \n" \ " j 3b \n" \ " .previous \n" \ " .section __ex_table,\"a\" \n" \ @@ -378,9 +360,9 @@ extern void __get_user_unknown(void); " " __UA_ADDR " 2b, 4b \n" \ " .previous" \ : "=r" (__pu_err) \ - : "0" (__pu_err), "r" (__pu_val), "o" (__m(__pu_addr)), \ - "o" (__m(__pu_addr + 4)), "i" (-EFAULT)); \ -}) + : "0" (0), "r" (__pu_val), "r" (ptr), \ + "i" (-EFAULT)); \ +} extern void __put_user_unknown(void); @@ -403,7 +385,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); #define __invoke_copy_to_user(to,from,n) \ ({ \ - register void *__cu_to_r __asm__ ("$4"); \ + register void __user *__cu_to_r __asm__ ("$4"); \ register const void *__cu_from_r __asm__ ("$5"); \ register long __cu_len_r __asm__ ("$6"); \ \ @@ -435,7 +417,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); */ #define __copy_to_user(to,from,n) \ ({ \ - void *__cu_to; \ + void __user *__cu_to; \ const void *__cu_from; \ long __cu_len; \ \ @@ -465,7 +447,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); */ #define copy_to_user(to,from,n) \ ({ \ - void *__cu_to; \ + void __user *__cu_to; \ const void *__cu_from; \ long __cu_len; \ \ @@ -482,7 +464,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); #define __invoke_copy_from_user(to,from,n) \ ({ \ register void *__cu_to_r __asm__ ("$4"); \ - register const void *__cu_from_r __asm__ ("$5"); \ + register const void __user *__cu_from_r __asm__ ("$5"); \ register long __cu_len_r __asm__ ("$6"); \ \ __cu_to_r = (to); \ @@ -521,7 +503,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); #define __copy_from_user(to,from,n) \ ({ \ void *__cu_to; \ - const void *__cu_from; \ + const void __user *__cu_from; \ long __cu_len; \ \ might_sleep(); \ @@ -552,7 +534,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); #define copy_from_user(to,from,n) \ ({ \ void *__cu_to; \ - const void *__cu_from; \ + const void __user *__cu_from; \ long __cu_len; \ \ might_sleep(); \ @@ -569,8 +551,8 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); #define copy_in_user(to,from,n) \ ({ \ - void *__cu_to; \ - const void *__cu_from; \ + void __user *__cu_to; \ + const void __user *__cu_from; \ long __cu_len; \ \ might_sleep(); \ @@ -596,7 +578,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); * On success, this will be zero. */ static inline __kernel_size_t -__clear_user(void *addr, __kernel_size_t size) +__clear_user(void __user *addr, __kernel_size_t size) { __kernel_size_t res; @@ -616,7 +598,7 @@ __clear_user(void *addr, __kernel_size_t size) #define clear_user(addr,n) \ ({ \ - void * __cl_addr = (addr); \ + void __user * __cl_addr = (addr); \ unsigned long __cl_size = (n); \ if (__cl_size && access_ok(VERIFY_WRITE, \ ((unsigned long)(__cl_addr)), __cl_size)) \ @@ -645,7 +627,7 @@ __clear_user(void *addr, __kernel_size_t size) * and returns @count. */ static inline long -__strncpy_from_user(char *__to, const char *__from, long __len) +__strncpy_from_user(char *__to, const char __user *__from, long __len) { long res; @@ -682,7 +664,7 @@ __strncpy_from_user(char *__to, const char *__from, long __len) * and returns @count. */ static inline long -strncpy_from_user(char *__to, const char *__from, long __len) +strncpy_from_user(char *__to, const char __user *__from, long __len) { long res; @@ -701,7 +683,7 @@ strncpy_from_user(char *__to, const char *__from, long __len) } /* Returns: 0 if bad, string length+1 (memory size) of string if ok */ -static inline long __strlen_user(const char *s) +static inline long __strlen_user(const char __user *s) { long res; @@ -731,7 +713,7 @@ static inline long __strlen_user(const char *s) * If there is a limit on the length of a valid string, you may wish to * consider using strnlen_user() instead. */ -static inline long strlen_user(const char *s) +static inline long strlen_user(const char __user *s) { long res; @@ -748,7 +730,7 @@ static inline long strlen_user(const char *s) } /* Returns: 0 if bad, string length+1 (memory size) of string if ok */ -static inline long __strnlen_user(const char *s, long n) +static inline long __strnlen_user(const char __user *s, long n) { long res; @@ -779,7 +761,7 @@ static inline long __strnlen_user(const char *s, long n) * If there is a limit on the length of a valid string, you may wish to * consider using strnlen_user() instead. */ -static inline long strnlen_user(const char *s, long n) +static inline long strnlen_user(const char __user *s, long n) { long res; diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index ad4d48056307..c9eaf4c104de 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h @@ -303,16 +303,21 @@ #define __NR_add_key (__NR_Linux + 280) #define __NR_request_key (__NR_Linux + 281) #define __NR_keyctl (__NR_Linux + 282) +#define __NR_set_thread_area (__NR_Linux + 283) +#define __NR_inotify_init (__NR_Linux + 284) +#define __NR_inotify_add_watch (__NR_Linux + 285) +#define __NR_inotify_rm_watch (__NR_Linux + 286) + /* * Offset of the last Linux o32 flavoured syscall */ -#define __NR_Linux_syscalls 282 +#define __NR_Linux_syscalls 286 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #define __NR_O32_Linux 4000 -#define __NR_O32_Linux_syscalls 282 +#define __NR_O32_Linux_syscalls 283 #if _MIPS_SIM == _MIPS_SIM_ABI64 @@ -562,16 +567,20 @@ #define __NR_add_key (__NR_Linux + 239) #define __NR_request_key (__NR_Linux + 240) #define __NR_keyctl (__NR_Linux + 241) +#define __NR_set_thread_area (__NR_Linux + 242) +#define __NR_inotify_init (__NR_Linux + 243) +#define __NR_inotify_add_watch (__NR_Linux + 244) +#define __NR_inotify_rm_watch (__NR_Linux + 245) /* * Offset of the last Linux 64-bit flavoured syscall */ -#define __NR_Linux_syscalls 241 +#define __NR_Linux_syscalls 245 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ #define __NR_64_Linux 5000 -#define __NR_64_Linux_syscalls 241 +#define __NR_64_Linux_syscalls 242 #if _MIPS_SIM == _MIPS_SIM_NABI32 @@ -825,16 +834,20 @@ #define __NR_add_key (__NR_Linux + 243) #define __NR_request_key (__NR_Linux + 244) #define __NR_keyctl (__NR_Linux + 245) +#define __NR_set_thread_area (__NR_Linux + 246) +#define __NR_inotify_init (__NR_Linux + 247) +#define __NR_inotify_add_watch (__NR_Linux + 248) +#define __NR_inotify_rm_watch (__NR_Linux + 249) /* * Offset of the last N32 flavoured syscall */ -#define __NR_Linux_syscalls 245 +#define __NR_Linux_syscalls 249 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ #define __NR_N32_Linux 6000 -#define __NR_N32_Linux_syscalls 245 +#define __NR_N32_Linux_syscalls 246 #ifndef __ASSEMBLY__ diff --git a/include/asm-mips/vga.h b/include/asm-mips/vga.h index 6b35cf054c79..ca5cec97e167 100644 --- a/include/asm-mips/vga.h +++ b/include/asm-mips/vga.h @@ -6,6 +6,8 @@ #ifndef _ASM_VGA_H #define _ASM_VGA_H +#include <asm/byteorder.h> + /* * On the PC, we can just recalculate addresses and then * access the videoram directly without any black magic. @@ -16,4 +18,27 @@ #define vga_readb(x) (*(x)) #define vga_writeb(x,y) (*(y) = (x)) +#define VT_BUF_HAVE_RW +/* + * These are only needed for supporting VGA or MDA text mode, which use little + * endian byte ordering. + * In other cases, we can optimize by using native byte ordering and + * <linux/vt_buffer.h> has already done the right job for us. + */ + +static inline void scr_writew(u16 val, volatile u16 *addr) +{ + *addr = cpu_to_le16(val); +} + +static inline u16 scr_readw(volatile const u16 *addr) +{ + return le16_to_cpu(*addr); +} + +#define scr_memcpyw(d, s, c) memcpy(d, s, c) +#define scr_memmovew(d, s, c) memmove(d, s, c) +#define VT_BUF_HAVE_MEMCPYW +#define VT_BUF_HAVE_MEMMOVEW + #endif /* _ASM_VGA_H */ diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index 04ee53b34c2e..ad374bd3f130 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -177,6 +177,17 @@ #endif /* + * The RM9000 has a bug (though PMC-Sierra opposes it being called that) + * where invalid instructions in the same I-cache line worth of instructions + * being fetched may case spurious exceptions. + */ +#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ + defined(CONFIG_PMC_YOSEMITE) +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#endif + + +/* * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. */ @@ -187,6 +198,9 @@ /* * Workarounds default to off */ +#ifndef ICACHE_REFILLS_WORKAROUND_WAR +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#endif #ifndef R4600_V1_INDEX_ICACHEOP_WAR #define R4600_V1_INDEX_ICACHEOP_WAR 0 #endif diff --git a/include/linux/ide.h b/include/linux/ide.h index a6dbb51ecd7b..3461abc1e854 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -218,7 +218,7 @@ typedef enum { ide_unknown, ide_generic, ide_pci, ide_rz1000, ide_trm290, ide_cmd646, ide_cy82c693, ide_4drives, ide_pmac, ide_etrax100, ide_acorn, - ide_forced + ide_au1xxx, ide_forced } hwif_chipset_t; /* diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index 27db8da43aa4..2b0401b93f2b 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -39,7 +39,8 @@ #define PORT_RSA 13 #define PORT_NS16550A 14 #define PORT_XSCALE 15 -#define PORT_MAX_8250 15 /* max port ID */ +#define PORT_IP3106 16 +#define PORT_MAX_8250 16 /* max port ID */ /* * ARM specific type numbers. These are not currently guaranteed diff --git a/include/linux/serial_ip3106.h b/include/linux/serial_ip3106.h new file mode 100644 index 000000000000..f500ac602c5c --- /dev/null +++ b/include/linux/serial_ip3106.h @@ -0,0 +1,81 @@ +/* + * Embedded Alley Solutions, source@embeddedalley.com. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _LINUX_SERIAL_IP3106_H +#define _LINUX_SERIAL_IP3106_H + +#include <linux/serial_core.h> +#include <linux/device.h> + +#define IP3106_NR_PORTS 2 + +struct ip3106_port { + struct uart_port port; + struct timer_list timer; + unsigned int old_status; +}; + +/* register offsets */ +#define IP3106_LCR 0 +#define IP3106_MCR 0x004 +#define IP3106_BAUD 0x008 +#define IP3106_CFG 0x00c +#define IP3106_FIFO 0x028 +#define IP3106_ISTAT 0xfe0 +#define IP3106_IEN 0xfe4 +#define IP3106_ICLR 0xfe8 +#define IP3106_ISET 0xfec +#define IP3106_PD 0xff4 +#define IP3106_MID 0xffc + +#define IP3106_UART_LCR_TXBREAK (1<<30) +#define IP3106_UART_LCR_PAREVN 0x10000000 +#define IP3106_UART_LCR_PAREN 0x08000000 +#define IP3106_UART_LCR_2STOPB 0x04000000 +#define IP3106_UART_LCR_8BIT 0x01000000 +#define IP3106_UART_LCR_TX_RST 0x00040000 +#define IP3106_UART_LCR_RX_RST 0x00020000 +#define IP3106_UART_LCR_RX_NEXT 0x00010000 + +#define IP3106_UART_MCR_SCR 0xFF000000 +#define IP3106_UART_MCR_DCD 0x00800000 +#define IP3106_UART_MCR_CTS 0x00100000 +#define IP3106_UART_MCR_LOOP 0x00000010 +#define IP3106_UART_MCR_RTS 0x00000002 +#define IP3106_UART_MCR_DTR 0x00000001 + +#define IP3106_UART_INT_TX 0x00000080 +#define IP3106_UART_INT_EMPTY 0x00000040 +#define IP3106_UART_INT_RCVTO 0x00000020 +#define IP3106_UART_INT_RX 0x00000010 +#define IP3106_UART_INT_RXOVRN 0x00000008 +#define IP3106_UART_INT_FRERR 0x00000004 +#define IP3106_UART_INT_BREAK 0x00000002 +#define IP3106_UART_INT_PARITY 0x00000001 +#define IP3106_UART_INT_ALLRX 0x0000003F +#define IP3106_UART_INT_ALLTX 0x000000C0 + +#define IP3106_UART_FIFO_TXFIFO 0x001F0000 +#define IP3106_UART_FIFO_TXFIFO_STA (0x1f<<16) +#define IP3106_UART_FIFO_RXBRK 0x00008000 +#define IP3106_UART_FIFO_RXFE 0x00004000 +#define IP3106_UART_FIFO_RXPAR 0x00002000 +#define IP3106_UART_FIFO_RXFIFO 0x00001F00 +#define IP3106_UART_FIFO_RBRTHR 0x000000FF + +#endif diff --git a/sound/oss/au1550_ac97.c b/sound/oss/au1550_ac97.c index a78e48d412d2..6b46a8a4b1cc 100644 --- a/sound/oss/au1550_ac97.c +++ b/sound/oss/au1550_ac97.c @@ -35,7 +35,6 @@ #undef DEBUG -#include <linux/version.h> #include <linux/module.h> #include <linux/string.h> #include <linux/ioport.h> |
