<feed xmlns='http://www.w3.org/2005/Atom'>
<title>blackbird-op-linux/drivers/soc/sifive, branch master</title>
<subtitle>Blackbird™ Linux sources for OpenPOWER</subtitle>
<id>https://git.raptorcs.com/git/blackbird-op-linux/atom?h=master</id>
<link rel='self' href='https://git.raptorcs.com/git/blackbird-op-linux/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/blackbird-op-linux/'/>
<updated>2020-01-12T18:12:44+00:00</updated>
<entry>
<title>riscv: move sifive_l2_cache.h to include/soc</title>
<updated>2020-01-12T18:12:44+00:00</updated>
<author>
<name>Yash Shah</name>
<email>yash.shah@sifive.com</email>
</author>
<published>2020-01-08T06:09:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/blackbird-op-linux/commit/?id=13cf4cf030183dd9a8731f3fe32456e83b6c7b68'/>
<id>urn:sha1:13cf4cf030183dd9a8731f3fe32456e83b6c7b68</id>
<content type='text'>
The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
moves the sifive L2 cache driver to driver/soc. It did not move the
header file along with the driver. Therefore this patch moves the header
file to driver/soc

Signed-off-by: Yash Shah &lt;yash.shah@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
[paul.walmsley@sifive.com: updated to fix the include guard]
Fixes: 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
<entry>
<title>riscv: move sifive_l2_cache.c to drivers/soc</title>
<updated>2019-12-20T11:40:24+00:00</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2019-11-07T09:20:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/blackbird-op-linux/commit/?id=9209fb51896fe0eef8dfac85afe1f357e9265c0d'/>
<id>urn:sha1:9209fb51896fe0eef8dfac85afe1f357e9265c0d</id>
<content type='text'>
The sifive_l2_cache.c is in no way related to RISC-V architecture
memory management.  It is a little stub driver working around the fact
that the EDAC maintainers prefer their drivers to be structured in a
certain way that doesn't fit the SiFive SOCs.

Move the file to drivers/soc and add a Kconfig option for it, as well
as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE.

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Borislav Petkov &lt;bp@suse.de&gt;
[paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code]
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
</feed>
