blackbird-op-linux/drivers/mmc, branch master

Merge tag 'ioremap-5.6' of git://git.infradead.org/users/hch/ioremap

2020-01-27T21:03:00+00:00

Pull ioremap updates from Christoph Hellwig: "Remove the ioremap_nocache API (plus wrappers) that are always identical to ioremap" * tag 'ioremap-5.6' of git://git.infradead.org/users/hch/ioremap: remove ioremap_nocache and devm_ioremap_nocache MIPS: define ioremap_nocache to ioremap

mmc: core: Default to generic_cmd6_time as timeout in __mmc_switch()

2020-01-24T11:17:05+00:00

All callers of __mmc_switch() should now be specifying a valid timeout for the CMD6 command. However, just to be sure, let's print a warning and default to use the generic_cmd6_time in case the provided timeout_ms argument is zero. In this context, let's also simplify some of the corresponding code and clarify some related comments. Signed-off-by: Ulf Hansson Link: https://lore.kernel.org/r/20200122142747.5690-4-ulf.hansson@linaro.org

mmc: block: Use generic_cmd6_time when modifying INAND_CMD38_ARG_EXT_CSD

2020-01-24T11:16:05+00:00

The INAND_CMD38_ARG_EXT_CSD is a vendor specific EXT_CSD register, which is used to prepare an erase/trim operation. However, it doesn't make sense to use a timeout of 10 minutes while updating the register, which becomes the case when the timeout_ms argument for mmc_switch() is set to zero. Instead, let's use the generic_cmd6_time, as that seems like a reasonable timeout to use for these cases. Signed-off-by: Ulf Hansson Link: https://lore.kernel.org/r/20200122142747.5690-3-ulf.hansson@linaro.org

mmc: core: Specify timeouts for BKOPS and CACHE_FLUSH for eMMC

2020-01-24T11:16:05+00:00

The timeout values used while waiting for a CMD6 for BKOPS or a CACHE_FLUSH to complete, are not defined by the eMMC spec. However, a timeout of 10 minutes as is currently being used, is just silly for both of these cases. Instead, let's specify more reasonable timeouts, 120s for BKOPS and 30s for CACHE_FLUSH. Signed-off-by: Ulf Hansson Link: https://lore.kernel.org/r/20200122142747.5690-2-ulf.hansson@linaro.org

mmc: sdhci-cadence: remove unneeded 'inline' marker

2020-01-24T11:14:31+00:00

'static inline' in .c files does not make much sense because functions may or may not be inlined irrespective of the 'inline' marker. It is just a hint. This function is quite small, so very likely to be inlined by the compiler's optimization (-O2 or -Os), but it is up to the compiler after all. Signed-off-by: Masahiro Yamada Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/20200121105858.13325-1-yamada.masahiro@socionext.com Signed-off-by: Ulf Hansson

mmc: sdhci-msm: Add CQHCI support for sdhci-msm

2020-01-24T11:11:48+00:00

This adds CQHCI support for sdhci-msm platforms. Signed-off-by: Ritesh Harjani Signed-off-by: Veerabhadrarao Badiganti Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/1579194192-7942-3-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson

mmc: sdhci: Let a vendor driver supply and update ADMA descriptor size

2020-01-24T11:11:48+00:00

Let a vendor driver supply the maximum descriptor size that it can operate on. ADMA descriptor table would be allocated using this supplied size. If any SD Host controller is of version prior to v4.10 spec but supports 16byte descriptor, this change allows them to supply correct descriptor size for ADMA table allocation. Also let a vendor driver update the descriptor size by overriding sdhc_host->desc_size if it has to operates on a different descriptor sizes in different conditions. Suggested-by: Adrian Hunter Signed-off-by: Veerabhadrarao Badiganti Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/1579531122-28341-1-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson

mmc: sdhci-of-esdhc: fix serious issue clock is always disabled

2020-01-20T11:10:36+00:00

This patch is to fix a serious issue that clock is always disabled in esdhc_of_set_clock(). Fixes: 1b21a701aed9 ("mmc: sdhci-of-esdhc: fix clock setting for different controller versions") Signed-off-by: Yangbo Lu Link: https://lore.kernel.org/r/20200120094835.28050-1-yangbo.lu@nxp.com Signed-off-by: Ulf Hansson

mmc: sdhci-of-esdhc: fix transfer mode register reading

2020-01-20T11:10:24+00:00

The standard SD controller uses two 16-bit registers for command sending. 0xC: Transfer Mode Register 0xE: Command Register But the eSDHC controller uses one 32-bit register instead. 0xC: XFERTYPE For Transfer Mode Register and Command Register writing, the eSDHC driver will store Transfer Mode Register value in a variable first. When Command Register writing happens, driver will directly write a 32-bit value into XFERTYPE register. But for Transfer Mode Register reading, driver just returns a actual value. This may cause issue for some read-modify-write operations. We should make both reading and write on that variable for Transfer Mode Register. Signed-off-by: Yangbo Lu Link: https://lore.kernel.org/r/20200117063858.37296-1-yangbo.lu@nxp.com Signed-off-by: Ulf Hansson

mmc: sdhci-brcmstb: Fix incorrect switch to HS mode

2020-01-20T11:01:19+00:00

When switching from any MMC speed mode that requires 1.8v (HS200, HS400 and HS400ES) to High Speed (HS) mode, the system ends up configured for SDR12 with a 50MHz clock which is an illegal mode. This happens because the SDHCI_CTRL_VDD_180 bit in the SDHCI_HOST_CONTROL2 register is left set and when this bit is set, the speed mode is controlled by the SDHCI_CTRL_UHS field in the SDHCI_HOST_CONTROL2 register. The SDHCI_CTRL_UHS field will end up being set to 0 (SDR12) by sdhci_set_uhs_signaling() because there is no UHS mode being set. The fix is to change sdhci_set_uhs_signaling() to set the SDHCI_CTRL_UHS field to SDR25 (which is the same as HS) for any switch to HS mode. This was found on a new eMMC controller that does strict checking of the speed mode and the corresponding clock rate. It caused the switch to HS400 mode to fail because part of the sequence to switch to HS400 requires a switch from HS200 to HS before going to HS400. This issue was previously fixed by commit c894e33ddc191 ("mmc: sdhci: Fix incorrect switch to HS mode") and later removed by commit 07bcc411567c ("Revert \"mmc: sdhci: Fix incorrect switch to HS mode\"") because it caused failures with some SD cards on AM65X systems. The fix will now be done in a platform specific callback instead of common sdhci code. Signed-off-by: Al Cooper Suggested-by: Adrian Hunter Link: https://lore.kernel.org/r/20200113210706.11972-7-alcooperx@gmail.com Signed-off-by: Ulf Hansson