<feed xmlns='http://www.w3.org/2005/Atom'>
<title>blackbird-op-linux/drivers/gpu/drm/amd/display/dc, branch master</title>
<subtitle>Blackbird™ Linux sources for OpenPOWER</subtitle>
<id>https://git.raptorcs.com/git/blackbird-op-linux/atom?h=master</id>
<link rel='self' href='https://git.raptorcs.com/git/blackbird-op-linux/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/blackbird-op-linux/'/>
<updated>2020-02-11T20:39:45+00:00</updated>
<entry>
<title>drm/amd/display: DCN2.x Do not program DPPCLK if same value</title>
<updated>2020-02-11T20:39:45+00:00</updated>
<author>
<name>Sung Lee</name>
<email>sung.lee@amd.com</email>
</author>
<published>2020-02-04T20:49:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/blackbird-op-linux/commit/?id=8fab6a2faa1eb388b5eaf1ead4394f380a6403be'/>
<id>urn:sha1:8fab6a2faa1eb388b5eaf1ead4394f380a6403be</id>
<content type='text'>
[WHY]
Programming DPPCLK to the same value currently set may cause
underflow while playing video in certain conditions.

[HOW]
Only program DPPCLK if clock is not the same as the
previous value programmed.

Signed-off-by: Sung Lee &lt;sung.lee@amd.com&gt;
Reviewed-by: Yongqiang Sun &lt;yongqiang.sun@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Don't map ATOM_ENABLE to ATOM_INIT</title>
<updated>2020-02-11T20:38:27+00:00</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2020-01-20T19:56:31+00:00</published>
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<id>urn:sha1:1094c34ec53bc147e53f52ed9fe50899ad075632</id>
<content type='text'>
[Why]
In DCN hardware sequencer we do actually call ATOM_INIT correctly per
pipe. The workaround is not necessary for command table offloading.

[How]
Drop the workaround since it's not needed.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Chris Park &lt;Chris.Park@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>amdgpu: Prevent build errors regarding soft/hard-float FP ABI tags</title>
<updated>2020-02-11T20:35:22+00:00</updated>
<author>
<name>Daniel Kolesa</name>
<email>daniel@octaforge.org</email>
</author>
<published>2020-02-06T19:14:35+00:00</published>
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<id>urn:sha1:416611d9b6eebaeae58ed26cc7d23131c69126b1</id>
<content type='text'>
On PowerPC, the compiler will tag object files with whether they
use hard or soft float FP ABI and whether they use 64 or 128-bit
long double ABI. On systems with 64-bit long double ABI, a tag
will get emitted whenever a double is used, as on those systems
a long double is the same as a double. This will prevent linkage
as other files are being compiled with hard-float.

On ppc64, this code will never actually get used for the time
being, as the only currently existing hardware using it are the
Renoir APUs. Therefore, until this is testable and can be fixed
properly, at least make sure the build will not fail.

Signed-off-by: Daniel Kolesa &lt;daniel@octaforge.org&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add initialitions for PLL2 clock source</title>
<updated>2020-02-11T20:09:18+00:00</updated>
<author>
<name>Isabel Zhang</name>
<email>isabel.zhang@amd.com</email>
</author>
<published>2020-01-27T15:57:16+00:00</published>
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<id>urn:sha1:c134c3cabae46a56ab2e1f5e5fa49405e1758838</id>
<content type='text'>
[Why]
Starting from 14nm, the PLL is built into the PHY and the PLL is mapped
to PHY on 1 to 1 basis. In the code, the DP port is mapped to a PLL that was not
initialized. This causes DP to HDMI dongle to not light up the display.

[How]
Initializations added for PLL2 when creating resources.

Signed-off-by: Isabel Zhang &lt;isabel.zhang@amd.com&gt;
Reviewed-by: Eric Yang &lt;eric.yang2@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Limit minimum DPPCLK to 100MHz.</title>
<updated>2020-02-11T20:08:13+00:00</updated>
<author>
<name>Yongqiang Sun</name>
<email>yongqiang.sun@amd.com</email>
</author>
<published>2020-01-23T21:30:15+00:00</published>
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<id>urn:sha1:6c81917a0485ee2a1be0dc23321ac10ecfd9578b</id>
<content type='text'>
[Why]
Underflow is observed when plug in a 4K@60 monitor with
1366x768 eDP due to DPPCLK is too low.

[How]
Limit minimum DPPCLK to 100MHz.

Signed-off-by: Yongqiang Sun &lt;yongqiang.sun@amd.com&gt;
Reviewed-by: Eric Yang &lt;eric.yang2@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Check engine is not NULL before acquiring</title>
<updated>2020-02-11T20:07:03+00:00</updated>
<author>
<name>Aric Cyr</name>
<email>aric.cyr@amd.com</email>
</author>
<published>2020-01-22T03:50:13+00:00</published>
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<id>urn:sha1:2b63d0ec0daf79ba503fa8bfa25e07dc3da274f3</id>
<content type='text'>
[Why]
Engine can be NULL in some cases, so we must not acquire it.

[How]
Check for NULL engine before acquiring.

Signed-off-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Use dcfclk to populate watermark ranges</title>
<updated>2020-02-11T17:15:02+00:00</updated>
<author>
<name>Sung Lee</name>
<email>sung.lee@amd.com</email>
</author>
<published>2020-01-20T23:58:45+00:00</published>
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<id>urn:sha1:aad927b5a863178a9d921044e52d66e0ccf0aff9</id>
<content type='text'>
[WHY &amp; HOW]
Previously drain clk was unconstrained and fill clk was constrained on fclk.
We want to change it to fill clk unconstrained and drain clock constrained
to dcfclk.

Signed-off-by: Sung Lee &lt;sung.lee@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Do not set optimized_require to false after plane disable</title>
<updated>2020-02-11T17:12:31+00:00</updated>
<author>
<name>Sung Lee</name>
<email>sung.lee@amd.com</email>
</author>
<published>2020-01-15T16:55:06+00:00</published>
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<id>urn:sha1:df36f6cf23ada812930afa8ee76681d4ad307c61</id>
<content type='text'>
[WHY]
The optimized_require flag is needed to set watermarks and clocks lower
in certain conditions. This flag is set to true and then set to false
while programming front end in dcn20.

[HOW]
Do not set the flag to false while disabling plane.

Signed-off-by: Sung Lee &lt;sung.lee@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/display: handle multiple numbers of fclks in dcn_calcs.c (v2)</title>
<updated>2020-02-04T15:37:52+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-01-28T19:39:45+00:00</published>
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<id>urn:sha1:c37243579d6c881c575dcfb54cf31c9ded88f946</id>
<content type='text'>
We might get different numbers of clocks from powerplay depending
on what the OEM has populated.

v2: add assert for at least one level

Bug: https://gitlab.freedesktop.org/drm/amd/issues/963
Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Only enable cursor on pipes that need it</title>
<updated>2020-02-04T15:32:22+00:00</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2020-01-30T18:29:05+00:00</published>
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<id>urn:sha1:c6a228be7f440ad5c341b3039f6033d4a8f070a4</id>
<content type='text'>
[Why]
In current code we're essentially drawing the cursor on every pipe
that contains it. This only works when the planes have the same
scaling for src to dest rect, otherwise we'll get "double cursor" where
one cursor is incorrectly filtered and offset from the real position.

[How]
Without dedicated cursor planes on DCN we require at least one pipe
that matches the scaling of the current timing.

This is an optimization and workaround for the most common case where
the top-most plane is not scaled but the bottom-most plane is scaled.

Whenever a pipe has a parent pipe in the blending tree whose recout
fully contains the current pipe we can disable the pipe.

This only applies when the pipe is actually visible of course.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
