blackbird-op-linux/drivers/gpu/drm/amd/display/dc/dcn21, branch master

drm/amd/display: Add initialitions for PLL2 clock source

2020-02-11T20:09:18+00:00

[Why] Starting from 14nm, the PLL is built into the PHY and the PLL is mapped to PHY on 1 to 1 basis. In the code, the DP port is mapped to a PLL that was not initialized. This causes DP to HDMI dongle to not light up the display. [How] Initializations added for PLL2 when creating resources. Signed-off-by: Isabel Zhang Reviewed-by: Eric Yang Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: changed max_downscale_src_width to 4096.

2020-01-22T21:55:28+00:00

[Why] MPO isn't enabled on some 4k videos due to video source width is 4096 and the current limit is 3840. [How] Changed the limit to 4096. Signed-off-by: Isabel Zhang Reviewed-by: Tony Cheng Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: fix rotation_angle to use enum values

2020-01-22T21:55:28+00:00

[Why] Hardcoded fixed values are not proper. [How] Use enum values instead of fixed numbers. Signed-off-by: Brandon Syu Reviewed-by: Eric Yang Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: Only program surface flip for video plane via dmcub

2020-01-16T19:16:33+00:00

Only need to do surface flip for video plane via dmcub. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: Use SMU ClockTable Values for DML Calculations

2020-01-16T19:15:35+00:00

[Why] DML Initialization was previously done on dcn21_resource initialization. This meant that DML soc struct was populated with hardcoded values. [How] Move DML initialization to after updating bounding box, to use clock table values from SMU. Signed-off-by: Sung Lee Reviewed-by: Tony Cheng Acked-by: Harry Wentland Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: Add w/a to reset PHY before link training in verify_link_cap

2020-01-16T19:15:17+00:00

[Why] PHY will sometimes be in bad state on hotplugging display from USB-C dongle. [How] Add additional calls to disable and then enable PHY before link training starts during verify_link_cap. Signed-off-by: George Shen Reviewed-by: Tony Cheng Acked-by: Harry Wentland Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: Refactor surface flip programming

2020-01-16T19:14:02+00:00

Rework surface programming for RN to separate preparing parameters and register programming. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: Indirect reg read macro with shift and mask

2020-01-16T19:13:53+00:00

[Why] Recent double buffering changes for dcn2 use IX_REG_READ. However, this macro returns the full register value, with the need to manually shift and mask it to retrieve field data. [How] Create new IX_REG_GET macro that handles shift and mask. Use this for double buffering reads instead of IX_REG_READ. Signed-off-by: Noah Abradjian Reviewed-by: Tony Cheng Acked-by: Harry Wentland Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: programing surface flip by dmcub.

2020-01-16T19:13:38+00:00

Programming surface flip addresses via dmcub uC for optimizing the data flush. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: Driverside changes to support PSR in DMCUB

2020-01-16T19:13:23+00:00

[Why] Moving PSR from DMCU to DMCUB. [How] Add driverside PSR changes required to send inbox messages to fw. These changes are non-functional until the psr structure allocation is uncommented. Signed-off-by: Wyatt Wood Reviewed-by: Nicholas Kazlauskas Acked-by: Harry Wentland Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher