<feed xmlns='http://www.w3.org/2005/Atom'>
<title>blackbird-op-linux/drivers/gpu/drm/amd/display/dc/dce/Makefile, branch master</title>
<subtitle>Blackbird™ Linux sources for OpenPOWER</subtitle>
<id>https://git.raptorcs.com/git/blackbird-op-linux/atom?h=master</id>
<link rel='self' href='https://git.raptorcs.com/git/blackbird-op-linux/atom?h=master'/>
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<updated>2019-05-31T15:39:31+00:00</updated>
<entry>
<title>drm/amd/display: move clk_mgr files to right place</title>
<updated>2019-05-31T15:39:31+00:00</updated>
<author>
<name>Eric Yang</name>
<email>Eric.Yang2@amd.com</email>
</author>
<published>2019-05-07T16:47:37+00:00</published>
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<id>urn:sha1:9b93eb475aa9e7ad856780886cb3c435b6176b76</id>
<content type='text'>
[Why]
Better organization

[How]
Move clk_mgr files under dc/clk_mgr

Signed-off-by: Eric Yang &lt;Eric.Yang2@amd.com&gt;
Reviewed-by: Yongqiang Sun &lt;yongqiang.sun@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: make clk mgr soc specific</title>
<updated>2019-05-31T15:39:29+00:00</updated>
<author>
<name>Eric Yang</name>
<email>Eric.Yang2@amd.com</email>
</author>
<published>2019-04-22T23:39:35+00:00</published>
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<id>urn:sha1:dc88b4a684d284a200c0ecfd8d87179d6f6c89a3</id>
<content type='text'>
[Why]
First step of refactoring clk mgr to better handle different
ways of handling clock operations. Clock operation policies are
soc specific and not just DCN vesion specific. It is not a hw resource,
should not be in the resource pool.

[How]
Change clock manager creation to be based on HW internal ID, rename
clock manager members to be more clear. Move clock manager out of
resource.

Signed-off-by: Eric Yang &lt;Eric.Yang2@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: rename dccg to clk_mgr</title>
<updated>2018-11-05T19:20:48+00:00</updated>
<author>
<name>Dmytro Laktyushkin</name>
<email>Dmytro.Laktyushkin@amd.com</email>
</author>
<published>2018-09-28T11:46:42+00:00</published>
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<id>urn:sha1:84e7fc05a92700297f1de945251fa3b14349532c</id>
<content type='text'>
In preparation for adding the actual dccg block since the
current implementation of dccg is mor eof a clock manager
than a hw block

Signed-off-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: split dccg clock manager into asic folders</title>
<updated>2018-11-05T19:20:42+00:00</updated>
<author>
<name>Dmytro Laktyushkin</name>
<email>Dmytro.Laktyushkin@amd.com</email>
</author>
<published>2018-09-24T19:28:00+00:00</published>
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<id>urn:sha1:4c5e8b54152795581a67bea94dcfe1393a955013</id>
<content type='text'>
Currently dccg contains code related to every dcn revision in
a single file.

This change splits out the dcn parts of code into correct folders

Signed-off-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Create new i2c resource</title>
<updated>2018-08-27T16:11:05+00:00</updated>
<author>
<name>David Francis</name>
<email>David.Francis@amd.com</email>
</author>
<published>2018-07-23T18:12:10+00:00</published>
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<id>urn:sha1:c85e6e546edd7e362693218a33a6f63217802fd3</id>
<content type='text'>
[Why]
I2C code did not match dc resource model and was generally
unpleasant

[How]
Move code into new svelte dce_i2c files, replacing various i2c
objects with two structs: dce_i2c_sw and dce_i2c_hw.  Fully split
sw and hw code paths.  Remove all redundant declarations.  Use
address lists to distinguish between versions.  Change dce80 code
to newer register access macros.

Signed-off-by: David Francis &lt;David.Francis@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Decouple aux from i2c</title>
<updated>2018-07-24T20:15:50+00:00</updated>
<author>
<name>Bhawanpreet Lakha</name>
<email>Bhawanpreet.Lakha@amd.com</email>
</author>
<published>2018-07-10T21:20:17+00:00</published>
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<id>urn:sha1:5c6ac7112fb2b73a5e4e7ac1648cdaceb558f268</id>
<content type='text'>
[Why]
Aux engine is created from i2caux layer. We want to remove this layer
and use the engine directly.

[How]
Decouple aux engine from i2caux. Move aux engine related code to dce folder and use
dc resource pool to manage the engine. And use the engine functions directly

Signed-off-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Reviewed-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add license to Makefiles</title>
<updated>2017-12-04T16:47:55+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-12-01T02:15:50+00:00</published>
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<id>urn:sha1:e2874a3c8c0c3b251d288a6149a80b9fd1c2f019</id>
<content type='text'>
Was missing license text.

Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Acked-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: dce120 to dce ipp refactor</title>
<updated>2017-09-26T22:06:38+00:00</updated>
<author>
<name>Dmytro Laktyushkin</name>
<email>Dmytro.Laktyushkin@amd.com</email>
</author>
<published>2017-04-24T19:20:24+00:00</published>
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<id>urn:sha1:86b6a203b966ea54e3225b49e53769cf4c116905</id>
<content type='text'>
Signed-off-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Acked-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: DMCU Compile and Load</title>
<updated>2017-09-26T21:12:52+00:00</updated>
<author>
<name>Anthony Koo</name>
<email>Anthony.Koo@amd.com</email>
</author>
<published>2017-01-23T21:55:20+00:00</published>
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<id>urn:sha1:5e7773a219f7821163ad2b17be0d02f8be8ce0c6</id>
<content type='text'>
Signed-off-by: Anthony Koo &lt;anthony.koo@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: OPP refactor and consolidation for DCE.</title>
<updated>2017-09-26T21:05:47+00:00</updated>
<author>
<name>Zeyu Fan</name>
<email>Zeyu.Fan@amd.com</email>
</author>
<published>2016-12-14T23:54:41+00:00</published>
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<id>urn:sha1:ab3ee7a556343c9549ccbefb9d31039377806f28</id>
<content type='text'>
Signed-off-by: Zeyu Fan &lt;Zeyu.Fan@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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