blackbird-op-linux/drivers/clk/zynqmp, branch master

clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag

2020-01-23T21:25:37+00:00

Existing clock divider functions is not checking for base of divider. So, if any clock divider is power of 2 then clock rate calculation will be wrong. Add support to calculate divider value for the clocks with CLK_DIVIDER_POWER_OF_TWO flag. Signed-off-by: Tejas Patel Signed-off-by: Radhey Shyam Pandey Signed-off-by: Rajan Vaja Link: https://lkml.kernel.org/r/1575527759-26452-7-git-send-email-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd

clk: zynqmp: Fix divider calculation

2020-01-23T21:25:37+00:00

zynqmp_clk_divider_round_rate() returns actual divider value after calculating from parent rate and desired rate, even though that rate is not supported by single divider of hardware. It is also possible that such divisor value can be achieved through 2 different dividers. As, Linux tries to set such divisor value(out of range) in single divider set divider is getting failed. Fix the same by computing best possible combination of two divisors which provides more accurate clock rate. Signed-off-by: Michal Simek Signed-off-by: Tejas Patel Signed-off-by: Rajan Vaja Link: https://lkml.kernel.org/r/1575527759-26452-6-git-send-email-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd

clk: zynqmp: Add support for get max divider

2020-01-23T21:25:32+00:00

To achieve best possible rate, maximum limit of divider is required while computation. Get maximum supported divisor from firmware. To maintain backward compatibility assign maximum possible value(0xFFFF) if query for max divisor is not successful. Signed-off-by: Rajan Vaja Link: https://lkml.kernel.org/r/1575527759-26452-5-git-send-email-rajan.vaja@xilinx.com Acked-by: Michal Simek [sboyd@kernel.org: Remove else return and just return] Signed-off-by: Stephen Boyd

clk: zynqmp: Warn user if clock user are more than allowed

2020-01-23T21:25:25+00:00

Warn user if clock is used by more than allowed devices. This check is done by firmware and returns respective error code. Upon receiving error code for excessive user, warn user for the same. This change is done to restrict VPLL use count. It is assumed that VPLL is used by one user only. Signed-off-by: Michal Simek Signed-off-by: Rajan Vaja Link: https://lkml.kernel.org/r/1575527759-26452-4-git-send-email-rajan.vaja@xilinx.com Acked-by: Michal Simek Signed-off-by: Stephen Boyd

clk: zynqmp: Extend driver for versal

2020-01-23T21:22:44+00:00

Add Versal compatible string to support Versal binding. Signed-off-by: Jolly Shah Signed-off-by: Michal Simek Signed-off-by: Rajan Vaja Link: https://lkml.kernel.org/r/1575527759-26452-3-git-send-email-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2019-05-16T16:19:14+00:00

Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms and a couple of the small driver subsystems we merge through our tree: Among the larger pieces: - Power management improvements for TI am335x and am437x (RTC suspend/wake) - Misc new additions for Amlogic (socinfo updates) - ZynqMP FPGA manager - Nvidia improvements for reset/powergate handling - PMIC wrapper for Mediatek MT8516 - Misc fixes/improvements for ARM SCMI, TEE, NXP i.MX SCU drivers" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (57 commits) soc: aspeed: fix Kconfig soc: add aspeed folder and misc drivers spi: zynqmp: Fix build break soc: imx: Add generic i.MX8 SoC driver MAINTAINERS: Update email for Qualcomm SoC maintainer memory: tegra: Fix a typos for "fdcdwr2" mc client Revert "ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+" memory: tegra: Replace readl-writel with mc_readl-mc_writel memory: tegra: Fix integer overflow on tick value calculation memory: tegra: Fix missed registers values latching ARM: tegra: cpuidle: Handle tick broadcasting within cpuidle core on Tegra20/30 optee: allow to work without static shared memory soc/tegra: pmc: Move powergate initialisation to probe soc/tegra: pmc: Remove reset sysfs entries on error soc/tegra: pmc: Fix reset sources and levels soc: amlogic: meson-gx-pwrc-vpu: Add support for G12A soc: amlogic: meson-gx-pwrc-vpu: Fix power on/off register bitmask fpga manager: Adding FPGA Manager support for Xilinx zynqmp dt-bindings: fpga: Add bindings for ZynqMP fpga driver firmware: xilinx: Add fpga API's ...

clk: zynqmp: use structs for clk query responses

2019-04-19T20:59:55+00:00

The driver retrieves the clock tree by querying the ATF for the clock names, the clock topology, the parents and other attributes. The driver needs to unmarshal the responses. The definition of the fields in the firmware responses to the queries is inconsistent. Some are specified as a mask, some as a shift, and by the length of the previous field. Define C structs for the entire firmware responses to avoid passing pointers to arrays of an implicit size and make the format of the responses to the queries obvious. Signed-off-by: Michael Tretter Reviewed-by: Jolly Shah [sboyd@kernel.org: Drop 0 initializers because sparse complains] Signed-off-by: Stephen Boyd

clk: zynqmp: fix check for fractional clock

2019-04-11T18:33:12+00:00

The firmware sets BIT(13) in clkflag to mark a divider as fractional divider. The clock driver copies the clkflag straight to the flags of the common clock framework. In the common clk framework flags, BIT(13) is defined as CLK_DUTY_CYCLE_PARENT. Add a new field to the zynqmp_clk_divider to specify if a divider is a fractional devider. Set this field based on the clkflag when registering a divider. At the same time, unset BIT(13) from clkflag when copying the flags to the common clk framework flags. Signed-off-by: Michael Tretter Signed-off-by: Stephen Boyd

clk: zynqmp: do not export zynqmp_clk_register_* functions

2019-04-11T18:33:11+00:00

The zynqmp_clk_register_* functions are internal functions of the driver. Only clkc.c uses these functions to register these clocks. Therefore, there is no need to export these functions. The gate and pll already don't export their register_* functions. Signed-off-by: Michael Tretter Signed-off-by: Stephen Boyd

clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parents

2019-04-11T18:33:09+00:00

The kerneldoc refers to __zynqmp_clock_get_topology(), but actually documents __zynqmp_clock_get_parents(). Refer to the correct function name in the kerneldoc. Signed-off-by: Michael Tretter Signed-off-by: Stephen Boyd