blackbird-op-linux/drivers/clk/imx/Makefile, branch master

clk: imx: Add support for i.MX8MP clock driver

2020-01-12T06:07:36+00:00

Add clock driver support for i.MX8MP which is a new SoC of i.MX8M family. Signed-off-by: Anson Huang Reviewed-by: Abel Vesa Signed-off-by: Shawn Guo

clk: imx: Rename the SCCG to SSCG

2019-12-11T11:19:35+00:00

According to the manual the acronym stands for Spread Sprectum Clock Generator. Signed-off-by: Abel Vesa Signed-off-by: Shawn Guo

clk: imx: Add support for i.MX8MN clock driver

2019-08-03T07:16:02+00:00

This patch adds i.MX8MN clock driver support. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo

clk: imx: rename clk-imx51-imx53.c to clk-imx5.c

2019-04-15T09:09:23+00:00

As the driver is handling all i.MX5 series SoCs inlcuding i.MX50, rather than just i.MX51 and i.MX53, let's rename it to clk-imx5.c. Signed-off-by: Shawn Guo Reviewed-by: Stephen Boyd

clk: imx: Add clock driver support for imx8mm

2019-02-21T20:41:16+00:00

Add clock driver support for i.MX8MM SOC. Signed-off-by: Bai Ping Signed-off-by: Stephen Boyd

clk: imx: Add PLLs driver for imx8mm soc

2019-02-21T20:41:16+00:00

New PLLs are introduced on i.MX8M Mini SOC. PLL1416X is Integer PLL, PLL1443X is a Frac PLL. Signed-off-by: Bai Ping Signed-off-by: Stephen Boyd

Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', 'clk-imx8qxp' and 'clk-imx8mq' into clk-next

2018-12-14T21:34:47+00:00

- NXP i.MX7ULP SoC clock support - Support for i.MX8QXP SoC clocks - Support for NXP i.MX8MQ clock controllers * clk-imx7ulp: clk: imx: add imx7ulp clk driver clk: imx: implement new clk_hw based APIs clk: imx: make mux parent strings const dt-bindings: clock: add imx7ulp clock binding doc clk: imx: add imx7ulp composite clk support clk: imx: add pfdv2 support clk: imx: add pllv4 support clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support clk: imx: add gatable clock divider support * clk-imx6-fixes: clk: imx6q: handle ENET PLL bypass clk: imx6q: optionally get CCM inputs via standard clock handles clk: imx6q: reset exclusive gates on init * clk-imx-fixes: clk: imx6q: add DCICx clocks gate clk: imx6sl: ensure MMDC CH0 handshake is bypassed clk: imx7d: remove UART1 clock setting * clk-imx8qxp: clk: imx: add imx8qxp lpcg driver clk: imx: add lpcg clock support clk: imx: add imx8qxp clk driver clk: imx: add scu clock common part clk: imx: add configuration option for mmio clks dt-bindings: clock: add imx8qxp lpcg clock binding dt-bindings: clock: imx8qxp: add SCU clock IDs firmware: imx: add pm svc headfile dt-bindings: fsl: scu: update power domain binding firmware: imx: remove resource id enums dt-bindings: imx: add scu resource id headfile * clk-imx8mq: clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant clk: imx: remove redundant initialization of ret to zero clk: imx: Add SCCG PLL type clk: imx: Add fractional PLL output clock clk: imx: Add clock driver for i.MX8MQ CCM clk: imx: Add imx composite clock dt-bindings: Add binding for i.MX8MQ CCM

clk: imx: add imx8qxp lpcg driver

2018-12-14T21:01:14+00:00

Add imx8qxp lpcg driver support Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Michael Turquette Signed-off-by: Dong Aisheng Signed-off-by: Stephen Boyd

clk: imx: add lpcg clock support

2018-12-14T21:00:51+00:00

The Low-Power Clock Gate (LPCG) modules contain a local programming model to control the clock gates for the peripherals. An LPCG module is used to locally gate the clocks for the associated peripheral. And they're bedind the SCU clock. Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Michael Turquette Signed-off-by: Dong Aisheng Signed-off-by: Stephen Boyd

clk: imx: add imx8qxp clk driver

2018-12-14T21:00:29+00:00

Add imx8qxp clk driver which is based on SCU firmware clock service. Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Stephen Boyd Cc: Michael Turquette Signed-off-by: Dong Aisheng [sboyd@kernel.org: Move the makefile rule higher in the file] Signed-off-by: Stephen Boyd