blackbird-op-linux/arch/mips/include/asm/mach-loongson64, branch master

MIPS: Loongson64: Disable exec hazard

2020-01-23T18:27:06+00:00

Loongson64 has hardware mechanism to prevent hazard issue, so we can simply disable exec hazard in cpu-features. Signed-off-by: Jiaxun Yang Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org Cc: chenhc@lemote.com Cc: paul.burton@mips.com Cc: linux-kernel@vger.kernel.org

MIPS: Loongson64: Select mac2008 only feature

2020-01-22T23:57:52+00:00

Some Loongson-64 processor didn't set MAC2008 bit in fcsr, but actually all Loongson64 processors are MAC2008 only. Signed-off-by: Jiaxun Yang Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org Cc: chenhc@lemote.com Cc: paul.burton@mips.com Cc: linux-kernel@vger.kernel.org

MIPS: Loongson{2ef, 32, 64} convert to generic fw cmdline

2019-11-11T18:44:56+00:00

All of Loongson firmwares are passing boot cmdline/env in the manner of YAMON/PMON. Thus we can remove duplicated cmdline initialize code and convert to generic fw method. Signed-off-by: Jiaxun Yang Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org Cc: chenhe@lemote.com

MIPS: Loongson64: Move files to the top-level directory

2019-11-01T21:31:28+00:00

Current Loongson-3 code can share among all Loongson64 processors. Signed-off-by: Jiaxun Yang Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org Cc: chenhc@lemote.com Cc: paul.burton@mips.com

MIPS: Loongson64: Cleanup unused code

2019-11-01T21:31:28+00:00

Clean up legacy code after stripping out Loongson2ef code. Signed-off-by: Jiaxun Yang Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org Cc: paul.burton@mips.com

MIPS: Loongson64: Rename CPU TYPES

2019-10-31T22:03:10+00:00

CPU_LOONGSON2 -> CPU_LOONGSON2EF CPU_LOONGSON3 -> CPU_LOONGSON64 As newer loongson-2 products (2G/2H/2K1000) can share kernel implementation with loongson-3 while 2E/2F are less similar with other LOONGSON64 products. Signed-off-by: Jiaxun Yang Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org Cc: chenhc@lemote.com Cc: paul.burton@mips.com

MIPS: Loongson: Fix GENMASK misuse

2019-10-24T03:57:38+00:00

Arguments are supposed to be ordered high then low. Fixes: 6a6f9b7dafd50efc1b2 ("MIPS: Loongson: Add CFUCFG&CSR support") Signed-off-by: Rikard Falkeborn Reviewed-by: Huacai Chen Signed-off-by: Paul Burton Cc: chenhuacai@gmail.com Cc: jhogan@kernel.org Cc: jiaxun.yang@flygoat.com Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: paul.burton@mips.com Cc: ralf@linux-mips.org Cc: wuzhangjin@gmail.com Cc: zhangfx@lemote.com

MIPS: Loongson: Add Loongson-3A R4 basic support

2019-10-07T16:45:24+00:00

All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R2.1 Loongson-3A2000 0x630c Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3A R3.1 Loongson-3A3000 0x630d Loongson-3A R4 Loongson-3A4000 0xc000 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R4 revision of Loongson-3A: - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc. - Support variable ASID bits. - Support MSA and VZ extensions. - Support CPUCFG (CPU config) and CSR (Control and Status Register) extensions. - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way set-associative). Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/ 2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R (e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G. Signed-off-by: Huacai Chen Signed-off-by: Jiaxun Yang Signed-off-by: Paul Burton Cc: Ralf Baechle Cc: James Hogan Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: Fuxin Zhang Cc: Zhangjin Wu Cc: Huacai Chen

MIPS: Loongson: Add CFUCFG&CSR support

2019-10-07T16:45:19+00:00

Loongson-3A R4+ (Loongson-3A4000 and newer) has CPUCFG (CPU config) and CSR (Control and Status Register) extensions. This patch add read/write functionalities for them. Signed-off-by: Huacai Chen Signed-off-by: Jiaxun Yang Signed-off-by: Paul Burton Cc: Ralf Baechle Cc: James Hogan Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: Fuxin Zhang Cc: Zhangjin Wu Cc: Huacai Chen

MIPS: tlbex: Remove cpu_has_local_ebase

2019-09-03T13:20:54+00:00

The cpu_has_local_ebase macro is, confusingly, not used to indicate whether the EBase register is local to a CPU or not. Instead it indicates whether we want to generate the TLB refill exception vector each time a CPU is brought online. Doing this makes little sense on any system, since we always use the same value for EBase & thus we cannot have different TLB refill exception handlers per CPU. Regenerating the code is not only pointless but also can be actively harmful, as commit 8759934e2b6b ("MIPS: Build uasm-generated code only once to avoid CPU Hotplug problem") described. That commit introduced cpu_has_local_ebase to disable the handler regeneration for Loongson machines, but this is by no means a Loongson-specific problem. Remove cpu_has_local_ebase & simply generate the TLB refill handler once during boot, just like the rest of the TLB exception handlers. Signed-off-by: Paul Burton Reviewed-by: Philippe Mathieu-Daudé Cc: linux-mips@vger.kernel.org