summaryrefslogtreecommitdiffstats
path: root/board/samsung/smdkc100/mem_setup.S
blob: 94a701d428d29158197f794cfc9a4ee0f331182b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
/*
 * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
 *
 * Copyright (C) 2009 Samsung Electrnoics
 * Inki Dae <inki.dae@samsung.com>
 * Heungjun Kim <riverful.kim@samsung.com>
 * Minkyu Kang <mk7.kang@samsung.com>
 * Kyungmin Park <kyungmin.park@samsung.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>

	.globl mem_ctrl_asm_init
mem_ctrl_asm_init:
	ldr	r6, =S5PC100_DMC_BASE			@ 0xE6000000

	/* DLL parameter setting */
	ldr	r1, =0x50101000
	str	r1, [r6, #0x018]			@ PHYCONTROL0
	ldr	r1, =0xf4
	str	r1, [r6, #0x01C]			@ PHYCONTROL1
	ldr	r1, =0x0
	str	r1, [r6, #0x020]			@ PHYCONTROL2

	/* DLL on */
	ldr	r1, =0x50101002
	str	r1, [r6, #0x018]			@ PHYCONTROL0

	/* DLL start */
	ldr	r1, =0x50101003
	str	r1, [r6, #0x018]			@ PHYCONTROL0

	/* Force value locking for DLL off */
	str	r1, [r6, #0x018]			@ PHYCONTROL0

	/* DLL off */
	ldr	r1, =0x50101001
	str	r1, [r6, #0x018]			@ PHYCONTROL0

	/* auto refresh off */
	ldr	r1, =0xff001010
	str	r1, [r6, #0x000]			@ CONCONTROL

	/*
	 * Burst Length 4, 2 chips, 32-bit, LPDDR
	 * OFF: dynamic self refresh, force precharge, dynamic power down off
	 */
	ldr	r1, =0x00212100
	str	r1, [r6, #0x004]			@ MEMCONTROL

	/*
	 * Note:
	 * If Bank0 has OneDRAM we place it at 0x2800'0000
	 * So finally Bank1 should address start at at 0x2000'0000
	 */
	mov	r4, #0x0

swap_memory:
	/*
	 * Bank0
	 * 0x30 -> 0x30000000
	 * 0xf8 -> 0x37FFFFFF
	 * [15:12] 0: Linear
	 * [11:8 ] 2: 9 bits
	 * [ 7:4 ] 2: 14 bits
	 * [ 3:0 ] 2: 4 banks
	 */
	ldr	r1, =0x30f80222
	/* if r4 is 1, swap the bank */
	cmp	r4, #0x1
	orreq	r1, r1, #0x08000000
	str	r1, [r6, #0x008]			@ MEMCONFIG0

	/*
	 * Bank1
	 * 0x38 -> 0x38000000
	 * 0xf8 -> 0x3fFFFFFF
	 * [15:12] 0: Linear
	 * [11:8 ] 2: 9 bits
	 * [ 7:4 ] 2: 14 bits
	 * [ 3:0 ] 2: 4 banks
	 */
	ldr	r1, =0x38f80222
	/* if r4 is 1, swap the bank */
	cmp	r4, #0x1
	biceq	r1, r1, #0x08000000
	str	r1, [r6, #0x00c]			@ MEMCONFIG1

	ldr	r1, =0x20000000
	str	r1, [r6, #0x014]			@ PRECHCONFIG

	/*
	 * FIXME: Please verify these values
	 * 7.8us * 166MHz %LE %LONG1294(0x50E)
	 * 7.8us * 133MHz %LE %LONG1038(0x40E),
	 * 7.8us * 100MHz %LE %LONG780(0x30C),
	 * 7.8us * 20MHz  %LE %LONG156(0x9C),
	 * 7.8us * 10MHz  %LE %LONG78(0x4E)
	 */
	ldr	r1, =0x0000050e
	str	r1, [r6, #0x030]			@ TIMINGAREF

	/* 166 MHz */
	ldr	r1, =0x0c233287
	str	r1, [r6, #0x034]			@ TIMINGROW

	/* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
	ldr	r1, =0x32330303
	str	r1, [r6, #0x038]			@ TIMINGDATA

	/* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
	ldr	r1, =0x04141433
	str	r1, [r6, #0x03C]			@ TIMINGPOWER

	/* chip0 Deselect */
	ldr	r1, =0x07000000
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* chip0 PALL */
	ldr	r1, =0x01000000
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* chip0 REFA */
	ldr	r1, =0x05000000
	str	r1, [r6, #0x010]			@ DIRECTCMD
	/* chip0 REFA */
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
	ldr	r1, =0x00000032
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* chip1 Deselect */
	ldr	r1, =0x07100000
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* chip1 PALL */
	ldr	r1, =0x01100000
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* chip1 REFA */
	ldr	r1, =0x05100000
	str	r1, [r6, #0x010]			@ DIRECTCMD
	/* chip1 REFA */
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
	ldr	r1, =0x00100032
	str	r1, [r6, #0x010]			@ DIRECTCMD

	/* auto refresh on */
	ldr	r1, =0xff002030
	str	r1, [r6, #0x000]			@ CONCONTROL

	/* PwrdnConfig */
	ldr	r1, =0x00100002
	str	r1, [r6, #0x028]			@ PWRDNCONFIG

	/* BL%LE %LONG */
	ldr	r1, =0xff212100
	str	r1, [r6, #0x004]			@ MEMCONTROL


	/* Try to test memory area */
	cmp	r4, #0x1
	beq	1f

	mov	r4, #0x1
	ldr	r1, =0x37ffff00
	str	r4, [r1]
	str	r4, [r1, #0x4]				@ dummy write
	ldr	r0, [r1]
	cmp	r0, r4
	bne	swap_memory

1:
	mov	pc, lr

	.ltorg
OpenPOWER on IntegriCloud