summaryrefslogtreecommitdiffstats
path: root/board/LaCie/net2big_v2/kwbimage.cfg
blob: 453fcb2a22d2d530cd3e6d69894c11a003120f6f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
#
# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
#
# Based on Kirkwood support:
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# SPDX-License-Identifier:	GPL-2.0+
#
# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#

# Boot Media configurations
BOOT_FROM	spi	# Boot from SPI flash

# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed

# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xFFD100e0 0x1B1B1B9B

#Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xFFD01400 0x43000C30	# DDR Configuration register
# bit13-0:  0xa00 (2560 DDR2 clks refresh rate)
# bit23-14: zero
# bit24: 1= enable exit self refresh mode on DDR access
# bit25: 1 required
# bit29-26: zero
# bit31-30: 01

DATA 0xFFD01404 0x38743000	# DDR Controller Control Low
# bit 4:    0=addr/cmd in smame cycle
# bit 5:    0=clk is driven during self refresh, we don't care for APX
# bit 6:    0=use recommended falling edge of clk for addr/cmd
# bit14:    0=input buffer always powered up
# bit18:    1=cpu lock transaction enabled
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 3 required
# bit31:    0=no additional STARTBURST delay

DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
# bit7-4:   TRCD
# bit11- 8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20:    TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP

DATA 0xFFD0140C 0x00000A32	#  DDR Timing (High)
# bit6-0:   TRFC
# bit8-7:   TR2R
# bit10-9:  TR2W
# bit12-11: TW2W
# bit31-13: zero required

DATA 0xFFD01410 0x0000CCCC	#  DDR Address Control
# bit1-0:   01, Cs0width=x16
# bit3-2:   11, Cs0size=1Gb
# bit5-4:   00, Cs2width=nonexistent
# bit7-6:   00, Cs1size =nonexistent
# bit9-8:   00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
# bit15-14: 00, Cs3size =nonexistent
# bit16:    0,  Cs0AddrSel
# bit17:    0,  Cs1AddrSel
# bit18:    0,  Cs2AddrSel
# bit19:    0,  Cs3AddrSel
# bit31-20: 0 required

DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
# bit0:    0,  OpenPage enabled
# bit31-1: 0 required

DATA 0xFFD01418 0x00000000	#  DDR Operation
# bit3-0:   0x0, DDR cmd
# bit31-4:  0 required

DATA 0xFFD0141C 0x00000662	#  DDR Mode
# bit2-0:   2, BurstLen=2 required
# bit3:     0, BurstType=0 required
# bit6-4:   4, CL=5
# bit7:     0, TestMode=0 normal
# bit8:     0, DLL reset=0 normal
# bit11-9:  6, auto-precharge write recovery ????????????
# bit12:    0, PD must be zero
# bit31-13: 0 required

DATA 0xFFD01420 0x00000044	#  DDR Extended Mode
# bit0:    0,  DDR DLL enabled
# bit1:    1,  DDR drive strenght reduced
# bit2:    1,  DDR ODT control lsd enabled
# bit5-3:  000, required
# bit6:    1,  DDR ODT control msb, enabled
# bit9-7:  000, required
# bit10:   0,  differential DQS enabled
# bit11:   0, required
# bit12:   0, DDR output buffer enabled
# bit31-13: 0 required

DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
# bit2-0:  111, required
# bit3  :  1  , MBUS Burst Chop disabled
# bit6-4:  111, required
# bit7  :  1  , D2P Latency enabled
# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
# bit9  :  0  , no half clock cycle addition to dataout
# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
# bit15-12: 1111 required
# bit31-16: 0    required

DATA 0xFFD01428 0x00096630	# DDR2 ODT Read Timing (default values)
DATA 0xFFD0147C 0x00009663	# DDR2 ODT Write Timing (default values)

DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
# bit0:    1,  Window enabled
# bit1:    0,  Write Protect disabled
# bit3-2:  00, CS0 hit selected
# bit23-4: ones, required
# bit31-24: 0x07, Size (i.e. 128MB)

DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled

DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
# bit3-0:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0

DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
# bit3-2:  01, ODT1 active NEVER!
# bit31-4: zero, required

DATA 0xFFD0149C 0x0000E40F	# CPU ODT Control
# bit3-0:  1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
# bit7-4:  1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
# bit11-10:1, DQ_ODTSel. ODT select turned on

DATA 0xFFD01480 0x00000001	# DDR Initialization Control
#bit0=1, enable DDR init upon this register write

# End of Header extension
DATA 0x0 0x0
OpenPOWER on IntegriCloud