/* * (C) Copyright 2001 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ */ /* * * Configuration settings for the MUSENKI board. * */ /* ------------------------------------------------------------------------- */ /* * board/config.h - configuration options, board specific */ #ifndef __CONFIG_H #define __CONFIG_H /* * High Level Configuration Options * (easy to change) */ #define CONFIG_MPC824X 1 #define CONFIG_MPC8245 1 #define CONFIG_MUSENKI 1 #define CONFIG_SYS_TEXT_BASE 0xFFF00000 #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 9600 #define CONFIG_BOOTDELAY 5 /* * BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME /* * Command line configuration. */ #include /* * Miscellaneous configurable options */ #undef CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- */ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #undef CONFIG_PCI_PNP #define CONFIG_TULIP #define PCI_ENET0_IOADDR 0x80000000 #define PCI_ENET0_MEMADDR 0x80000000 #define PCI_ENET1_IOADDR 0x81000000 #define PCI_ENET1_MEMADDR 0x81000000 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */ #define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the * reset vector is actually located at FFB00100, but the 8245 * takes care of us. */ #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 #define CONFIG_SYS_EUMB_ADDR 0xFC000000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ /* Maximum amount of RAM. */ #define CONFIG_SYS_MAX_RAM_SIZE 0x08000000 /* 0 .. 128 MB of (S)DRAM */ #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE #undef CONFIG_SYS_RAMBOOT #else #define CONFIG_SYS_RAMBOOT #endif /* * NS16550 Configuration */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area */ /* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. * For the detail description refer to the MPC8240 user's manual. */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ /* Bit-field values for MCCR1. */ #define CONFIG_SYS_ROMNAL 7 #define CONFIG_SYS_ROMFAL 11 #define CONFIG_SYS_DBUS_SIZE 0x3 /* Bit-field values for MCCR2. */ #define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ #define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ #define CONFIG_SYS_BSTOPRE 121 /* Bit-field values for MCCR3. */ #define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ /* Bit-field values for MCCR4. */ #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ #define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */ #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 #define CONFIG_SYS_EXTROM 1 #define CONFIG_SYS_REGDIMM 0 #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ #define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ /* Memory bank settings. * Only bits 20-29 are actually used from these vales to set the * start/end addresses. The upper two bits will always be 0, and the lower * 20 bits will be 0x00000 for a start address, or 0xfffff for an end * address. Refer to the MPC8240 book. */ #define CONFIG_SYS_BANK0_START 0x00000000 #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) #define CONFIG_SYS_BANK0_ENABLE 1 #define CONFIG_SYS_BANK1_START 0x3ff00000 #define CONFIG_SYS_BANK1_END 0x3fffffff #define CONFIG_SYS_BANK1_ENABLE 0 #define CONFIG_SYS_BANK2_START 0x3ff00000 #define CONFIG_SYS_BANK2_END 0x3fffffff #define CONFIG_SYS_BANK2_ENABLE 0 #define CONFIG_SYS_BANK3_START 0x3ff00000 #define CONFIG_SYS_BANK3_END 0x3fffffff #define CONFIG_SYS_BANK3_ENABLE 0 #define CONFIG_SYS_BANK4_START 0x3ff00000 #define CONFIG_SYS_BANK4_END 0x3fffffff #define CONFIG_SYS_BANK4_ENABLE 0 #define CONFIG_SYS_BANK5_START 0x3ff00000 #define CONFIG_SYS_BANK5_END 0x3fffffff #define CONFIG_SYS_BANK5_ENABLE 0 #define CONFIG_SYS_BANK6_START 0x3ff00000 #define CONFIG_SYS_BANK6_END 0x3fffffff #define CONFIG_SYS_BANK6_ENABLE 0 #define CONFIG_SYS_BANK7_START 0x3ff00000 #define CONFIG_SYS_BANK7_END 0x3fffffff #define CONFIG_SYS_BANK7_ENABLE 0 #define CONFIG_SYS_ODCR 0xff #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ /* Warining: environment is not EMBEDDED in the U-Boot code. * It's stored in flash separately. */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR 0xFFFF0000 #define CONFIG_ENV_SIZE 0x00010000 /* Size of the Environment */ #define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of the Environment Sector */ /*----------------------------------------------------------------------- * Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 32 #if defined(CONFIG_CMD_KGDB) # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif #endif /* __CONFIG_H */