/* * (C) Copyright 2001-2004 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * (C) Copyright 2006 * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com * * SPDX-License-Identifier: GPL-2.0+ */ /* * board/config.h - configuration options, board specific */ #ifndef __CONFIG_H #define __CONFIG_H /* * High Level Configuration Options * (easy to change) */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ #define CONFIG_HH405 1 /* ...on a HH405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_BAUDRATE 9600 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #undef CONFIG_BOOTARGS #undef CONFIG_BOOTCOMMAND #define CONFIG_PREBOOT "autoupd" #define CONFIG_EXTRA_ENV_SETTINGS \ "pciconfighost=1\0" \ "" #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_PPC4xx_EMAC #undef CONFIG_HAS_ETH1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ /* * Video console */ #define CONFIG_VIDEO /* for sm501 video support */ #ifdef CONFIG_VIDEO #define CONFIG_VIDEO_SM501 #if 0 #define CONFIG_VIDEO_SM501_32BPP #else #define CONFIG_VIDEO_SM501_16BPP #endif #define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000 #define CONFIG_CFB_CONSOLE #define CONFIG_VIDEO_LOGO #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_CONSOLE_EXTRA_INFO #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_SPLASH_SCREEN #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SPLASH_SCREEN #define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */ #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */ #endif /* CONFIG_VIDEO */ /* * BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME /* * Command line configuration. */ #include #define CONFIG_CMD_DHCP #define CONFIG_CMD_PCI #define CONFIG_CMD_IRQ #define CONFIG_CMD_IDE #define CONFIG_CMD_FAT #define CONFIG_CMD_EXT2 #define CONFIG_CMD_ELF #define CONFIG_CMD_NAND #define CONFIG_CMD_I2C #define CONFIG_CMD_DATE #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_EEPROM #ifdef CONFIG_VIDEO #define CONFIG_CMD_BMP #endif #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ #undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */ #undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ /* * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ #undef CONFIG_SYS_CONSOLE_INFO_QUIET /* print console @ startup */ #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CONFIG_CONS_INDEX 2 /* Use UART1 */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 57600, 115200, 230400, 460800, 921600 } #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ /*----------------------------------------------------------------------- * RTC stuff *----------------------------------------------------------------------- */ #define CONFIG_RTC_DS1338 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /*----------------------------------------------------------------------- * NAND-FLASH stuff *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- */ #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ #define PCI_HOST_FORCE 1 /* configure as pci host */ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- */ #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_LED /* no led for ide supported */ #define CONFIG_IDE_RESET 1 /* reset for ide supported */ #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ /* * The following defines are added for buggy IOP480 byte interface. * All other boards should use the standard values (CPCI405 etc.) */ #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #if 0 /* test-only */ #define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ #define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ #endif /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_FLASH_BASE 0xFFF80000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */ #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) # define CONFIG_SYS_RAMBOOT 1 #else # undef CONFIG_SYS_RAMBOOT #endif /*----------------------------------------------------------------------- * Environment Variable setup */ #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ /* total size of a CAT24WC16 is 2048 bytes */ #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */ #define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ /*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_PPC4XX #define CONFIG_SYS_I2C_PPC4XX_CH0 #if 0 /* test-only */ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 #else #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 #endif #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ #define CONFIG_SYS_EEPROM_WREN 1 #if 1 /* test-only */ /* CAT24WC08/16... */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ /* 16 byte page write mode using*/ /* last 4 bits of the address */ #else /* CAT24WC32/64... */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ /* 32 byte page write mode using*/ /* last 5 bits of the address */ #endif #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ #define CAN_BA 0xF0000000 /* CAN Base Address */ #define LCD_BA 0xF1000000 /* Epson LCD Base Address */ #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ #define CONFIG_SYS_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */ /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ #define CONFIG_SYS_EBC_PB0AP 0x92015480 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ /* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */ #define CONFIG_SYS_EBC_PB1AP 0x92015480 #define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ /* Memory Bank 4 (Epson LCD) initialization */ #define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ #define CONFIG_SYS_EBC_PB4CR LCD_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ /*----------------------------------------------------------------------- * LCD Setup */ #define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ #define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ #define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ #define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ /*----------------------------------------------------------------------- * Universal Interrupt Controller (UIC) Setup */ /* * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high */ #define CONFIG_SYS_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6)) /*----------------------------------------------------------------------- * FPGA stuff */ #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ #define LCD_CLK_OFF 0x0000 /* Off */ #define LCD_CLK_02083 0x1000 /* 2.083 MHz */ #define LCD_CLK_03135 0x2000 /* 3.135 MHz */ #define LCD_CLK_04165 0x3000 /* 4.165 MHz */ #define LCD_CLK_06250 0x4000 /* 6.250 MHz */ #define LCD_CLK_08330 0x5000 /* 8.330 MHz */ #define LCD_CLK_12500 0x6000 /* 12.50 MHz */ #define LCD_CLK_25000 0x7000 /* 25.00 MHz */ #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ /* FPGA program pin configuration */ #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) */ /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ #define CONFIG_SYS_TEMP_STACK_OCM 1 /* On Chip Memory location */ #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Definitions for GPIO setup (PPC405EP specific) * * GPIO0[0] - External Bus Controller BLAST output * GPIO0[1-9] - Instruction trace outputs -> GPIO * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs * GPIO0[24-27] - UART0 control signal inputs/outputs * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ #define CONFIG_SYS_GPIO0_OSRL 0x40000550 #define CONFIG_SYS_GPIO0_OSRH 0x00000110 #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 #define CONFIG_SYS_GPIO0_ISR1H 0x15555440 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 #define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FE0017 #define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7) #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ #define CONFIG_SYS_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */ #define CONFIG_SYS_LCD0_RST (0x80000000 >> 30) #define CONFIG_SYS_LCD1_RST (0x80000000 >> 31) /* * Default speed selection (cpu_plb_opb_ebc) in mhz. * This value will be set if iic boot eprom is disabled. */ #if 0 #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 #endif #if 0 #define PLLMR0_DEFAULT PLLMR0_200_100_50_33 #define PLLMR1_DEFAULT PLLMR1_200_100_50_33 #endif #if 1 #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 #endif #endif /* __CONFIG_H */