# # Copyright (C) 2014, Simon Glass # Copyright (C) 2014, Bin Meng # # SPDX-License-Identifier: GPL-2.0+ # U-Boot on x86 ============= This document describes the information about U-Boot running on x86 targets, including supported boards, build instructions, todo list, etc. Status ------ U-Boot supports running as a coreboot [1] payload on x86. So far only Link (Chromebook Pixel) has been tested, but it should work with minimal adjustments on other x86 boards since coreboot deals with most of the low-level details. U-Boot also supports booting directly from x86 reset vector without coreboot, aka raw support or bare support. Currently Link and Intel Crown Bay board support running U-Boot 'bare metal'. As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux kernel as part of a FIT image. It also supports a compressed zImage. Build Instructions ------------------ Building U-Boot as a coreboot payload is just like building U-Boot for targets on other architectures, like below: $ make coreboot-x86_defconfig $ make all Note this default configuration will build a U-Boot payload for the Link board. To build a coreboot payload against another board, you can change the build configuration during the 'make menuconfig' process. x86 architecture ---> ... (chromebook_link) Board configuration file (chromebook_link) Board Device Tree Source (dts) file (0x19200000) Board specific Cache-As-RAM (CAR) address (0x4000) Board specific Cache-As-RAM (CAR) size Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' to point to a new board. You can also change the Cache-As-RAM (CAR) related settings here if the default values do not fit your new board. Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a little bit tricky, as generally it requires several binary blobs which are not shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is not turned on by default in the U-Boot source tree. Firstly, you need turn it on by uncommenting the following line in the main U-Boot Makefile: # ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom Link-specific instructions: First, you need the following binary blobs: * descriptor.bin - Intel flash descriptor * me.bin - Intel Management Engine * mrc.bin - Memory Reference Code, which sets up SDRAM * video ROM - sets up the display You can get these binary blobs by: $ git clone http://review.coreboot.org/p/blobs.git $ cd blobs Find the following files: * ./mainboard/google/link/descriptor.bin * ./mainboard/google/link/me.bin * ./northbridge/intel/sandybridge/systemagent-ivybridge.bin The 3rd one should be renamed to mrc.bin. As for the video ROM, you can get it here [2]. Make sure all these binary blobs are put in the board directory. Now you can build U-Boot and obtain u-boot.rom: $ make chromebook_link_defconfig $ make all Intel Crown Bay specific instructions: U-Boot support of Intel Crown Bay board [3] relies on a binary blob called Firmware Support Package [4] to perform all the necessary initialization steps as documented in the BIOS Writer Guide, including initialization of the CPU, memory controller, chipset and certain bus interfaces. Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, install it on your host and locate the FSP binary blob. Note this platform also requires a Chipset Micro Code (CMC) state machine binary to be present in the SPI flash where u-boot.rom resides, and this CMC binary blob can be found in this FSP package too. * ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd * ./Microcode/C0_22211.BIN Rename the first one to fsp.bin and second one to cmc.bin and put them in the board directory. Now you can build U-Boot and obtain u-boot.rom $ make crownbay_defconfig $ make all Test with coreboot ------------------ For testing U-Boot as the coreboot payload, there are things that need be paid attention to. coreboot supports loading an ELF executable and a 32-bit plain binary, as well as other supported payloads. With the default configuration, U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool provided by coreboot) manually as coreboot's 'make menuconfig' does not provide this capability yet. The command is as follows: # in the coreboot root directory $ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \ -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015 Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the symbol address of _start (in arch/x86/cpu/start.S). If you want to use ELF as the coreboot payload, change U-Boot configuration to use CONFIG_OF_EMBED. CPU Microcode ------------- Modern CPU usually requires a special bit stream called microcode [5] to be loaded on the processor after power up in order to function properly. U-Boot has already integrated these as hex dumps in the source tree. Driver Model ------------ x86 has been converted to use driver model for serial and GPIO. Device Tree ----------- x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to be turned on. Not every device on the board is configured via device tree, but more and more devices will be added as time goes by. Check out the directory arch/x86/dts/ for these device tree source files. Useful Commands --------------- In keeping with the U-Boot philosophy of providing functions to check and adjust internal settings, there are several x86-specific commands that may be useful: hob - Display information about Firmware Support Package (FSP) Hand-off Block. This is only available on platforms which use FSP, mostly Atom. iod - Display I/O memory iow - Write I/O memory mtrr - List and set the Memory Type Range Registers (MTRR). These are used to tell the CPU whether memory is cacheable and if so the cache write mode to use. U-Boot sets up some reasonable values but you can adjust then with this command. TODO List --------- - Audio - Chrome OS verified boot - SMI and ACPI support, to provide platform info and facilities to Linux References ---------- [1] http://www.coreboot.org [2] http://www.coreboot.org/~stepan/pci8086,0166.rom [3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html [4] http://www.intel.com/fsp [5] http://en.wikipedia.org/wiki/Microcode