/* * (C) Copyright 2013 * Texas Instruments Incorporated, * * Lokesh Vutla * * Based on previous work by: * Aneesh V * Steve Sakoman * * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include #include #include #include #include "mux_data.h" #ifdef CONFIG_DRIVER_TI_CPSW #include #endif DECLARE_GLOBAL_DATA_PTR; const struct omap_sysinfo sysinfo = { "Board: DRA7xx\n" }; /* * Adjust I/O delays on the Tx control and data lines of each MAC port. This * is a workaround in order to work properly with the DP83865 PHYs on the EVM. * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we * essentially need to counteract the DRA7xx internal delay, and we do this * by delaying the control and data lines. If not using this PHY, you probably * don't need to do this stuff! */ static void dra7xx_adj_io_delay(const struct io_delay *io_dly) { int i = 0; u32 reg_val; u32 delta; u32 coarse; u32 fine; writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK); while(io_dly[i].addr) { writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK, io_dly[i].addr); delta = io_dly[i].dly; reg_val = readl(io_dly[i].addr) & 0x3ff; coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F); coarse = (coarse > 0x1F) ? (0x1F) : (coarse); fine = (reg_val & 0x1F) + (delta & 0x1F); fine = (fine > 0x1F) ? (0x1F) : (fine); reg_val = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine)); writel(reg_val, io_dly[i].addr); i++; } writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK); } /** * @brief board_init * * @return 0 */ int board_init(void) { gpmc_init(); gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ return 0; } int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG if (omap_revision() == DRA722_ES1_0) setenv("board_name", "dra72x"); else setenv("board_name", "dra7xx"); #endif init_sata(0); return 0; } /** * @brief misc_init_r - Configure EVM board specific configurations * such as power configurations, ethernet initialization as phase2 of * boot sequence * * @return 0 */ int misc_init_r(void) { return 0; } static void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size) { int i; struct pad_conf_entry *pad = (struct pad_conf_entry *)array; for (i = 0; i < size; i++, pad++) writel(pad->val, base + pad->offset); } void set_muxconf_regs_essential(void) { do_set_mux32((*ctrl)->control_padconf_core_base, core_padconf_array_essential, sizeof(core_padconf_array_essential) / sizeof(struct pad_conf_entry)); } #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0, -1, -1); omap_mmc_init(1, 0, 0, -1, -1); return 0; } #endif #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) int spl_start_uboot(void) { /* break into full u-boot on 'c' */ if (serial_tstc() && serial_getc() == 'c') return 1; #ifdef CONFIG_SPL_ENV_SUPPORT env_init(); env_relocate_spec(); if (getenv_yesno("boot_os") != 1) return 1; #endif return 0; } #endif #ifdef CONFIG_DRIVER_TI_CPSW /* Delay value to add to calibrated value */ #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) extern u32 *const omap_si_rev; static void cpsw_control(int enabled) { /* VTP can be added here */ return; } static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, .phy_addr = 2, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, .phy_addr = 3, }, }; static struct cpsw_platform_data cpsw_data = { .mdio_base = CPSW_MDIO_BASE, .cpsw_base = CPSW_BASE, .mdio_div = 0xff, .channels = 8, .cpdma_reg_ofs = 0x800, .slaves = 2, .slave_data = cpsw_slaves, .ale_reg_ofs = 0xd00, .ale_entries = 1024, .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, .mac_control = (1 << 5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, }; int board_eth_init(bd_t *bis) { int ret; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; uint32_t ctrl_val; const struct io_delay io_dly[] = { {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL}, {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL}, {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL}, {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL}, {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL}, {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL}, {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL}, {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL}, {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL}, {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL}, {0} }; /* Adjust IO delay for RGMII tx path */ dra7xx_adj_io_delay(io_dly); /* try reading mac address from efuse */ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); mac_addr[0] = (mac_hi & 0xFF0000) >> 16; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = mac_hi & 0xFF; mac_addr[3] = (mac_lo & 0xFF0000) >> 16; mac_addr[4] = (mac_lo & 0xFF00) >> 8; mac_addr[5] = mac_lo & 0xFF; if (!getenv("ethaddr")) { printf(" not set. Validating first E-fuse MAC\n"); if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); } mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); mac_addr[0] = (mac_hi & 0xFF0000) >> 16; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = mac_hi & 0xFF; mac_addr[3] = (mac_lo & 0xFF0000) >> 16; mac_addr[4] = (mac_lo & 0xFF00) >> 8; mac_addr[5] = mac_lo & 0xFF; if (!getenv("eth1addr")) { if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("eth1addr", mac_addr); } ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); ctrl_val |= 0x22; writel(ctrl_val, (*ctrl)->control_core_control_io1); if (*omap_si_rev == DRA722_ES1_0) cpsw_data.active_slave = 1; ret = cpsw_register(&cpsw_data); if (ret < 0) printf("Error %d registering CPSW switch\n", ret); return ret; } #endif