/* * Copyright (C) 2015 Freescale Semiconductor, Inc. * * Author: Fabio Estevam * * Copyright (C) 2013 Jon Nettleton * * Based on SPL code from Solidrun tree, which is: * Author: Tungyi Lin * * Derived from EDM_CF_IMX6 code by TechNexion,Inc * Ported to SolidRun microSOM by Rabeeh Khoury * * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) #define ETH_PHY_RESET IMX_GPIO_NR(4, 15) #define USB_H1_VBUS IMX_GPIO_NR(1, 0) int dram_init(void) { gd->ram_size = imx_ddr_size(); return 0; } static iomux_v3_cfg_t const uart1_pads[] = { IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; static iomux_v3_cfg_t const usdhc2_pads[] = { IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), }; static iomux_v3_cfg_t const hb_cbi_sense[] = { /* These pins are for sensing if it is a CuBox-i or a HummingBoard */ IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)), IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)), }; static iomux_v3_cfg_t const usb_pads[] = { IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; static void setup_iomux_uart(void) { SETUP_IOMUX_PADS(uart1_pads); } static struct fsl_esdhc_cfg usdhc_cfg[1] = { {USDHC2_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) { return 1; /* uSDHC2 is always present */ } int board_mmc_init(bd_t *bis) { SETUP_IOMUX_PADS(usdhc2_pads); usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); } static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), /* AR8035 reset */ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), /* AR8035 interrupt */ IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* GPIO16 -> AR8035 25MHz */ IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)), IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), }; static void setup_iomux_enet(void) { SETUP_IOMUX_PADS(enet_pads); gpio_direction_output(ETH_PHY_RESET, 0); mdelay(2); gpio_set_value(ETH_PHY_RESET, 1); } int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) phydev->drv->config(phydev); return 0; } /* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */ #define ETH_PHY_MASK ((1 << 0x0) | (1 << 0x4)) int board_eth_init(bd_t *bis) { struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; struct mii_dev *bus; struct phy_device *phydev; int ret = enable_fec_anatop_clock(0, ENET_25MHZ); if (ret) return ret; /* set gpr1[ENET_CLK_SEL] */ setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); setup_iomux_enet(); bus = fec_get_miibus(IMX_FEC_BASE, -1); if (!bus) return -EINVAL; phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII); if (!phydev) { ret = -EINVAL; goto free_bus; } debug("using phy at address %d\n", phydev->addr); ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev); if (ret) goto free_phydev; return 0; free_phydev: free(phydev); free_bus: free(bus); return ret; } #ifdef CONFIG_VIDEO_IPUV3 static void do_enable_hdmi(struct display_info_t const *dev) { imx_enable_hdmi_phy(); } struct display_info_t const displays[] = { { .bus = -1, .addr = 0, .pixfmt = IPU_PIX_FMT_RGB24, .detect = detect_hdmi, .enable = do_enable_hdmi, .mode = { .name = "HDMI", /* 1024x768@60Hz (VESA)*/ .refresh = 60, .xres = 1024, .yres = 768, .pixclock = 15384, .left_margin = 160, .right_margin = 24, .upper_margin = 29, .lower_margin = 3, .hsync_len = 136, .vsync_len = 6, .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED } } }; size_t display_count = ARRAY_SIZE(displays); static int setup_display(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; int reg; int timeout = 100000; enable_ipu_clock(); imx_setup_hdmi(); /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */ setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); reg = readl(&ccm->analog_pll_video); reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37); reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1); writel(reg, &ccm->analog_pll_video); writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; writel(reg, &ccm->analog_pll_video); while (timeout--) if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) break; if (timeout < 0) { printf("Warning: video pll lock timeout!\n"); return -ETIMEDOUT; } reg = readl(&ccm->analog_pll_video); reg |= BM_ANADIG_PLL_VIDEO_ENABLE; reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; writel(reg, &ccm->analog_pll_video); /* gate ipu1_di0_clk */ clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */ reg = readl(&ccm->chsccdr); reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) | (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) | (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); writel(reg, &ccm->chsccdr); /* enable ipu1_di0_clk */ setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); return 0; } #endif /* CONFIG_VIDEO_IPUV3 */ #ifdef CONFIG_USB_EHCI_MX6 static void setup_usb(void) { SETUP_IOMUX_PADS(usb_pads); } int board_ehci_hcd_init(int port) { if (port == 1) gpio_direction_output(USB_H1_VBUS, 1); return 0; } #endif int board_early_init_f(void) { int ret = 0; setup_iomux_uart(); #ifdef CONFIG_VIDEO_IPUV3 ret = setup_display(); #endif #ifdef CONFIG_USB_EHCI_MX6 setup_usb(); #endif return ret; } int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } static bool is_hummingboard(void) { int val1, val2; SETUP_IOMUX_PADS(hb_cbi_sense); gpio_direction_input(IMX_GPIO_NR(4, 9)); gpio_direction_input(IMX_GPIO_NR(3, 4)); val1 = gpio_get_value(IMX_GPIO_NR(4, 9)); val2 = gpio_get_value(IMX_GPIO_NR(3, 4)); /* * Machine selection - * Machine val1, val2 * ------------------------- * HB rev 3.x x 0 * CBi 0 1 * HB 1 1 */ if (val2 == 0) return true; else if (val1 == 0) return false; else return true; } int checkboard(void) { if (is_hummingboard()) puts("Board: MX6 Hummingboard\n"); else puts("Board: MX6 Cubox-i\n"); return 0; } static bool is_mx6q(void) { if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) return true; else return false; } int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG if (is_hummingboard()) setenv("board_name", "HUMMINGBOARD"); else setenv("board_name", "CUBOXI"); if (is_mx6q()) setenv("board_rev", "MX6Q"); else setenv("board_rev", "MX6DL"); #endif return 0; } #ifdef CONFIG_SPL_BUILD #include static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = { .dram_sdclk_0 = 0x00020030, .dram_sdclk_1 = 0x00020030, .dram_cas = 0x00020030, .dram_ras = 0x00020030, .dram_reset = 0x00020030, .dram_sdcke0 = 0x00003000, .dram_sdcke1 = 0x00003000, .dram_sdba2 = 0x00000000, .dram_sdodt0 = 0x00003030, .dram_sdodt1 = 0x00003030, .dram_sdqs0 = 0x00000030, .dram_sdqs1 = 0x00000030, .dram_sdqs2 = 0x00000030, .dram_sdqs3 = 0x00000030, .dram_sdqs4 = 0x00000030, .dram_sdqs5 = 0x00000030, .dram_sdqs6 = 0x00000030, .dram_sdqs7 = 0x00000030, .dram_dqm0 = 0x00020030, .dram_dqm1 = 0x00020030, .dram_dqm2 = 0x00020030, .dram_dqm3 = 0x00020030, .dram_dqm4 = 0x00020030, .dram_dqm5 = 0x00020030, .dram_dqm6 = 0x00020030, .dram_dqm7 = 0x00020030, }; static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = { .dram_sdclk_0 = 0x00000028, .dram_sdclk_1 = 0x00000028, .dram_cas = 0x00000028, .dram_ras = 0x00000028, .dram_reset = 0x000c0028, .dram_sdcke0 = 0x00003000, .dram_sdcke1 = 0x00003000, .dram_sdba2 = 0x00000000, .dram_sdodt0 = 0x00003030, .dram_sdodt1 = 0x00003030, .dram_sdqs0 = 0x00000028, .dram_sdqs1 = 0x00000028, .dram_sdqs2 = 0x00000028, .dram_sdqs3 = 0x00000028, .dram_sdqs4 = 0x00000028, .dram_sdqs5 = 0x00000028, .dram_sdqs6 = 0x00000028, .dram_sdqs7 = 0x00000028, .dram_dqm0 = 0x00000028, .dram_dqm1 = 0x00000028, .dram_dqm2 = 0x00000028, .dram_dqm3 = 0x00000028, .dram_dqm4 = 0x00000028, .dram_dqm5 = 0x00000028, .dram_dqm6 = 0x00000028, .dram_dqm7 = 0x00000028, }; static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = { .grp_ddr_type = 0x000C0000, .grp_ddrmode_ctl = 0x00020000, .grp_ddrpke = 0x00000000, .grp_addds = 0x00000030, .grp_ctlds = 0x00000030, .grp_ddrmode = 0x00020000, .grp_b0ds = 0x00000030, .grp_b1ds = 0x00000030, .grp_b2ds = 0x00000030, .grp_b3ds = 0x00000030, .grp_b4ds = 0x00000030, .grp_b5ds = 0x00000030, .grp_b6ds = 0x00000030, .grp_b7ds = 0x00000030, }; static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { .grp_ddr_type = 0x000c0000, .grp_ddrmode_ctl = 0x00020000, .grp_ddrpke = 0x00000000, .grp_addds = 0x00000028, .grp_ctlds = 0x00000028, .grp_ddrmode = 0x00020000, .grp_b0ds = 0x00000028, .grp_b1ds = 0x00000028, .grp_b2ds = 0x00000028, .grp_b3ds = 0x00000028, .grp_b4ds = 0x00000028, .grp_b5ds = 0x00000028, .grp_b6ds = 0x00000028, .grp_b7ds = 0x00000028, }; /* microSOM with Dual processor and 1GB memory */ static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = { .p0_mpwldectrl0 = 0x00000000, .p0_mpwldectrl1 = 0x00000000, .p1_mpwldectrl0 = 0x00000000, .p1_mpwldectrl1 = 0x00000000, .p0_mpdgctrl0 = 0x0314031c, .p0_mpdgctrl1 = 0x023e0304, .p1_mpdgctrl0 = 0x03240330, .p1_mpdgctrl1 = 0x03180260, .p0_mprddlctl = 0x3630323c, .p1_mprddlctl = 0x3436283a, .p0_mpwrdlctl = 0x36344038, .p1_mpwrdlctl = 0x422a423c, }; /* microSOM with Quad processor and 2GB memory */ static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = { .p0_mpwldectrl0 = 0x00000000, .p0_mpwldectrl1 = 0x00000000, .p1_mpwldectrl0 = 0x00000000, .p1_mpwldectrl1 = 0x00000000, .p0_mpdgctrl0 = 0x0314031c, .p0_mpdgctrl1 = 0x023e0304, .p1_mpdgctrl0 = 0x03240330, .p1_mpdgctrl1 = 0x03180260, .p0_mprddlctl = 0x3630323c, .p1_mprddlctl = 0x3436283a, .p0_mpwrdlctl = 0x36344038, .p1_mpwrdlctl = 0x422a423c, }; /* microSOM with Solo processor and 512MB memory */ static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = { .p0_mpwldectrl0 = 0x0045004D, .p0_mpwldectrl1 = 0x003A0047, .p0_mpdgctrl0 = 0x023C0224, .p0_mpdgctrl1 = 0x02000220, .p0_mprddlctl = 0x44444846, .p0_mpwrdlctl = 0x32343032, }; /* microSOM with Dual lite processor and 1GB memory */ static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = { .p0_mpwldectrl0 = 0x0045004D, .p0_mpwldectrl1 = 0x003A0047, .p1_mpwldectrl0 = 0x001F001F, .p1_mpwldectrl1 = 0x00210035, .p0_mpdgctrl0 = 0x023C0224, .p0_mpdgctrl1 = 0x02000220, .p1_mpdgctrl0 = 0x02200220, .p1_mpdgctrl1 = 0x02040208, .p0_mprddlctl = 0x44444846, .p1_mprddlctl = 0x4042463C, .p0_mpwrdlctl = 0x32343032, .p1_mpwrdlctl = 0x36363430, }; static struct mx6_ddr3_cfg mem_ddr_2g = { .mem_speed = 1600, .density = 2, .width = 16, .banks = 8, .rowaddr = 14, .coladdr = 10, .pagesz = 2, .trcd = 1375, .trcmin = 4875, .trasmin = 3500, .SRT = 1, }; static struct mx6_ddr3_cfg mem_ddr_4g = { .mem_speed = 1600, .density = 4, .width = 16, .banks = 8, .rowaddr = 15, .coladdr = 10, .pagesz = 2, .trcd = 1375, .trcmin = 4875, .trasmin = 3500, }; static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; writel(0x00C03F3F, &ccm->CCGR0); writel(0x0030FC03, &ccm->CCGR1); writel(0x0FFFC000, &ccm->CCGR2); writel(0x3FF00000, &ccm->CCGR3); writel(0x00FFF300, &ccm->CCGR4); writel(0x0F0000C3, &ccm->CCGR5); writel(0x000003FF, &ccm->CCGR6); } static void gpr_init(void) { struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; /* enable AXI cache for VDOA/VPU/IPU */ writel(0xF00000CF, &iomux->gpr[4]); /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ writel(0x007F007F, &iomux->gpr[6]); writel(0x007F007F, &iomux->gpr[7]); } /* * This section requires the differentiation between Solidrun mx6 boards, but * for now, it will configure only for the mx6dual hummingboard version. */ static void spl_dram_init(int width) { struct mx6_ddr_sysinfo sysinfo = { /* width of data bus: 0=16, 1=32, 2=64 */ .dsize = width / 32, /* config for full 4GB range so that get_mem_size() works */ .cs_density = 32, /* 32Gb per CS */ .ncs = 1, /* single chip select */ .cs1_mirror = 0, .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ .walat = 1, /* Write additional latency */ .ralat = 5, /* Read additional latency */ .mif3_mode = 3, /* Command prediction working mode */ .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ }; if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q)) mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); else mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); if (is_cpu_type(MXC_CPU_MX6D)) mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g); else if (is_cpu_type(MXC_CPU_MX6Q)) mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g); else if (is_cpu_type(MXC_CPU_MX6DL)) mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g); else if (is_cpu_type(MXC_CPU_MX6SOLO)) mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g); } void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ arch_cpu_init(); ccgr_init(); gpr_init(); /* iomux and setup of i2c */ board_early_init_f(); /* setup GP timer */ timer_init(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* DDR initialization */ if (is_cpu_type(MXC_CPU_MX6SOLO)) spl_dram_init(32); else spl_dram_init(64); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); } #endif