/* * Copyright 2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include #include #include #include #include #include #include #include DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_PCIE1 static struct pci_controller pcie1_hose; #endif #ifdef CONFIG_PCIE2 static struct pci_controller pcie2_hose; #endif void pci_init_board(void) { struct fsl_pci_info pci_info[2]; volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint devdisr = in_be32(&gur->devdisr); uint io_sel = (in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; int num = 0; int first_free_busno = 0; int pcie_ep, pcie_configured; debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", devdisr, io_sel, host_agent); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) printf (" eTSEC2 is in sgmii mode.\n"); #ifdef CONFIG_PCIE2 SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ puts ("\n PCIE2 connected to Slot 1 as "); printf ("%s (base address %lx)", pcie_ep ? "End Point": "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num], &pcie2_hose, first_free_busno); num++; } else { printf (" PCIE2: disabled\n"); } #else set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ #endif #ifdef CONFIG_PCIE1 SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ puts ("\n PCIE1 connected to Slot 2 as "); printf ("%s (base address %lx)", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num], &pcie1_hose, first_free_busno); num++; } else { printf (" PCIE1: disabled\n"); } #else set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif } void ft_pci_board_setup(void *blob) { /* According to h/w manual, PCIE2 is at lower address(0x9000) * than PCIE1(0xa000). * Hence PCIE2 is made to occupy the pci1 position in dts to * keep the addresses sorted there. * Generally the case with all FSL SOCs. */ #ifdef CONFIG_PCIE2 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); #endif #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); #endif }