/* * (C) Copyright 2015 Google, Inc * * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include #include #include DECLARE_GLOBAL_DATA_PTR; int board_init(void) { return 0; } int dram_init(void) { struct ram_info ram; struct udevice *dev; int ret; ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return ret; } ret = ram_get_info(dev, &ram); if (ret) { debug("Cannot get DRAM size: %d\n", ret); return ret; } debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); gd->ram_size = ram.size; return 0; } #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } #endif void lowlevel_init(void) { } static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { static const struct { char *name; int id; } clks[] = { { "osc", CLK_OSC }, { "apll", CLK_ARM }, { "dpll", CLK_DDR }, { "cpll", CLK_CODEC }, { "gpll", CLK_GENERAL }, #ifdef CONFIG_ROCKCHIP_RK3036 { "mpll", CLK_NEW }, #else { "npll", CLK_NEW }, #endif }; int ret, i; struct udevice *dev; ret = uclass_get_device(UCLASS_CLK, 0, &dev); if (ret) { printf("clk-uclass not found\n"); return 0; } for (i = 0; i < ARRAY_SIZE(clks); i++) { struct clk clk; ulong rate; clk.id = clks[i].id; ret = clk_request(dev, &clk); if (ret < 0) continue; rate = clk_get_rate(&clk); printf("%s: %lu\n", clks[i].name, rate); clk_free(&clk); } return 0; } U_BOOT_CMD( clock, 2, 1, do_clock, "display information about clocks", "" );