/* * Copyright 2014-2015 Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include #include DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_LS2085A static void erratum_a008751(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A008751 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4); #endif } static void erratum_rcw_src(void) { #if defined(CONFIG_SPL) u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; u32 val; val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); val &= ~DCFG_PORSR1_RCW_SRC; val |= DCFG_PORSR1_RCW_SRC_NOR; out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); #endif } #define I2C_DEBUG_REG 0x6 #define I2C_GLITCH_EN 0x8 /* * This erratum requires setting glitch_en bit to enable * digital glitch filter to improve clock stability. */ static void erratum_a009203(void) { u8 __iomem *ptr; #ifdef CONFIG_SYS_I2C #ifdef I2C1_BASE_ADDR ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); writeb(I2C_GLITCH_EN, ptr); #endif #ifdef I2C2_BASE_ADDR ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); writeb(I2C_GLITCH_EN, ptr); #endif #ifdef I2C3_BASE_ADDR ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); writeb(I2C_GLITCH_EN, ptr); #endif #ifdef I2C4_BASE_ADDR ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); writeb(I2C_GLITCH_EN, ptr); #endif #endif } void fsl_lsch3_early_init_f(void) { erratum_a008751(); erratum_rcw_src(); init_early_memctl_regs(); /* tighten IFC timing */ erratum_a009203(); } #elif defined(CONFIG_LS1043A) void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; #ifdef CONFIG_FSL_IFC init_early_memctl_regs(); /* tighten IFC timing */ #endif /* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A53 core cluster) */ out_le32(&cci->slave[4].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); } #endif #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { return 0; } #endif