From c70564e6b1bd08f3230182392238907f3531a87e Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Tue, 2 Dec 2008 11:48:51 +0800 Subject: NAND: Fix cache and memory inconsistency issue We load the secondary stage u-boot image from NAND to system memory by nand_load, but we did not flush d-cache to memory, nor invalidate i-cache before we jump to RAM. When the system has cache enabled and the TLB/page attribute of system memory is cacheable, it will cause issues. - 83xx family is using the d-cache lock, so all of d-cache access is cache-inhibited. so you can't see the issue. - 85xx family is using d-cache, i-cache enable, partial cache lock. you will see the issue. This patch fixes the cache issue. Signed-off-by: Dave Liu Signed-off-by: Scott Wood --- nand_spl/nand_boot_fsl_elbc.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'nand_spl/nand_boot_fsl_elbc.c') diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c index 4a961ea7b0..0d0c44e1e3 100644 --- a/nand_spl/nand_boot_fsl_elbc.c +++ b/nand_spl/nand_boot_fsl_elbc.c @@ -143,6 +143,11 @@ void nand_boot(void) * Jump to U-Boot image */ puts("transfering control\n"); + /* + * Clean d-cache and invalidate i-cache, to + * make sure that no stale data is executed. + */ + flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; uboot(); } -- cgit v1.2.1