From debb7354d1ea4f694154818df5e5b523f5c1cc1d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 26 Apr 2006 17:58:56 -0500 Subject: Initial support for MPC8641 HPCN board. --- include/asm-ppc/immap_86xx.h | 1362 +++++++++++++++++++++++++++++++++++++++++ include/asm-ppc/mmu.h | 15 +- include/asm-ppc/processor.h | 18 +- include/asm-ppc/u-boot.h | 2 +- include/common.h | 11 +- include/configs/MPC8641HPCN.h | 629 +++++++++++++++++++ include/ft_build.h | 4 +- include/mpc86xx.h | 119 ++++ include/pci.h | 6 + 9 files changed, 2160 insertions(+), 6 deletions(-) create mode 100644 include/asm-ppc/immap_86xx.h create mode 100644 include/configs/MPC8641HPCN.h create mode 100644 include/mpc86xx.h (limited to 'include') diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h new file mode 100644 index 0000000000..6bbe072b2d --- /dev/null +++ b/include/asm-ppc/immap_86xx.h @@ -0,0 +1,1362 @@ +/* + * MPC86xx Internal Memory Map + * + * Copyright(c) 2004 Freescale Semiconductor + * Jeff Brown (Jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + */ + +#ifndef __IMMAP_86xx__ +#define __IMMAP_86xx__ + + +/* Local-Access Registers and MCM Registers(0x0000-0x2000) */ +typedef struct ccsr_local_mcm { + uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */ + char res1[4]; + uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */ + char res2[4]; + uint altcar; /* 0x10 - Alternate Configuration Attribute Register */ + char res3[12]; + uint bptr; /* 0x20 - Boot Page Translation Register */ + char res4[3044]; + uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */ + char res5[4]; + uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */ + char res6[20]; + uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */ + char res7[4]; + uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */ + char res8[20]; + uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */ + char res9[4]; + uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */ + char res10[20]; + uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */ + char res11[4]; + uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */ + char res12[20]; + uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */ + char res13[4]; + uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */ + char res14[20]; + uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */ + char res15[4]; + uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */ + char res16[20]; + uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */ + char res17[4]; + uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */ + char res18[20]; + uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ + char res19[4]; + uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ + char res20[16]; + uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ + char res21[4]; + uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ + char res22[20]; + uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ + char res23[4]; + uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ + char res24[720]; + uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */ + char res25[4]; + uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ + char res26[4]; + uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */ + char res27[44]; + uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */ + uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */ + uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */ + uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */ + char res28[16]; + uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */ + uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */ + uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */ + char res29[3476]; + uint edr; /* 0x1e00 - MCM Error Detect Register */ + char res30[4]; + uint eer; /* 0x1e08 - MCM Error Enable Register */ + uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */ + uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */ + uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */ + char res31[488]; +} ccsr_local_mcm_t; + +/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */ + +typedef struct ccsr_ddr { + uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ + char res1[4]; + uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */ + char res2[4]; + uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */ + char res3[4]; + uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */ + char res4[4]; + uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */ + char res5[4]; + uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */ + char res6[84]; + uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */ + uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ + uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ + uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ + uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ + uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ + char res7[104]; + uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ + uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ + uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ + uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ + uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */ + uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ + uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ + uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ + uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ + uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ + uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ + char res8[4]; + uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ + char res9[12]; + uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ + uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ + uint init_addr; /* 0x2148 - DDR training initialzation address */ + uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */ + char res10[2728]; + uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ + uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ + char res11[512]; + uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ + uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ + uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */ + char res12[20]; + uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */ + uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */ + uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */ + char res13[20]; + uint err_detect; /* 0x2e40 - DDR Memory Error Detect */ + uint err_disable; /* 0x2e44 - DDR Memory Error Disable */ + uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */ + uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ + uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ + uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ + uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ + char res14[164]; + uint debug_1; /* 0x2f00 */ + uint debug_2; + uint debug_3; + uint debug_4; + uint debug_5; + char res15[236]; +} ccsr_ddr_t; + + +/* Daul I2C Registers(0x3000-0x4000) */ + +typedef struct ccsr_i2c { + u_char i2cadr1; /* 0x3000 - I2C 1 Address Register */ +#define MPC86xx_I2CADR_MASK 0xFE + char res1[3]; + u_char i2cfdr1; /* 0x3004 - I2C 1 Frequency Divider Register */ +#define MPC86xx_I2CFDR_MASK 0x3F + char res2[3]; + u_char i2ccr1; /* 0x3008 - I2C 1 Control Register */ +#define MPC86xx_I2CCR_MEN 0x80 +#define MPC86xx_I2CCR_MIEN 0x40 +#define MPC86xx_I2CCR_MSTA 0x20 +#define MPC86xx_I2CCR_MTX 0x10 +#define MPC86xx_I2CCR_TXAK 0x08 +#define MPC86xx_I2CCR_RSTA 0x04 +#define MPC86xx_I2CCR_BCST 0x01 + char res3[3]; + u_char i2csr1; /* 0x300c - I2C 1 Status Register */ +#define MPC86xx_I2CSR_MCF 0x80 +#define MPC86xx_I2CSR_MAAS 0x40 +#define MPC86xx_I2CSR_MBB 0x20 +#define MPC86xx_I2CSR_MAL 0x10 +#define MPC86xx_I2CSR_BCSTM 0x08 +#define MPC86xx_I2CSR_SRW 0x04 +#define MPC86xx_I2CSR_MIF 0x02 +#define MPC86xx_I2CSR_RXAK 0x01 + char res4[3]; + u_char i2cdr1; /* 0x3010 - I2C 1 Data Register */ +#define MPC86xx_I2CDR_DATA 0xFF + char res5[3]; + u_char i2cdfsrr1; /* 0x3014 - I2C 1 Digital Filtering Sampling Rate Register */ +#define MPC86xx_I2CDFSRR 0x3F + char res6[235]; + + u_char i2cadr2; /* 0x3100 - I2C 2 Address Register */ + char res7[3]; + u_char i2cfdr2; /* 0x3104 - I2C 2 Frequency Divider Register */ + char res8[3]; + u_char i2ccr2; /* 0x3108 - I2C 2 Control Register */ + char res9[3]; + u_char i2csr2; /* 0x310c - I2C 2 Status Register */ + char res10[3]; + u_char i2cdr2; /* 0x3110 - I2C 2 Data Register */ + char res11[3]; + u_char i2cdfsrr2; /* 0x3114 - I2C 2 Digital Filtering Sampling Rate Register */ + char res12[3819]; +} ccsr_i2c_t; + +/* DUART Registers(0x4000-0x5000) */ +typedef struct ccsr_duart { + char res1[1280]; + u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */ + u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */ + u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */ + u_char ulcr1; /* 0x4503 - UART1 Line Control Register */ + u_char umcr1; /* 0x4504 - UART1 Modem Control Register */ + u_char ulsr1; /* 0x4505 - UART1 Line Status Register */ + u_char umsr1; /* 0x4506 - UART1 Modem Status Register */ + u_char uscr1; /* 0x4507 - UART1 Scratch Register */ + char res2[8]; + u_char udsr1; /* 0x4510 - UART1 DMA Status Register */ + char res3[239]; + u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */ + u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */ + u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */ + u_char ulcr2; /* 0x4603 - UART2 Line Control Register */ + u_char umcr2; /* 0x4604 - UART2 Modem Control Register */ + u_char ulsr2; /* 0x4605 - UART2 Line Status Register */ + u_char umsr2; /* 0x4606 - UART2 Modem Status Register */ + u_char uscr2; /* 0x4607 - UART2 Scratch Register */ + char res4[8]; + u_char udsr2; /* 0x4610 - UART2 DMA Status Register */ + char res5[2543]; +} ccsr_duart_t; + + +/* Local Bus Controller Registers(0x5000-0x6000) */ +typedef struct ccsr_lbc { + uint br0; /* 0x5000 - LBC Base Register 0 */ + uint or0; /* 0x5004 - LBC Options Register 0 */ + uint br1; /* 0x5008 - LBC Base Register 1 */ + uint or1; /* 0x500c - LBC Options Register 1 */ + uint br2; /* 0x5010 - LBC Base Register 2 */ + uint or2; /* 0x5014 - LBC Options Register 2 */ + uint br3; /* 0x5018 - LBC Base Register 3 */ + uint or3; /* 0x501c - LBC Options Register 3 */ + uint br4; /* 0x5020 - LBC Base Register 4 */ + uint or4; /* 0x5024 - LBC Options Register 4 */ + uint br5; /* 0x5028 - LBC Base Register 5 */ + uint or5; /* 0x502c - LBC Options Register 5 */ + uint br6; /* 0x5030 - LBC Base Register 6 */ + uint or6; /* 0x5034 - LBC Options Register 6 */ + uint br7; /* 0x5038 - LBC Base Register 7 */ + uint or7; /* 0x503c - LBC Options Register 7 */ + char res1[40]; + uint mar; /* 0x5068 - LBC UPM Address Register */ + char res2[4]; + uint mamr; /* 0x5070 - LBC UPMA Mode Register */ + uint mbmr; /* 0x5074 - LBC UPMB Mode Register */ + uint mcmr; /* 0x5078 - LBC UPMC Mode Register */ + char res3[8]; + uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */ + uint mdr; /* 0x5088 - LBC UPM Data Register */ + char res4[8]; + uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */ + char res5[8]; + uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */ + uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */ + char res6[8]; + uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */ + uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */ + uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */ + uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */ + uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */ + char res7[12]; + uint lbcr; /* 0x50d0 - LBC Configuration Register */ + uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */ + char res8[3880]; +} ccsr_lbc_t; + +/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */ +typedef struct ccsr_pex { + uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */ + uint cfg_data; /* 0x8004 - PEX Configuration Data Register */ + char res1[4]; + uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */ + char res2[16]; + uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */ + uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */ + uint pme_msg_dis; /* 0x802C - PEX PME & message disable register */ + char res3[4]; + uint pm_command; /* 0x8030 - PEX PM Command register */ + char res4[3016]; + uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */ + uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */ + uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */ + uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */ + char res5[8]; + uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */ + char res6[12]; + uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */ + uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */ + uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */ + char res7[4]; + uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */ + char res8[12]; + uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */ + uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */ + uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */ + char res9[4]; + uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */ + char res10[12]; + uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */ + uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */ + uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */ + char res11[4]; + uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */ + char res12[12]; + uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */ + uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */ + uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */ + char res13[4]; + uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */ + char res14[268]; + uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */ + char res15[4]; + uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */ + uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */ + uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */ + char res16[12]; + uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */ + char res17[4]; + uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */ + uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */ + uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */ + char res18[12]; + uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */ + char res19[4]; + uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */ + char res20[4]; + uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */ + char res21[12]; + uint pedr; /* 0x8e00 - PEX Error Detect Register */ + uint pecdr; /* 0x8e04 - PEX Error Capture Disable Register */ + uint peer; /* 0x8e08 - PEX Error Enable Register */ + uint perr_cap0; /* 0x8e0c - PEX Error Capture Register 0 */ + uint perr_cap1; /* 0x8e10 - PEX Error Capture Register 1 */ + uint perr_cap2; /* 0x8e14 - PEX Error Capture Register 2 */ + uint perr_cap3; /* 0x8e18 - PEX Error Capture Register 3 */ + char res22[100]; + uint perr_stat; /* 0x8e80 - PEX Error Status Register */ + char res23[124]; + uint pdebug; /* 0x8f00 - PEX Debug Register */ + char res24[248]; //Sri: changed this because of adding 4 bytes before 0x?8020. +} ccsr_pex_t; + +/* Hyper Transport Register Block (0xA000-0xB000) */ +typedef struct ccsr_ht { + uint hcfg_addr; /* 0xa000 - HT Configuration Address register */ + uint hcfg_data; /* 0xa004 - HT Configuration Data register */ + char res1[3064]; + uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */ + char res2[12]; + uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */ + char res3[12]; + uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */ + char res4[4]; + uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */ + char res5[4]; + uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */ + char res6[12]; + uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */ + char res7[4]; + uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */ + char res8[4]; + uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */ + char res9[12]; + uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */ + char res10[4]; + uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */ + char res11[4]; + uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */ + char res12[12]; + uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */ + char res13[4]; + uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */ + char res14[4]; + uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */ + char res15[236]; + uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */ + char res16[4]; + uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */ + char res17[4]; + uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */ + char res18[12]; + uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */ + char res19[4]; + uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */ + char res20[4]; + uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */ + char res21[12]; + uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */ + char res22[4]; + uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */ + char res23[4]; + uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */ + char res24[12]; + uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */ + char res25[4]; + uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */ + char res26[4]; + uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */ + char res27[12]; + uint hedr; /* 0xae00 - HT Error Detect register */ + char res28[4]; + uint heier; /* 0xae08 - HT Error Interrupt Enable register */ + char res29[4]; + uint hecdr; /* 0xae10 - HT Error Capture Disbale register */ + char res30[12]; + uint hecsr; /* 0xae20 - HT Error Capture Status register */ + char res31[4]; + uint hec0; /* 0xae28 - HT Error Capture 0 register */ + uint hec1; /* 0xae2c - HT Error Capture 1 register */ + uint hec2; /* 0xae30 - HT Error Capture 2 register */ + char res32[460]; +} ccsr_ht_t; + +/* DMA Registers(0x2_1000-0x2_2000) */ +typedef struct ccsr_dma { + char res1[256]; + uint mr0; /* 0x21100 - DMA 0 Mode Register */ + uint sr0; /* 0x21104 - DMA 0 Status Register */ + char res2[4]; + uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */ + uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */ + uint sar0; /* 0x21114 - DMA 0 Source Address Register */ + uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */ + uint dar0; /* 0x2111c - DMA 0 Destination Address Register */ + uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */ + char res3[4]; + uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */ + char res4[8]; + uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */ + char res5[4]; + uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */ + uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */ + uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */ + char res6[56]; + uint mr1; /* 0x21180 - DMA 1 Mode Register */ + uint sr1; /* 0x21184 - DMA 1 Status Register */ + char res7[4]; + uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */ + uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */ + uint sar1; /* 0x21194 - DMA 1 Source Address Register */ + uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */ + uint dar1; /* 0x2119c - DMA 1 Destination Address Register */ + uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */ + char res8[4]; + uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */ + char res9[8]; + uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */ + char res10[4]; + uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */ + uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */ + uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */ + char res11[56]; + uint mr2; /* 0x21200 - DMA 2 Mode Register */ + uint sr2; /* 0x21204 - DMA 2 Status Register */ + char res12[4]; + uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */ + uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */ + uint sar2; /* 0x21214 - DMA 2 Source Address Register */ + uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */ + uint dar2; /* 0x2121c - DMA 2 Destination Address Register */ + uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */ + char res13[4]; + uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */ + char res14[8]; + uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */ + char res15[4]; + uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */ + uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */ + uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */ + char res16[56]; + uint mr3; /* 0x21280 - DMA 3 Mode Register */ + uint sr3; /* 0x21284 - DMA 3 Status Register */ + char res17[4]; + uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */ + uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */ + uint sar3; /* 0x21294 - DMA 3 Source Address Register */ + uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */ + uint dar3; /* 0x2129c - DMA 3 Destination Address Register */ + uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */ + char res18[4]; + uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */ + char res19[8]; + uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */ + char res20[4]; + uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */ + uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */ + uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */ + char res21[56]; + uint dgsr; /* 0x21300 - DMA General Status Register */ + char res22[3324]; +} ccsr_dma_t; + +/* tsec1-4: 24000-28000 */ +typedef struct ccsr_tsec { + uint id; /* 0x24000 - Controller ID Register */ + char res1[12]; + uint ievent; /* 0x24010 - Interrupt Event Register */ + uint imask; /* 0x24014 - Interrupt Mask Register */ + uint edis; /* 0x24018 - Error Disabled Register */ + char res2[4]; + uint ecntrl; /* 0x24020 - Ethernet Control Register */ + char res2_1[4]; + uint ptv; /* 0x24028 - Pause Time Value Register */ + uint dmactrl; /* 0x2402c - DMA Control Register */ + uint tbipa; /* 0x24030 - TBI PHY Address Register */ + char res3[88]; + uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */ + char res4[8]; + uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */ + uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */ + char res4_1[4]; + uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */ + uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */ + char res5[84]; + uint tctrl; /* 0x24100 - Transmit Control Register */ + uint tstat; /* 0x24104 - Transmit Status Register */ + uint dfvlan; /* 0x24108 - Default VLAN control word */ + char res6[4]; + uint txic; /* 0x24110 - Transmit interrupt coalescing Register */ + uint tqueue; /* 0x24114 - Transmit Queue Control Register */ + char res7[40]; + uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */ + uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */ + char res8[52]; + uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */ + char res9[4]; + uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */ + char res10[4]; + uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */ + char res11[4]; + uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */ + char res12[4]; + uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */ + char res13[4]; + uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */ + char res14[4]; + uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */ + char res15[4]; + uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */ + char res16[4]; + uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */ + char res17[64]; + uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */ + uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */ + char res18[4]; + uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */ + char res19[4]; + uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */ + char res20[4]; + uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */ + char res21[4]; + uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */ + char res22[4]; + uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */ + char res23[4]; + uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */ + char res24[4]; + uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */ + char res25[192]; + uint rctrl; /* 0x24300 - Receive Control Register */ + uint rstat; /* 0x24304 - Receive Status Register */ + char res26[8]; + uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */ + uint rqueue; /* 0x24314 - Receive queue control register */ + char res27[24]; + uint rbifx; /* 0x24330 - Receive bit field extract control Register */ + uint rqfar; /* 0x24334 - Receive queue filing table address Register */ + uint rqfcr; /* 0x24338 - Receive queue filing table control Register */ + uint rqfpr; /* 0x2433c - Receive queue filing table property Register */ + uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */ + char res28[56]; + uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */ + char res29[4]; + uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */ + char res30[4]; + uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */ + char res31[4]; + uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */ + char res32[4]; + uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */ + char res33[4]; + uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */ + char res34[4]; + uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */ + char res35[4]; + uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */ + char res36[4]; + uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */ + char res37[64]; + uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */ + uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */ + char res38[4]; + uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */ + char res39[4]; + uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */ + char res40[4]; + uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */ + char res41[4]; + uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */ + char res42[4]; + uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */ + char res43[4]; + uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */ + char res44[4]; + uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */ + char res45[192]; + uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */ + uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */ + uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */ + uint hafdup; /* 0x2450c - Half Duplex Register */ + uint maxfrm; /* 0x24510 - Maximum Frame Length Register */ + char res46[12]; + uint miimcfg; /* 0x24520 - MII Management Configuration Register */ + uint miimcom; /* 0x24524 - MII Management Command Register */ + uint miimadd; /* 0x24528 - MII Management Address Register */ + uint miimcon; /* 0x2452c - MII Management Control Register */ + uint miimstat; /* 0x24530 - MII Management Status Register */ + uint miimind; /* 0x24534 - MII Management Indicator Register */ + uint ifctrl; /* 0x24538 - Interface Contrl Register */ + uint ifstat; /* 0x2453c - Interface Status Register */ + uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */ + uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */ + uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */ + uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */ + uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */ + uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */ + uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */ + uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */ + uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */ + uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */ + uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */ + uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */ + uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */ + uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */ + uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */ + uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */ + uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */ + uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */ + uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */ + uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */ + uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */ + uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */ + uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */ + uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */ + uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */ + uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */ + uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */ + uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */ + uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */ + uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */ + uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */ + uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */ + char res48[192]; + uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */ + uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */ + uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */ + uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */ + uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */ + uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */ + uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ + uint rbyt; /* 0x2469c - Receive Byte Counter */ + uint rpkt; /* 0x246a0 - Receive Packet Counter */ + uint rfcs; /* 0x246a4 - Receive FCS Error Counter */ + uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */ + uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */ + uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */ + uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */ + uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */ + uint raln; /* 0x246bc - Receive Alignment Error Counter */ + uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */ + uint rcde; /* 0x246c4 - Receive Code Error Counter */ + uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */ + uint rund; /* 0x246cc - Receive Undersize Packet Counter */ + uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */ + uint rfrg; /* 0x246d4 - Receive Fragments Counter */ + uint rjbr; /* 0x246d8 - Receive Jabber Counter */ + uint rdrp; /* 0x246dc - Receive Drop Counter */ + uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */ + uint tpkt; /* 0x246e4 - Transmit Packet Counter */ + uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */ + uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */ + uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */ + uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */ + uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */ + uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */ + uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */ + uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */ + uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */ + uint tncl; /* 0x2470c - Transmit Total Collision Counter */ + char res49[4]; + uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */ + uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */ + uint tfcs; /* 0x2471c - Transmit FCS Error Counter */ + uint txcf; /* 0x24720 - Transmit Control Frame Counter */ + uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */ + uint tund; /* 0x24728 - Transmit Undersize Frame Counter */ + uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */ + uint car1; /* 0x24730 - Carry Register One */ + uint car2; /* 0x24734 - Carry Register Two */ + uint cam1; /* 0x24738 - Carry Mask Register One */ + uint cam2; /* 0x2473c - Carry Mask Register Two */ + uint rrej; /* 0x24740 - Receive filer rejected packet counter */ + char res50[188]; + uint iaddr0; /* 0x24800 - Indivdual address register 0 */ + uint iaddr1; /* 0x24804 - Indivdual address register 1 */ + uint iaddr2; /* 0x24808 - Indivdual address register 2 */ + uint iaddr3; /* 0x2480c - Indivdual address register 3 */ + uint iaddr4; /* 0x24810 - Indivdual address register 4 */ + uint iaddr5; /* 0x24814 - Indivdual address register 5 */ + uint iaddr6; /* 0x24818 - Indivdual address register 6 */ + uint iaddr7; /* 0x2481c - Indivdual address register 7 */ + char res51[96]; + uint gaddr0; /* 0x24880 - Global address register 0 */ + uint gaddr1; /* 0x24884 - Global address register 1 */ + uint gaddr2; /* 0x24888 - Global address register 2 */ + uint gaddr3; /* 0x2488c - Global address register 3 */ + uint gaddr4; /* 0x24890 - Global address register 4 */ + uint gaddr5; /* 0x24894 - Global address register 5 */ + uint gaddr6; /* 0x24898 - Global address register 6 */ + uint gaddr7; /* 0x2489c - Global address register 7 */ + char res52[352]; + uint fifocfg; /* 0x24A00 - FIFO interface configuration register */ + char res53[500]; + uint attr; /* 0x24BF8 - DMA Attribute register */ + uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */ + char res54[1024]; +} ccsr_tsec_t; + +/* PIC Registers(0x4_0000-0x6_1000) */ + +typedef struct ccsr_pic { + char res1[64]; + uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */ + char res2[12]; + uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */ + char res3[12]; + uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */ + char res4[12]; + uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */ + char res5[12]; + uint ctpr; /* 0x40080 - Current Task Priority Register */ + char res6[12]; + uint whoami; /* 0x40090 - Who Am I Register */ + char res7[12]; + uint iack; /* 0x400a0 - Interrupt Acknowledge Register */ + char res8[12]; + uint eoi; /* 0x400b0 - End Of Interrupt Register */ + char res9[3916]; + uint frr; /* 0x41000 - Feature Reporting Register */ + char res10[28]; + uint gcr; /* 0x41020 - Global Configuration Register */ + char res11[92]; + uint vir; /* 0x41080 - Vendor Identification Register */ + char res12[12]; + uint pir; /* 0x41090 - Processor Initialization Register */ + char res13[12]; + uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */ + char res14[12]; + uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */ + char res15[12]; + uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */ + char res16[12]; + uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */ + char res17[12]; + uint svr; /* 0x410e0 - Spurious Vector Register */ + char res18[12]; + uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */ + char res19[12]; + uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */ + char res20[12]; + uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */ + char res21[12]; + uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */ + char res22[12]; + uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */ + char res23[12]; + uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */ + char res24[12]; + uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */ + char res25[12]; + uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */ + char res26[12]; + uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */ + char res27[12]; + uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */ + char res28[12]; + uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */ + char res29[12]; + uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */ + char res30[12]; + uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */ + char res31[12]; + uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */ + char res32[12]; + uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */ + char res33[12]; + uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */ + char res34[12]; + uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */ + char res35[268]; + uint tcr; /* 0x41300 - Timer Control Register */ + char res36[12]; + uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */ + char res37[12]; + uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */ + char res38[12]; + uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */ + char res39[12]; + uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */ + char res40[12]; + uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */ + char res41[12]; + uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */ + char res42[12]; + uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */ + char res43[12]; + uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */ + char res44[12]; + uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */ + char res45[12]; + uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */ + char res46[12]; + uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */ + char res47[12]; + uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */ + char res48[60]; + uint msgr0; /* 0x41400 - Message Register 0 */ + char res49[12]; + uint msgr1; /* 0x41410 - Message Register 1 */ + char res50[12]; + uint msgr2; /* 0x41420 - Message Register 2 */ + char res51[12]; + uint msgr3; /* 0x41430 - Message Register 3 */ + char res52[204]; + uint mer; /* 0x41500 - Message Enable Register */ + char res53[12]; + uint msr; /* 0x41510 - Message Status Register */ + char res54[60140]; + uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */ + char res55[12]; + uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */ + char res56[12]; + uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */ + char res57[12]; + uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */ + char res58[12]; + uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */ + char res59[12]; + uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */ + char res60[12]; + uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */ + char res61[12]; + uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */ + char res62[12]; + uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */ + char res63[12]; + uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */ + char res64[12]; + uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */ + char res65[12]; + uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */ + char res66[12]; + uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */ + char res67[12]; + uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */ + char res68[12]; + uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */ + char res69[12]; + uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */ + char res70[12]; + uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */ + char res71[12]; + uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */ + char res72[12]; + uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */ + char res73[12]; + uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */ + char res74[12]; + uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */ + char res75[12]; + uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */ + char res76[12]; + uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */ + char res77[12]; + uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */ + char res78[140]; + uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */ + char res79[12]; + uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */ + char res80[12]; + uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */ + char res81[12]; + uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */ + char res82[12]; + uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */ + char res83[12]; + uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */ + char res84[12]; + uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */ + char res85[12]; + uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */ + char res86[12]; + uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */ + char res87[12]; + uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */ + char res88[12]; + uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */ + char res89[12]; + uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */ + char res90[12]; + uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */ + char res91[12]; + uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */ + char res92[12]; + uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */ + char res93[12]; + uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */ + char res94[12]; + uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */ + char res95[12]; + uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */ + char res96[12]; + uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */ + char res97[12]; + uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */ + char res98[12]; + uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */ + char res99[12]; + uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */ + char res100[12]; + uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */ + char res101[12]; + uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */ + char res102[12]; + uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */ + char res103[12]; + uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */ + char res104[12]; + uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */ + char res105[12]; + uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */ + char res106[12]; + uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */ + char res107[12]; + uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */ + char res108[12]; + uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */ + char res109[12]; + uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */ + char res110[12]; + uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */ + char res111[12]; + uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */ + char res112[12]; + uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */ + char res113[12]; + uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */ + char res114[12]; + uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */ + char res115[12]; + uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */ + char res116[12]; + uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */ + char res117[12]; + uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */ + char res118[12]; + uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */ + char res119[12]; + uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */ + char res120[12]; + uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */ + char res121[12]; + uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */ + char res122[12]; + uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */ + char res123[12]; + uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */ + char res124[12]; + uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */ + char res125[12]; + uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */ + char res126[12]; + uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */ + char res127[12]; + uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */ + char res128[12]; + uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */ + char res129[12]; + uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */ + char res130[12]; + uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */ + char res131[12]; + uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */ + char res132[12]; + uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */ + char res133[12]; + uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */ + char res134[12]; + uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */ + char res135[12]; + uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */ + char res136[12]; + uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */ + char res137[12]; + uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */ + char res138[12]; + uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */ + char res139[12]; + uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */ + char res140[12]; + uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */ + char res141[12]; + uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */ + char res142[4108]; + uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */ + char res143[12]; + uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */ + char res144[12]; + uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */ + char res145[12]; + uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */ + char res146[12]; + uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */ + char res147[12]; + uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */ + char res148[12]; + uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */ + char res149[12]; + uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */ + char res150[59852]; + uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */ + char res151[12]; + uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */ + char res152[12]; + uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */ + char res153[12]; + uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */ + char res154[12]; + uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */ + char res155[12]; + uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */ + char res156[12]; + uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */ + char res157[12]; + uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */ + char res158[3916]; +} ccsr_pic_t; + +/* RapidIO Registers(0xc_0000-0xe_0000) */ + +typedef struct ccsr_rio { + uint didcar; /* 0xc0000 - Device Identity Capability Register */ + uint dicar; /* 0xc0004 - Device Information Capability Register */ + uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */ + uint aicar; /* 0xc000c - Assembly Information Capability Register */ + uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */ + uint spicar; /* 0xc0014 - Switch Port Information Capability Register */ + uint socar; /* 0xc0018 - Source Operations Capability Register */ + uint docar; /* 0xc001c - Destination Operations Capability Register */ + char res1[32]; + uint msr; /* 0xc0040 - Mailbox Command And Status Register */ + uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */ + char res2[4]; + uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */ + char res3[12]; + uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */ + uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */ + char res4[4]; + uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */ + uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */ + char res5[144]; + uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */ + char res6[28]; + uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */ + uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */ + char res7[20]; + uint pgccsr; /* 0xc013c - Port General Command and Status Register */ + uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */ + uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */ + uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */ + char res8[12]; + uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */ + uint pccsr; /* 0xc015c - Port Control Command and Status Register */ + char res9[1184]; + uint erbh; /* 0xc0600 - Error Reporting Block Header Register */ + char res10[4]; + uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */ + uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */ + char res11[4]; + uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */ + uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */ + uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */ + char res12[32]; + uint edcsr; /* 0xc0640 - Port 0 error detect status register */ + uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */ + uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */ + uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */ + uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */ + uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */ + uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */ + char res13[12]; + uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */ + uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/ + char res14[63892]; + uint llcr; /* 0xd0004 - Logical Layer Configuration Register */ + char res15[12]; + uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */ + char res16[12]; + uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */ + char res17[92]; + uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */ + char res18[124]; + uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */ + char res19[28]; + uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */ + char res20[12]; + uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */ + char res21[12]; + uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */ + char res22[20]; + uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */ + char res23[4]; + uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */ + char res24[2716]; + uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ + uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */ + char res25[8]; + uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ + char res26[12]; + uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */ + uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */ + uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */ + char res27[4]; + uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ + uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */ + uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */ + uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */ + uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */ + uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */ + uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */ + char res28[4]; + uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ + uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */ + uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */ + uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */ + uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */ + uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */ + uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */ + char res29[4]; + uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ + uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */ + uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */ + uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */ + uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */ + uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */ + uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */ + char res30[4]; + uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ + uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */ + uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */ + uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */ + uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */ + uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */ + uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */ + char res31[4]; + uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ + uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */ + uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */ + uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */ + uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */ + uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */ + uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */ + char res32[4]; + uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ + uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */ + uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */ + uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */ + uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */ + uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */ + uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */ + char res33[4]; + uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ + uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */ + uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */ + uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */ + uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */ + uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */ + uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */ + char res34[4]; + uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ + uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */ + uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */ + uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */ + char res35[64]; + uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */ + uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */ + char res36[4]; + uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ + char res37[12]; + uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */ + char res38[4]; + uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */ + char res39[4]; + uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ + char res40[12]; + uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */ + char res41[4]; + uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */ + char res42[4]; + uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ + char res43[12]; + uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */ + char res44[4]; + uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */ + char res45[4]; + uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ + char res46[12]; + uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */ + char res47[12]; + uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ + char res48[12]; + uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */ + uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */ + uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */ + uint pecr; /* 0xd0e0c - Port Error Control Register */ + uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */ + uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ + uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ + char res49[4]; + uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ + char res50[4]; + uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ + uint prtr; /* 0xd0e2c - Port Retry Threshold Register */ + char res51[8656]; + uint omr; /* 0xd3000 - Outbound Mode Register */ + uint osr; /* 0xd3004 - Outbound Status Register */ + uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */ + uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */ + uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */ + uint osar; /* 0xd3014 - Outbound Unit Source Address Register */ + uint odpr; /* 0xd3018 - Outbound Destination Port Register */ + uint odatr; /* 0xd301c - Outbound Destination Attributes Register */ + uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */ + uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */ + uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */ + uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */ + uint omgr; /* 0xd3030 - Outbound Multicast Group Register */ + uint omlr; /* 0xd3034 - Outbound Multicast List Register */ + char res52[40]; + uint imr; /* 0xd3060 - Outbound Mode Register */ + uint isr; /* 0xd3064 - Inbound Status Register */ + uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */ + uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */ + uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */ + uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */ + uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */ + char res53[900]; + uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */ + uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */ + char res54[16]; + uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */ + uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */ + char res55[12]; + uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */ + char res56[48]; + uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */ + uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */ + uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */ + uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */ + uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */ + uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */ + uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */ + char res57[100]; + uint pwmr; /* 0xd34e0 - Port-Write Mode Register */ + uint pwsr; /* 0xd34e4 - Port-Write Status Register */ + uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */ + uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */ + char res58[51984]; +} ccsr_rio_t; + +/* Global Utilities Register Block(0xe_0000-0xf_ffff) */ +typedef struct ccsr_gur { + uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ + uint porbmsr; /* 0xe0004 - POR boot mode status register */ +#define MPC86xx_PORBMSR_HA 0x00060000 + uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ + uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ +#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000 + uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ + char res1[12]; + uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ + char res2[12]; + uint gpiocr; /* 0xe0030 - GPIO control register */ + char res3[12]; + uint gpoutdr; /* 0xe0040 - General-purpose output data register */ + char res4[12]; + uint gpindr; /* 0xe0050 - General-purpose input data register */ + char res5[12]; + uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ + char res6[12]; + uint devdisr; /* 0xe0070 - Device disable control */ +#define MPC86xx_DEVDISR_PCIEX1 0x80000000 +#define MPC86xx_DEVDISR_PCIEX2 0x40000000 + char res7[12]; + uint powmgtcsr; /* 0xe0080 - Power management status and control register */ + char res8[12]; + uint mcpsumr; /* 0xe0090 - Machine check summary register */ + char res9[12]; + uint pvr; /* 0xe00a0 - Processor version register */ + uint svr; /* 0xe00a4 - System version register */ + char res10[3416]; + uint clkocr; /* 0xe0e00 - Clock out select register */ + char res11[12]; + uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ + char res12[12]; + uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ + int res13[57]; + uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/ + int res14[6]; + uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ + char res15[61656]; +} ccsr_gur_t; + +typedef struct immap { + ccsr_local_mcm_t im_local_mcm; + ccsr_ddr_t im_ddr1; + ccsr_i2c_t im_i2c; + ccsr_duart_t im_duart; + ccsr_lbc_t im_lbc; + ccsr_ddr_t im_ddr2; + char res1[4096]; + ccsr_pex_t im_pex1; + ccsr_pex_t im_pex2; + ccsr_ht_t im_ht; + char res2[90112]; + ccsr_dma_t im_dma; + char res3[8192]; + ccsr_tsec_t im_tsec1; + ccsr_tsec_t im_tsec2; + ccsr_tsec_t im_tsec3; + ccsr_tsec_t im_tsec4; + char res4[98304]; + ccsr_pic_t im_pic; + char res5[389120]; + ccsr_rio_t im_rio; + ccsr_gur_t im_gur; +} immap_t; + +extern immap_t *immr; + +#endif /*__IMMAP_86xx__*/ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 2606b79a24..612b5df487 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -434,19 +434,28 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define BOOKE_PAGESZ_1GB 10 #define BOOKE_PAGESZ_4GB 11 +#if defined(CONFIG_MPC86xx) +#define LAWBAR_BASE_ADDR 0x00FFFFFF +#define LAWAR_TRGT_IF 0x01F00000 +#else #define LAWBAR_BASE_ADDR 0x000FFFFF -#define LAWAR_EN 0x80000000 #define LAWAR_TRGT_IF 0x00F00000 +#endif +#define LAWAR_EN 0x80000000 #define LAWAR_SIZE 0x0000003F #define LAWAR_TRGT_IF_PCI 0x00000000 #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 +#define LAWAR_TRGT_IF_HT 0x00200000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 +#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 #define LAWAR_TRGT_IF_RIO 0x00c00000 #define LAWAR_TRGT_IF_DDR 0x00f00000 +#define LAWAR_TRGT_IF_DDR1 0x00f00000 +#define LAWAR_TRGT_IF_DDR2 0x01600000 #define LAWAR_SIZE_BASE 0xa #define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) @@ -469,5 +478,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) #define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) #define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) +#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) +#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) +#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) +#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) #endif /* _PPC_MMU_H_ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 811378383d..1848aaf8cd 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -264,6 +264,7 @@ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ #define SPRN_MBAR 0x137 /* System memory base address */ @@ -443,6 +444,11 @@ #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ #define ESR_ST 0x00800000 /* Store Operation */ +#if defined(CONFIG_MPC86xx) +#define SPRN_MSSCRO 0x3f6 +#endif + + /* Short-hand versions for a number of the above SPRNs */ #define CTR SPRN_CTR /* Counter Register */ @@ -501,10 +507,14 @@ #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ +#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ -#if defined(CONFIG_E500) +#if defined(CONFIG_MPC86xx) +#define MSSCR0 SPRN_MSSCRO +#endif +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define PIR SPRN_PIR #endif #define SVR SPRN_SVR /* System-On-Chip Version Register */ @@ -538,7 +548,7 @@ #define CSRR0 SPRN_CSRR0 #define CSRR1 SPRN_CSRR1 #define IVPR SPRN_IVPR -#define USPRG0 SPRN_USPRG0 +#define USPRG0 SPRN_USPRG #define SPRG4R SPRN_SPRG4R #define SPRG5R SPRN_SPRG5R #define SPRG6R SPRN_SPRG6R @@ -755,6 +765,8 @@ #define PVR_85xx_REV1 (PVR_85xx | 0x0010) #define PVR_85xx_REV2 (PVR_85xx | 0x0020) +#define PVR_86xx 0x80040000 +#define PVR_86xx_REV1 (PVR_86xx | 0x0010) /* * For the 8xx processors, all of them report the same PVR family for @@ -808,6 +820,8 @@ #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 +#define SVR_8641 0x8090 +#define SVR_8641D 0x8091 /* I am just adding a single entry for 8260 boards. I think we may be * able to combine mbx, fads, rpxlite, bseip, and classic into a single diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index f7aa55f334..f335cd856a 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -45,7 +45,7 @@ typedef struct bd_info { unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ #if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ - || defined(CONFIG_E500) + || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif #if defined(CONFIG_MPC5xxx) diff --git a/include/common.h b/include/common.h index 5d8b15628b..83ccf7c987 100644 --- a/include/common.h +++ b/include/common.h @@ -79,6 +79,10 @@ typedef volatile unsigned char vu_char; #endif #include #endif +#ifdef CONFIG_MPC86xx +#include +#include +#endif #ifdef CONFIG_MPC85xx #include #include @@ -366,6 +370,7 @@ void trap_init (ulong); defined (CONFIG_74xx) || \ defined (CONFIG_MPC8220) || \ defined (CONFIG_MPC85xx) || \ + defined (CONFIG_MPC86xx) || \ defined (CONFIG_MPC83XX) unsigned char in8(unsigned int); void out8(unsigned int, unsigned char); @@ -454,6 +459,10 @@ ulong get_bus_freq (ulong); typedef MPC85xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); #endif +#if defined(CONFIG_MPC86xx) +typedef MPC86xx_SYS_INFO sys_info_t; +void get_sys_info ( sys_info_t * ); +#endif #if defined(CONFIG_4xx) || defined(CONFIG_IOP480) # if defined(CONFIG_440) @@ -468,7 +477,7 @@ void get_sys_info ( sys_info_t * ); #if defined(CONFIG_8xx) || defined(CONFIG_8260) void cpu_init_f (volatile immap_t *immr); #endif -#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx) void cpu_init_f (void); #endif diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h new file mode 100644 index 0000000000..8d2e08851e --- /dev/null +++ b/include/configs/MPC8641HPCN.h @@ -0,0 +1,629 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8641hpc3 board configuration file + * + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_MPC86xx 1 /* MPC86xx */ +#define CONFIG_MPC8641 1 /* MPC8641 specific */ +#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ +#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ +#undef DEBUG + +//#define RUN_DIAG 1 +#ifdef RUN_DIAG +#define CFG_DIAG_ADDR 0xff800000 +#endif +#define CFG_RESET_ADDRESS 0xfff00100 + +//#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +/*#define CONFIG_DDR_ECC */ /* only for ECC DDR module */ +/*#define CONFIG_DDR_DLL */ /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + + +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + + +#define CONFIG_ALTIVEC 1 +/*----------------------------------------------------------------------- + * L2CR setup -- make sure this is right for your board! + */ + +#define CFG_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +#ifndef CONFIG_SYS_CLK_FREQ +//#define CONFIG_SYS_CLK_FREQ 33000000 +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +/* JB - XXX - Are these available on 86xx? */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define MPC86xx_DDR_SDRAM_CLK_CNTL + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +#else + /* + * Manually set up DDR parameters + */ + +/* DDR I */ +#if 1 + #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ + + #define CFG_DDR_CS0_BNDS 0x0000000F + #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ + #define CFG_DDR_EXT_REFRESH 0x00000000 + #define CFG_DDR_TIMING_0 0x00260802 + #define CFG_DDR_TIMING_1 0x39357322 + #define CFG_DDR_TIMING_2 0x14904cc8 + #define CFG_DDR_MODE_1 0x00480432 + #define CFG_DDR_MODE_2 0x00000000 + #define CFG_DDR_INTERVAL 0x06090100 + #define CFG_DDR_DATA_INIT 0xdeadbeef + #define CFG_DDR_CLK_CTRL 0x03800000 + #define CFG_DDR_OCD_CTRL 0x00000000 + #define CFG_DDR_OCD_STATUS 0x00000000 + #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ + #define CFG_DDR_CONTROL2 0x04400000 + + //Not used in fixed_sdram function + + #define CFG_DDR_MODE 0x00000022 + #define CFG_DDR_CS1_BNDS 0x00000000 + #define CFG_DDR_CS2_BNDS 0x00000FFF //Not done + #define CFG_DDR_CS3_BNDS 0x00000FFF //Not done + #define CFG_DDR_CS4_BNDS 0x00000FFF //Not done + #define CFG_DDR_CS5_BNDS 0x00000FFF //Not done + + + +#endif +#endif + + +/* + * SDRAM on the Local Bus + */ +//#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +//#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 + * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff + * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. + * However, when u-boot comes up, the flash_init needs hard start addresses + * to build its info table. For user convenience, we have the flash addresses + * as fe800000 and ff800000. That way, when we do flash operations, u-boot + * knows where the flash is and the user can download u-boot code from promjet to + * fef00000 <- more intuitive than fe700000. Note that, on switching the boot + * location, fef00000 becomes fff00000. +*/ +#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ +#define CFG_FLASH_BASE2 0xff800000 + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} + + +/*Sri: This looks like a good place to init all the Local Bus chip selects*/ + +#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ +#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ + +#define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ +#define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ + +#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ +#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ + +#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ +#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ + +#define PIXIS_BASE 0xf8100000 /* PIXIS registers*/ +#define PIXIS_ID 0x0 /* MPC8641HPCN Board ID at offset 0*/ +#define PIXIS_VER 0x1 /* MPC8641HPCN board version version at offset 1*/ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2*/ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register*/ +#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ + + +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +//#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +/*#define CFG_HPCN_FLASH_CFI_DRIVER */ +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#if !defined(CFG_RAMBOOT) +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +#define CONFIG_L1_INIT_RAM +#undef CFG_INIT_RAM_LOCK +#ifndef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ +#else +#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ +#endif +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8641@0" +#define OF_SOC "soc8641@f8000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/* RapidIO MMU */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +//#define CFG_PCI1_MEM_BASE 0xd0000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +//#define CFG_PCI1_IO_BASE 0xe0000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +//#define CFG_PCI1_IO_BUS 0x00000000 +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +/* For RTL8139 */ +#define _IO_BASE 0x00000000 + +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0xe3000000 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ + +// #define CFG_PCI1_MEM_BASE 0x80000000 +// #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +// #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +// #define CFG_PCI1_IO_BASE 0xe2000000 +// #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +// #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + + + +#if defined(CONFIG_PCI) + + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +//#define CFG_SCSI_SCAN_BUS_REVERSE + + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_RTL8139 + + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +//#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ + +#define CONFIG_MPC86XX_TSEC1 1 +#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" +#define CONFIG_MPC86XX_TSEC2 1 +#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" +#define CONFIG_MPC86XX_TSEC3 1 +#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" +#define CONFIG_MPC86XX_TSEC4 1 +#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" + + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 2 +#define TSEC4_PHY_ADDR 3 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#endif /* CONFIG_TSEC_ENET */ + + +/* BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +//#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (0x0 | BATU_BL_512M | BATU_VS | BATU_VP) +//#define CFG_IBAT0L CFG_DBAT0L +//#define CFG_IBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT0L (0x0| BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) +#define CFG_IBAT0U CFG_DBAT0U + +/* BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 512M PCI-Express 1 Memory + * 0xa000_0000 512M PCI-Express 2 Memory + ** SS - Changed it for operating from 0xd0000000 + */ +#define CFG_DBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT1U CFG_DBAT1U + +/* BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M RapidIO Memory + */ +#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT2U CFG_DBAT2U + +/* BAT3 4M Cache-inhibited, guarded + * 0xf800_0000 4M CCSR + */ +#define CFG_DBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT3U CFG_DBAT3U + +/* BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 + ** SS - Note that this is at 0xe0000000 + */ +#define CFG_DBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT4U CFG_DBAT4U + +/* BAT5 128K Cacheable, non-guarded + * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_IBAT5L CFG_DBAT5L +#define CFG_IBAT5U CFG_DBAT5U + +/* BAT6 32M Cache-inhibited, guarded + * 0xfe00_0000 32M FLASH + */ +#define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT6U CFG_DBAT6U + + +#define CFG_DBAT7L 0x00000000 +#define CFG_DBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 +#define CFG_IBAT7U 0x00000000 + + + + +/* + * Environment + */ + #ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 + #else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 + #endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_IMLS \ + | CFG_CMD_FLASH \ + | CFG_CMD_LOADS)) + #else + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_IMLS \ + | CFG_CMD_FLASH \ + | CFG_CMD_LOADS)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #else + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:00:00:01 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD +#endif + +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 +#define CONFIG_HAS_ETH3 1 + +#define CONFIG_IPADDR 10.82.193.138 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage + +#define CONFIG_SERVERIP 10.82.193.104 +#define CONFIG_GATEWAYIP 10.82.193.254 +#define CONFIG_NETMASK 255.255.252.0 + +#define CONFIG_LOADADDR 1000000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ +#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0" \ + "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ + "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ + "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ + "pex=run pexstat; run pex1; run pexd\0" \ + "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ + "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ + "maxcpus=2" + + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/ft_build.h b/include/ft_build.h index 47ca575d9f..5c5e06309b 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -58,7 +58,9 @@ void ft_begin(struct ft_cxt *cxt, void *blob, int max_size); void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size); void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end); - +#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup(void *blob, bd_t *bd); +#endif void ft_dump_blob(const void *bphp); void ft_merge_blob(struct ft_cxt *cxt, void *blob); void *ft_get_prop(void *bphp, const char *propname, int *szp); diff --git a/include/mpc86xx.h b/include/mpc86xx.h new file mode 100644 index 0000000000..61b527979c --- /dev/null +++ b/include/mpc86xx.h @@ -0,0 +1,119 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeffrey Brown (jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + */ + +#ifndef __MPC86xx_H__ +#define __MPC86xx_H__ + +#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ + +/*---------------------------------------------------------------- + * l2cr values. Look in config_.h for the actual setup + */ +#define l2cr 1017 + +#define L2CR_L2E 0x80000000 /* bit 0 - enable */ +#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ +#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ +#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ +#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */ +#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */ +#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ +#define L2CR_L2IP 0x00000001 /* global invalidate in progress */ + +/*---------------------------------------------------------------- + * BAT settings. Look in config_.h for the actual setup + */ + +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc +#define BATU_BL_512M 0x00003ffc +#define BATU_BL_1G 0x00007ffc +#define BATU_BL_2G 0x0000fffc +#define BATU_BL_4G 0x0001fffc + +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 +#define BATU_INVALID 0x00000000 + +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 +#define BATL_NO_ACCESS 0x00000000 + +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 + +#define BATL_PP_NO_ACCESS BATL_PP_00 +#define BATL_PP_RO BATL_PP_01 +#define BATL_PP_RW BATL_PP_10 + +#define HID0_XBSEN 0x00000100 +#define HID0_HIGH_BAT_EN 0x00800000 +#define HID0_XAEN 0x00020000 + +#ifndef __ASSEMBLY__ + +typedef struct +{ + unsigned long freqProcessor; + unsigned long freqSystemBus; +} MPC86xx_SYS_INFO; + +#define l1icache_enable icache_enable + +void l2cache_enable(void); +void l1dcache_enable(void); + +static __inline__ unsigned long get_hid0 (void) +{ + unsigned long hid0; + asm volatile("mfspr %0, 1008" : "=r" (hid0) :); + return hid0; +} + +static __inline__ unsigned long get_hid1 (void) +{ + unsigned long hid1; + asm volatile("mfspr %0, 1009" : "=r" (hid1) :); + return hid1; +} + +static __inline__ void set_hid0 (unsigned long hid0) +{ + asm volatile("mtspr 1008, %0" : : "r" (hid0)); +} + +static __inline__ void set_hid1 (unsigned long hid1) +{ + asm volatile("mtspr 1009, %0" : : "r" (hid1)); +} + + +static __inline__ unsigned long get_l2cr (void) +{ + unsigned long l2cr_val; + asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :); + return l2cr_val; +} + +#endif /* _ASMLANGUAGE */ +#endif /* __MPC86xx_H__ */ + + diff --git a/include/pci.h b/include/pci.h index 0fc00e4276..705d1fcd8a 100644 --- a/include/pci.h +++ b/include/pci.h @@ -270,6 +270,12 @@ #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ #define PCI_AGP_SIZEOF 12 +/* PCI-X registers */ +#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */+#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ +#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ +#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ + /* Slot Identification */ #define PCI_SID_ESR 2 /* Expansion Slot Register */ -- cgit v1.2.1 From 5c9efb36a6b5431423f52888a0e3b4b515fe7eca Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 27 Apr 2006 10:15:16 -0500 Subject: Cleanup whitespaces and style issues. Removed //-style comments. Use 80-column lines. Remove trailing whitespace. Remove dead code and debug cruft. --- include/configs/MPC8641HPCN.h | 203 +++++++++++++++++------------------------- include/mpc86xx.h | 6 +- 2 files changed, 87 insertions(+), 122 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 8d2e08851e..76efd7c604 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -1,5 +1,6 @@ -/* - * Copyright 2004 Freescale Semiconductor. +/* + * Copyright 2006 Freescale Semiconductor. + * * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -22,8 +23,7 @@ */ /* - * mpc8641hpc3 board configuration file - * + * MPC8641HPCN board configuration file * * Make sure you change the MAC address and other network params first, * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. @@ -38,48 +38,38 @@ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ -#undef DEBUG +#undef DEBUG -//#define RUN_DIAG 1 #ifdef RUN_DIAG #define CFG_DIAG_ADDR 0xff800000 #endif + #define CFG_RESET_ADDRESS 0xfff00100 -//#define CONFIG_PCI +#undef CONFIG_PCI + #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -/*#define CONFIG_DDR_ECC */ /* only for ECC DDR module */ -/*#define CONFIG_DDR_DLL */ /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - +#undef CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_ALTIVEC 1 -#define CONFIG_ALTIVEC 1 -/*----------------------------------------------------------------------- +/* * L2CR setup -- make sure this is right for your board! */ - -#define CFG_L2 +#define CFG_L2 #define L2_INIT 0 #define L2_ENABLE (L2CR_L2E) #ifndef CONFIG_SYS_CLK_FREQ -//#define CONFIG_SYS_CLK_FREQ 33000000 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) #endif -/* - * These can be toggled for performance analysis, otherwise use default. - */ -/* JB - XXX - Are these available on 86xx? */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #undef CFG_DRAM_TEST /* memory test, takes time */ @@ -130,10 +120,10 @@ #define CFG_DDR_INTERVAL 0x06090100 #define CFG_DDR_DATA_INIT 0xdeadbeef #define CFG_DDR_CLK_CTRL 0x03800000 - #define CFG_DDR_OCD_CTRL 0x00000000 - #define CFG_DDR_OCD_STATUS 0x00000000 + #define CFG_DDR_OCD_CTRL 0x00000000 + #define CFG_DDR_OCD_STATUS 0x00000000 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ - #define CFG_DDR_CONTROL2 0x04400000 + #define CFG_DDR_CONTROL2 0x04400000 //Not used in fixed_sdram function @@ -143,20 +133,12 @@ #define CFG_DDR_CS3_BNDS 0x00000FFF //Not done #define CFG_DDR_CS4_BNDS 0x00000FFF //Not done #define CFG_DDR_CS5_BNDS 0x00000FFF //Not done - - - #endif #endif /* - * SDRAM on the Local Bus - */ -//#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -//#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 + * In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. * However, when u-boot comes up, the flash_init needs hard start addresses @@ -165,15 +147,12 @@ * knows where the flash is and the user can download u-boot code from promjet to * fef00000 <- more intuitive than fe700000. Note that, on switching the boot * location, fef00000 becomes fff00000. -*/ + */ #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ -#define CFG_FLASH_BASE2 0xff800000 +#define CFG_FLASH_BASE2 0xff800000 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} - -/*Sri: This looks like a good place to init all the Local Bus chip selects*/ - #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ @@ -186,25 +165,24 @@ #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ -#define PIXIS_BASE 0xf8100000 /* PIXIS registers*/ -#define PIXIS_ID 0x0 /* MPC8641HPCN Board ID at offset 0*/ -#define PIXIS_VER 0x1 /* MPC8641HPCN board version version at offset 1*/ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2*/ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register*/ -#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define PIXIS_BASE 0xf8100000 /* PIXIS registers */ +#define PIXIS_ID 0x0 /* Board ID at offset 0 */ +#define PIXIS_VER 0x1 /* Board version at offset 1 */ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ +#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -//#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ #undef CFG_FLASH_CHECKSUM @@ -212,11 +190,9 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -/*#define CFG_HPCN_FLASH_CFI_DRIVER */ #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO - #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT #else @@ -230,7 +206,7 @@ #undef CONFIG_CLOCKS_IN_MHZ #define CONFIG_L1_INIT_RAM -#undef CFG_INIT_RAM_LOCK +#undef CFG_INIT_RAM_LOCK #ifndef CFG_INIT_RAM_LOCK #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ #else @@ -265,20 +241,22 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 +/* + * Pass open firmware flat tree to kernel + */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 /* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 +#define OF_FLAT_TREE_MAX_SIZE 8192 -#define OF_CPU "PowerPC,8641@0" -#define OF_SOC "soc8641@f8000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" +#define OF_CPU "PowerPC,8641@0" +#define OF_SOC "soc8641@f8000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" -#define CFG_64BIT_VSPRINTF 1 -#define CFG_64BIT_STRTOUL 1 +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ @@ -297,13 +275,10 @@ * Addresses are mapped 1-1. */ #define CFG_PCI1_MEM_BASE 0x80000000 -//#define CFG_PCI1_MEM_BASE 0xd0000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0xe2000000 -//#define CFG_PCI1_IO_BASE 0xe0000000 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -//#define CFG_PCI1_IO_BUS 0x00000000 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ /* For RTL8139 */ @@ -316,29 +291,18 @@ #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ -// #define CFG_PCI1_MEM_BASE 0x80000000 -// #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -// #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -// #define CFG_PCI1_IO_BASE 0xe2000000 -// #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -// #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - - #if defined(CONFIG_PCI) - #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -//#define CFG_SCSI_SCAN_BUS_REVERSE - +#undef CFG_SCSI_SCAN_BUS_REVERSE #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_RTL8139 - #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -349,7 +313,6 @@ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -//#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #endif /* CONFIG_PCI */ @@ -371,7 +334,6 @@ #define CONFIG_MPC86XX_TSEC4 1 #define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" - #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2 @@ -389,12 +351,10 @@ /* BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR */ -//#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE) -#define CFG_DBAT0U (0x0 | BATU_BL_512M | BATU_VS | BATU_VP) -//#define CFG_IBAT0L CFG_DBAT0L -//#define CFG_IBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0L (0x0| BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) +#define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE ) +#define CFG_DBAT0U ( BATU_BL_512M | BATU_VS | BATU_VP ) +#define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) #define CFG_IBAT0U CFG_DBAT0U /* BAT1 1G Cache-inhibited, guarded @@ -402,7 +362,8 @@ * 0xa000_0000 512M PCI-Express 2 Memory ** SS - Changed it for operating from 0xd0000000 */ -#define CFG_DBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT1U CFG_DBAT1U @@ -410,7 +371,8 @@ /* BAT2 512M Cache-inhibited, guarded * 0xc000_0000 512M RapidIO Memory */ -#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT2U CFG_DBAT2U @@ -418,7 +380,8 @@ /* BAT3 4M Cache-inhibited, guarded * 0xf800_0000 4M CCSR */ -#define CFG_DBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT3U CFG_DBAT3U @@ -428,7 +391,8 @@ * 0xe300_0000 16M PCI-Express 2 I/0 ** SS - Note that this is at 0xe0000000 */ -#define CFG_DBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT4U CFG_DBAT4U @@ -444,12 +408,12 @@ /* BAT6 32M Cache-inhibited, guarded * 0xfe00_0000 32M FLASH */ -#define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) #define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CFG_IBAT6U CFG_DBAT6U - #define CFG_DBAT7L 0x00000000 #define CFG_DBAT7U 0x00000000 #define CFG_IBAT7L 0x00000000 @@ -461,17 +425,17 @@ /* * Environment */ - #ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 - #else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 - #endif +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -572,24 +536,25 @@ #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif -#define CONFIG_HAS_ETH1 1 -#define CONFIG_HAS_ETH2 1 -#define CONFIG_HAS_ETH3 1 +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 +#define CONFIG_HAS_ETH3 1 -#define CONFIG_IPADDR 10.82.193.138 +#define CONFIG_IPADDR 10.82.193.138 #define CONFIG_HOSTNAME unknown #define CONFIG_ROOTPATH /opt/nfsroot #define CONFIG_BOOTFILE uImage -#define CONFIG_SERVERIP 10.82.193.104 -#define CONFIG_GATEWAYIP 10.82.193.254 -#define CONFIG_NETMASK 255.255.252.0 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 10.82.193.104 +#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 1000000 /* default location for tftp and bootm */ +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ +//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" #define CONFIG_BAUDRATE 115200 @@ -599,7 +564,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=400000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \ - "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0" \ + "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\ "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 61b527979c..4edeae1647 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2006 Freescale Semiconductor. * Jeffrey Brown (jeffrey@freescale.com) * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) */ @@ -9,7 +9,7 @@ #define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ -/*---------------------------------------------------------------- +/* * l2cr values. Look in config_.h for the actual setup */ #define l2cr 1017 @@ -23,7 +23,7 @@ #define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ #define L2CR_L2IP 0x00000001 /* global invalidate in progress */ -/*---------------------------------------------------------------- +/* * BAT settings. Look in config_.h for the actual setup */ -- cgit v1.2.1 From 18b6c8cd8af6cc7f35180cedc4adb3236cc1a1b8 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 9 May 2006 08:23:49 -0500 Subject: Get MPC8641HPCN flash images working. Enable the CFI driver. Remove bogus LAWBAR7 cruft. Use correct TEXT_BASE, Fixup load script. Enable SPD EEPROM during DDR setup. Use generic RFC 1918 IP addresses by default. --- include/configs/MPC8641HPCN.h | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 76efd7c604..d4a28edf9b 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -51,6 +51,7 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #undef CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ @@ -102,11 +103,9 @@ #else /* - * Manually set up DDR parameters + * Manually set up DDR1 parameters */ -/* DDR I */ -#if 1 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ #define CFG_DDR_CS0_BNDS 0x0000000F @@ -125,15 +124,14 @@ #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ #define CFG_DDR_CONTROL2 0x04400000 - //Not used in fixed_sdram function + /* Not used in fixed_sdram function */ #define CFG_DDR_MODE 0x00000022 #define CFG_DDR_CS1_BNDS 0x00000000 - #define CFG_DDR_CS2_BNDS 0x00000FFF //Not done - #define CFG_DDR_CS3_BNDS 0x00000FFF //Not done - #define CFG_DDR_CS4_BNDS 0x00000FFF //Not done - #define CFG_DDR_CS5_BNDS 0x00000FFF //Not done -#endif + #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ + #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ + #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ + #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ #endif @@ -190,6 +188,7 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO @@ -199,14 +198,14 @@ #undef CFG_RAMBOOT #endif -#if !defined(CFG_RAMBOOT) -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#if !defined(CONFIG_SPD_EEPROM) && !defined(CFG_RAMBOOT) +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #endif #undef CONFIG_CLOCKS_IN_MHZ #define CONFIG_L1_INIT_RAM -#undef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_LOCK 1 #ifndef CFG_INIT_RAM_LOCK #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ #else @@ -540,22 +539,21 @@ #define CONFIG_HAS_ETH2 1 #define CONFIG_HAS_ETH3 1 -#define CONFIG_IPADDR 10.82.193.138 +#define CONFIG_IPADDR 192.168.1.100 #define CONFIG_HOSTNAME unknown #define CONFIG_ROOTPATH /opt/nfsroot #define CONFIG_BOOTFILE uImage #define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 10.82.193.104 +#define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.255.0 /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 -- cgit v1.2.1 From 586d1d5abd3e525f1e1d9b81e5a61a4da6b2fa3c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 19 May 2006 13:22:44 -0500 Subject: Update 86xx address map and LAWBARs. --- include/asm-ppc/immap_86xx.h | 4 ++-- include/configs/MPC8641HPCN.h | 52 ++++++++++++++++++++++++++----------------- 2 files changed, 34 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 6bbe072b2d..9e81b47071 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -52,7 +52,7 @@ typedef struct ccsr_local_mcm { uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ char res19[4]; uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ - char res20[16]; + char res20[20]; uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ char res21[4]; uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ @@ -60,7 +60,7 @@ typedef struct ccsr_local_mcm { uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ char res23[4]; uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ - char res24[720]; + char res24[716]; uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */ char res25[4]; uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index d4a28edf9b..aaf99c150f 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -136,15 +136,16 @@ /* - * In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 - * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff + * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. + * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. * However, when u-boot comes up, the flash_init needs hard start addresses - * to build its info table. For user convenience, we have the flash addresses - * as fe800000 and ff800000. That way, when we do flash operations, u-boot - * knows where the flash is and the user can download u-boot code from promjet to - * fef00000 <- more intuitive than fe700000. Note that, on switching the boot - * location, fef00000 becomes fff00000. + * to build its info table. For user convenience, the flash addresses is + * fe800000 and ff800000. That way, u-boot knows where the flash is + * and the user can download u-boot code from promjet to fef00000, a + * more intuitive location than fe700000. + * + * Note that, on switching the boot location, fef00000 becomes fff00000. */ #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ #define CFG_FLASH_BASE2 0xff800000 @@ -257,14 +258,18 @@ #define CFG_64BIT_VSPRINTF 1 #define CFG_64BIT_STRTOUL 1 -/* I2C */ +/* + * I2C + */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -/* RapidIO MMU */ +/* + * RapidIO MMU + */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ @@ -347,19 +352,21 @@ #endif /* CONFIG_TSEC_ENET */ -/* BAT0 2G Cacheable, non-guarded +/* + * BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR */ #define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE ) -#define CFG_DBAT0U ( BATU_BL_512M | BATU_VS | BATU_VP ) +#define CFG_DBAT0U ( BATU_BL_2G | BATU_VS | BATU_VP ) #define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) #define CFG_IBAT0U CFG_DBAT0U -/* BAT1 1G Cache-inhibited, guarded +/* + * BAT1 1G Cache-inhibited, guarded * 0x8000_0000 512M PCI-Express 1 Memory * 0xa000_0000 512M PCI-Express 2 Memory - ** SS - Changed it for operating from 0xd0000000 + * Changed it for operating from 0xd0000000 */ #define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) @@ -367,7 +374,8 @@ #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT1U CFG_DBAT1U -/* BAT2 512M Cache-inhibited, guarded +/* + * BAT2 512M Cache-inhibited, guarded * 0xc000_0000 512M RapidIO Memory */ #define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ @@ -376,7 +384,8 @@ #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT2U CFG_DBAT2U -/* BAT3 4M Cache-inhibited, guarded +/* + * BAT3 4M Cache-inhibited, guarded * 0xf800_0000 4M CCSR */ #define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ @@ -385,10 +394,11 @@ #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT3U CFG_DBAT3U -/* BAT4 32M Cache-inhibited, guarded +/* + * BAT4 32M Cache-inhibited, guarded * 0xe200_0000 16M PCI-Express 1 I/O * 0xe300_0000 16M PCI-Express 2 I/0 - ** SS - Note that this is at 0xe0000000 + * Note that this is at 0xe0000000 */ #define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) @@ -396,7 +406,8 @@ #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT4U CFG_DBAT4U -/* BAT5 128K Cacheable, non-guarded +/* + * BAT5 128K Cacheable, non-guarded * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) */ #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) @@ -404,7 +415,8 @@ #define CFG_IBAT5L CFG_DBAT5L #define CFG_IBAT5U CFG_DBAT5U -/* BAT6 32M Cache-inhibited, guarded +/* + * BAT6 32M Cache-inhibited, guarded * 0xfe00_0000 32M FLASH */ #define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \ @@ -427,7 +439,7 @@ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH 1 /* Flash is not usable now */ -- cgit v1.2.1 From 9a655876e5995be80f49054e2509500e871e4d3a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 19 May 2006 13:26:34 -0500 Subject: Enable dual DDR controllers and interleaving. --- include/configs/MPC8641HPCN.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index aaf99c150f..2a197be294 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -57,6 +57,13 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_NUM_DDR_CONTROLLERS 2 +/* #define CONFIG_DDR_INTERLEAVE 1 */ +#define CACHE_LINE_INTERLEAVING 0x20000000 +#define PAGE_INTERLEAVING 0x21000000 +#define BANK_INTERLEAVING 0x22000000 +#define SUPER_BANK_INTERLEAVING 0x23000000 + #define CONFIG_ALTIVEC 1 @@ -99,7 +106,10 @@ /* * Determine DDR configuration from I2C interface. */ - #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ #else /* -- cgit v1.2.1 From fa7db9c377bc2353a17bf1d381d65a6c418728f0 Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong-R64188 Date: Tue, 27 Jun 2006 18:11:54 +0800 Subject: Enable PCIE1 for MPC8641HPCN board Signed-off-by: Jason Jin --- include/asm-ppc/immap_86xx.h | 62 ++++++++++++++++++++++--------------------- include/configs/MPC8641HPCN.h | 20 +++++++++----- 2 files changed, 46 insertions(+), 36 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 9e81b47071..5b1f0f4ea6 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -284,41 +284,41 @@ typedef struct ccsr_pex { char res2[16]; uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */ uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */ - uint pme_msg_dis; /* 0x802C - PEX PME & message disable register */ - char res3[4]; - uint pm_command; /* 0x8030 - PEX PM Command register */ - char res4[3016]; - uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */ - uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */ + uint pme_msg_dis; /* 0x8028 - PEX PME & message disable register */ + uint pm_command; /* 0x802c - PEX PM Command register */ + char res3[3016]; + uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */ + uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */ uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */ uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */ - char res5[8]; + char res4[8]; uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */ - char res6[12]; + char res5[12]; uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */ uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */ uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */ - char res7[4]; + char res6[4]; uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */ - char res8[12]; + char res7[12]; uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */ uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */ uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */ - char res9[4]; + char res8[4]; uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */ - char res10[12]; + char res9[12]; uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */ uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */ uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */ - char res11[4]; + char res10[4]; uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */ - char res12[12]; + char res11[12]; uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */ uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */ uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */ - char res13[4]; + char res12[4]; uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */ - char res14[268]; + char res13[12]; + char res14[256]; uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */ char res15[4]; uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */ @@ -332,23 +332,25 @@ typedef struct ccsr_pex { uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */ char res18[12]; uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */ - char res19[4]; + char res19[4]; uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */ - char res20[4]; + uint piwbear1; uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */ - char res21[12]; + char res20[12]; uint pedr; /* 0x8e00 - PEX Error Detect Register */ - uint pecdr; /* 0x8e04 - PEX Error Capture Disable Register */ - uint peer; /* 0x8e08 - PEX Error Enable Register */ - uint perr_cap0; /* 0x8e0c - PEX Error Capture Register 0 */ - uint perr_cap1; /* 0x8e10 - PEX Error Capture Register 1 */ - uint perr_cap2; /* 0x8e14 - PEX Error Capture Register 2 */ - uint perr_cap3; /* 0x8e18 - PEX Error Capture Register 3 */ - char res22[100]; - uint perr_stat; /* 0x8e80 - PEX Error Status Register */ - char res23[124]; - uint pdebug; /* 0x8f00 - PEX Debug Register */ - char res24[248]; //Sri: changed this because of adding 4 bytes before 0x?8020. + char res21[4]; + uint peer; /* 0x8e08 - PEX Error Interrupt Enable Register */ + char res22[4]; + uint pecdr; /* 0x8e10 - PEX Error Disable Register */ + char res23[12]; + uint peer_stat; /* 0x8e20 - PEX Error Capture Status Register */ + char res24[4]; + uint perr_cap0; /* 0x8e28 - PEX Error Capture Register 0 */ + uint perr_cap1; /* 0x8e2c - PEX Error Capture Register 1 */ + uint perr_cap2; /* 0x8e30 - PEX Error Capture Register 2 */ + uint perr_cap3; /* 0x8e34 - PEX Error Capture Register 3 */ + char res25[452]; + char res26[4]; } ccsr_pex_t; /* Hyper Transport Register Block (0xA000-0xB000) */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 2a197be294..4453171d45 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -46,7 +46,8 @@ #define CFG_RESET_ADDRESS 0xfff00100 -#undef CONFIG_PCI +/*#undef CONFIG_PCI*/ +#define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -209,8 +210,10 @@ #undef CFG_RAMBOOT #endif -#if !defined(CONFIG_SPD_EEPROM) && !defined(CFG_RAMBOOT) -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#if defined(CFG_RAMBOOT) +#undef CFG_FLASH_CFI_DRIVER +#undef CONFIG_SPD_EEPROM +#define CFG_SDRAM_SIZE 256 #endif #undef CONFIG_CLOCKS_IN_MHZ @@ -295,6 +298,11 @@ #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + /* For RTL8139 */ #define _IO_BASE 0x00000000 @@ -429,10 +437,10 @@ * BAT6 32M Cache-inhibited, guarded * 0xfe00_0000 32M FLASH */ -#define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \ +#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) #define CFG_IBAT6U CFG_DBAT6U #define CFG_DBAT7L 0x00000000 -- cgit v1.2.1 From bc09cf3c2bfb8d54c659cbb332f79d0950982fd0 Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong-R64188 Date: Tue, 27 Jun 2006 18:12:10 +0800 Subject: Fix RTL8139 in big endian signed-off-by: Jason Jin signed-off-by: Wei Zhang --- include/configs/MPC8641HPCN.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 4453171d45..b0897695a7 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -304,6 +304,7 @@ #define CFG_PCI_MEMORY_SIZE 0x80000000 /* For RTL8139 */ +#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) #define _IO_BASE 0x00000000 #define CFG_PCI2_MEM_BASE 0xa0000000 -- cgit v1.2.1 From da012ab661fd4ab169dd7b9b32201a4df62cf34a Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong Date: Wed, 28 Jun 2006 08:43:56 -0500 Subject: Change Id to symbolic name for RTL8139 Signed-off-by: Jason Jin --- include/pci_ids.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/pci_ids.h b/include/pci_ids.h index 8cc3ec0a23..3b10452416 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1045,6 +1045,9 @@ #define PCI_DEVICE_ID_REALTEK_8139 0x8139 #define PCI_DEVICE_ID_REALTEK_8169 0x8169 +#define PCI_VENDOR_ID_DLINK 0x1186 +#define PCI_DEVICE_ID_DLINK_8139 0x1300 + #define PCI_VENDOR_ID_XILINX 0x10ee #define PCI_DEVICE_ID_TURBOPAM 0x4020 -- cgit v1.2.1 From 1b380ec225665e73959677f3893dc658c5925e05 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:42:24 -0500 Subject: * Patch to modify ft_build.c to update flat device trees in place Patch by Matthew McClintock 26-June-2006 --- include/ft_build.h | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/ft_build.h b/include/ft_build.h index 47ca575d9f..f5156879de 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -36,19 +36,18 @@ struct boot_param_header { struct ft_cxt { struct boot_param_header *bph; - int max_size; /* maximum size of tree */ - int overflow; /* set when this happens */ - u8 *p, *pstr, *pres; /* running pointers */ - u8 *p_begin, *pstr_begin, *pres_begin; /* starting pointers */ - u8 *p_anchor; /* start of constructed area */ - int struct_size, strings_size, res_size; + u8 *p_rsvmap; + u8 *p_start; /* pointer to beginning of dt_struct */ + u8 *p_end; /* pointer to end of dt_strings */ + u8 *p; /* pointer to end of dt_struct and beginning of dt_strings */ }; void ft_begin_node(struct ft_cxt *cxt, const char *name); +void ft_init_cxt(struct ft_cxt *cxt, void *blob); void ft_end_node(struct ft_cxt *cxt); -void ft_begin_tree(struct ft_cxt *cxt); -int ft_end_tree(struct ft_cxt *cxt); +void ft_end_tree(struct ft_cxt *cxt); +void ft_finalize_tree(struct ft_cxt *cxt); void ft_nop(struct ft_cxt *cxt); void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz); @@ -57,12 +56,14 @@ void ft_prop_int(struct ft_cxt *cxt, const char *name, int val); void ft_begin(struct ft_cxt *cxt, void *blob, int max_size); void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size); -void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end); +void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end); void ft_dump_blob(const void *bphp); void ft_merge_blob(struct ft_cxt *cxt, void *blob); void *ft_get_prop(void *bphp, const char *propname, int *szp); +#ifdef CONFIG_OF_BOARD_SETUP void ft_board_setup(void *blob, bd_t *bd); +#endif #endif -- cgit v1.2.1 From 40d5fa35d02df22580593bf0039ab173367e8ef0 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:43:36 -0500 Subject: * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards Patch by Jon Loeliger 17-Jan-2006 Signed-off-by: Jon Loeliger --- include/configs/MPC8540ADS.h | 15 +++++++++++++++ include/configs/MPC8541CDS.h | 12 ++++++++++++ include/configs/MPC8548CDS.h | 12 ++++++++++++ include/configs/MPC8555CDS.h | 12 ++++++++++++ include/configs/MPC8560ADS.h | 12 ++++++++++++ 5 files changed, 63 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 131c832242..d31a18b794 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -293,6 +293,21 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8540@0" +#define OF_SOC "soc8540@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index c96b98b54d..86bcfe324c 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -308,6 +308,18 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8541@0" +#define OF_SOC "soc8541@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 4ca8bc35db..b1f8a192df 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -314,6 +314,18 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8548@0" +#define OF_SOC "soc8548@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index a44e3ec845..b725dac52b 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -308,6 +308,18 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8555@0" +#define OF_SOC "soc8555@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 2d5031b77d..1c684f2fd1 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -290,6 +290,18 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8560@0" +#define OF_SOC "soc8560@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -- cgit v1.2.1 From b636aaeb6fd516a442fb611bbeeddf3077a687fb Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:44:49 -0500 Subject: * Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming --- include/pci.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/pci.h b/include/pci.h index 0fc00e4276..e0e8783a7a 100644 --- a/include/pci.h +++ b/include/pci.h @@ -270,6 +270,15 @@ #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ #define PCI_AGP_SIZEOF 12 +/* PCI-X registers */ + +#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ +#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ +#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ +#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ + + /* Slot Identification */ #define PCI_SID_ESR 2 /* Expansion Slot Register */ -- cgit v1.2.1 From 087454609e47295443af793a282cddcd91a5f49c Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:45:17 -0500 Subject: * Added support for initializing second PCI bus on 85xx Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- include/asm-ppc/immap_85xx.h | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 2f10e9591d..7a4345a740 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -246,7 +246,6 @@ typedef struct ccsr_lbc { /* * PCI Registers(0x8000-0x9000) - * Omitting Reserved(0x9000-0x2_0000) */ typedef struct ccsr_pcix { uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */ @@ -309,9 +308,27 @@ typedef struct ccsr_pcix { uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */ uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */ uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */ - char res11[94688]; + uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */ + char res11[476]; } ccsr_pcix_t; +#define PCIX_COMMAND 0x62 +#define POWAR_EN 0x80000000 +#define POWAR_IO_READ 0x00080000 +#define POWAR_MEM_READ 0x00040000 +#define POWAR_IO_WRITE 0x00008000 +#define POWAR_MEM_WRITE 0x00004000 +#define POWAR_MEM_512M 0x0000001c +#define POWAR_IO_1M 0x00000013 + +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_LOCAL 0x00f00000 +#define PIWAR_READ_SNOOP 0x00050000 +#define PIWAR_WRITE_SNOOP 0x00005000 +#define PIWAR_MEM_2G 0x0000001e + + /* * L2 Cache Registers(0x2_0000-0x2_1000) */ @@ -1572,6 +1589,8 @@ typedef struct ccsr_gur { char res15[61651]; } ccsr_gur_t; +#define PORDEVSR_PCI (0x00800000) /* PCI Mode */ + typedef struct immap { ccsr_local_ecm_t im_local_ecm; ccsr_ddr_t im_ddr; @@ -1579,6 +1598,8 @@ typedef struct immap { ccsr_duart_t im_duart; ccsr_lbc_t im_lbc; ccsr_pcix_t im_pcix; + ccsr_pcix_t im_pcix2; + char reserved[90112]; ccsr_l2cache_t im_l2cache; ccsr_dma_t im_dma; ccsr_tsec_t im_tsec1; -- cgit v1.2.1 From 52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:45:41 -0500 Subject: * Fixed PCI memory definitions Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- include/configs/MPC8540ADS.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index d31a18b794..81ee945d49 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -71,7 +71,7 @@ */ #ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33000000 +#define CONFIG_SYS_CLK_FREQ 66000000 #endif @@ -327,9 +327,10 @@ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#define CFG_PCI1_IO_BASE 0x0 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) -- cgit v1.2.1 From cbfc7ce756b88eb26e5537bc7b625c445c6dcfac Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:46:13 -0500 Subject: * Added VIA configuration table * Added support for PCI2 on CDS Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- include/configs/MPC8541CDS.h | 21 ++++++++------------- include/configs/MPC8548CDS.h | 23 +++++++++-------------- include/configs/MPC8555CDS.h | 23 +++++++++-------------- 3 files changed, 26 insertions(+), 41 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 86bcfe324c..f73caf0319 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8541@0" #define OF_SOC "soc8541@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -335,32 +335,27 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) +#define CONFIG_MPC85XX_PCI2 #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b1f8a192df..37b518cca5 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -324,7 +324,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8548@0" #define OF_SOC "soc8548@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -341,32 +341,27 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_85XX_PCI2 #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ @@ -386,7 +381,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" #define CONFIG_MPC85XX_TSEC3 1 #define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#define CONFIG_MPC85XX_TSEC4 1 +#undef CONFIG_MPC85XX_TSEC4 #define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index b725dac52b..b94e38ae34 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8555@0" #define OF_SOC "soc8555@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -335,33 +335,28 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_MPC85XX_PCI2 #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #endif /* CONFIG_PCI */ -- cgit v1.2.1 From 38433ccc5850ee70549af0b2bc5b920355ef5388 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:47:03 -0500 Subject: * Switched default PCI speed for 8540 ADS back to 33MHz * Added comments and a printf to warn that PCI-X won't work at 33MHz Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- include/configs/MPC8540ADS.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 81ee945d49..8e4d2c95a4 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -68,10 +68,14 @@ * The board, however, can run at 66MHz. In any event, this value * must match the settings of some switches. Details can be found * in the README.mpc85xxads. + * + * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to + * 33MHz to accommodate, based on a PCI pin. + * Note that PCI-X won't work at 33MHz. */ #ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_SYS_CLK_FREQ 33000000 #endif -- cgit v1.2.1 From fcb28e763415e0e4e66b0f45842d1557ae198e5e Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong Date: Thu, 13 Jul 2006 10:35:10 -0500 Subject: Fixed initrd issue by define big RAM Signed-off-by:Jason Jin --- include/configs/MPC8641HPCN.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index b0897695a7..aca2ecc234 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -100,6 +100,7 @@ */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM #define MPC86xx_DDR_SDRAM_CLK_CNTL -- cgit v1.2.1 From bea3f28d285942bf3f7ab339ce85178ded544225 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 12 Jul 2006 10:48:05 -0400 Subject: Add support for reading and writing mac addresses to or from ID EEPROM. Added code for reading and writing Mac addresses to/from ID EEPROM(0x57). With attached patch, we can use command "mac/mac read/mac save/" to read and write EEPROM under u-boot prompt. U-boot will calculate the checksum of EEPROM while bootup, if it is right, then u-boot will check whether the mac address of eTSEC0/1/2/3 is availalbe (non-zero). If there is mac address availabe in EEPROM, u-boot will use it, otherewise, u-boot will use the mac address defined in MPC8641HPCN.h. This matches the requirement to set unique mac address for each TSEC port. Signed-off-by: Haiying Wang Signed-off-by: York Sun --- include/common.h | 3 +++ include/configs/MPC8641HPCN.h | 2 ++ 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/include/common.h b/include/common.h index 83ccf7c987..7e54da93bf 100644 --- a/include/common.h +++ b/include/common.h @@ -197,6 +197,9 @@ int checkdram (void); char * strmhz(char *buf, long hz); int last_stage_init(void); extern ulong monitor_flash_len; +#ifdef CFG_ID_EEPROM +int mac_read_from_eeprom(void); +#endif /* common/flash.c */ void flash_perror (int); diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index aca2ecc234..7e91e644b1 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -146,6 +146,8 @@ #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ #endif +#define CFG_ID_EEPROM 1 +#define ID_EEPROM_ADDR 0x57 /* * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. -- cgit v1.2.1 From 515ab8a62e8574e2babc6e8dcc43544ad221c5b2 Mon Sep 17 00:00:00 2001 From: John Traill Date: Fri, 28 Jul 2006 08:16:06 +0100 Subject: Fix 8641HPCN timebase --- include/configs/MPC8641HPCN.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 7e91e644b1..15e987139a 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -268,7 +268,7 @@ #define OF_CPU "PowerPC,8641@0" #define OF_SOC "soc8641@f8000000" -#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" #define CFG_64BIT_VSPRINTF 1 -- cgit v1.2.1 From 5498d90312aad9f6bdbf047986027c35b03cd163 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:42:24 -0500 Subject: * Patch to modify ft_build.c to update flat device trees in place Patch by Matthew McClintock 26-June-2006 --- include/ft_build.h | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/ft_build.h b/include/ft_build.h index 47ca575d9f..f5156879de 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -36,19 +36,18 @@ struct boot_param_header { struct ft_cxt { struct boot_param_header *bph; - int max_size; /* maximum size of tree */ - int overflow; /* set when this happens */ - u8 *p, *pstr, *pres; /* running pointers */ - u8 *p_begin, *pstr_begin, *pres_begin; /* starting pointers */ - u8 *p_anchor; /* start of constructed area */ - int struct_size, strings_size, res_size; + u8 *p_rsvmap; + u8 *p_start; /* pointer to beginning of dt_struct */ + u8 *p_end; /* pointer to end of dt_strings */ + u8 *p; /* pointer to end of dt_struct and beginning of dt_strings */ }; void ft_begin_node(struct ft_cxt *cxt, const char *name); +void ft_init_cxt(struct ft_cxt *cxt, void *blob); void ft_end_node(struct ft_cxt *cxt); -void ft_begin_tree(struct ft_cxt *cxt); -int ft_end_tree(struct ft_cxt *cxt); +void ft_end_tree(struct ft_cxt *cxt); +void ft_finalize_tree(struct ft_cxt *cxt); void ft_nop(struct ft_cxt *cxt); void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz); @@ -57,12 +56,14 @@ void ft_prop_int(struct ft_cxt *cxt, const char *name, int val); void ft_begin(struct ft_cxt *cxt, void *blob, int max_size); void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size); -void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end); +void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end); void ft_dump_blob(const void *bphp); void ft_merge_blob(struct ft_cxt *cxt, void *blob); void *ft_get_prop(void *bphp, const char *propname, int *szp); +#ifdef CONFIG_OF_BOARD_SETUP void ft_board_setup(void *blob, bd_t *bd); +#endif #endif -- cgit v1.2.1 From 0e16387db1d4aacd5bf35cb6d7c1942765c0347b Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:43:36 -0500 Subject: * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards Patch by Jon Loeliger 17-Jan-2006 Signed-off-by: Jon Loeliger --- include/configs/MPC8540ADS.h | 15 +++++++++++++++ include/configs/MPC8541CDS.h | 12 ++++++++++++ include/configs/MPC8548CDS.h | 12 ++++++++++++ include/configs/MPC8555CDS.h | 12 ++++++++++++ include/configs/MPC8560ADS.h | 12 ++++++++++++ 5 files changed, 63 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 131c832242..d31a18b794 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -293,6 +293,21 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8540@0" +#define OF_SOC "soc8540@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index c96b98b54d..86bcfe324c 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -308,6 +308,18 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8541@0" +#define OF_SOC "soc8541@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 4ca8bc35db..b1f8a192df 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -314,6 +314,18 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8548@0" +#define OF_SOC "soc8548@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index a44e3ec845..b725dac52b 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -308,6 +308,18 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8555@0" +#define OF_SOC "soc8555@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 2d5031b77d..1c684f2fd1 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -290,6 +290,18 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8560@0" +#define OF_SOC "soc8560@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -- cgit v1.2.1 From f0e6f57f71b3c4fdd13028eb03c3f3e91926dda2 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:44:49 -0500 Subject: * Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming --- include/pci.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/pci.h b/include/pci.h index 0fc00e4276..e0e8783a7a 100644 --- a/include/pci.h +++ b/include/pci.h @@ -270,6 +270,15 @@ #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ #define PCI_AGP_SIZEOF 12 +/* PCI-X registers */ + +#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ +#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ +#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ +#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ + + /* Slot Identification */ #define PCI_SID_ESR 2 /* Expansion Slot Register */ -- cgit v1.2.1 From 97074ed9655309b64231bc2cee69fe85399f8055 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:45:17 -0500 Subject: * Added support for initializing second PCI bus on 85xx Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- include/asm-ppc/immap_85xx.h | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 2f10e9591d..7a4345a740 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -246,7 +246,6 @@ typedef struct ccsr_lbc { /* * PCI Registers(0x8000-0x9000) - * Omitting Reserved(0x9000-0x2_0000) */ typedef struct ccsr_pcix { uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */ @@ -309,9 +308,27 @@ typedef struct ccsr_pcix { uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */ uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */ uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */ - char res11[94688]; + uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */ + char res11[476]; } ccsr_pcix_t; +#define PCIX_COMMAND 0x62 +#define POWAR_EN 0x80000000 +#define POWAR_IO_READ 0x00080000 +#define POWAR_MEM_READ 0x00040000 +#define POWAR_IO_WRITE 0x00008000 +#define POWAR_MEM_WRITE 0x00004000 +#define POWAR_MEM_512M 0x0000001c +#define POWAR_IO_1M 0x00000013 + +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_LOCAL 0x00f00000 +#define PIWAR_READ_SNOOP 0x00050000 +#define PIWAR_WRITE_SNOOP 0x00005000 +#define PIWAR_MEM_2G 0x0000001e + + /* * L2 Cache Registers(0x2_0000-0x2_1000) */ @@ -1572,6 +1589,8 @@ typedef struct ccsr_gur { char res15[61651]; } ccsr_gur_t; +#define PORDEVSR_PCI (0x00800000) /* PCI Mode */ + typedef struct immap { ccsr_local_ecm_t im_local_ecm; ccsr_ddr_t im_ddr; @@ -1579,6 +1598,8 @@ typedef struct immap { ccsr_duart_t im_duart; ccsr_lbc_t im_lbc; ccsr_pcix_t im_pcix; + ccsr_pcix_t im_pcix2; + char reserved[90112]; ccsr_l2cache_t im_l2cache; ccsr_dma_t im_dma; ccsr_tsec_t im_tsec1; -- cgit v1.2.1 From c88f9fe66b64247e5b6a38410ba315ca25596d16 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:45:41 -0500 Subject: * Fixed PCI memory definitions Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- include/configs/MPC8540ADS.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index d31a18b794..81ee945d49 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -71,7 +71,7 @@ */ #ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33000000 +#define CONFIG_SYS_CLK_FREQ 66000000 #endif @@ -327,9 +327,10 @@ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#define CFG_PCI1_IO_BASE 0x0 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) -- cgit v1.2.1 From bf1dfffd8c26f8ecdd630a0ae4c834e751e4e452 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:46:13 -0500 Subject: * Added VIA configuration table * Added support for PCI2 on CDS Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- include/configs/MPC8541CDS.h | 21 ++++++++------------- include/configs/MPC8548CDS.h | 23 +++++++++-------------- include/configs/MPC8555CDS.h | 23 +++++++++-------------- 3 files changed, 26 insertions(+), 41 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 86bcfe324c..f73caf0319 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8541@0" #define OF_SOC "soc8541@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -335,32 +335,27 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) +#define CONFIG_MPC85XX_PCI2 #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b1f8a192df..37b518cca5 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -324,7 +324,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8548@0" #define OF_SOC "soc8548@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -341,32 +341,27 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_85XX_PCI2 #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ @@ -386,7 +381,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" #define CONFIG_MPC85XX_TSEC3 1 #define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#define CONFIG_MPC85XX_TSEC4 1 +#undef CONFIG_MPC85XX_TSEC4 #define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index b725dac52b..b94e38ae34 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8555@0" #define OF_SOC "soc8555@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -335,33 +335,28 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_MPC85XX_PCI2 #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #endif /* CONFIG_PCI */ -- cgit v1.2.1 From 34c3c0e01dbf1f8cc2bd08de92f2b89ba84921eb Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:47:03 -0500 Subject: * Switched default PCI speed for 8540 ADS back to 33MHz * Added comments and a printf to warn that PCI-X won't work at 33MHz Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- include/configs/MPC8540ADS.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 81ee945d49..8e4d2c95a4 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -68,10 +68,14 @@ * The board, however, can run at 66MHz. In any event, this value * must match the settings of some switches. Details can be found * in the README.mpc85xxads. + * + * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to + * 33MHz to accommodate, based on a PCI pin. + * Note that PCI-X won't work at 33MHz. */ #ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_SYS_CLK_FREQ 33000000 #endif -- cgit v1.2.1 From fecf1c7e4de1b2779edc18742b91c22bdc32b68b Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 14 Aug 2006 15:33:38 -0500 Subject: Fix BAT0 to actually be cacheable, non-guarded as documented. Signed-off-by: Jon Loeliger --- include/configs/MPC8641HPCN.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 15e987139a..200a38f3e8 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -378,10 +378,9 @@ * BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR */ -#define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE ) -#define CFG_DBAT0U ( BATU_BL_2G | BATU_VS | BATU_VP ) -#define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) +#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) #define CFG_IBAT0U CFG_DBAT0U /* -- cgit v1.2.1 From 25c751e9adc86e22fe3b5b47cf2806379b575db7 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 16 Aug 2006 10:54:09 -0500 Subject: * Support for FDT in uImage format, error when using FDT from flash Signed-off-by: Matthew McClintock --- include/image.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/image.h b/include/image.h index 139df0b2d1..ea7e9531dc 100644 --- a/include/image.h +++ b/include/image.h @@ -124,6 +124,7 @@ #define IH_TYPE_FIRMWARE 5 /* Firmware Image */ #define IH_TYPE_SCRIPT 6 /* Script file */ #define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ +#define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ /* * Compression Types -- cgit v1.2.1 From 87a449c8ac396420cb24260f717ea9e6faa82047 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Tue, 22 Aug 2006 09:23:55 -0500 Subject: Support for FDT in uImage format, error when using FDT from flash Signed-off-by: Matthew McClintock --- include/image.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/image.h b/include/image.h index 139df0b2d1..ea7e9531dc 100644 --- a/include/image.h +++ b/include/image.h @@ -124,6 +124,7 @@ #define IH_TYPE_FIRMWARE 5 /* Firmware Image */ #define IH_TYPE_SCRIPT 6 /* Script file */ #define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ +#define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ /* * Compression Types -- cgit v1.2.1 From 2c33e8a1c535b3ae91cf0b284480600bf3f57c57 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 22 Aug 2006 17:54:05 -0500 Subject: Cleanup poorly introduced whitespace. --- include/asm-ppc/mmu.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 612b5df487..4f49789f63 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -435,8 +435,8 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define BOOKE_PAGESZ_4GB 11 #if defined(CONFIG_MPC86xx) -#define LAWBAR_BASE_ADDR 0x00FFFFFF -#define LAWAR_TRGT_IF 0x01F00000 +#define LAWBAR_BASE_ADDR 0x00FFFFFF +#define LAWAR_TRGT_IF 0x01F00000 #else #define LAWBAR_BASE_ADDR 0x000FFFFF #define LAWAR_TRGT_IF 0x00F00000 @@ -448,14 +448,14 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 -#define LAWAR_TRGT_IF_HT 0x00200000 +#define LAWAR_TRGT_IF_HT 0x00200000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 #define LAWAR_TRGT_IF_RIO 0x00c00000 #define LAWAR_TRGT_IF_DDR 0x00f00000 -#define LAWAR_TRGT_IF_DDR1 0x00f00000 -#define LAWAR_TRGT_IF_DDR2 0x01600000 +#define LAWAR_TRGT_IF_DDR1 0x00f00000 +#define LAWAR_TRGT_IF_DDR2 0x01600000 #define LAWAR_SIZE_BASE 0xa #define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) @@ -478,9 +478,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) #define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) #define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) -#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) -#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) -#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) -#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) +#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) +#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) +#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) +#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) #endif /* _PPC_MMU_H_ */ -- cgit v1.2.1 From ae6241685cbcf0c79a3636530d2ceab1fb291a94 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 22 Aug 2006 18:07:00 -0500 Subject: Cleanup more poorly introduced whitespace. --- include/asm-ppc/processor.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 1848aaf8cd..0060cd030b 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -264,7 +264,7 @@ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ -#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ +#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ #define SPRN_MBAR 0x137 /* System memory base address */ @@ -445,7 +445,7 @@ #define ESR_ST 0x00800000 /* Store Operation */ #if defined(CONFIG_MPC86xx) -#define SPRN_MSSCRO 0x3f6 +#define SPRN_MSSCRO 0x3f6 #endif @@ -507,12 +507,12 @@ #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ -#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ +#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ #if defined(CONFIG_MPC86xx) -#define MSSCR0 SPRN_MSSCRO +#define MSSCR0 SPRN_MSSCRO #endif #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define PIR SPRN_PIR @@ -548,7 +548,7 @@ #define CSRR0 SPRN_CSRR0 #define CSRR1 SPRN_CSRR1 #define IVPR SPRN_IVPR -#define USPRG0 SPRN_USPRG +#define USPRG0 SPRN_USPRG #define SPRG4R SPRN_SPRG4R #define SPRG5R SPRN_SPRG5R #define SPRG6R SPRN_SPRG6R -- cgit v1.2.1 From b93775c2036b99baa390ea425c4771895bbc63c4 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 22 Aug 2006 18:26:08 -0500 Subject: Cleanup even more poorly introduced whitespace. --- include/mpc86xx.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 4edeae1647..bc8ba3f2da 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -1,6 +1,6 @@ /* * Copyright 2006 Freescale Semiconductor. - * Jeffrey Brown (jeffrey@freescale.com) + * Jeffrey Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) */ @@ -70,10 +70,9 @@ #ifndef __ASSEMBLY__ -typedef struct -{ - unsigned long freqProcessor; - unsigned long freqSystemBus; +typedef struct { + unsigned long freqProcessor; + unsigned long freqSystemBus; } MPC86xx_SYS_INFO; #define l1icache_enable icache_enable @@ -115,5 +114,3 @@ static __inline__ unsigned long get_l2cr (void) #endif /* _ASMLANGUAGE */ #endif /* __MPC86xx_H__ */ - - -- cgit v1.2.1 From d8ea2acf5f137cae99417df4f573d036ee384668 Mon Sep 17 00:00:00 2001 From: Zhang Wei Date: Wed, 23 Aug 2006 17:54:32 +0800 Subject: Add dtb boot-up parameter to default boot commands. Signed-off-by: Zhang Wei --- include/configs/MPC8641HPCN.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 200a38f3e8..1f5e2dfd94 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -595,6 +595,8 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=400000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \ + "dtbaddr=2000000\0" \ + "dtbfile=mpc8641_hpcn.dtb\0" \ "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\ "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ @@ -611,14 +613,16 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr $ramdiskaddr $dtbaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND -- cgit v1.2.1 From 4782ac80b02f0d01afd309e2200dd3c7037f2ba4 Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong Date: Wed, 23 Aug 2006 19:10:44 +0800 Subject: Add AHCI support to u-boot Add AHCI support in u-boot, enable the sata disk controllers which following the AHCI protocol. Signed-off-by:Jason Jin --- include/ahci.h | 190 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 190 insertions(+) create mode 100644 include/ahci.h (limited to 'include') diff --git a/include/ahci.h b/include/ahci.h new file mode 100644 index 0000000000..80701e298c --- /dev/null +++ b/include/ahci.h @@ -0,0 +1,190 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * Author: Jason Jin + * Zhang Wei + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#ifndef _AHCI_H_ +#define _AHCI_H_ + +#define AHCI_PCI_BAR 0x24 +#define AHCI_MAX_SG 56 /* hardware max is 64K */ +#define AHCI_CMD_SLOT_SZ 32 +#define AHCI_RX_FIS_SZ 256 +#define AHCI_CMD_TBL_HDR 0x80 +#define AHCI_CMD_TBL_CDB 0x40 +#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) +#define AHCI_PORT_PRIV_DMA_SZ AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ \ + + AHCI_RX_FIS_SZ +#define AHCI_CMD_ATAPI (1 << 5) +#define AHCI_CMD_WRITE (1 << 6) +#define AHCI_CMD_PREFETCH (1 << 7) +#define AHCI_CMD_RESET (1 << 8) +#define AHCI_CMD_CLR_BUSY (1 << 10) + +#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ + +/* Global controller registers */ +#define HOST_CAP 0x00 /* host capabilities */ +#define HOST_CTL 0x04 /* global host control */ +#define HOST_IRQ_STAT 0x08 /* interrupt status */ +#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ +#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ + +/* HOST_CTL bits */ +#define HOST_RESET (1 << 0) /* reset controller; self-clear */ +#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */ +#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */ + +/* Registers for each SATA port */ +#define PORT_LST_ADDR 0x00 /* command list DMA addr */ +#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */ +#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */ +#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */ +#define PORT_IRQ_STAT 0x10 /* interrupt status */ +#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */ +#define PORT_CMD 0x18 /* port command */ +#define PORT_TFDATA 0x20 /* taskfile data */ +#define PORT_SIG 0x24 /* device TF signature */ +#define PORT_CMD_ISSUE 0x38 /* command issue */ +#define PORT_SCR 0x28 /* SATA phy register block */ +#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */ +#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */ +#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ +#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */ + +/* PORT_IRQ_{STAT,MASK} bits */ +#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ +#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ +#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ +#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ +#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ +#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ +#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ +#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ + +#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ +#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ +#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ +#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ +#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ +#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ +#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ +#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ +#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ + +#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \ + | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR + +#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \ + | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \ + | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \ + | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \ + | PORT_IRQ_D2H_REG_FIS + +/* PORT_CMD bits */ +#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ +#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ +#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ +#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ +#define PORT_CMD_CLO (1 << 3) /* Command list override */ +#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ +#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ +#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ + +#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ +#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ +#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ + +#define AHCI_MAX_PORTS 32 + +/* SETFEATURES stuff */ +#define SETFEATURES_XFER 0x03 +#define XFER_UDMA_7 0x47 +#define XFER_UDMA_6 0x46 +#define XFER_UDMA_5 0x45 +#define XFER_UDMA_4 0x44 +#define XFER_UDMA_3 0x43 +#define XFER_UDMA_2 0x42 +#define XFER_UDMA_1 0x41 +#define XFER_UDMA_0 0x40 +#define XFER_MW_DMA_2 0x22 +#define XFER_MW_DMA_1 0x21 +#define XFER_MW_DMA_0 0x20 +#define XFER_SW_DMA_2 0x12 +#define XFER_SW_DMA_1 0x11 +#define XFER_SW_DMA_0 0x10 +#define XFER_PIO_4 0x0C +#define XFER_PIO_3 0x0B +#define XFER_PIO_2 0x0A +#define XFER_PIO_1 0x09 +#define XFER_PIO_0 0x08 +#define XFER_PIO_SLOW 0x00 + +#define ATA_FLAG_SATA (1 << 3) +#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */ +#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */ +#define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */ +#define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */ +#define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */ + +struct ahci_cmd_hdr { + u32 opts; + u32 status; + u32 tbl_addr; + u32 tbl_addr_hi; + u32 reserved[4]; +}; + +struct ahci_sg { + u32 addr; + u32 addr_hi; + u32 reserved; + u32 flags_size; +}; + +struct ahci_ioports { + u32 cmd_addr; + u32 scr_addr; + u32 port_mmio; + struct ahci_cmd_hdr *cmd_slot; + struct ahci_sg *cmd_tbl_sg; + u32 cmd_tbl; + u32 rx_fis; +}; + +struct ahci_probe_ent { + pci_dev_t dev; + struct ahci_ioports port[AHCI_MAX_PORTS]; + u32 n_ports; + u32 hard_port_no; + u32 host_flags; + u32 host_set_flags; + u32 mmio_base; + u32 pio_mask; + u32 udma_mask; + u32 flags; + u32 cap; /* cache of HOST_CAP register */ + u32 port_map; /* cache of HOST_PORTS_IMPL reg */ + u32 link_port_map; /*linkup port map*/ +}; + +#endif -- cgit v1.2.1 From dabf9ef8c10b4dead5ef2106ef742b1c06b542de Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong Date: Wed, 23 Aug 2006 19:15:12 +0800 Subject: Add AHCI define and sata support for MPC8641HPCN board. Signed-off-by:Jason Jin --- include/configs/MPC8641HPCN.h | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 1f5e2dfd94..7097b3eee4 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -340,6 +340,17 @@ #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#define CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_ULI5288 +#define CFG_SCSI_MAX_SCSI_ID 4 +#define CFG_SCSI_MAX_LUN 1 +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE +#endif + #endif /* CONFIG_PCI */ @@ -477,7 +488,9 @@ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | CFG_CMD_PING \ | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ + | CFG_CMD_I2C \ + | CFG_CMD_SCSI \ + | CFG_CMD_EXT2) \ & \ ~(CFG_CMD_ENV \ | CFG_CMD_IMLS \ @@ -486,7 +499,9 @@ #else #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | CFG_CMD_PING \ - | CFG_CMD_I2C) \ + | CFG_CMD_I2C \ + | CFG_CMD_SCSI \ + | CGF_CMD_EXT2) \ & \ ~(CFG_CMD_ENV \ | CFG_CMD_IMLS \ @@ -498,7 +513,9 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_PCI \ | CFG_CMD_PING \ - | CFG_CMD_I2C) + | CFG_CMD_I2C \ + | CFG_CMD_SCSI \ + | CFG_CMD_EXT2) #else #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_PING \ -- cgit v1.2.1 From 5567806b67d0ae83493aa8823ad3b6c914f581d7 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 25 Aug 2006 14:38:34 -0400 Subject: Change ramdiskaddr and dtbaddr Remove PEX fluff commands. Signed-off-by: Haiying Wang Signed-off-by: Jon Loeliger --- include/configs/MPC8641HPCN.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 7097b3eee4..c704d4659a 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -610,15 +610,10 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ + "ramdiskaddr=2000000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \ - "dtbaddr=2000000\0" \ + "dtbaddr=400000\0" \ "dtbfile=mpc8641_hpcn.dtb\0" \ - "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\ - "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ - "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ - "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ - "pex=run pexstat; run pex1; run pexd\0" \ "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ "maxcpus=2" -- cgit v1.2.1 From d14ba6a798beb753e7a864500414fcc2d198b8bc Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 14 Sep 2006 08:40:36 -0500 Subject: Handle 86xx SVR values according to the new Reference Manual. Both 8641 and 8641D have SVR == 0x8090, and are distinguished by the byte in bits 16-23 instead. Thanks to Jason Jin for noticing. Signed-off-by: Jon Loeliger --- include/asm-ppc/processor.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 0060cd030b..553ef3d945 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -802,6 +802,8 @@ #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ +#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ + #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ @@ -819,9 +821,8 @@ #define SVR_8541 0x807A #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 - #define SVR_8641 0x8090 -#define SVR_8641D 0x8091 + /* I am just adding a single entry for 8260 boards. I think we may be * able to combine mbx, fads, rpxlite, bseip, and classic into a single -- cgit v1.2.1 From 09f3e09e9ebcfa7919ca8931a4b5504fadd1f1d3 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 13 Sep 2006 10:34:18 -0500 Subject: Add support for eTSEC 3 & 4 on 8548 CDS * Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS. This will only work on rev 1.3 boards (but doesn't break older boards) * Cleaned up some comments to reflect the expanded role of tsec in other systems --- include/configs/MPC8548CDS.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 37b518cca5..767ab337b3 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -381,7 +381,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" #define CONFIG_MPC85XX_TSEC3 1 #define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#undef CONFIG_MPC85XX_TSEC4 +#define CONFIG_MPC85XX_TSEC4 1 #define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC @@ -483,6 +483,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif #define CONFIG_IPADDR 192.168.1.253 -- cgit v1.2.1 From 8272dc2f58f2473d8995fcc9b916440cfba080f0 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 13 Sep 2006 10:33:35 -0500 Subject: Updated config headers to add default FDT-based booting --- include/configs/MPC8540ADS.h | 10 +++++++--- include/configs/MPC8541CDS.h | 9 ++++++--- include/configs/MPC8548CDS.h | 13 ++++++++----- include/configs/MPC8555CDS.h | 9 ++++++--- 4 files changed, 27 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 8e4d2c95a4..31ffbaf15b 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -517,8 +517,10 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -526,13 +528,15 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index f73caf0319..2b87f1bd6a 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -489,8 +489,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -498,7 +500,8 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 767ab337b3..03ab976d11 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -389,13 +389,11 @@ extern unsigned long get_clock_freq(void); #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2 #define TSEC4_PHY_ADDR 3 -#define FEC_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 -#define FEC_PHYIDX 0 /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" @@ -507,8 +505,11 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" + #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -516,7 +517,9 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index b94e38ae34..771a9d3b95 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -489,8 +489,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -498,7 +500,8 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ -- cgit v1.2.1 From ac611700e5bcdd5a762dcc4d28db256fcc5a4bf2 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 20 Sep 2006 23:47:49 +0200 Subject: Fix comments in include/ppc440.h Patch by Martin Hicks, 16 Jun 2006 --- include/ppc440.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/ppc440.h b/include/ppc440.h index c4a3ed5483..e407320a9e 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1570,8 +1570,8 @@ #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ #if defined(CONFIG_440GX) -#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */ -#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */ +#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */ +#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */ #endif /* CONFIG_440GX */ #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ -- cgit v1.2.1 From 7299712c869ce1f409a854ca0d2b268783038ab2 Mon Sep 17 00:00:00 2001 From: Marian Balakowicz Date: Tue, 3 Oct 2006 20:28:38 +0200 Subject: Update for CAM5200 board: - Map in a additional chip selects CS4 and CS5. - Modify the port configration, configure six UARTs and no PCI, ATA and USB. - Add custom flash driver to handle specific byte swapping --- include/configs/TQM5200.h | 101 +++++++++++++++++++++++++++++++--------------- include/flash.h | 4 ++ 2 files changed, 72 insertions(+), 33 deletions(-) (limited to 'include') diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index e0de5c1b36..897d1b262b 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -285,7 +285,7 @@ */ #define CFG_IPBSPEED_133 /* define for 133MHz speed */ -#if defined(CFG_IPBSPEED_133) +#if defined(CFG_IPBSPEED_133) && !defined(CONFIG_CAM5200) /* * PCI Bus clocking configuration * @@ -349,13 +349,29 @@ */ #define CFG_FLASH_BASE 0xFC000000 +#ifndef CONFIG_CAM5200 /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#else /* CONFIG_CAM5200 */ +#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks + (= chip selects) */ +#define CFG_FLASH_WORD_SIZE unsigned int /* main flash device with */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_ADDR0 0x555 +#define CFG_FLASH_ADDR1 0x2AA +#define CFG_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */ +#define CFG_MAX_FLASH_SECT 128 +#endif /* ifndef CONFIG_CAM5200 */ + #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ #define CFG_FLASH_USE_BUFFER_WRITE 1 #if defined (CONFIG_CAM5200) @@ -366,9 +382,6 @@ # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) #endif -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ - /* Dynamic MTD partition support */ #define CONFIG_JFFS2_CMDLINE #define MTDIDS_DEFAULT "nor0=TQM5200-0" @@ -401,10 +414,8 @@ #elif defined (CONFIG_CAM5200) # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \ "1792k(kernel)," \ - "3584k(small-fs)," \ - "2m(initrd)," \ - "8m(misc)," \ - "16m(big-fs)" + "5632k(rootfs)," \ + "24m(home)" #elif defined (CONFIG_FO300) # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ "1408k(kernel)," \ @@ -479,31 +490,43 @@ /* * GPIO configuration * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 + * use CS1: Bit 0 (mask: 0x80000000): + * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1). * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards and FO300 boards. Do not use - * with REV100 modules (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * 01x -> Use AC97 - * use PSC3: Bits 20-23 (mask: 0x00000f00) - * 1100 -> UART/SPI (on FO300 board) - * use PSC6: - * on STK52xx and FO300: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. + * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. + * SPI on PSC3 according to PSC3 setting. Use for CAM5200. + * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. + * Use for REV200 STK52XX boards and FO300 boards. Do not use + * with REV100 modules (because, there I2C1 is used as I2C bus). + * use ATA: Bits 6-7 (mask 0x03000000): + * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects. + * Use for CAM5200 board. + * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards. + * use PSC6: Bits 9-11 (mask 0x00700000): + * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as + * UART, CODEC or IrDA. + * GPIO on PSC6_3 is used in post_hotkeys_pressed() to + * enable extended POST tests. + * Use for MINI-FAP and TQM5200_IB boards. + * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used. + * Extended POST test is not available. + * Use for STK52xx, FO300 and CAM5200 boards. + * use PCI_DIS: Bit 16 (mask 0x00008000): + * 1 -> disable PCI controller (on CAM5200 board). + * use USB: Bits 18-19 (mask 0x00003000): + * 10 -> two UARTs (on FO300 and CAM5200). + * use PSC3: Bits 20-23 (mask: 0x00000f00): + * 0000 -> All PSC3 pins are GPIOs. + * 1100 -> UART/SPI (on FO300 board). + * 0100 -> UART (on CAM5200 board). + * use PSC2: Bits 25:27 (mask: 0x00000030): + * 000 -> All PSC2 pins are GPIOs. + * 100 -> UART (on CAM5200 board). + * 001 -> CAN1/2 on PSC2 pins. + * Use for REV100 STK52xx boards + * 01x -> Use AC97 (on FO300 board). + * use PSC1: Bits 29-31 (mask: 0x00000007): + * 100 -> UART (on all boards). */ #if defined (CONFIG_MINIFAP) # define CFG_GPS_PORT_CONFIG 0x91000004 @@ -519,6 +542,8 @@ # endif #elif defined (CONFIG_FO300) # define CFG_GPS_PORT_CONFIG 0x91502c24 +#elif defined (CONFIG_CAM5200) +# define CFG_GPS_PORT_CONFIG 0x8050A444 #else /* TMQ5200 Inbetriebnahme-Board */ # define CFG_GPS_PORT_CONFIG 0x81000004 #endif @@ -613,6 +638,16 @@ #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ +#if defined(CONFIG_CAM5200) +#define CFG_CS4_START 0xB0000000 +#define CFG_CS4_SIZE 0x00010000 +#define CFG_CS4_CFG 0x01019C10 + +#define CFG_CS5_START 0xD0000000 +#define CFG_CS5_SIZE 0x01208000 +#define CFG_CS5_CFG 0x1414BF10 +#endif + #define CFG_RESET_ADDRESS 0xff000000 /*----------------------------------------------------------------------- diff --git a/include/flash.h b/include/flash.h index 84b48a9f2e..d91589a6c0 100644 --- a/include/flash.h +++ b/include/flash.h @@ -209,6 +209,9 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define AMD_ID_GL064M_3 0x22012201 /* 3rd ID word for S29GL064M-R6 */ #define AMD_ID_GL064MT_2 0x22102210 /* 2nd ID word for S29GL064M-R3 (top boot sector) */ #define AMD_ID_GL064MT_3 0x22012201 /* 3rd ID word for S29GL064M-R3 (top boot sector) */ +#define AMD_ID_GL128N_2 0x22212221 /* 2nd ID word for S29GL128N */ +#define AMD_ID_GL128N_3 0x22012201 /* 3rd ID word for S29GL128N */ + #define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */ #define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */ @@ -417,6 +420,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */ #define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */ #define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */ +#define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */ #define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ -- cgit v1.2.1 From 511d0c72b82aab9b807efde50fc9e390365f5ca1 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 9 Oct 2006 00:42:01 +0200 Subject: Coding style cleanup --- include/common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index bee2fb7022..a873fa99b7 100644 --- a/include/common.h +++ b/include/common.h @@ -110,7 +110,7 @@ typedef volatile unsigned char vu_char; #endif /* DEBUG */ #define BUG() do { \ - printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ + printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ panic("BUG!"); \ } while (0) #define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0) -- cgit v1.2.1 From 7ce343e49993341f2cdd559e0c44ad7507f71eb7 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 9 Oct 2006 00:48:57 +0200 Subject: Add missing files for EP82xxM boards Patch by Aaron Sells, 20 Jun 2006 --- include/configs/ep82xxm.h | 395 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 395 insertions(+) create mode 100644 include/configs/ep82xxm.h (limited to 'include') diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h new file mode 100644 index 0000000000..5d7bed611a --- /dev/null +++ b/include/configs/ep82xxm.h @@ -0,0 +1,395 @@ +/* + * Copyright (C) 2006 Embedded Planet, LLC. + * + * U-Boot configuration for Embedded Planet EP82xxM boards. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MPC8260 +#define CPU_ID_STR "MPC8270" + +#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board /* + /* 256MB SDRAM / 64MB FLASH */ + +#undef DEBUG + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +/* + * Select serial console configuration + * + * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + */ +#define CONFIG_CONS_ON_SMC /* Console is on SMC */ +#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ +#undef CONFIG_CONS_NONE /* It's not on external UART */ +#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ + +#define CFG_BCSR 0xFA000000 + +/* + * Select ethernet configuration + * + * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, + * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for + * SCC, 1-3 for FCC) + * + * If CONFIG_ETHER_NONE is defined, then either the ethernet routines + * must be defined elsewhere (as for the console), or CFG_CMD_NET must + * be removed from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ +#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ +#undef CONFIG_ETHER_NONE /* No external Ethernet */ + +#define CONFIG_NET_MULTI + +#define CONFIG_ETHER_ON_FCC2 +#define CONFIG_ETHER_ON_FCC3 + +#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) +#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16) +#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) + +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ + +/* + * GPIO pins used for bit-banged MII communications + */ +#define MDIO_PORT 0 /* Not used - implemented in BCSR */ +#define MDIO_ACTIVE (*(vu_char *)(CFG_BCSR + 8) &= 0xFB) +#define MDIO_TRISTATE (*(vu_char *)(CFG_BCSR + 8) |= 0x04) +#define MDIO_READ (*(vu_char *)(CFG_BCSR + 8) & 1) + +#define MDIO(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \ + else *(vu_char *)(CFG_BCSR + 8) &= 0xFE + +#define MDC(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \ + else *(vu_char *)(CFG_BCSR + 8) &= 0xFD + +#define MIIDELAY udelay(1) + + +#ifndef CONFIG_8260_CLKIN +#define CONFIG_8260_CLKIN 66000000 /* in Hz */ +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_ECHO \ + | CFG_CMD_I2C \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + | CFG_CMD_DATE \ + | CFG_CMD_DTT \ + | CFG_CMD_EEPROM \ + | CFG_CMD_PCI \ + | CFG_CMD_DIAG \ + ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_ETHADDR 00:10:EC:00:88:65 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:10:EC:80:88:65 +#define CONFIG_IPADDR 10.0.0.245 +#define CONFIG_HOSTNAME EP82xxM +#define CONFIG_SERVERIP 10.0.0.26 +#define CONFIG_GATEWAYIP 10.0.0.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CFG_ENV_IN_OWN_SECT 1 +#define CFG_AUTO_COMPLETE +#define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3 ETHERNET" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#endif + +#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "ep82xxm=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +/* + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#if 1 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#endif + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_BASE 0xFC000000 +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +/* EEPROM Configuration */ +#define CFG_EEPROM_SIZE 0x1000 +#define CFG_I2C_EEPROM_ADDR 0x54 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x0 +#endif /* CFG_ENV_IS_IN_EEPROM */ + +/* RTC Configuration */ +#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */ +#define CFG_I2C_RTC_ADDR 0x68 +#define CONFIG_M41T11_BASE_YEAR 1900 + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM75 1 +#define CONFIG_DTT_SENSORS {0} +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +/*----------------------------------------------------------------------- + * NVRAM Configuration + *----------------------------------------------------------------------- + */ +#define CFG_NVRAM_BASE_ADDR 0xFA080000 +#define CFG_NVRAM_SIZE (128*1024)-16 + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_BOOTDELAY 0 + +/* PCI Memory map (if different from default map */ +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ +#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ +#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ + PICMR_PREFETCH_EN) + +/* + * These are the windows that allow the CPU to access PCI address space. + * All three PCI master windows, which allow the CPU to access PCI + * prefetch, non prefetch, and IO space (see below), must all fit within + * these windows. + */ + +/* + * Master window that allows the CPU to access PCI Memory (prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ +#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ +#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL +#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) + +/* + * Master window that allows the CPU to access PCI Memory (non-prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ +#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ +#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL +#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) + +/* + * Master window that allows the CPU to access PCI IO space. + * This window will be setup with the first set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ +#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ +#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL +#define CFG_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ +#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) + + +/* PCIBR0 - for PCI IO*/ +#define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */ +#define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ +/* PCIBR1 - prefetch and non-prefetch regions joined together */ +#define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL +#define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U) + + +#define CFG_DIRECT_FLASH_TFTP + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS +#define CFG_JFFS2_FIRST_SECTOR 0 +#define CFG_JFFS2_LAST_SECTOR 62 +#define CFG_JFFS2_SORT_FRAGMENTS +#define CFG_JFFS_CUSTOM_PART +#endif /* CFG_CMD_JFFS2 */ + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#define CFG_I2C_SPEED 100000 /* I2C speed */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ +#endif /* CFG_CMD_I2C */ + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 256KB for Monitor */ + +#define CFG_DEFAULT_IMMR 0x00010000 +#define CFG_IMMR 0xF0000000 + +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/* Hard reset configuration word */ +#define CFG_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */ +/* No slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 + +#define CFG_HID2 0 + +#define CFG_SIUMCR 0x02610000 +#define CFG_SYPCR 0xFFFF0689 +#define CFG_BCR 0x8080E000 +#define CFG_SCCR 0x00000001 + +#define CFG_RMR 0 +#define CFG_TMCNTSC 0x000000C3 +#define CFG_PISCR 0x00000083 +#define CFG_RCCR 0 + +#define CFG_MPTPR 0x0A00 +#define CFG_PSDMR 0xC432246E +#define CFG_PSRT 0x32 + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00000041) +#define CFG_SDRAM_OR 0xF0002900 + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801) +#define CFG_OR0_PRELIM 0xFC000882 +#define CFG_BR4_PRELIM (CFG_BCSR | 0x00001001) +#define CFG_OR4_PRELIM 0xFFF00050 + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From 1a1b7374b89a04737c76948b00207b56a1bb37b6 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 9 Oct 2006 12:55:38 +0200 Subject: Define IH_CPU_AVR32 Make it possible to generate AVR32 uImage files with mkimage and make cmd_bootm recognize them. Patch by Haavard Skinnemoen, 22 Sep 2006 --- include/image.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/image.h b/include/image.h index 139df0b2d1..d9f2d461a5 100644 --- a/include/image.h +++ b/include/image.h @@ -76,6 +76,7 @@ #define IH_CPU_MICROBLAZE 14 /* MicroBlaze */ #define IH_CPU_NIOS2 15 /* Nios-II */ #define IH_CPU_BLACKFIN 16 /* Blackfin */ +#define IH_CPU_AVR32 17 /* AVR32 */ /* * Image Types -- cgit v1.2.1 From 2255b2d2044d434463eb2661e18018e50f1643d9 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 10 Oct 2006 12:36:02 +0200 Subject: * Several improvements to the new NAND subsystem: - JFFS2 related commands implemented in mtd-utils style - Support for bad blocks - Bad block testing commands - NAND lock commands Please take a look at doc/README.nand for more details Patch by Guido Classen, 10 Oct 2006 --- include/nand.h | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) (limited to 'include') diff --git a/include/nand.h b/include/nand.h index 905115b3da..5c7311fd50 100644 --- a/include/nand.h +++ b/include/nand.h @@ -60,4 +60,61 @@ static inline int nand_erase(nand_info_t *info, ulong off, ulong size) return info->erase(info, &instr); } + +/***************************************************************************** + * declarations from nand_util.c + ****************************************************************************/ + +struct nand_write_options { + u_char *buffer; /* memory block containing image to write */ + ulong length; /* number of bytes to write */ + ulong offset; /* start address in NAND */ + int quiet; /* don't display progress messages */ + int autoplace; /* if true use auto oob layout */ + int forcejffs2; /* force jffs2 oob layout */ + int forceyaffs; /* force yaffs oob layout */ + int noecc; /* write without ecc */ + int writeoob; /* image contains oob data */ + int pad; /* pad to page size */ + int blockalign; /* 1|2|4 set multiple of eraseblocks + * to align to */ +}; + +typedef struct nand_write_options nand_write_options_t; + +struct nand_read_options { + u_char *buffer; /* memory block in which read image is written*/ + ulong length; /* number of bytes to read */ + ulong offset; /* start address in NAND */ + int quiet; /* don't display progress messages */ + int readoob; /* put oob data in image */ +}; + +typedef struct nand_read_options nand_read_options_t; + +struct nand_erase_options { + ulong length; /* number of bytes to erase */ + ulong offset; /* first address in NAND to erase */ + int quiet; /* don't display progress messages */ + int jffs2; /* if true: format for jffs2 usage + * (write appropriate cleanmarker blocks) */ + int scrub; /* if true, really clean NAND by erasing + * bad blocks (UNSAFE) */ +}; + +typedef struct nand_erase_options nand_erase_options_t; + +int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts); + +int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts); +int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); + +#define NAND_LOCK_STATUS_TIGHT 0x01 +#define NAND_LOCK_STATUS_LOCK 0x02 +#define NAND_LOCK_STATUS_UNLOCK 0x04 + +int nand_lock( nand_info_t *meminfo, int tight ); +int nand_unlock( nand_info_t *meminfo, ulong start, ulong length ); +int nand_get_lock_status(nand_info_t *meminfo, ulong offset); + #endif -- cgit v1.2.1 From 8b283dbb3a08d1b8d406bc15f119e081b3e2606a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Oct 2006 17:16:04 -0500 Subject: Fix whitespace issues. --- include/asm-ppc/immap_86xx.h | 466 +++++++++++++++++++++--------------------- include/configs/MPC8641HPCN.h | 9 - 2 files changed, 233 insertions(+), 242 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 5b1f0f4ea6..685fcafdf2 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -59,29 +59,29 @@ typedef struct ccsr_local_mcm { char res22[20]; uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ char res23[4]; - uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ + uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ char res24[716]; uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */ char res25[4]; - uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ - char res26[4]; - uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */ - char res27[44]; - uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */ - uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */ - uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */ - uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */ - char res28[16]; - uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */ - uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */ - uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */ - char res29[3476]; + uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ + char res26[4]; + uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */ + char res27[44]; + uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */ + uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */ + uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */ + uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */ + char res28[16]; + uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */ + uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */ + uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */ + char res29[3476]; uint edr; /* 0x1e00 - MCM Error Detect Register */ char res30[4]; uint eer; /* 0x1e08 - MCM Error Enable Register */ uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */ uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */ - uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */ + uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */ char res31[488]; } ccsr_local_mcm_t; @@ -106,28 +106,28 @@ typedef struct ccsr_ddr { uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ - char res7[104]; - uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ + char res7[104]; + uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */ - uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ + uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ - uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ - uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ + uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ + uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ - uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ + uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ char res8[4]; uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ - char res9[12]; - uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ - uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ - uint init_addr; /* 0x2148 - DDR training initialzation address */ - uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */ - char res10[2728]; - uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ - uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ + char res9[12]; + uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ + uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ + uint init_addr; /* 0x2148 - DDR training initialzation address */ + uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */ + char res10[2728]; + uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ + uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ char res11[512]; uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ @@ -142,7 +142,7 @@ typedef struct ccsr_ddr { uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */ uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ - uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ + uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ char res14[164]; uint debug_1; /* 0x2f00 */ @@ -279,7 +279,7 @@ typedef struct ccsr_lbc { typedef struct ccsr_pex { uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */ uint cfg_data; /* 0x8004 - PEX Configuration Data Register */ - char res1[4]; + char res1[4]; uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */ char res2[16]; uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */ @@ -326,7 +326,7 @@ typedef struct ccsr_pex { uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */ char res16[12]; uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */ - char res17[4]; + char res17[4]; uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */ uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */ uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */ @@ -355,73 +355,73 @@ typedef struct ccsr_pex { /* Hyper Transport Register Block (0xA000-0xB000) */ typedef struct ccsr_ht { - uint hcfg_addr; /* 0xa000 - HT Configuration Address register */ - uint hcfg_data; /* 0xa004 - HT Configuration Data register */ + uint hcfg_addr; /* 0xa000 - HT Configuration Address register */ + uint hcfg_data; /* 0xa004 - HT Configuration Data register */ char res1[3064]; - uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */ + uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */ char res2[12]; - uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */ - char res3[12]; - uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */ - char res4[4]; - uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */ - char res5[4]; - uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */ - char res6[12]; - uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */ - char res7[4]; - uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */ - char res8[4]; - uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */ - char res9[12]; - uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */ - char res10[4]; - uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */ - char res11[4]; - uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */ - char res12[12]; - uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */ - char res13[4]; - uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */ - char res14[4]; - uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */ - char res15[236]; - uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */ - char res16[4]; - uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */ - char res17[4]; - uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */ - char res18[12]; - uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */ - char res19[4]; - uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */ - char res20[4]; - uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */ - char res21[12]; - uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */ - char res22[4]; - uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */ - char res23[4]; - uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */ - char res24[12]; - uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */ - char res25[4]; - uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */ - char res26[4]; - uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */ - char res27[12]; - uint hedr; /* 0xae00 - HT Error Detect register */ - char res28[4]; - uint heier; /* 0xae08 - HT Error Interrupt Enable register */ - char res29[4]; - uint hecdr; /* 0xae10 - HT Error Capture Disbale register */ - char res30[12]; - uint hecsr; /* 0xae20 - HT Error Capture Status register */ - char res31[4]; - uint hec0; /* 0xae28 - HT Error Capture 0 register */ - uint hec1; /* 0xae2c - HT Error Capture 1 register */ - uint hec2; /* 0xae30 - HT Error Capture 2 register */ - char res32[460]; + uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */ + char res3[12]; + uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */ + char res4[4]; + uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */ + char res5[4]; + uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */ + char res6[12]; + uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */ + char res7[4]; + uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */ + char res8[4]; + uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */ + char res9[12]; + uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */ + char res10[4]; + uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */ + char res11[4]; + uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */ + char res12[12]; + uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */ + char res13[4]; + uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */ + char res14[4]; + uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */ + char res15[236]; + uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */ + char res16[4]; + uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */ + char res17[4]; + uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */ + char res18[12]; + uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */ + char res19[4]; + uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */ + char res20[4]; + uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */ + char res21[12]; + uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */ + char res22[4]; + uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */ + char res23[4]; + uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */ + char res24[12]; + uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */ + char res25[4]; + uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */ + char res26[4]; + uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */ + char res27[12]; + uint hedr; /* 0xae00 - HT Error Detect register */ + char res28[4]; + uint heier; /* 0xae08 - HT Error Interrupt Enable register */ + char res29[4]; + uint hecdr; /* 0xae10 - HT Error Capture Disbale register */ + char res30[12]; + uint hecsr; /* 0xae20 - HT Error Capture Status register */ + char res31[4]; + uint hec0; /* 0xae28 - HT Error Capture 0 register */ + uint hec1; /* 0xae2c - HT Error Capture 1 register */ + uint hec2; /* 0xae30 - HT Error Capture 2 register */ + char res32[460]; } ccsr_ht_t; /* DMA Registers(0x2_1000-0x2_2000) */ @@ -505,14 +505,14 @@ typedef struct ccsr_dma { /* tsec1-4: 24000-28000 */ typedef struct ccsr_tsec { - uint id; /* 0x24000 - Controller ID Register */ + uint id; /* 0x24000 - Controller ID Register */ char res1[12]; uint ievent; /* 0x24010 - Interrupt Event Register */ uint imask; /* 0x24014 - Interrupt Mask Register */ uint edis; /* 0x24018 - Error Disabled Register */ char res2[4]; uint ecntrl; /* 0x24020 - Ethernet Control Register */ - char res2_1[4]; + char res2_1[4]; uint ptv; /* 0x24028 - Pause Time Value Register */ uint dmactrl; /* 0x2402c - DMA Control Register */ uint tbipa; /* 0x24030 - TBI PHY Address Register */ @@ -521,102 +521,102 @@ typedef struct ccsr_tsec { char res4[8]; uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */ uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */ - char res4_1[4]; - uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */ - uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */ + char res4_1[4]; + uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */ + uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */ char res5[84]; uint tctrl; /* 0x24100 - Transmit Control Register */ uint tstat; /* 0x24104 - Transmit Status Register */ - uint dfvlan; /* 0x24108 - Default VLAN control word */ - char res6[4]; - uint txic; /* 0x24110 - Transmit interrupt coalescing Register */ - uint tqueue; /* 0x24114 - Transmit Queue Control Register */ + uint dfvlan; /* 0x24108 - Default VLAN control word */ + char res6[4]; + uint txic; /* 0x24110 - Transmit interrupt coalescing Register */ + uint tqueue; /* 0x24114 - Transmit Queue Control Register */ char res7[40]; - uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */ - uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */ - char res8[52]; - uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */ - char res9[4]; - uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */ - char res10[4]; - uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */ - char res11[4]; - uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */ - char res12[4]; - uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */ - char res13[4]; - uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */ - char res14[4]; - uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */ - char res15[4]; - uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */ - char res16[4]; - uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */ - char res17[64]; + uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */ + uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */ + char res8[52]; + uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */ + char res9[4]; + uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */ + char res10[4]; + uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */ + char res11[4]; + uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */ + char res12[4]; + uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */ + char res13[4]; + uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */ + char res14[4]; + uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */ + char res15[4]; + uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */ + char res16[4]; + uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */ + char res17[64]; uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */ uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */ - char res18[4]; - uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */ - char res19[4]; - uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */ - char res20[4]; - uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */ - char res21[4]; - uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */ - char res22[4]; - uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */ - char res23[4]; - uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */ - char res24[4]; - uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */ - char res25[192]; + char res18[4]; + uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */ + char res19[4]; + uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */ + char res20[4]; + uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */ + char res21[4]; + uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */ + char res22[4]; + uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */ + char res23[4]; + uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */ + char res24[4]; + uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */ + char res25[192]; uint rctrl; /* 0x24300 - Receive Control Register */ uint rstat; /* 0x24304 - Receive Status Register */ char res26[8]; - uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */ - uint rqueue; /* 0x24314 - Receive queue control register */ + uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */ + uint rqueue; /* 0x24314 - Receive queue control register */ char res27[24]; - uint rbifx; /* 0x24330 - Receive bit field extract control Register */ - uint rqfar; /* 0x24334 - Receive queue filing table address Register */ - uint rqfcr; /* 0x24338 - Receive queue filing table control Register */ - uint rqfpr; /* 0x2433c - Receive queue filing table property Register */ + uint rbifx; /* 0x24330 - Receive bit field extract control Register */ + uint rqfar; /* 0x24334 - Receive queue filing table address Register */ + uint rqfcr; /* 0x24338 - Receive queue filing table control Register */ + uint rqfpr; /* 0x2433c - Receive queue filing table property Register */ uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */ char res28[56]; - uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */ - char res29[4]; - uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */ - char res30[4]; - uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */ - char res31[4]; - uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */ - char res32[4]; - uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */ - char res33[4]; - uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */ - char res34[4]; - uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */ - char res35[4]; - uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */ - char res36[4]; - uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */ - char res37[64]; + uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */ + char res29[4]; + uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */ + char res30[4]; + uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */ + char res31[4]; + uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */ + char res32[4]; + uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */ + char res33[4]; + uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */ + char res34[4]; + uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */ + char res35[4]; + uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */ + char res36[4]; + uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */ + char res37[64]; uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */ uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */ - char res38[4]; + char res38[4]; uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */ - char res39[4]; + char res39[4]; uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */ - char res40[4]; + char res40[4]; uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */ - char res41[4]; + char res41[4]; uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */ - char res42[4]; + char res42[4]; uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */ - char res43[4]; + char res43[4]; uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */ - char res44[4]; + char res44[4]; uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */ - char res45[192]; + char res45[192]; uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */ uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */ uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */ @@ -629,40 +629,40 @@ typedef struct ccsr_tsec { uint miimcon; /* 0x2452c - MII Management Control Register */ uint miimstat; /* 0x24530 - MII Management Status Register */ uint miimind; /* 0x24534 - MII Management Indicator Register */ - uint ifctrl; /* 0x24538 - Interface Contrl Register */ + uint ifctrl; /* 0x24538 - Interface Contrl Register */ uint ifstat; /* 0x2453c - Interface Status Register */ uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */ uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */ - uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */ - uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */ - uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */ - uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */ - uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */ - uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */ - uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */ - uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */ - uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */ - uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */ - uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */ - uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */ - uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */ - uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */ - uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */ - uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */ - uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */ - uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */ - uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */ - uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */ - uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */ - uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */ - uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */ - uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */ - uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */ - uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */ - uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */ - uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */ - uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */ - uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */ + uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */ + uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */ + uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */ + uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */ + uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */ + uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */ + uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */ + uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */ + uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */ + uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */ + uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */ + uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */ + uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */ + uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */ + uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */ + uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */ + uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */ + uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */ + uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */ + uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */ + uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */ + uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */ + uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */ + uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */ + uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */ + uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */ + uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */ + uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */ + uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */ + uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */ char res48[192]; uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */ uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */ @@ -712,7 +712,7 @@ typedef struct ccsr_tsec { uint car2; /* 0x24734 - Carry Register Two */ uint cam1; /* 0x24738 - Carry Mask Register One */ uint cam2; /* 0x2473c - Carry Mask Register Two */ - uint rrej; /* 0x24740 - Receive filer rejected packet counter */ + uint rrej; /* 0x24740 - Receive filer rejected packet counter */ char res50[188]; uint iaddr0; /* 0x24800 - Indivdual address register 0 */ uint iaddr1; /* 0x24804 - Indivdual address register 1 */ @@ -732,11 +732,11 @@ typedef struct ccsr_tsec { uint gaddr6; /* 0x24898 - Global address register 6 */ uint gaddr7; /* 0x2489c - Global address register 7 */ char res52[352]; - uint fifocfg; /* 0x24A00 - FIFO interface configuration register */ - char res53[500]; - uint attr; /* 0x24BF8 - DMA Attribute register */ - uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */ - char res54[1024]; + uint fifocfg; /* 0x24A00 - FIFO interface configuration register */ + char res53[500]; + uint attr; /* 0x24BF8 - DMA Attribute register */ + uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */ + char res54[1024]; } ccsr_tsec_t; /* PIC Registers(0x4_0000-0x6_1000) */ @@ -833,7 +833,7 @@ typedef struct ccsr_pic { char res45[12]; uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */ char res46[12]; - uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */ + uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */ char res47[12]; uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */ char res48[60]; @@ -1024,7 +1024,7 @@ typedef struct ccsr_pic { uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */ char res141[12]; uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */ - char res142[4108]; + char res142[4108]; uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */ char res143[12]; uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */ @@ -1109,7 +1109,7 @@ typedef struct ccsr_rio { uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */ uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */ uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */ - uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */ + uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */ uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */ char res13[12]; uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */ @@ -1133,7 +1133,7 @@ typedef struct ccsr_rio { char res22[20]; uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */ char res23[4]; - uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */ + uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */ char res24[2716]; uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */ @@ -1282,13 +1282,13 @@ typedef struct ccsr_rio { uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */ uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */ uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */ - uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */ + uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */ char res57[100]; uint pwmr; /* 0xd34e0 - Port-Write Mode Register */ uint pwsr; /* 0xd34e4 - Port-Write Status Register */ uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */ uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */ - char res58[51984]; + char res58[51984]; } ccsr_rio_t; /* Global Utilities Register Block(0xe_0000-0xf_ffff) */ @@ -1313,7 +1313,7 @@ typedef struct ccsr_gur { char res6[12]; uint devdisr; /* 0xe0070 - Device disable control */ #define MPC86xx_DEVDISR_PCIEX1 0x80000000 -#define MPC86xx_DEVDISR_PCIEX2 0x40000000 +#define MPC86xx_DEVDISR_PCIEX2 0x40000000 char res7[12]; uint powmgtcsr; /* 0xe0080 - Power management status and control register */ char res8[12]; @@ -1327,11 +1327,11 @@ typedef struct ccsr_gur { uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ char res12[12]; uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ - int res13[57]; - uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/ - int res14[6]; - uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ - char res15[61656]; + int res13[57]; + uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/ + int res14[6]; + uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ + char res15[61656]; } ccsr_gur_t; typedef struct immap { @@ -1340,21 +1340,21 @@ typedef struct immap { ccsr_i2c_t im_i2c; ccsr_duart_t im_duart; ccsr_lbc_t im_lbc; - ccsr_ddr_t im_ddr2; - char res1[4096]; + ccsr_ddr_t im_ddr2; + char res1[4096]; ccsr_pex_t im_pex1; - ccsr_pex_t im_pex2; - ccsr_ht_t im_ht; - char res2[90112]; + ccsr_pex_t im_pex2; + ccsr_ht_t im_ht; + char res2[90112]; ccsr_dma_t im_dma; - char res3[8192]; + char res3[8192]; ccsr_tsec_t im_tsec1; ccsr_tsec_t im_tsec2; - ccsr_tsec_t im_tsec3; - ccsr_tsec_t im_tsec4; - char res4[98304]; + ccsr_tsec_t im_tsec3; + ccsr_tsec_t im_tsec4; + char res4[98304]; ccsr_pic_t im_pic; - char res5[389120]; + char res5[389120]; ccsr_rio_t im_rio; ccsr_gur_t im_gur; } immap_t; diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index c704d4659a..6e883f73f8 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -85,7 +85,6 @@ #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 - /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) @@ -94,7 +93,6 @@ #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - /* * DDR Setup */ @@ -317,7 +315,6 @@ #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ - #if defined(CONFIG_PCI) #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -353,7 +350,6 @@ #endif /* CONFIG_PCI */ - #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI @@ -384,7 +380,6 @@ #endif /* CONFIG_TSEC_ENET */ - /* * BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR @@ -462,9 +457,6 @@ #define CFG_IBAT7L 0x00000000 #define CFG_IBAT7U 0x00000000 - - - /* * Environment */ @@ -572,7 +564,6 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif - /* * Environment Configuration */ -- cgit v1.2.1 From 7376eb87aaa601f728f9b8e5e9cd2711a67f529e Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 11 Oct 2006 15:13:01 -0500 Subject: * Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock --- include/ft_build.h | 2 ++ include/pci.h | 3 +++ 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/include/ft_build.h b/include/ft_build.h index f5156879de..89c689c084 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -64,6 +64,8 @@ void *ft_get_prop(void *bphp, const char *propname, int *szp); #ifdef CONFIG_OF_BOARD_SETUP void ft_board_setup(void *blob, bd_t *bd); +void ft_cpu_setup(void *blob, bd_t *bd); +void ft_pci_setup(void *blob, bd_t *bd); #endif #endif diff --git a/include/pci.h b/include/pci.h index e0e8783a7a..cc216e17d4 100644 --- a/include/pci.h +++ b/include/pci.h @@ -501,4 +501,7 @@ extern int pci_hose_config_device(struct pci_controller *hose, extern void pci_mpc824x_init (struct pci_controller *hose); #endif +#ifdef CONFIG_MPC85xx +extern void pci_mpc85xx_init (struct pci_controller *hose); +#endif #endif /* _PCI_H */ -- cgit v1.2.1 From 4707fb50cc9f815996be5f2e5a8660de852b2c37 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Fri, 13 Oct 2006 21:09:09 +0200 Subject: Preliminary patch adding support for the MarelV38B board. --- include/common.h | 3 +- include/configs/V38B.h | 368 +++++++++++++++++++++++++++++++++++++++++++++++++ include/status_led.h | 9 ++ 3 files changed, 379 insertions(+), 1 deletion(-) create mode 100644 include/configs/V38B.h (limited to 'include') diff --git a/include/common.h b/include/common.h index bee2fb7022..e296e684a0 100644 --- a/include/common.h +++ b/include/common.h @@ -313,7 +313,8 @@ void board_ether_init (void); #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_MBX) || \ defined(CONFIG_IAD210) || defined(CONFIG_XPEDITE1K) || \ - defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) + defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) || \ + defined(CONFIG_V38B) void board_get_enetaddr (uchar *addr); #endif diff --git a/include/configs/V38B.h b/include/configs/V38B.h new file mode 100644 index 0000000000..9b8fc699a9 --- /dev/null +++ b/include/configs/V38B.h @@ -0,0 +1,368 @@ +/* + * (C) Copyright 2003-2004 Wolfgang Denk, DENX Software Engineering, + * wd@denx.de. + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#if 0 +#define DEBUG 0xFFF +#endif + +#if 0 +#define DEBUG 0x01 +#endif + +/* + * High Level Configuration Options + * (easy to change) +*/ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ +#define CONFIG_V38B 1 /* ... on V38B board */ +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ +#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ +#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ + +#define CONFIG_NETCONSOLE 1 + +#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ + +#define CFG_XLB_PIPELINING 1 /* gives better performance */ + + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + + +/* + * DDR + */ +#define SDRAM_DDR 1 /* is DDR */ +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x704f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + + +/* + * PCI - no suport + */ +#undef CONFIG_PCI + +/* + * Partitions + */ +#define CONFIG_MAC_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 + +/* + * USB + */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_SDRAMi | \ + CFG_CMD_DATE | \ + CFG_CMD_USB | \ + CFG_CMD_FAT) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Boot low with 16 MB Flash + */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT16 1 + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "devno=5\0" \ + "hostname=V38B_$(devno)\0" \ + "ipaddr=10.100.99.$(devno)\0" \ + "netmask=255.255.0.0\0" \ + "serverip=10.100.10.90\0" \ + "gatewayip=10.100.254.254\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=mpc5200/uImage\0" \ + "bootcmd=run net_nfs\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off panic=1\0" \ + "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip;bootm $(kernel_addr) " \ + "$(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs " \ + "addip;bootm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#if defined(CONFIG_MPC5200) +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#endif +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 + +/* + * RTC configuration + */ +#define CFG_I2C_RTC_ADDR 0x51 + +/* + * Flash configuration - use CFI driver + */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OVERWRITE 1 + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_MII 1 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x90000404 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00047801 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +/* Status LED */ + +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ + +#define CFG_LED_BASE (0xf0000600 + 0x70) /* Timer 7 GPIO */ + +#ifndef __ASSEMBLY__ +/* LEDs */ +typedef unsigned int led_id_t; + +#define __led_toggle(_msk) \ + do { \ + *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \ + } while(0) + +#define __led_set(_msk, _st) \ + do { \ + if ((_st)) \ + *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \ + else \ + *((volatile long *) (CFG_LED_BASE)) |= (_msk); \ + } while(0) + +#define __led_init(_msk, st) \ + { \ + *((volatile long *) (CFG_LED_BASE)) |= 0x34; \ + } + +#endif + +#endif /* __CONFIG_H */ diff --git a/include/status_led.h b/include/status_led.h index a56883b9a5..db4c60fe3f 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -346,6 +346,15 @@ void status_led_set (int led, int state); #elif defined(CONFIG_NIOS2) /* XXX empty just to avoid the error */ /************************************************************************/ +#elif defined(CONFIG_V38B) + +# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */ +# define STATUS_LED_PERIOD (CFG_HZ / 2) +# define STATUS_LED_STATE STATUS_LED_BLINKING + +# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + #else # error Status LED configuration missing #endif -- cgit v1.2.1 From 5f3249a0a168e446a4cc9669b2bce0bc456f0a09 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 13 Oct 2006 16:47:53 -0500 Subject: Fixed leading whitespace issues. Removed spurious LAWAR thing. Signed-off-by: Jon Loeliger --- include/asm-ppc/mmu.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 5c38ce1e78..914f28b461 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -117,8 +117,8 @@ typedef struct _P601_BAT { */ typedef struct _pte { - unsigned long page_num:20; - unsigned long flags:12; /* Page flags (some unused bits) */ + unsigned long page_num:20; + unsigned long flags:12; /* Page flags (some unused bits) */ } pte; #define PD_SHIFT (10+12) /* Page directory */ @@ -448,7 +448,6 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 -#define LAWAR_TRGT_IF_HT 0x00200000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 -- cgit v1.2.1 From fcfed4f2f234836a0b308fd0a782f4625cd40bad Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 18 Oct 2006 22:44:38 +0200 Subject: Coding Style cleanup. --- include/configs/V38B.h | 112 ++++++++++++++++++++++++------------------------- 1 file changed, 56 insertions(+), 56 deletions(-) (limited to 'include') diff --git a/include/configs/V38B.h b/include/configs/V38B.h index 9b8fc699a9..8eea504742 100644 --- a/include/configs/V38B.h +++ b/include/configs/V38B.h @@ -11,7 +11,7 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. * * You should have received a copy of the GNU General Public License along @@ -35,35 +35,35 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_V38B 1 /* ... on V38B board */ -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ +#define CONFIG_V38B 1 /* ... on V38B board */ +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ -#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ -#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ -#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ +#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ +#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ +#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ #define CONFIG_NETCONSOLE 1 -#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ -#define CFG_XLB_PIPELINING 1 /* gives better performance */ +#define CFG_XLB_PIPELINING 1 /* gives better performance */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /* * Serial console configuration */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } @@ -97,12 +97,12 @@ #define CONFIG_USB_OHCI #define CONFIG_USB_STORAGE -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ /* * Supported commands */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_FAT | \ CFG_CMD_I2C | \ CFG_CMD_IDE | \ @@ -112,7 +112,7 @@ CFG_CMD_IRQ | \ CFG_CMD_JFFS2 | \ CFG_CMD_MII | \ - CFG_CMD_SDRAMi | \ + CFG_CMD_SDRAMi | \ CFG_CMD_DATE | \ CFG_CMD_USB | \ CFG_CMD_FAT) @@ -123,7 +123,7 @@ /* * Boot low with 16 MB Flash */ -# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT 1 # define CFG_LOWBOOT16 1 /* @@ -131,35 +131,35 @@ */ #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ -#define CONFIG_PREBOOT "echo;" \ +#define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "devno=5\0" \ - "hostname=V38B_$(devno)\0" \ - "ipaddr=10.100.99.$(devno)\0" \ - "netmask=255.255.0.0\0" \ - "serverip=10.100.10.90\0" \ - "gatewayip=10.100.254.254\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=mpc5200/uImage\0" \ - "bootcmd=run net_nfs\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;bootm $(kernel_addr) " \ - "$(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs " \ - "addip;bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "devno=5\0" \ + "hostname=V38B_$(devno)\0" \ + "ipaddr=10.100.99.$(devno)\0" \ + "netmask=255.255.0.0\0" \ + "serverip=10.100.10.90\0" \ + "gatewayip=10.100.254.254\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=mpc5200/uImage\0" \ + "bootcmd=run net_nfs\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off panic=1\0" \ + "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip;bootm $(kernel_addr) " \ + "$(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs " \ + "addip;bootm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "" #define CONFIG_BOOTCOMMAND "run net_nfs" @@ -196,13 +196,13 @@ */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 +#define CFG_FLASH_CFI_AMD_RESET 1 #define CFG_FLASH_BASE 0xFF000000 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ /* * Environment settings @@ -243,7 +243,7 @@ */ #define CONFIG_MPC5xxx_FEC 1 #define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 +#define CONFIG_MII 1 /* * GPIO configuration @@ -307,12 +307,12 @@ *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ -#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_RESET /* reset for ide supported */ #define CONFIG_IDE_PREINIT #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ @@ -331,13 +331,13 @@ /* Offset for alternate registers */ #define CFG_ATA_ALT_OFFSET (0x005C) -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 -/* Status LED */ +/* Status LED */ -#define CONFIG_STATUS_LED /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ #define CFG_LED_BASE (0xf0000600 + 0x70) /* Timer 7 GPIO */ -- cgit v1.2.1 From 13a7fcdf37f6ea9429ae04c9df67f893364cfe4b Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 19 Oct 2006 11:33:52 -0500 Subject: * Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock --- include/ft_build.h | 2 ++ include/pci.h | 3 +++ 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/include/ft_build.h b/include/ft_build.h index f5156879de..89c689c084 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -64,6 +64,8 @@ void *ft_get_prop(void *bphp, const char *propname, int *szp); #ifdef CONFIG_OF_BOARD_SETUP void ft_board_setup(void *blob, bd_t *bd); +void ft_cpu_setup(void *blob, bd_t *bd); +void ft_pci_setup(void *blob, bd_t *bd); #endif #endif diff --git a/include/pci.h b/include/pci.h index e0e8783a7a..7c9a0e3441 100644 --- a/include/pci.h +++ b/include/pci.h @@ -501,4 +501,7 @@ extern int pci_hose_config_device(struct pci_controller *hose, extern void pci_mpc824x_init (struct pci_controller *hose); #endif +#ifdef CONFIG_MPC85xx +extern void pci_mpc85xx_init (struct pci_controller *hose); +#endif #endif /* _PCI_H */ -- cgit v1.2.1 From 7237c033b02fe295880435f1eb80819a0c987532 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 19 Oct 2006 11:02:16 -0500 Subject: Moved i2c driver out of cpu/mpc86xx/i2c.c into drivers/fsl_i2c.c in an effort to begin to unify the umpteen FSL I2C drivers that are all otherwise very similar. Signed-off-by: Jon Loeliger --- include/asm-ppc/fsl_i2c.h | 90 +++++++++++++++++++++++++++++++++++++++++++ include/configs/MPC8641HPCN.h | 1 + 2 files changed, 91 insertions(+) create mode 100644 include/asm-ppc/fsl_i2c.h (limited to 'include') diff --git a/include/asm-ppc/fsl_i2c.h b/include/asm-ppc/fsl_i2c.h new file mode 100644 index 0000000000..76b1c4309b --- /dev/null +++ b/include/asm-ppc/fsl_i2c.h @@ -0,0 +1,90 @@ +/* + * Freescale I2C Controller + * + * Copyright 2006 Freescale Semiconductor, Inc. + * + * Based on earlier versions by Gleb Natapov , + * Xianghua Xiao , Eran Liberty (liberty@freescale.com), + * and Jeff Brown. + * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_FSL_I2C_H_ +#define _ASM_FSL_I2C_H_ + +#include + +typedef struct fsl_i2c { + + u8 adr; /* I2C slave address */ + u8 res0[3]; +#define I2C_ADR 0xFE +#define I2C_ADR_SHIFT 1 +#define I2C_ADR_RES ~(I2C_ADR) + + u8 fdr; /* I2C frequency divider register */ + u8 res1[3]; +#define IC2_FDR 0x3F +#define IC2_FDR_SHIFT 0 +#define IC2_FDR_RES ~(IC2_FDR) + + u8 cr; /* I2C control redister */ + u8 res2[3]; +#define I2C_CR_MEN 0x80 +#define I2C_CR_MIEN 0x40 +#define I2C_CR_MSTA 0x20 +#define I2C_CR_MTX 0x10 +#define I2C_CR_TXAK 0x08 +#define I2C_CR_RSTA 0x04 +#define I2C_CR_BCST 0x01 + + u8 sr; /* I2C status register */ + u8 res3[3]; +#define I2C_SR_MCF 0x80 +#define I2C_SR_MAAS 0x40 +#define I2C_SR_MBB 0x20 +#define I2C_SR_MAL 0x10 +#define I2C_SR_BCSTM 0x08 +#define I2C_SR_SRW 0x04 +#define I2C_SR_MIF 0x02 +#define I2C_SR_RXAK 0x01 + + u8 dr; /* I2C data register */ + u8 res4[3]; +#define I2C_DR 0xFF +#define I2C_DR_SHIFT 0 +#define I2C_DR_RES ~(I2C_DR) + + u8 dfsrr; /* I2C digital filter sampling rate register */ + u8 res5[3]; +#define I2C_DFSRR 0x3F +#define I2C_DFSRR_SHIFT 0 +#define I2C_DFSRR_RES ~(I2C_DR) + + /* Fill out the reserved block */ + u8 res6[0xE8]; +} fsl_i2c_t; + + +#define I2C_READ 1 +#define I2C_WRITE 0 + +#endif /* _ASM_I2C_H_ */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 6e883f73f8..81bb7cf134 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -279,6 +279,7 @@ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x3100 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ /* -- cgit v1.2.1 From 43a2b0e76a56995f17e1b7628c192ebafe6051ee Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 20 Oct 2006 14:28:52 +0200 Subject: Add board/cpu specific NAND chip select function to 440 NDFC Based on idea and implementation from Jeff Mann Patch by Stefan Roese, 20 Oct 2006 --- include/configs/sequoia.h | 15 ++++++++------- include/nand.h | 4 ++++ 2 files changed, 12 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index f67fd9163d..3a76315b44 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -134,13 +134,6 @@ #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) #endif -/*----------------------------------------------------------------------- - * NAND FLASH - *----------------------------------------------------------------------*/ -#define CFG_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CFG_NAND_BASE CFG_NAND_ADDR - /* * IPL (Initial Program Loader, integrated inside CPU) * Will load first 4k from NAND (SPL) into cache and execute it from there. @@ -405,6 +398,14 @@ #define CFG_EBC_PB2AP 0x24814580 #define CFG_EBC_PB2CR (CFG_CPLD | 0x38000) +/*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ + /*----------------------------------------------------------------------- * Cache Configuration *----------------------------------------------------------------------*/ diff --git a/include/nand.h b/include/nand.h index 5c7311fd50..23493f7e98 100644 --- a/include/nand.h +++ b/include/nand.h @@ -117,4 +117,8 @@ int nand_lock( nand_info_t *meminfo, int tight ); int nand_unlock( nand_info_t *meminfo, ulong start, ulong length ); int nand_get_lock_status(nand_info_t *meminfo, ulong offset); +#ifdef CFG_NAND_SELECT_DEVICE +void board_nand_select_device(struct nand_chip *nand, int chip); +#endif + #endif -- cgit v1.2.1 From f836e4146088a46d9cd18bbd2f36447ea63e039c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 20 Oct 2006 16:12:14 +0200 Subject: Fix compile problem in include/configs/ep82xxm.h (must have never been tested before!) --- include/configs/ep82xxm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h index 5d7bed611a..372b10c623 100644 --- a/include/configs/ep82xxm.h +++ b/include/configs/ep82xxm.h @@ -28,7 +28,7 @@ #define CONFIG_MPC8260 #define CPU_ID_STR "MPC8270" -#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board /* +#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */ /* 256MB SDRAM / 64MB FLASH */ #undef DEBUG -- cgit v1.2.1 From 2047672684cf85cb6f96a1fbc993180aaaf19a99 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 20 Oct 2006 15:50:15 -0500 Subject: Converted all 85xx boards to use a common FSL I2C driver. Introduced COFIG_FSL_I2C to select the common FSL I2C driver. And removed hard i2c path from a few u-boot.lds scipts too. Minor whitespace cleanups along the way. Signed-off-by: Jon Loeliger --- include/configs/MPC8540ADS.h | 8 ++++++-- include/configs/MPC8540EVAL.h | 8 ++++++-- include/configs/MPC8541CDS.h | 8 ++++++-- include/configs/MPC8548CDS.h | 8 ++++++-- include/configs/MPC8555CDS.h | 8 ++++++-- include/configs/MPC8560ADS.h | 8 ++++++-- include/configs/MPC8641HPCN.h | 5 +++-- include/configs/PM854.h | 8 ++++++-- include/configs/PM856.h | 8 ++++++-- include/configs/SBC8540.h | 8 ++++++-- include/configs/TQM85xx.h | 7 ++++++- include/configs/sbc8560.h | 8 ++++++-- include/configs/stxgp3.h | 8 ++++++-- 13 files changed, 75 insertions(+), 25 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 31ffbaf15b..74a84f4e86 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -312,12 +312,16 @@ #define CFG_64BIT_VSPRINTF 1 #define CFG_64BIT_STRTOUL 1 -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* RapidIO MMU */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 1af923103f..418a3a38e6 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -179,12 +179,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* General PCI */ #define CFG_PCI_MEM_BASE 0x80000000 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 2b87f1bd6a..db389cfe67 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -320,13 +320,17 @@ extern unsigned long get_clock_freq(void); #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * General PCI diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 03ab976d11..be8f93ffb8 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -326,13 +326,17 @@ extern unsigned long get_clock_freq(void); #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * General PCI diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 771a9d3b95..4c8b4e73f3 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -320,13 +320,17 @@ extern unsigned long get_clock_freq(void); #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600" -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * General PCI diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 1c684f2fd1..835bf5cb64 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -302,12 +302,16 @@ #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500" -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* RapidIO MMU */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 81bb7cf134..246ac7f316 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -275,12 +275,13 @@ /* * I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_OFFSET 0x3100 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3100 /* * RapidIO MMU diff --git a/include/configs/PM854.h b/include/configs/PM854.h index da01186771..4fb54402b1 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -193,12 +193,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * EEPROM configuration diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 4d834878ee..87ab934873 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -190,12 +190,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * EEPROM configuration diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 0451b20819..f8e3397a3f 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -214,12 +214,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 #define CFG_PCI_MEM_BASE 0xC0000000 #define CFG_PCI_MEM_PHYS 0xC0000000 diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index bc3b9aa1d0..cce4624904 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -192,12 +192,17 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* I2C RTC */ #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 5a434dc767..6e4fdb2498 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -197,12 +197,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 #define CFG_PCI_MEM_BASE 0xC0000000 #define CFG_PCI_MEM_PHYS 0xC0000000 diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index e218597db0..625cf20144 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -172,8 +172,11 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F @@ -183,6 +186,7 @@ /* I did the 'if 0' so we could keep the syntax above if ever needed. */ #undef CFG_I2C_NOPROBES #endif +#define CFG_I2C_OFFSET 0x3000 /* RapdIO Map configuration, mapped 1:1. */ -- cgit v1.2.1 From 3dfa9cfdcee78b30da3432318b32821ffabe974b Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 20 Oct 2006 17:16:35 -0500 Subject: Use generic I2C register block on 85xx and 86xx. Replace private IMMAP I2C structures with generic reg block and allow 86xx to have multiple I2C device busses. Signed-off-by: Jon Loeliger --- include/asm-ppc/immap_85xx.h | 36 +++++--------------------------- include/asm-ppc/immap_86xx.h | 49 ++++---------------------------------------- 2 files changed, 9 insertions(+), 76 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 7a4345a740..5377c2eb5b 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -9,6 +9,9 @@ #ifndef __IMMAP_85xx__ #define __IMMAP_85xx__ +#include +#include + /* * Local-Access Registers and ECM Registers(0x0000-0x2000) */ @@ -129,37 +132,8 @@ typedef struct ccsr_ddr { * I2C Registers(0x3000-0x4000) */ typedef struct ccsr_i2c { - u_char i2cadr; /* 0x3000 - I2C Address Register */ -#define MPC85xx_I2CADR_MASK 0xFE - char res1[3]; - u_char i2cfdr; /* 0x3004 - I2C Frequency Divider Register */ -#define MPC85xx_I2CFDR_MASK 0x3F - char res2[3]; - u_char i2ccr; /* 0x3008 - I2C Control Register */ -#define MPC85xx_I2CCR_MEN 0x80 -#define MPC85xx_I2CCR_MIEN 0x40 -#define MPC85xx_I2CCR_MSTA 0x20 -#define MPC85xx_I2CCR_MTX 0x10 -#define MPC85xx_I2CCR_TXAK 0x08 -#define MPC85xx_I2CCR_RSTA 0x04 -#define MPC85xx_I2CCR_BCST 0x01 - char res3[3]; - u_char i2csr; /* 0x300c - I2C Status Register */ -#define MPC85xx_I2CSR_MCF 0x80 -#define MPC85xx_I2CSR_MAAS 0x40 -#define MPC85xx_I2CSR_MBB 0x20 -#define MPC85xx_I2CSR_MAL 0x10 -#define MPC85xx_I2CSR_BCSTM 0x08 -#define MPC85xx_I2CSR_SRW 0x04 -#define MPC85xx_I2CSR_MIF 0x02 -#define MPC85xx_I2CSR_RXAK 0x01 - char res4[3]; - u_char i2cdr; /* 0x3010 - I2C Data Register */ -#define MPC85xx_I2CDR_DATA 0xFF - char res5[3]; - u_char i2cdfsrr; /* 0x3014 - I2C Digital Filtering Sampling Rate Register */ -#define MPC85xx_I2CDFSRR 0x3F - char res6[4075]; + struct fsl_i2c i2c[1]; + u8 res[4096 - 1 * sizeof(struct fsl_i2c)]; } ccsr_i2c_t; #if defined(CONFIG_MPC8540) \ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 685fcafdf2..a5552c48ee 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -10,6 +10,8 @@ #ifndef __IMMAP_86xx__ #define __IMMAP_86xx__ +#include +#include /* Local-Access Registers and MCM Registers(0x0000-0x2000) */ typedef struct ccsr_local_mcm { @@ -155,52 +157,9 @@ typedef struct ccsr_ddr { /* Daul I2C Registers(0x3000-0x4000) */ - typedef struct ccsr_i2c { - u_char i2cadr1; /* 0x3000 - I2C 1 Address Register */ -#define MPC86xx_I2CADR_MASK 0xFE - char res1[3]; - u_char i2cfdr1; /* 0x3004 - I2C 1 Frequency Divider Register */ -#define MPC86xx_I2CFDR_MASK 0x3F - char res2[3]; - u_char i2ccr1; /* 0x3008 - I2C 1 Control Register */ -#define MPC86xx_I2CCR_MEN 0x80 -#define MPC86xx_I2CCR_MIEN 0x40 -#define MPC86xx_I2CCR_MSTA 0x20 -#define MPC86xx_I2CCR_MTX 0x10 -#define MPC86xx_I2CCR_TXAK 0x08 -#define MPC86xx_I2CCR_RSTA 0x04 -#define MPC86xx_I2CCR_BCST 0x01 - char res3[3]; - u_char i2csr1; /* 0x300c - I2C 1 Status Register */ -#define MPC86xx_I2CSR_MCF 0x80 -#define MPC86xx_I2CSR_MAAS 0x40 -#define MPC86xx_I2CSR_MBB 0x20 -#define MPC86xx_I2CSR_MAL 0x10 -#define MPC86xx_I2CSR_BCSTM 0x08 -#define MPC86xx_I2CSR_SRW 0x04 -#define MPC86xx_I2CSR_MIF 0x02 -#define MPC86xx_I2CSR_RXAK 0x01 - char res4[3]; - u_char i2cdr1; /* 0x3010 - I2C 1 Data Register */ -#define MPC86xx_I2CDR_DATA 0xFF - char res5[3]; - u_char i2cdfsrr1; /* 0x3014 - I2C 1 Digital Filtering Sampling Rate Register */ -#define MPC86xx_I2CDFSRR 0x3F - char res6[235]; - - u_char i2cadr2; /* 0x3100 - I2C 2 Address Register */ - char res7[3]; - u_char i2cfdr2; /* 0x3104 - I2C 2 Frequency Divider Register */ - char res8[3]; - u_char i2ccr2; /* 0x3108 - I2C 2 Control Register */ - char res9[3]; - u_char i2csr2; /* 0x310c - I2C 2 Status Register */ - char res10[3]; - u_char i2cdr2; /* 0x3110 - I2C 2 Data Register */ - char res11[3]; - u_char i2cdfsrr2; /* 0x3114 - I2C 2 Digital Filtering Sampling Rate Register */ - char res12[3819]; + struct fsl_i2c i2c[2]; + u8 res[4096 - 2 * sizeof(struct fsl_i2c)]; } ccsr_i2c_t; /* DUART Registers(0x4000-0x5000) */ -- cgit v1.2.1 From 7b64fef33c66be648826c0ff9758298ef13d0604 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 24 Oct 2006 14:21:16 +0200 Subject: Add AVR32 architecture support Patch by Haavard Skinnemoen, 6 Sep 2006 16:23:02 +0200 This patch adds common infrastructure code for the Atmel AVR32 architecture. See doc/README.AVR32 for details. Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/addrspace.h | 46 +++++++ include/asm-avr32/bitops.h | 25 ++++ include/asm-avr32/byteorder.h | 37 ++++++ include/asm-avr32/cacheflush.h | 83 ++++++++++++ include/asm-avr32/div64.h | 39 ++++++ include/asm-avr32/dma-mapping.h | 64 +++++++++ include/asm-avr32/errno.h | 132 +++++++++++++++++++ include/asm-avr32/global_data.h | 59 +++++++++ include/asm-avr32/initcalls.h | 33 +++++ include/asm-avr32/io.h | 92 +++++++++++++ include/asm-avr32/posix_types.h | 144 +++++++++++++++++++++ include/asm-avr32/processor.h | 97 ++++++++++++++ include/asm-avr32/ptrace.h | 148 +++++++++++++++++++++ include/asm-avr32/sdram.h | 33 +++++ include/asm-avr32/sections.h | 39 ++++++ include/asm-avr32/setup.h | 142 ++++++++++++++++++++ include/asm-avr32/string.h | 28 ++++ include/asm-avr32/sysreg.h | 279 ++++++++++++++++++++++++++++++++++++++++ include/asm-avr32/types.h | 84 ++++++++++++ include/asm-avr32/u-boot.h | 56 ++++++++ 20 files changed, 1660 insertions(+) create mode 100644 include/asm-avr32/addrspace.h create mode 100644 include/asm-avr32/bitops.h create mode 100644 include/asm-avr32/byteorder.h create mode 100644 include/asm-avr32/cacheflush.h create mode 100644 include/asm-avr32/div64.h create mode 100644 include/asm-avr32/dma-mapping.h create mode 100644 include/asm-avr32/errno.h create mode 100644 include/asm-avr32/global_data.h create mode 100644 include/asm-avr32/initcalls.h create mode 100644 include/asm-avr32/io.h create mode 100644 include/asm-avr32/posix_types.h create mode 100644 include/asm-avr32/processor.h create mode 100644 include/asm-avr32/ptrace.h create mode 100644 include/asm-avr32/sdram.h create mode 100644 include/asm-avr32/sections.h create mode 100644 include/asm-avr32/setup.h create mode 100644 include/asm-avr32/string.h create mode 100644 include/asm-avr32/sysreg.h create mode 100644 include/asm-avr32/types.h create mode 100644 include/asm-avr32/u-boot.h (limited to 'include') diff --git a/include/asm-avr32/addrspace.h b/include/asm-avr32/addrspace.h new file mode 100644 index 0000000000..b2ba1ee2fe --- /dev/null +++ b/include/asm-avr32/addrspace.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ADDRSPACE_H +#define __ASM_AVR32_ADDRSPACE_H + +/* Memory segments when segmentation is enabled */ +#define P0SEG 0x00000000 +#define P1SEG 0x80000000 +#define P2SEG 0xa0000000 +#define P3SEG 0xc0000000 +#define P4SEG 0xe0000000 + +/* Returns the privileged segment base of a given address */ +#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) + +/* Returns the physical address of a PnSEG (n=1,2) address */ +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) + +/* + * Map an address to a certain privileged segment + */ +#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) +#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) +#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) +#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) + +#endif /* __ASM_AVR32_ADDRSPACE_H */ diff --git a/include/asm-avr32/bitops.h b/include/asm-avr32/bitops.h new file mode 100644 index 0000000000..f15fd4647e --- /dev/null +++ b/include/asm-avr32/bitops.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_BITOPS_H +#define __ASM_AVR32_BITOPS_H + +#endif /* __ASM_AVR32_BITOPS_H */ diff --git a/include/asm-avr32/byteorder.h b/include/asm-avr32/byteorder.h new file mode 100644 index 0000000000..2fe867e978 --- /dev/null +++ b/include/asm-avr32/byteorder.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_BYTEORDER_H +#define __ASM_AVR32_BYTEORDER_H + +#include + +#define __arch__swab32(x) __builtin_bswap_32(x) +#define __arch__swab16(x) __builtin_bswap_16(x) + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#include + +#endif /* __ASM_AVR32_BYTEORDER_H */ diff --git a/include/asm-avr32/cacheflush.h b/include/asm-avr32/cacheflush.h new file mode 100644 index 0000000000..929f68e1a0 --- /dev/null +++ b/include/asm-avr32/cacheflush.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_CACHEFLUSH_H +#define __ASM_AVR32_CACHEFLUSH_H + +/* + * Invalidate any cacheline containing virtual address vaddr without + * writing anything back to memory. + * + * Note that this function may corrupt unrelated data structures when + * applied on buffers that are not cacheline aligned in both ends. + */ +static inline void dcache_invalidate_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory"); +} + +/* + * Make sure any cacheline containing virtual address vaddr is written + * to memory. + */ +static inline void dcache_clean_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory"); +} + +/* + * Make sure any cacheline containing virtual address vaddr is written + * to memory and then invalidate it. + */ +static inline void dcache_flush_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory"); +} + +/* + * Invalidate any instruction cacheline containing virtual address + * vaddr. + */ +static inline void icache_invalidate_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory"); +} + +/* + * Applies the above functions on all lines that are touched by the + * specified virtual address range. + */ +void dcache_invalidate_range(volatile void *start, size_t len); +void dcache_clean_range(volatile void *start, size_t len); +void dcache_flush_range(volatile void *start, size_t len); +void icache_invalidate_range(volatile void *start, size_t len); + +static inline void dcache_flush_unlocked(void) +{ + asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory"); +} + +/* + * Make sure any pending writes are completed before continuing. + */ +#define sync_write_buffer() asm volatile("sync 0" : : : "memory") + +#endif /* __ASM_AVR32_CACHEFLUSH_H */ diff --git a/include/asm-avr32/div64.h b/include/asm-avr32/div64.h new file mode 100644 index 0000000000..2e0ba8389e --- /dev/null +++ b/include/asm-avr32/div64.h @@ -0,0 +1,39 @@ +#ifndef _ASM_GENERIC_DIV64_H +#define _ASM_GENERIC_DIV64_H +/* + * Copyright (C) 2003 Bernardo Innocenti + * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h + * + * The semantics of do_div() are: + * + * uint32_t do_div(uint64_t *n, uint32_t base) + * { + * uint32_t remainder = *n % base; + * *n = *n / base; + * return remainder; + * } + * + * NOTE: macro parameter n is evaluated multiple times, + * beware of side effects! + */ + +#include + +extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor); + +/* The unnecessary pointer compare is there + * to check for type safety (n must be 64bit) + */ +# define do_div(n,base) ({ \ + uint32_t __base = (base); \ + uint32_t __rem; \ + (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \ + if (((n) >> 32) == 0) { \ + __rem = (uint32_t)(n) % __base; \ + (n) = (uint32_t)(n) / __base; \ + } else \ + __rem = __div64_32(&(n), __base); \ + __rem; \ + }) + +#endif /* _ASM_GENERIC_DIV64_H */ diff --git a/include/asm-avr32/dma-mapping.h b/include/asm-avr32/dma-mapping.h new file mode 100644 index 0000000000..3b46fa3e62 --- /dev/null +++ b/include/asm-avr32/dma-mapping.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_DMA_MAPPING_H +#define __ASM_AVR32_DMA_MAPPING_H + +#include +#include + +enum dma_data_direction { + DMA_BIDIRECTIONAL = 0, + DMA_TO_DEVICE = 1, + DMA_FROM_DEVICE = 2, +}; +extern void *dma_alloc_coherent(size_t len, unsigned long *handle); + +static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, + enum dma_data_direction dir) +{ + extern void __bad_dma_data_direction(void); + + switch (dir) { + case DMA_BIDIRECTIONAL: + dcache_flush_range(vaddr, len); + break; + case DMA_TO_DEVICE: + dcache_clean_range(vaddr, len); + break; + case DMA_FROM_DEVICE: + dcache_invalidate_range(vaddr, len); + break; + default: + /* This will cause a linker error */ + __bad_dma_data_direction(); + } + + return virt_to_phys(vaddr); +} + +static inline void dma_unmap_single(volatile void *vaddr, size_t len, + unsigned long paddr) +{ + +} + +#endif /* __ASM_AVR32_DMA_MAPPING_H */ diff --git a/include/asm-avr32/errno.h b/include/asm-avr32/errno.h new file mode 100644 index 0000000000..ea3506ff38 --- /dev/null +++ b/include/asm-avr32/errno.h @@ -0,0 +1,132 @@ +#ifndef _ASM_AVR32_ERRNO_H +#define _ASM_AVR32_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +#endif /* _ASM_AVR32_ERRNO_H */ diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h new file mode 100644 index 0000000000..01d836c639 --- /dev/null +++ b/include/asm-avr32/global_data.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_GLOBAL_DATA_H__ +#define __ASM_GLOBAL_DATA_H__ + +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + const struct device *console_uart; + const struct device *sm; + unsigned long baudrate; + unsigned long sdram_size; + unsigned long have_console; /* serial_init() was called */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of env struct */ + unsigned long env_valid; /* Checksum of env valid? */ + unsigned long cpu_hz; /* cpu core clock frequency */ + void **jt; /* jump table */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5") + +#endif /* __ASM_GLOBAL_DATA_H__ */ diff --git a/include/asm-avr32/initcalls.h b/include/asm-avr32/initcalls.h new file mode 100644 index 0000000000..7ba25cde53 --- /dev/null +++ b/include/asm-avr32/initcalls.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2005, 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_INITCALLS_H__ +#define __ASM_AVR32_INITCALLS_H__ + +#include + +extern int cpu_init(void); +extern int timer_init(void); +extern void board_init_memories(void); +extern void board_init_pio(void); +extern void board_init_info(void); + +#endif /* __ASM_AVR32_INITCALLS_H__ */ diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h new file mode 100644 index 0000000000..e86c456ae1 --- /dev/null +++ b/include/asm-avr32/io.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_IO_H +#define __ASM_AVR32_IO_H + +#ifdef __KERNEL__ + +/* + * Generic IO read/write. These perform native-endian accesses. Note + * that some architectures will want to re-define __raw_{read,write}w. + */ +extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); +extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); +extern void __raw_writesl(unsigned int addr, const void *data, int longlen); + +extern void __raw_readsb(unsigned int addr, void *data, int bytelen); +extern void __raw_readsw(unsigned int addr, void *data, int wordlen); +extern void __raw_readsl(unsigned int addr, void *data, int longlen); + +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + +/* As long as I/O is only performed in P4 (or possibly P3), we're safe */ +#define writeb(v,a) __raw_writeb(v,a) +#define writew(v,a) __raw_writew(v,a) +#define writel(v,a) __raw_writel(v,a) + +#define readb(a) __raw_readb(a) +#define readw(a) __raw_readw(a) +#define readl(a) __raw_readl(a) + +/* + * Bad read/write accesses... + */ +extern void __readwrite_bug(const char *fn); + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * All I/O is memory mapped, so these macros doesn't make very much sense + */ +#define outb(v,p) __raw_writeb(v, p) +#define outw(v,p) __raw_writew(cpu_to_le16(v),p) +#define outl(v,p) __raw_writel(cpu_to_le32(v),p) + +#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; }) +#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; }) +#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; }) + +#include + +/* virt_to_phys will only work when address is in P1 or P2 */ +static __inline__ unsigned long virt_to_phys(volatile void *address) +{ + return PHYSADDR(address); +} + +static __inline__ void * phys_to_virt(unsigned long address) +{ + return (void *)P1SEGADDR(address); +} + +#define cached(addr) ((void *)P1SEGADDR(addr)) +#define uncached(addr) ((void *)P2SEGADDR(addr)) + +#endif /* __KERNEL__ */ + +#endif /* __ASM_AVR32_IO_H */ diff --git a/include/asm-avr32/posix_types.h b/include/asm-avr32/posix_types.h new file mode 100644 index 0000000000..edf1bc14d2 --- /dev/null +++ b/include/asm-avr32/posix_types.h @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_POSIX_TYPES_H +#define __ASM_AVR32_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned long __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned int __kernel_uid_t; +typedef unsigned int __kernel_gid_t; +typedef unsigned long __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_timer_t; +typedef int __kernel_clockid_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; +typedef unsigned short __kernel_old_dev_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) + +#undef __FD_SET +static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); +} + +#undef __FD_CLR +static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); +} + + +#undef __FD_ISSET +static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; +} + +/* + * This will unroll the loop for the normal constant case (8 ints, + * for a 256-bit fd_set) + */ +#undef __FD_ZERO +static __inline__ void __FD_ZERO(__kernel_fd_set *__p) +{ + unsigned long *__tmp = __p->fds_bits; + int __i; + + if (__builtin_constant_p(__FDSET_LONGS)) { + switch (__FDSET_LONGS) { + case 16: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + __tmp[ 8] = 0; __tmp[ 9] = 0; + __tmp[10] = 0; __tmp[11] = 0; + __tmp[12] = 0; __tmp[13] = 0; + __tmp[14] = 0; __tmp[15] = 0; + return; + + case 8: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + return; + + case 4: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + return; + } + } + __i = __FDSET_LONGS; + while (__i) { + __i--; + *__tmp = 0; + __tmp++; + } +} + +#endif /* defined(__KERNEL__) */ + +#endif /* __ASM_AVR32_POSIX_TYPES_H */ diff --git a/include/asm-avr32/processor.h b/include/asm-avr32/processor.h new file mode 100644 index 0000000000..cc59dfad56 --- /dev/null +++ b/include/asm-avr32/processor.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_PROCESSOR_H +#define __ASM_AVR32_PROCESSOR_H + +#ifndef __ASSEMBLY__ + +#define current_text_addr() ({ void *pc; __asm__("mov %0,pc" : "=r"(pc)); pc; }) + +struct avr32_cpuinfo { + unsigned long loops_per_jiffy; +}; + +extern struct avr32_cpuinfo boot_cpu_data; + +#ifdef CONFIG_SMP +extern struct avr32_cpuinfo cpu_data[]; +#define current_cpu_data cpu_data[smp_processor_id()] +#else +#define cpu_data (&boot_cpu_data) +#define current_cpu_data boot_cpu_data +#endif + +/* TODO: Make configurable (2GB will serve as a reasonable default) */ +#define TASK_SIZE 0x80000000 + +/* This decides where the kernel will search for a free chunk of vm + * space during mmap's + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) + +#define cpu_relax() barrier() +#define cpu_sync_pipeline() asm volatile("sub pc, -2" : : : "memory") + +/* This struct contains the CPU context as stored by switch_to() */ +struct thread_struct { + unsigned long pc; + unsigned long ksp; /* Kernel stack pointer */ + unsigned long r7; + unsigned long r6; + unsigned long r5; + unsigned long r4; + unsigned long r3; + unsigned long r2; + unsigned long r1; + unsigned long r0; +}; + +#define INIT_THREAD { \ + .ksp = sizeof(init_stack) + (long)&init_stack, \ +} + +/* + * Do necessary setup to start up a newly executed thread. + */ +#define start_thread(regs, new_pc, new_sp) \ + set_fs(USER_DS); \ + regs->sr = 0; /* User mode. */ \ + regs->gr[REG_PC] = new_pc; \ + regs->gr[REG_SP] = new_sp + +struct task_struct; + +/* Free all resources held by a thread */ +extern void release_thread(struct task_struct *); + +/* Create a kernel thread without removing it from tasklists */ +extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); + +/* Prepare to copy thread state - unlazy all lazy status */ +#define prepare_to_copy(tsk) do { } while(0) + +/* Return saved PC of a blocked thread */ +#define thread_saved_pc(tsk) (tsk->thread.pc) + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_AVR32_PROCESSOR_H */ diff --git a/include/asm-avr32/ptrace.h b/include/asm-avr32/ptrace.h new file mode 100644 index 0000000000..c770ba02c3 --- /dev/null +++ b/include/asm-avr32/ptrace.h @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_PTRACE_H +#define __ASM_AVR32_PTRACE_H + +/* + * Status Register bits + */ +#define SR_H 0x40000000 +#define SR_R 0x20000000 +#define SR_J 0x10000000 +#define SR_DM 0x08000000 +#define SR_D 0x04000000 +#define MODE_NMI 0x01c00000 +#define MODE_EXCEPTION 0x01800000 +#define MODE_INT3 0x01400000 +#define MODE_INT2 0x01000000 +#define MODE_INT1 0x00c00000 +#define MODE_INT0 0x00800000 +#define MODE_SUPERVISOR 0x00400000 +#define MODE_USER 0x00000000 +#define MODE_MASK 0x01c00000 +#define SR_EM 0x00200000 +#define SR_I3M 0x00100000 +#define SR_I2M 0x00080000 +#define SR_I1M 0x00040000 +#define SR_I0M 0x00020000 +#define SR_GM 0x00010000 + +#define MODE_SHIFT 22 +#define SR_EM_BIT 21 +#define SR_I3M_BIT 20 +#define SR_I2M_BIT 19 +#define SR_I1M_BIT 18 +#define SR_I0M_BIT 17 +#define SR_GM_BIT 16 + +/* The user-visible part */ +#define SR_Q 0x00000010 +#define SR_V 0x00000008 +#define SR_N 0x00000004 +#define SR_Z 0x00000002 +#define SR_C 0x00000001 + +/* + * The order is defined by the stdsp instruction. r0 is stored first, so it + * gets the highest address. + * + * Registers 0-12 are general-purpose registers (r12 is normally used for + * the function return value). + * Register 13 is the stack pointer + * Register 14 is the link register + * Register 15 is the program counter + */ +#define FRAME_SIZE_FULL 72 +#define REG_R12_ORIG 68 +#define REG_R0 64 +#define REG_R1 60 +#define REG_R2 56 +#define REG_R3 52 +#define REG_R4 48 +#define REG_R5 44 +#define REG_R6 40 +#define REG_R7 36 +#define REG_R8 32 +#define REG_R9 28 +#define REG_R10 34 +#define REG_R11 20 +#define REG_R12 16 +#define REG_SP 12 +#define REG_LR 8 + +#define FRAME_SIZE_MIN 8 +#define REG_PC 4 +#define REG_SR 0 + +#ifndef __ASSEMBLY__ +struct pt_regs { + /* These are always saved */ + unsigned long sr; + unsigned long pc; + + /* These are sometimes saved */ + unsigned long lr; + unsigned long sp; + unsigned long r12; + unsigned long r11; + unsigned long r10; + unsigned long r9; + unsigned long r8; + unsigned long r7; + unsigned long r6; + unsigned long r5; + unsigned long r4; + unsigned long r3; + unsigned long r2; + unsigned long r1; + unsigned long r0; + + /* Only saved on system call */ + unsigned long r12_orig; +}; + +#ifdef __KERNEL__ +# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER) +# define instruction_pointer(regs) ((regs)->pc) +extern void show_regs (struct pt_regs *); + +static __inline__ int valid_user_regs(struct pt_regs *regs) +{ + /* + * Some of the Java bits might be acceptable if/when we + * implement some support for that stuff... + */ + if ((regs->sr & 0xffff0000) == 0) + return 1; + + /* + * Force status register flags to be sane and report this + * illegal behaviour... + */ + regs->sr &= 0x0000ffff; + return 0; +} +#endif + +#endif /* ! __ASSEMBLY__ */ + +#endif /* __ASM_AVR32_PTRACE_H */ diff --git a/include/asm-avr32/sdram.h b/include/asm-avr32/sdram.h new file mode 100644 index 0000000000..5057eefa8a --- /dev/null +++ b/include/asm-avr32/sdram.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_SDRAM_H +#define __ASM_AVR32_SDRAM_H + +struct sdram_info { + unsigned long phys_addr; + unsigned int row_bits, col_bits, bank_bits; + unsigned int cas, twr, trc, trp, trcd, tras, txsr; +}; + +extern unsigned long sdram_init(const struct sdram_info *info); + +#endif /* __ASM_AVR32_SDRAM_H */ diff --git a/include/asm-avr32/sections.h b/include/asm-avr32/sections.h new file mode 100644 index 0000000000..75373abde7 --- /dev/null +++ b/include/asm-avr32/sections.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_SECTIONS_H +#define __ASM_AVR32_SECTIONS_H + +/* References to section boundaries */ + +extern char _text[], _etext[]; +extern char __flashprog_start[], __flashprog_end[]; +extern char _data[], __data_lma[], _edata[], __edata_lma[]; +extern char __got_start[], __got_lma[], __got_end[]; +extern char _end[]; + +/* + * Everything in .flashprog will be locked in the icache so it doesn't + * get disturbed when executing flash commands. + */ +#define __flashprog __attribute__((section(".flashprog"), __noinline__)) + +#endif /* __ASM_AVR32_SECTIONS_H */ diff --git a/include/asm-avr32/setup.h b/include/asm-avr32/setup.h new file mode 100644 index 0000000000..e6ef8d6b50 --- /dev/null +++ b/include/asm-avr32/setup.h @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * Based on linux/include/asm-arm/setup.h + * Copyright (C) 1997-1999 Russel King + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_SETUP_H__ +#define __ASM_AVR32_SETUP_H__ + +#define COMMAND_LINE_SIZE 256 + +/* Magic number indicating that a tag table is present */ +#define ATAG_MAGIC 0xa2a25441 + +#ifndef __ASSEMBLY__ + +/* + * Generic memory range, used by several tags. + * + * addr is always physical. + * size is measured in bytes. + * next is for use by the OS, e.g. for grouping regions into + * linked lists. + */ +struct tag_mem_range { + u32 addr; + u32 size; + struct tag_mem_range * next; +}; + +/* The list ends with an ATAG_NONE node. */ +#define ATAG_NONE 0x00000000 + +struct tag_header { + u32 size; + u32 tag; +}; + +/* The list must start with an ATAG_CORE node */ +#define ATAG_CORE 0x54410001 + +struct tag_core { + u32 flags; + u32 pagesize; + u32 rootdev; +}; + +/* it is allowed to have multiple ATAG_MEM nodes */ +#define ATAG_MEM 0x54410002 +/* ATAG_MEM uses tag_mem_range */ + +/* command line: \0 terminated string */ +#define ATAG_CMDLINE 0x54410003 + +struct tag_cmdline { + char cmdline[1]; /* this is the minimum size */ +}; + +/* Ramdisk image (may be compressed) */ +#define ATAG_RDIMG 0x54410004 +/* ATAG_RDIMG uses tag_mem_range */ + +/* Information about various clocks present in the system */ +#define ATAG_CLOCK 0x54410005 + +struct tag_clock { + u32 clock_id; /* Which clock are we talking about? */ + u32 clock_flags; /* Special features */ + u64 clock_hz; /* Clock speed in Hz */ +}; + +/* The clock types we know about */ +#define ACLOCK_BOOTCPU 0 /* The CPU we're booting from */ +#define ACLOCK_HSB 1 /* Deprecated */ + +/* Memory reserved for the system (e.g. the bootloader) */ +#define ATAG_RSVD_MEM 0x54410006 +/* ATAG_RSVD_MEM uses tag_mem_range */ + +/* Ethernet information */ + +#define ATAG_ETHERNET 0x54410007 + +struct tag_ethernet { + u8 mac_index; + u8 mii_phy_addr; + u8 hw_address[6]; +}; + +#define AETH_INVALID_PHY 0xff + +struct tag { + struct tag_header hdr; + union { + struct tag_core core; + struct tag_mem_range mem_range; + struct tag_cmdline cmdline; + struct tag_clock clock; + struct tag_ethernet ethernet; + } u; +}; + +struct tagtable { + u32 tag; + int (*parse)(struct tag *); +}; + +#define __tag __attribute_used__ __attribute__((__section__(".taglist"))) +#define __tagtable(tag, fn) \ + static struct tagtable __tagtable_##fn __tag = { tag, fn } + +#define tag_member_present(tag,member) \ + ((unsigned long)(&((struct tag *)0L)->member + 1) \ + <= (tag)->hdr.size * 4) + +#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) +#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) + +#define for_each_tag(t,base) \ + for (t = base; t->hdr.size; t = tag_next(t)) + +#endif /* !__ASSEMBLY__ */ + +#endif /* __ASM_AVR32_SETUP_H__ */ diff --git a/include/asm-avr32/string.h b/include/asm-avr32/string.h new file mode 100644 index 0000000000..8b05d1a031 --- /dev/null +++ b/include/asm-avr32/string.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_STRING_H +#define __ASM_AVR32_STRING_H + +#define __HAVE_ARCH_MEMSET +extern void *memset(void *s, int c, size_t n); + +#endif /* __ASM_AVR32_STRING_H */ diff --git a/include/asm-avr32/sysreg.h b/include/asm-avr32/sysreg.h new file mode 100644 index 0000000000..72ad49e5e2 --- /dev/null +++ b/include/asm-avr32/sysreg.h @@ -0,0 +1,279 @@ +/* + * System registers for AVR32 + */ +#ifndef __ASM_AVR32_SYSREG_H__ +#define __ASM_AVR32_SYSREG_H__ + +/* system register offsets */ +#define SYSREG_SR 0x0000 +#define SYSREG_EVBA 0x0004 +#define SYSREG_ACBA 0x0008 +#define SYSREG_CPUCR 0x000c +#define SYSREG_ECR 0x0010 +#define SYSREG_RSR_SUP 0x0014 +#define SYSREG_RSR_INT0 0x0018 +#define SYSREG_RSR_INT1 0x001c +#define SYSREG_RSR_INT2 0x0020 +#define SYSREG_RSR_INT3 0x0024 +#define SYSREG_RSR_EX 0x0028 +#define SYSREG_RSR_NMI 0x002c +#define SYSREG_RSR_DBG 0x0030 +#define SYSREG_RAR_SUP 0x0034 +#define SYSREG_RAR_INT0 0x0038 +#define SYSREG_RAR_INT1 0x003c +#define SYSREG_RAR_INT2 0x0040 +#define SYSREG_RAR_INT3 0x0044 +#define SYSREG_RAR_EX 0x0048 +#define SYSREG_RAR_NMI 0x004c +#define SYSREG_RAR_DBG 0x0050 +#define SYSREG_JECR 0x0054 +#define SYSREG_JOSP 0x0058 +#define SYSREG_JAVA_LV0 0x005c +#define SYSREG_JAVA_LV1 0x0060 +#define SYSREG_JAVA_LV2 0x0064 +#define SYSREG_JAVA_LV3 0x0068 +#define SYSREG_JAVA_LV4 0x006c +#define SYSREG_JAVA_LV5 0x0070 +#define SYSREG_JAVA_LV6 0x0074 +#define SYSREG_JAVA_LV7 0x0078 +#define SYSREG_JTBA 0x007c +#define SYSREG_JBCR 0x0080 +#define SYSREG_CONFIG0 0x0100 +#define SYSREG_CONFIG1 0x0104 +#define SYSREG_COUNT 0x0108 +#define SYSREG_COMPARE 0x010c +#define SYSREG_TLBEHI 0x0110 +#define SYSREG_TLBELO 0x0114 +#define SYSREG_PTBR 0x0118 +#define SYSREG_TLBEAR 0x011c +#define SYSREG_MMUCR 0x0120 +#define SYSREG_TLBARLO 0x0124 +#define SYSREG_TLBARHI 0x0128 +#define SYSREG_PCCNT 0x012c +#define SYSREG_PCNT0 0x0130 +#define SYSREG_PCNT1 0x0134 +#define SYSREG_PCCR 0x0138 +#define SYSREG_BEAR 0x013c +#define SYSREG_SABAL 0x0300 +#define SYSREG_SABAH 0x0304 +#define SYSREG_SABD 0x0308 + +/* Bitfields in SR */ +#define SYSREG_SR_C_OFFSET 0 +#define SYSREG_SR_C_SIZE 1 +#define SYSREG_Z_OFFSET 1 +#define SYSREG_Z_SIZE 1 +#define SYSREG_SR_N_OFFSET 2 +#define SYSREG_SR_N_SIZE 1 +#define SYSREG_SR_V_OFFSET 3 +#define SYSREG_SR_V_SIZE 1 +#define SYSREG_Q_OFFSET 4 +#define SYSREG_Q_SIZE 1 +#define SYSREG_L_OFFSET 5 +#define SYSREG_L_SIZE 1 +#define SYSREG_T_OFFSET 14 +#define SYSREG_T_SIZE 1 +#define SYSREG_SR_R_OFFSET 15 +#define SYSREG_SR_R_SIZE 1 +#define SYSREG_GM_OFFSET 16 +#define SYSREG_GM_SIZE 1 +#define SYSREG_I0M_OFFSET 17 +#define SYSREG_I0M_SIZE 1 +#define SYSREG_I1M_OFFSET 18 +#define SYSREG_I1M_SIZE 1 +#define SYSREG_I2M_OFFSET 19 +#define SYSREG_I2M_SIZE 1 +#define SYSREG_I3M_OFFSET 20 +#define SYSREG_I3M_SIZE 1 +#define SYSREG_EM_OFFSET 21 +#define SYSREG_EM_SIZE 1 +#define SYSREG_M0_OFFSET 22 +#define SYSREG_M0_SIZE 1 +#define SYSREG_M1_OFFSET 23 +#define SYSREG_M1_SIZE 1 +#define SYSREG_M2_OFFSET 24 +#define SYSREG_M2_SIZE 1 +#define SYSREG_SR_D_OFFSET 26 +#define SYSREG_SR_D_SIZE 1 +#define SYSREG_DM_OFFSET 27 +#define SYSREG_DM_SIZE 1 +#define SYSREG_SR_J_OFFSET 28 +#define SYSREG_SR_J_SIZE 1 +#define SYSREG_H_OFFSET 29 +#define SYSREG_H_SIZE 1 + +/* Bitfields in CPUCR */ +#define SYSREG_BI_OFFSET 0 +#define SYSREG_BI_SIZE 1 +#define SYSREG_BE_OFFSET 1 +#define SYSREG_BE_SIZE 1 +#define SYSREG_FE_OFFSET 2 +#define SYSREG_FE_SIZE 1 +#define SYSREG_RE_OFFSET 3 +#define SYSREG_RE_SIZE 1 +#define SYSREG_IBE_OFFSET 4 +#define SYSREG_IBE_SIZE 1 +#define SYSREG_IEE_OFFSET 5 +#define SYSREG_IEE_SIZE 1 + +/* Bitfields in ECR */ +#define SYSREG_ECR_OFFSET 0 +#define SYSREG_ECR_SIZE 32 + +/* Bitfields in CONFIG0 */ +#define SYSREG_CONFIG0_R_OFFSET 0 +#define SYSREG_CONFIG0_R_SIZE 1 +#define SYSREG_CONFIG0_D_OFFSET 1 +#define SYSREG_CONFIG0_D_SIZE 1 +#define SYSREG_CONFIG0_S_OFFSET 2 +#define SYSREG_CONFIG0_S_SIZE 1 +#define SYSREG_O_OFFSET 3 +#define SYSREG_O_SIZE 1 +#define SYSREG_P_OFFSET 4 +#define SYSREG_P_SIZE 1 +#define SYSREG_CONFIG0_J_OFFSET 5 +#define SYSREG_CONFIG0_J_SIZE 1 +#define SYSREG_F_OFFSET 6 +#define SYSREG_F_SIZE 1 +#define SYSREG_MMUT_OFFSET 7 +#define SYSREG_MMUT_SIZE 3 +#define SYSREG_AR_OFFSET 10 +#define SYSREG_AR_SIZE 3 +#define SYSREG_AT_OFFSET 13 +#define SYSREG_AT_SIZE 3 +#define SYSREG_PROCESSORREVISION_OFFSET 16 +#define SYSREG_PROCESSORREVISION_SIZE 8 +#define SYSREG_PROCESSORID_OFFSET 24 +#define SYSREG_PROCESSORID_SIZE 8 + +/* Bitfields in CONFIG1 */ +#define SYSREG_DASS_OFFSET 0 +#define SYSREG_DASS_SIZE 3 +#define SYSREG_DLSZ_OFFSET 3 +#define SYSREG_DLSZ_SIZE 3 +#define SYSREG_DSET_OFFSET 6 +#define SYSREG_DSET_SIZE 4 +#define SYSREG_IASS_OFFSET 10 +#define SYSREG_IASS_SIZE 3 +#define SYSREG_ILSZ_OFFSET 13 +#define SYSREG_ILSZ_SIZE 3 +#define SYSREG_ISET_OFFSET 16 +#define SYSREG_ISET_SIZE 4 +#define SYSREG_DMMUSZ_OFFSET 20 +#define SYSREG_DMMUSZ_SIZE 6 +#define SYSREG_IMMUSZ_OFFSET 26 +#define SYSREG_IMMUSZ_SIZE 6 + +/* Bitfields in TLBEHI */ +#define SYSREG_ASID_OFFSET 0 +#define SYSREG_ASID_SIZE 8 +#define SYSREG_TLBEHI_I_OFFSET 8 +#define SYSREG_TLBEHI_I_SIZE 1 +#define SYSREG_TLBEHI_V_OFFSET 9 +#define SYSREG_TLBEHI_V_SIZE 1 +#define SYSREG_VPN_OFFSET 10 +#define SYSREG_VPN_SIZE 22 + +/* Bitfields in TLBELO */ +#define SYSREG_W_OFFSET 0 +#define SYSREG_W_SIZE 1 +#define SYSREG_TLBELO_D_OFFSET 1 +#define SYSREG_TLBELO_D_SIZE 1 +#define SYSREG_SZ_OFFSET 2 +#define SYSREG_SZ_SIZE 2 +#define SYSREG_AP_OFFSET 4 +#define SYSREG_AP_SIZE 3 +#define SYSREG_B_OFFSET 7 +#define SYSREG_B_SIZE 1 +#define SYSREG_G_OFFSET 8 +#define SYSREG_G_SIZE 1 +#define SYSREG_TLBELO_C_OFFSET 9 +#define SYSREG_TLBELO_C_SIZE 1 +#define SYSREG_PFN_OFFSET 10 +#define SYSREG_PFN_SIZE 22 + +/* Bitfields in MMUCR */ +#define SYSREG_E_OFFSET 0 +#define SYSREG_E_SIZE 1 +#define SYSREG_M_OFFSET 1 +#define SYSREG_M_SIZE 1 +#define SYSREG_MMUCR_I_OFFSET 2 +#define SYSREG_MMUCR_I_SIZE 1 +#define SYSREG_MMUCR_N_OFFSET 3 +#define SYSREG_MMUCR_N_SIZE 1 +#define SYSREG_MMUCR_S_OFFSET 4 +#define SYSREG_MMUCR_S_SIZE 1 +#define SYSREG_DLA_OFFSET 8 +#define SYSREG_DLA_SIZE 6 +#define SYSREG_DRP_OFFSET 14 +#define SYSREG_DRP_SIZE 6 +#define SYSREG_ILA_OFFSET 20 +#define SYSREG_ILA_SIZE 6 +#define SYSREG_IRP_OFFSET 26 +#define SYSREG_IRP_SIZE 6 + +/* Bitfields in PCCR */ +#define SYSREG_PCCR_R_OFFSET 1 +#define SYSREG_PCCR_R_SIZE 1 +#define SYSREG_PCCR_C_OFFSET 2 +#define SYSREG_PCCR_C_SIZE 1 +#define SYSREG_PCCR_S_OFFSET 3 +#define SYSREG_PCCR_S_SIZE 1 +#define SYSREG_IEC_OFFSET 4 +#define SYSREG_IEC_SIZE 1 +#define SYSREG_IE0_OFFSET 5 +#define SYSREG_IE0_SIZE 1 +#define SYSREG_IE1_OFFSET 6 +#define SYSREG_IE1_SIZE 1 +#define SYSREG_FC_OFFSET 8 +#define SYSREG_FC_SIZE 1 +#define SYSREG_F0_OFFSET 9 +#define SYSREG_F0_SIZE 1 +#define SYSREG_F1_OFFSET 10 +#define SYSREG_F1_SIZE 1 +#define SYSREG_CONF0_OFFSET 12 +#define SYSREG_CONF0_SIZE 6 +#define SYSREG_CONF1_OFFSET 18 +#define SYSREG_CONF1_SIZE 6 + +/* Constants for ECR */ +#define ECR_UNRECOVERABLE 0 +#define ECR_TLB_MULTIPLE 1 +#define ECR_BUS_ERROR_WRITE 2 +#define ECR_BUS_ERROR_READ 3 +#define ECR_NMI 4 +#define ECR_ADDR_ALIGN_X 5 +#define ECR_PROTECTION_X 6 +#define ECR_DEBUG 7 +#define ECR_ILLEGAL_OPCODE 8 +#define ECR_UNIMPL_INSTRUCTION 9 +#define ECR_PRIVILEGE_VIOLATION 10 +#define ECR_FPE 11 +#define ECR_COPROC_ABSENT 12 +#define ECR_ADDR_ALIGN_R 13 +#define ECR_ADDR_ALIGN_W 14 +#define ECR_PROTECTION_R 15 +#define ECR_PROTECTION_W 16 +#define ECR_DTLB_MODIFIED 17 +#define ECR_TLB_MISS_X 20 +#define ECR_TLB_MISS_R 24 +#define ECR_TLB_MISS_W 28 + +/* Bit manipulation macros */ +#define SYSREG_BIT(name) (1 << SYSREG_##name##_OFFSET) +#define SYSREG_BF(name,value) \ + (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) \ + << SYSREG_##name##_OFFSET) +#define SYSREG_BFEXT(name,value) \ + (((value) >> SYSREG_##name##_OFFSET) \ + & ((1 << SYSREG_##name##_SIZE) - 1)) +#define SYSREG_BFINS(name,value,old) \ + (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) \ + << SYSREG_##name##_OFFSET)) \ + | SYSREG_BF(name,value)) + +/* Register access macros */ +#define sysreg_read(reg) __builtin_mfsr(SYSREG_##reg) +#define sysreg_write(reg, value) __builtin_mtsr(SYSREG_##reg, value) + +#endif /* __ASM_AVR32_SYSREG_H__ */ diff --git a/include/asm-avr32/types.h b/include/asm-avr32/types.h new file mode 100644 index 0000000000..e6c65d9179 --- /dev/null +++ b/include/asm-avr32/types.h @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_TYPES_H +#define __ASM_AVR32_TYPES_H + +#ifndef __ASSEMBLY__ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +#endif /* __ASSEMBLY__ */ + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +#define BITS_PER_LONG 32 + +#ifndef __ASSEMBLY__ + +typedef __signed__ char s8; +typedef unsigned char u8; + +typedef __signed__ short s16; +typedef unsigned short u16; + +typedef __signed__ int s32; +typedef unsigned int u32; + +typedef __signed__ long long s64; +typedef unsigned long long u64; + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +#ifdef CONFIG_LBD +typedef u64 sector_t; +#define HAVE_SECTOR_T +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __KERNEL__ */ + + +#endif /* __ASM_AVR32_TYPES_H */ diff --git a/include/asm-avr32/u-boot.h b/include/asm-avr32/u-boot.h new file mode 100644 index 0000000000..71dfcaf284 --- /dev/null +++ b/include/asm-avr32/u-boot.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_U_BOOT_H__ +#define __ASM_U_BOOT_H__ 1 + +typedef struct bd_info { + unsigned long bi_baudrate; + unsigned long bi_ip_addr; + unsigned char bi_enetaddr[6]; + unsigned char bi_phy_id[4]; + struct environment_s *bi_env; + unsigned long bi_board_number; + void *bi_boot_params; + struct { + unsigned long start; + unsigned long size; + } bi_dram[CONFIG_NR_DRAM_BANKS]; + unsigned long bi_flashstart; + unsigned long bi_flashsize; + unsigned long bi_flashoffset; +} bd_t; + +#define bi_memstart bi_dram[0].start +#define bi_memsize bi_dram[0].size + +/** + * container_of - cast a member of a structure out to the containing structure + * + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + +#endif /* __ASM_U_BOOT_H__ */ -- cgit v1.2.1 From 72a087e04705c26cad982879ebd06b5281bf825a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 24 Oct 2006 14:27:35 +0200 Subject: Add AT32AP CPU and AT32AP7000 SoC support Patch by Haavard Skinnemoen, 06 Sep 2006 This patch adds support for the AT32AP CPU family and the AT32AP7000 chip, which is the first chip implementing the AVR32 architecture. The AT32AP CPU core is a high-performance implementation featuring a 7-stage pipeline, separate instruction- and data caches, and a MMU. For more information, please see the "AVR32 AP Technical Reference": http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf In addition to this, the AT32AP7000 chip comes with a large set of integrated peripherals, many of which are shared with the AT91 series of ARM-based microcontrollers from Atmel. Full data sheet is available here: http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/arch-at32ap7000/hmatrix2.h | 232 +++++++++++++++++++++++++ include/asm-avr32/arch-at32ap7000/memory-map.h | 61 +++++++ include/asm-avr32/arch-at32ap7000/platform.h | 146 ++++++++++++++++ 3 files changed, 439 insertions(+) create mode 100644 include/asm-avr32/arch-at32ap7000/hmatrix2.h create mode 100644 include/asm-avr32/arch-at32ap7000/memory-map.h create mode 100644 include/asm-avr32/arch-at32ap7000/platform.h (limited to 'include') diff --git a/include/asm-avr32/arch-at32ap7000/hmatrix2.h b/include/asm-avr32/arch-at32ap7000/hmatrix2.h new file mode 100644 index 0000000000..e6df4b7fe3 --- /dev/null +++ b/include/asm-avr32/arch-at32ap7000/hmatrix2.h @@ -0,0 +1,232 @@ +/* + * Register definition for the High-speed Bus Matrix + */ +#ifndef __ASM_AVR32_HMATRIX2_H__ +#define __ASM_AVR32_HMATRIX2_H__ + +/* HMATRIX2 register offsets */ +#define HMATRIX2_MCFG0 0x0000 +#define HMATRIX2_MCFG1 0x0004 +#define HMATRIX2_MCFG2 0x0008 +#define HMATRIX2_MCFG3 0x000c +#define HMATRIX2_MCFG4 0x0010 +#define HMATRIX2_MCFG5 0x0014 +#define HMATRIX2_MCFG6 0x0018 +#define HMATRIX2_MCFG7 0x001c +#define HMATRIX2_MCFG8 0x0020 +#define HMATRIX2_MCFG9 0x0024 +#define HMATRIX2_MCFG10 0x0028 +#define HMATRIX2_MCFG11 0x002c +#define HMATRIX2_MCFG12 0x0030 +#define HMATRIX2_MCFG13 0x0034 +#define HMATRIX2_MCFG14 0x0038 +#define HMATRIX2_MCFG15 0x003c +#define HMATRIX2_SCFG0 0x0040 +#define HMATRIX2_SCFG1 0x0044 +#define HMATRIX2_SCFG2 0x0048 +#define HMATRIX2_SCFG3 0x004c +#define HMATRIX2_SCFG4 0x0050 +#define HMATRIX2_SCFG5 0x0054 +#define HMATRIX2_SCFG6 0x0058 +#define HMATRIX2_SCFG7 0x005c +#define HMATRIX2_SCFG8 0x0060 +#define HMATRIX2_SCFG9 0x0064 +#define HMATRIX2_SCFG10 0x0068 +#define HMATRIX2_SCFG11 0x006c +#define HMATRIX2_SCFG12 0x0070 +#define HMATRIX2_SCFG13 0x0074 +#define HMATRIX2_SCFG14 0x0078 +#define HMATRIX2_SCFG15 0x007c +#define HMATRIX2_PRAS0 0x0080 +#define HMATRIX2_PRBS0 0x0084 +#define HMATRIX2_PRAS1 0x0088 +#define HMATRIX2_PRBS1 0x008c +#define HMATRIX2_PRAS2 0x0090 +#define HMATRIX2_PRBS2 0x0094 +#define HMATRIX2_PRAS3 0x0098 +#define HMATRIX2_PRBS3 0x009c +#define HMATRIX2_PRAS4 0x00a0 +#define HMATRIX2_PRBS4 0x00a4 +#define HMATRIX2_PRAS5 0x00a8 +#define HMATRIX2_PRBS5 0x00ac +#define HMATRIX2_PRAS6 0x00b0 +#define HMATRIX2_PRBS6 0x00b4 +#define HMATRIX2_PRAS7 0x00b8 +#define HMATRIX2_PRBS7 0x00bc +#define HMATRIX2_PRAS8 0x00c0 +#define HMATRIX2_PRBS8 0x00c4 +#define HMATRIX2_PRAS9 0x00c8 +#define HMATRIX2_PRBS9 0x00cc +#define HMATRIX2_PRAS10 0x00d0 +#define HMATRIX2_PRBS10 0x00d4 +#define HMATRIX2_PRAS11 0x00d8 +#define HMATRIX2_PRBS11 0x00dc +#define HMATRIX2_PRAS12 0x00e0 +#define HMATRIX2_PRBS12 0x00e4 +#define HMATRIX2_PRAS13 0x00e8 +#define HMATRIX2_PRBS13 0x00ec +#define HMATRIX2_PRAS14 0x00f0 +#define HMATRIX2_PRBS14 0x00f4 +#define HMATRIX2_PRAS15 0x00f8 +#define HMATRIX2_PRBS15 0x00fc +#define HMATRIX2_MRCR 0x0100 +#define HMATRIX2_SFR0 0x0110 +#define HMATRIX2_SFR1 0x0114 +#define HMATRIX2_SFR2 0x0118 +#define HMATRIX2_SFR3 0x011c +#define HMATRIX2_SFR4 0x0120 +#define HMATRIX2_SFR5 0x0124 +#define HMATRIX2_SFR6 0x0128 +#define HMATRIX2_SFR7 0x012c +#define HMATRIX2_SFR8 0x0130 +#define HMATRIX2_SFR9 0x0134 +#define HMATRIX2_SFR10 0x0138 +#define HMATRIX2_SFR11 0x013c +#define HMATRIX2_SFR12 0x0140 +#define HMATRIX2_SFR13 0x0144 +#define HMATRIX2_SFR14 0x0148 +#define HMATRIX2_SFR15 0x014c +#define HMATRIX2_VERSION 0x01fc + +/* Bitfields in MCFG0 */ +#define HMATRIX2_ULBT_OFFSET 0 +#define HMATRIX2_ULBT_SIZE 3 + +/* Bitfields in SCFG0 */ +#define HMATRIX2_SLOT_CYCLE_OFFSET 0 +#define HMATRIX2_SLOT_CYCLE_SIZE 8 +#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16 +#define HMATRIX2_DEFMSTR_TYPE_SIZE 2 +#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18 +#define HMATRIX2_FIXED_DEFMSTR_SIZE 4 +#define HMATRIX2_ARBT_OFFSET 24 +#define HMATRIX2_ARBT_SIZE 2 + +/* Bitfields in PRAS0 */ +#define HMATRIX2_M0PR_OFFSET 0 +#define HMATRIX2_M0PR_SIZE 4 +#define HMATRIX2_M1PR_OFFSET 4 +#define HMATRIX2_M1PR_SIZE 4 +#define HMATRIX2_M2PR_OFFSET 8 +#define HMATRIX2_M2PR_SIZE 4 +#define HMATRIX2_M3PR_OFFSET 12 +#define HMATRIX2_M3PR_SIZE 4 +#define HMATRIX2_M4PR_OFFSET 16 +#define HMATRIX2_M4PR_SIZE 4 +#define HMATRIX2_M5PR_OFFSET 20 +#define HMATRIX2_M5PR_SIZE 4 +#define HMATRIX2_M6PR_OFFSET 24 +#define HMATRIX2_M6PR_SIZE 4 +#define HMATRIX2_M7PR_OFFSET 28 +#define HMATRIX2_M7PR_SIZE 4 + +/* Bitfields in PRBS0 */ +#define HMATRIX2_M8PR_OFFSET 0 +#define HMATRIX2_M8PR_SIZE 4 +#define HMATRIX2_M9PR_OFFSET 4 +#define HMATRIX2_M9PR_SIZE 4 +#define HMATRIX2_M10PR_OFFSET 8 +#define HMATRIX2_M10PR_SIZE 4 +#define HMATRIX2_M11PR_OFFSET 12 +#define HMATRIX2_M11PR_SIZE 4 +#define HMATRIX2_M12PR_OFFSET 16 +#define HMATRIX2_M12PR_SIZE 4 +#define HMATRIX2_M13PR_OFFSET 20 +#define HMATRIX2_M13PR_SIZE 4 +#define HMATRIX2_M14PR_OFFSET 24 +#define HMATRIX2_M14PR_SIZE 4 +#define HMATRIX2_M15PR_OFFSET 28 +#define HMATRIX2_M15PR_SIZE 4 + +/* Bitfields in MRCR */ +#define HMATRIX2_RBC0_OFFSET 0 +#define HMATRIX2_RBC0_SIZE 1 +#define HMATRIX2_RBC1_OFFSET 1 +#define HMATRIX2_RBC1_SIZE 1 +#define HMATRIX2_RBC2_OFFSET 2 +#define HMATRIX2_RBC2_SIZE 1 +#define HMATRIX2_RBC3_OFFSET 3 +#define HMATRIX2_RBC3_SIZE 1 +#define HMATRIX2_RBC4_OFFSET 4 +#define HMATRIX2_RBC4_SIZE 1 +#define HMATRIX2_RBC5_OFFSET 5 +#define HMATRIX2_RBC5_SIZE 1 +#define HMATRIX2_RBC6_OFFSET 6 +#define HMATRIX2_RBC6_SIZE 1 +#define HMATRIX2_RBC7_OFFSET 7 +#define HMATRIX2_RBC7_SIZE 1 +#define HMATRIX2_RBC8_OFFSET 8 +#define HMATRIX2_RBC8_SIZE 1 +#define HMATRIX2_RBC9_OFFSET 9 +#define HMATRIX2_RBC9_SIZE 1 +#define HMATRIX2_RBC10_OFFSET 10 +#define HMATRIX2_RBC10_SIZE 1 +#define HMATRIX2_RBC11_OFFSET 11 +#define HMATRIX2_RBC11_SIZE 1 +#define HMATRIX2_RBC12_OFFSET 12 +#define HMATRIX2_RBC12_SIZE 1 +#define HMATRIX2_RBC13_OFFSET 13 +#define HMATRIX2_RBC13_SIZE 1 +#define HMATRIX2_RBC14_OFFSET 14 +#define HMATRIX2_RBC14_SIZE 1 +#define HMATRIX2_RBC15_OFFSET 15 +#define HMATRIX2_RBC15_SIZE 1 + +/* Bitfields in SFR0 */ +#define HMATRIX2_SFR_OFFSET 0 +#define HMATRIX2_SFR_SIZE 32 + +/* Bitfields in SFR4 */ +#define HMATRIX2_CS1A_OFFSET 1 +#define HMATRIX2_CS1A_SIZE 1 +#define HMATRIX2_CS3A_OFFSET 3 +#define HMATRIX2_CS3A_SIZE 1 +#define HMATRIX2_CS4A_OFFSET 4 +#define HMATRIX2_CS4A_SIZE 1 +#define HMATRIX2_CS5A_OFFSET 5 +#define HMATRIX2_CS5A_SIZE 1 +#define HMATRIX2_DBPUC_OFFSET 8 +#define HMATRIX2_DBPUC_SIZE 1 + +/* Bitfields in VERSION */ +#define HMATRIX2_VERSION_OFFSET 0 +#define HMATRIX2_VERSION_SIZE 12 +#define HMATRIX2_MFN_OFFSET 16 +#define HMATRIX2_MFN_SIZE 3 + +/* Constants for ULBT */ +#define HMATRIX2_ULBT_INFINITE 0 +#define HMATRIX2_ULBT_SINGLE 1 +#define HMATRIX2_ULBT_FOUR_BEAT 2 +#define HMATRIX2_ULBT_SIXTEEN_BEAT 4 + +/* Constants for DEFMSTR_TYPE */ +#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0 +#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1 +#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2 + +/* Constants for ARBT */ +#define HMATRIX2_ARBT_ROUND_ROBIN 0 +#define HMATRIX2_ARBT_FIXED_PRIORITY 1 + +/* Bit manipulation macros */ +#define HMATRIX2_BIT(name) \ + (1 << HMATRIX2_##name##_OFFSET) +#define HMATRIX2_BF(name,value) \ + (((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) \ + << HMATRIX2_##name##_OFFSET) +#define HMATRIX2_BFEXT(name,value) \ + (((value) >> HMATRIX2_##name##_OFFSET) \ + & ((1 << HMATRIX2_##name##_SIZE) - 1)) +#define HMATRIX2_BFINS(name,value,old) \ + (((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) \ + << HMATRIX2_##name##_OFFSET)) \ + | HMATRIX2_BF(name,value)) + +/* Register access macros */ +#define hmatrix2_readl(port,reg) \ + readl((port)->regs + HMATRIX2_##reg) +#define hmatrix2_writel(port,reg,value) \ + writel((value), (port)->regs + HMATRIX2_##reg) + +#endif /* __ASM_AVR32_HMATRIX2_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/memory-map.h b/include/asm-avr32/arch-at32ap7000/memory-map.h new file mode 100644 index 0000000000..8ffe851c89 --- /dev/null +++ b/include/asm-avr32/arch-at32ap7000/memory-map.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_PART_MEMORY_MAP_H__ +#define __ASM_AVR32_PART_MEMORY_MAP_H__ + +#define AUDIOC_BASE 0xFFF02800 +#define DAC_BASE 0xFFF02000 +#define DMAC_BASE 0xFF200000 +#define ECC_BASE 0xFFF03C00 +#define HISI_BASE 0xFFF02C00 +#define HMATRIX_BASE 0xFFF00800 +#define HSDRAMC_BASE 0xFFF03800 +#define HSMC_BASE 0xFFF03400 +#define LCDC_BASE 0xFF000000 +#define MACB0_BASE 0xFFF01800 +#define MACB1_BASE 0xFFF01C00 +#define MMCI_BASE 0xFFF02400 +#define PIOA_BASE 0xFFE02800 +#define PIOB_BASE 0xFFE02C00 +#define PIOC_BASE 0xFFE03000 +#define PIOD_BASE 0xFFE03400 +#define PIOE_BASE 0xFFE03800 +#define PSIF_BASE 0xFFE03C00 +#define PWM_BASE 0xFFF01400 +#define SM_BASE 0xFFF00000 +#define INTC_BASE 0XFFF00400 +#define SPI0_BASE 0xFFE00000 +#define SPI1_BASE 0xFFE00400 +#define SSC0_BASE 0xFFE01C00 +#define SSC1_BASE 0xFFE02000 +#define SSC2_BASE 0xFFE02400 +#define TIMER0_BASE 0xFFF00C00 +#define TIMER1_BASE 0xFFF01000 +#define TWI_BASE 0xFFE00800 +#define USART0_BASE 0xFFE00C00 +#define USART1_BASE 0xFFE01000 +#define USART2_BASE 0xFFE01400 +#define USART3_BASE 0xFFE01800 +#define USB_FIFO 0xFF300000 +#define USB_BASE 0xFFF03000 + +#endif /* __ASM_AVR32_PART_MEMORY_MAP_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/platform.h b/include/asm-avr32/arch-at32ap7000/platform.h new file mode 100644 index 0000000000..759050116a --- /dev/null +++ b/include/asm-avr32/arch-at32ap7000/platform.h @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _ASM_AVR32_ARCH_PM_H +#define _ASM_AVR32_ARCH_PM_H + +#include + +enum clock_domain_id { + CLOCK_CPU, + CLOCK_HSB, + CLOCK_PBA, + CLOCK_PBB, + NR_CLOCK_DOMAINS, +}; + +enum resource_type { + RESOURCE_GPIO, + RESOURCE_CLOCK, +}; + +enum gpio_func { + GPIO_FUNC_GPIO, + GPIO_FUNC_A, + GPIO_FUNC_B, +}; + +enum device_id { + DEVICE_HEBI, + DEVICE_PBA_BRIDGE, + DEVICE_PBB_BRIDGE, + DEVICE_HRAMC, + /* GPIO controllers must be kept together */ + DEVICE_PIOA, + DEVICE_PIOB, + DEVICE_PIOC, + DEVICE_PIOD, + DEVICE_PIOE, + DEVICE_SM, + DEVICE_INTC, + DEVICE_HMATRIX, +#if defined(CFG_HPDC) + DEVICE_HPDC, +#endif +#if defined(CFG_MACB0) + DEVICE_MACB0, +#endif +#if defined(CFG_MACB1) + DEVICE_MACB1, +#endif +#if defined(CFG_LCDC) + DEVICE_LCDC, +#endif +#if defined(CFG_USART0) + DEVICE_USART0, +#endif +#if defined(CFG_USART1) + DEVICE_USART1, +#endif +#if defined(CFG_USART2) + DEVICE_USART2, +#endif +#if defined(CFG_USART3) + DEVICE_USART3, +#endif +#if defined(CFG_MMCI) + DEVICE_MMCI, +#endif +#if defined(CFG_DMAC) + DEVICE_DMAC, +#endif + NR_DEVICES, + NO_DEVICE = -1, +}; + +struct resource { + enum resource_type type; + union { + struct { + unsigned long base; + } iomem; + struct { + unsigned char nr_pins; + enum device_id gpio_dev; + enum gpio_func func; + unsigned short start; + } gpio; + struct { + enum clock_domain_id id; + unsigned char index; + } clock; + } u; +}; + +struct device { + void *regs; + unsigned int nr_resources; + const struct resource *resource; +}; + +struct clock_domain { + unsigned short reg; + enum clock_domain_id id; + enum device_id bridge; +}; + +extern const struct device chip_device[NR_DEVICES]; +extern const struct clock_domain chip_clock[NR_CLOCK_DOMAINS]; + +/** + * Set up PIO, clock management and I/O memory for a device. + */ +const struct device *get_device(enum device_id devid); +void put_device(const struct device *dev); + +int gpio_set_func(enum device_id gpio_devid, unsigned int start, + unsigned int nr_pins, enum gpio_func func); +void gpio_free(enum device_id gpio_devid, unsigned int start, + unsigned int nr_pins); + +void pm_init(void); +int pm_enable_clock(enum clock_domain_id id, unsigned int index); +void pm_disable_clock(enum clock_domain_id id, unsigned int index); +unsigned long pm_get_clock_freq(enum clock_domain_id domain); + +void cpu_enable_sdram(void); + +#endif /* _ASM_AVR32_ARCH_PM_H */ -- cgit v1.2.1 From 6ccec4492e77428fd6eafd3dfe94fbdf08e91d37 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 24 Oct 2006 14:42:37 +0200 Subject: Add ATSTK1000 and ATSTK1002 board support Patch by Haavard Skinnemoen, 06 Sep 2006 This patch adds support for the ATSTK1000 with the ATSTK1002 CPU daughterboard. ATSTK1000 is a full-featured development board for AT32AP CPUs. It has two ethernet ports, a high quality QVGA LCD panel, a loudspeaker, and connectors for USART, PS/2, VGA, USB, MMC/SD cards and CompactFlash cards. For more information, please see this page: http://www.atmel.com/dyn/products/tools.asp?family_id=682 The ATSTK1002 is a daughterboard for the ATSTK1000 supporting the AT32AP7000 chip. Signed-off-by: Haavard Skinnemoen --- include/configs/atstk1002.h | 183 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) create mode 100644 include/configs/atstk1002.h (limited to 'include') diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h new file mode 100644 index 0000000000..458ebabeb9 --- /dev/null +++ b/include/configs/atstk1002.h @@ -0,0 +1,183 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * Configuration settings for the ATSTK1002 CPU daughterboard + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_ATSTK1002 1 +#define CONFIG_ATSTK1000 1 + +#define CONFIG_ATSTK1000_EXT_FLASH 1 + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL + * frequency and the peripherals to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 20000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 7 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +#define CFG_CLKDIV_CPU 0 +#define CFG_CLKDIV_HSB 1 +#define CFG_CLKDIV_PBA 2 +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#define CFG_USART1 1 + +#define CFG_CONSOLE_UART_DEV DEVICE_USART1 + +/* User serviceable stuff */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyUS0 root=/dev/mtdblock1 fbmem=600k" + +#define CONFIG_COMMANDS (CFG_CMD_BDI \ + | CFG_CMD_LOADS \ + | CFG_CMD_LOADB \ + /* | CFG_CMD_IMI */ \ + /* | CFG_CMD_CACHE */ \ + | CFG_CMD_FLASH \ + | CFG_CMD_MEMORY \ + /* | CFG_CMD_NET */ \ + | CFG_CMD_ENV \ + /* | CFG_CMD_IRQ */ \ + | CFG_CMD_BOOTD \ + | CFG_CMD_CONSOLE \ + /* | CFG_CMD_EEPROM */ \ + | CFG_CMD_ASKENV \ + | CFG_CMD_RUN \ + | CFG_CMD_ECHO \ + /* | CFG_CMD_I2C */ \ + | CFG_CMD_REGINFO \ + /* | CFG_CMD_DATE */ \ + /* | CFG_CMD_DHCP */ \ + /* | CFG_CMD_AUTOSCRIPT */ \ + /* | CFG_CMD_MII */ \ + | CFG_CMD_MISC \ + /* | CFG_CMD_SDRAM */ \ + /* | CFG_CMD_DIAG */ \ + /* | CFG_CMD_HWFLOW */ \ + /* | CFG_CMD_SAVES */ \ + /* | CFG_CMD_SPI */ \ + /* | CFG_CMD_PING */ \ + /* | CFG_CMD_MMC */ \ + /* | CFG_CMD_FAT */ \ + /* | CFG_CMD_IMLS */ \ + /* | CFG_CMD_ITEST */ \ + /* | CFG_CMD_EXT2 */ \ + ) + +#include + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 +#define CFG_HSDRAMC 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +/* External flash on STK1000 */ +#if 0 +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#endif + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE 0x24000000 +#define CFG_INTRAM_SIZE 0x8000 + +#define CFG_SDRAM_BASE 0x10000000 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) +#define CFG_MALLOC_END \ + ({ \ + DECLARE_GLOBAL_DATA_PTR; \ + CFG_SDRAM_BASE + gd->sdram_size; \ + }) +#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN) + +#define CFG_DMA_ALLOC_LEN (16384) +#define CFG_DMA_ALLOC_END (CFG_MALLOC_START) +#define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN) +/* Allow 2MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "Uboot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 8 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START \ + ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; }) +#define CFG_MEMTEST_END \ + ({ \ + DECLARE_GLOBAL_DATA_PTR; \ + gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \ + }) +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From 8078f1a5f63a739b8533478f6c2b62fb1e2f79d7 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 28 Oct 2006 02:28:02 +0200 Subject: README says CFG_AUTO_COMPLETE, but ocde uses CONFIG_AUTO_COMPLETE --- include/configs/CPCI750.h | 2 +- include/configs/KAREF.h | 1 - include/configs/METROBOX.h | 2 +- include/configs/ep82xxm.h | 2 +- 4 files changed, 3 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 244e45a750..bc23fc0278 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -74,7 +74,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_AUTO_COMPLETE 1 +#define CONFIG_AUTO_COMPLETE 1 /* Define which ETH port will be used for connecting the network */ #define CFG_ETH_PORT ETH_0 diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 7bbceb01bd..2ad6f06985 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -200,7 +200,6 @@ /* Include auto complete with tabs */ #define CONFIG_AUTO_COMPLETE 1 -#define CFG_AUTO_COMPLETE 1 #define CFG_ALT_MEMTEST 1 /* use real memory test */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index b96557148a..465a4ecb8b 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -268,7 +268,7 @@ /* Include auto complete with tabs */ #define CONFIG_AUTO_COMPLETE 1 -#define CFG_AUTO_COMPLETE 1 +#define CONFIG_AUTO_COMPLETE 1 #define CFG_ALT_MEMTEST 1 /* use real memory test */ diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h index 372b10c623..a77ccef63b 100644 --- a/include/configs/ep82xxm.h +++ b/include/configs/ep82xxm.h @@ -135,7 +135,7 @@ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CFG_ENV_IN_OWN_SECT 1 -#define CFG_AUTO_COMPLETE +#define CONFIG_AUTO_COMPLETE 1 #define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3 ETHERNET" #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -- cgit v1.2.1 From 2751a95abd1b96911081c357e96a12fa97b40dee Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 28 Oct 2006 02:29:14 +0200 Subject: Enable commandline editing and hush shell on all TQM boards. --- include/configs/TQM5200.h | 1 + include/configs/TQM823L.h | 5 ++--- include/configs/TQM823M.h | 5 ++--- include/configs/TQM8260.h | 7 +++++++ include/configs/TQM834x.h | 6 ++++++ include/configs/TQM850L.h | 5 ++--- include/configs/TQM850M.h | 5 ++--- include/configs/TQM855L.h | 5 ++--- include/configs/TQM855M.h | 5 ++--- include/configs/TQM85xx.h | 6 +++--- include/configs/TQM860L.h | 5 ++--- include/configs/TQM860M.h | 5 ++--- include/configs/TQM862L.h | 5 ++--- include/configs/TQM862M.h | 5 ++--- include/configs/TQM866M.h | 7 +++---- include/configs/TQM885D.h | 7 +++---- 16 files changed, 43 insertions(+), 41 deletions(-) (limited to 'include') diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 897d1b262b..4bae103e09 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -566,6 +566,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ #define CFG_PROMPT_HUSH_PS2 "> " diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index b1c70f88c2..247f705fb6 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -123,9 +123,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 9f958f5477..1461b5f203 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -112,9 +112,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h index 49c3872630..ffd5c0b95c 100644 --- a/include/configs/TQM8260.h +++ b/include/configs/TQM8260.h @@ -237,6 +237,13 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 92c7016e6b..4bbee97db5 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -353,6 +353,12 @@ extern int tqm834x_num_flash_banks; #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 16b2ce3f05..90ecbadb2e 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -104,9 +104,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index bbc69608b2..b3f8f8d835 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -102,9 +102,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 198db1954d..49aaeea44d 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -107,9 +107,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index e25a7a204f..50df49e93c 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -141,9 +141,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index cce4624904..f45f3a2f5a 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -186,10 +186,10 @@ #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 4a1a4325dc..9be5db1e42 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -110,9 +110,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 4b754ba9cb..37f6c985d3 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -108,9 +108,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index 1dc9f74d5e..f03690a7b2 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -110,9 +110,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 3df060c619..495934045f 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -110,9 +110,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index 8f9c2c9cbb..148490b586 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -151,11 +151,10 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " #endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index ede4e3b9b3..d470ade847 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -160,11 +160,10 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " #endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -- cgit v1.2.1 From fae684e89844856383bdf101440889557df3e6b1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 28 Oct 2006 16:45:00 +0200 Subject: [PATCH] omap925.c: Remove unused functions Signed-off-by: Ladislav Michl Signed-off-by: Stefan Roese --- include/arm925t.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'include') diff --git a/include/arm925t.h b/include/arm925t.h index ab343eaace..3d767b35c0 100644 --- a/include/arm925t.h +++ b/include/arm925t.h @@ -6,10 +6,6 @@ #ifndef __ARM925T_H__ #define __ARM925T_H__ -void gpioreserve(ushort mask); -void gpiosetdir(ushort mask, ushort in); -void gpiosetout(ushort mask, ushort out); -void gpioinit(void); void archflashwp(void *archdata, int wp); #endif /*__ARM925T_H__*/ -- cgit v1.2.1 From 82d9c9ec29a1bec1b03ba616425ebaed231072c8 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Wed, 1 Nov 2006 01:34:29 +0100 Subject: Changed MarelV38B board make target to lowercase. Config file cleanup. --- include/configs/V38B.h | 368 ------------------------------------------------- include/configs/v38b.h | 343 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 343 insertions(+), 368 deletions(-) delete mode 100644 include/configs/V38B.h create mode 100644 include/configs/v38b.h (limited to 'include') diff --git a/include/configs/V38B.h b/include/configs/V38B.h deleted file mode 100644 index 8eea504742..0000000000 --- a/include/configs/V38B.h +++ /dev/null @@ -1,368 +0,0 @@ -/* - * (C) Copyright 2003-2004 Wolfgang Denk, DENX Software Engineering, - * wd@denx.de. - * - * See file CREDITS for list of people who contributed to this project. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., 59 - * Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#if 0 -#define DEBUG 0xFFF -#endif - -#if 0 -#define DEBUG 0x01 -#endif - -/* - * High Level Configuration Options - * (easy to change) -*/ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_V38B 1 /* ... on V38B board */ -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ -#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ -#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ - -#define CONFIG_NETCONSOLE 1 - -#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ - -#define CFG_XLB_PIPELINING 1 /* gives better performance */ - - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -/* - * DDR - */ -#define SDRAM_DDR 1 /* is DDR */ -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x704f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - - -/* - * PCI - no suport - */ -#undef CONFIG_PCI - -/* - * Partitions - */ -#define CONFIG_MAC_PARTITION 1 -#define CONFIG_DOS_PARTITION 1 - -/* - * USB - */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_PING | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_IRQ | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_SDRAMi | \ - CFG_CMD_DATE | \ - CFG_CMD_USB | \ - CFG_CMD_FAT) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Boot low with 16 MB Flash - */ -# define CFG_LOWBOOT 1 -# define CFG_LOWBOOT16 1 - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "devno=5\0" \ - "hostname=V38B_$(devno)\0" \ - "ipaddr=10.100.99.$(devno)\0" \ - "netmask=255.255.0.0\0" \ - "serverip=10.100.10.90\0" \ - "gatewayip=10.100.254.254\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=mpc5200/uImage\0" \ - "bootcmd=run net_nfs\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;bootm $(kernel_addr) " \ - "$(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs " \ - "addip;bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#if defined(CONFIG_MPC5200) -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ -#endif -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 - -/* - * RTC configuration - */ -#define CFG_I2C_RTC_ADDR 0x51 - -/* - * Flash configuration - use CFI driver - */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 -#define CFG_FLASH_BASE 0xFF000000 -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } -#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ -#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 - -/* - * GPIO configuration - */ -#define CFG_GPS_PORT_CONFIG 0x90000404 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x00047801 -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -#define CFG_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -/* Status LED */ - -#define CONFIG_STATUS_LED /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ - -#define CFG_LED_BASE (0xf0000600 + 0x70) /* Timer 7 GPIO */ - -#ifndef __ASSEMBLY__ -/* LEDs */ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \ - else \ - *((volatile long *) (CFG_LED_BASE)) |= (_msk); \ - } while(0) - -#define __led_init(_msk, st) \ - { \ - *((volatile long *) (CFG_LED_BASE)) |= 0x34; \ - } - -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h new file mode 100644 index 0000000000..cf2d031c9f --- /dev/null +++ b/include/configs/v38b.h @@ -0,0 +1,343 @@ +/* + * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering, + * wd@denx.de. + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ +#define CONFIG_V38B 1 /* ...on V38B board */ +#define CFG_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */ + +#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ +#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ + +#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ + +#define CONFIG_NETCONSOLE 1 + +#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */ + +#define CFG_XLB_PIPELINING 1 /* gives better performance */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * DDR + */ +#define SDRAM_DDR 1 /* is DDR */ +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x704f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +/* + * PCI - no suport + */ +#undef CONFIG_PCI + +/* + * Partitions + */ +#define CONFIG_MAC_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 + +/* + * USB + */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_SDRAMi | \ + CFG_CMD_DATE | \ + CFG_CMD_USB | \ + CFG_CMD_FAT) + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Boot low with 16 MB Flash + */ +#define CFG_LOWBOOT 1 +#define CFG_LOWBOOT16 1 + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootcmd=run net_nfs\0" \ + "bootdelay=3\0" \ + "baudrate=115200\0" \ + "preboot=echo;echo Type \"run flash_nfs\" to mount root " \ + "filesystem over NFS; echo\0" \ + "netdev=eth0\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off panic=1\0" \ + "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip;bootm $(kernel_addr) " \ + "$(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "hostname=v38b\0" \ + "ethact=FEC ETHERNET\0" \ + "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \ + "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ + "cp.b 200000 ff000000 $(filesize);" \ + "prot on ff000000 ff03ffff\0" \ + "load=tftp 200000 $(u-boot)\0" \ + "netmask=255.255.0.0\0" \ + "ipaddr=192.168.160.18\0" \ + "serverip=192.168.1.1\0" \ + "ethaddr=00:e0:ee:00:05:2e\0" \ + "bootfile=/tftpboot/v38b/uImage\0" \ + "u-boot=/tftpboot/v38b/u-boot.bin\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#if defined(CONFIG_MPC5200) +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#endif + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 + +/* + * RTC configuration + */ +#define CFG_I2C_RTC_ADDR 0x51 + +/* + * Flash configuration - use CFI driver + */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OVERWRITE 1 + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_MII 1 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x90000404 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00047801 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +/* + * IDE/ATA (supports IDE harddisk) + */ +#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +#define CFG_ATA_DATA_OFFSET (0x0060) /* data I/O offset */ + +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* normal register accesses offset */ + +#define CFG_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */ + +#define CFG_ATA_STRIDE 4 /* Interval between registers */ + +/* + * Status LED + */ +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ + +#define CFG_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */ +#ifndef __ASSEMBLY__ +typedef unsigned int led_id_t; + +#define __led_toggle(_msk) \ + do { \ + *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \ + } while(0) + +#define __led_set(_msk, _st) \ + do { \ + if ((_st)) \ + *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \ + else \ + *((volatile long *) (CFG_LED_BASE)) |= (_msk); \ + } while(0) + +#define __led_init(_msk, st) \ + do { \ + *((volatile long *) (CFG_LED_BASE)) |= 0x34; \ + } while(0) +#endif /* __ASSEMBLY__ */ + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From dae80f3caf9754a6dd3ddf3cf903d0c46cbd4385 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Wed, 1 Nov 2006 01:38:16 +0100 Subject: - Add MPC5XXX register definition MPC5XXX_WU_GPIO_DATA_I and change the MPC5XXX_WU_GPIO_DATA macro to MPC5XXX_WU_GPIO_DATA_O (per MPC5200 User's Manual). Replace the uses of MPC5XXX_WU_GPIO_DATA with MPC5XXX_WU_GPIO_DATA_O for affected boards. - Add defintions for some MPC5XXX GPIO pins. --- include/mpc5xxx.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index 1d20d1dcf5..089aa1322b 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -188,7 +188,14 @@ #define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000) #define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004) #define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008) -#define MPC5XXX_WU_GPIO_DATA (MPC5XXX_WU_GPIO + 0x000c) +#define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c) +#define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020) + +/* GPIO pins */ +#define GPIO_WKUP_7 0x80000000UL +#define GPIO_PSC6_0 0x10000000UL +#define GPIO_PSC3_9 0x04000000UL +#define GPIO_PSC1_4 0x01000000UL /* PCI registers */ #define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04) -- cgit v1.2.1 From 91650b3e4de688038d4f71279c44858e3e2c6870 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 6 Nov 2006 17:06:36 +0100 Subject: Sequential accesses to non-existent memory must be synchronized, at least on G2 cores. This fixes get_ram_size() problems on MPC5200 Rev. B boards. --- include/common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index 349d5cf726..ac78d1c001 100644 --- a/include/common.h +++ b/include/common.h @@ -270,7 +270,7 @@ int misc_init_r (void); void jumptable_init(void); /* common/memsize.c */ -int get_ram_size (volatile long *, long); +long get_ram_size (volatile long *, long); /* $(BOARD)/$(BOARD).c */ void reset_phy (void); -- cgit v1.2.1