From 7fc63cca611b9d2b5f170f9f37e6f99ddf5992a9 Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 21 Apr 2015 10:09:52 -0700 Subject: mpc85xx/T4240EMU: Remove T4240EMU board T4240 SoC has been available for a long time. Emulator support is no longer needed. Signed-off-by: York Sun --- include/configs/T4240EMU.h | 181 --------------------------------------------- 1 file changed, 181 deletions(-) delete mode 100644 include/configs/T4240EMU.h (limited to 'include') diff --git a/include/configs/T4240EMU.h b/include/configs/T4240EMU.h deleted file mode 100644 index e8ba5d6b26..0000000000 --- a/include/configs/T4240EMU.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * T4240 EMU board configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_T4240EMU -#define CONFIG_PHYS_64BIT - -#define CONFIG_SYS_NO_FLASH 1 -#define CONFIG_SYS_FSL_DDR_EMU 1 -#define CONFIG_SYS_FSL_NO_QIXIS 1 -#define CONFIG_SYS_FSL_NO_SERDES 1 - -#include "t4qds.h" - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CACHE_FLUSH - -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x2000 - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 133333333 -#define CONFIG_FSL_TBCLK_EXTRA_DIV 100 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS3 0x53 -#define SPD_EEPROM_ADDRESS4 0x54 -#define SPD_EEPROM_ADDRESS5 0x55 -#define SPD_EEPROM_ADDRESS6 0x56 -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_32 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(0) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ - FTIM0_NOR_TEADC(0x1) | \ - FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ - FTIM1_NOR_TRAD_NOR(0x1)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ - FTIM2_NOR_TCH(0x0) | \ - FTIM2_NOR_TWP(0x1)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 - -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 - -/* I2C */ -#define CONFIG_SYS_FSL_I2C_SPEED 4000000 /* faster speed for emulator */ -#define CONFIG_SYS_FSL_I2C2_SPEED 4000000 - -/* Qman/Bman */ -#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 50 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 50 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN -#define CONFIG_SYS_INTERLAKEN - -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) - -#define CONFIG_BOOTDELAY 0 - -/* - * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be - * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way - * interleaving. It can be cacheline, page, bank, superbank. - * See doc/README.fsl-ddr for details. - */ -#ifdef CONFIG_PPC_T4240 -#define CTRL_INTLV_PREFERED 3way_4KB -#else -#define CTRL_INTLV_PREFERED cacheline -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:" \ - "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ - "bank_intlv=auto;" \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=t4240emu/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=t4240emu/t4240emu.dtb\0" \ - "bdev=sda3\0" - -/* - * For emulation this causes u-boot to jump to the start of the proof point - * app code automatically - */ -#define CONFIG_PROOF_POINTS \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x29000000 - - -;" \ - "cpu 2 release 0x29000000 - - -;" \ - "cpu 3 release 0x29000000 - - -;" \ - "cpu 4 release 0x29000000 - - -;" \ - "cpu 5 release 0x29000000 - - -;" \ - "cpu 6 release 0x29000000 - - -;" \ - "cpu 7 release 0x29000000 - - -;" \ - "go 0x29000000" - -#define CONFIG_HVBOOT \ - "setenv bootargs config-addr=0x60000000; " \ - "bootm 0x01000000 - 0x00f00000" - -#define CONFIG_LINUX \ - "errata;" \ - "setenv othbootargs ignore_loglevel;" \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#endif /* __CONFIG_H */ -- cgit v1.2.1 From 0dc78ff857337a82d39d7e4390e317ffbc93097f Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Fri, 21 Nov 2014 17:25:21 +0530 Subject: drivers: usb: fsl: Workaround for Erratum A004477 Add a delay of 1 microsecond before issuing soft reset to the controller to let ongoing ULPI transaction complete. This prevents corruption of ULPI Function Control Register which eventually prevents phy clock from entering to low power mode Signed-off-by: Nikhil Badola Reviewed-by: York Sun --- include/fsl_usb.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'include') diff --git a/include/fsl_usb.h b/include/fsl_usb.h index 33d9f03096..8e3ddedfad 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -209,6 +209,30 @@ static inline bool has_erratum_a005697(void) return false; } +static inline bool has_erratum_a004477(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P1022: + case SVR_9131: + case SVR_9132: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); + case SVR_P2020: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0) || + IS_SVR_REV(svr, 2, 1); + case SVR_B4860: + case SVR_B4420: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P4080: + return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0); + } + + return false; +} #else static inline bool has_dual_phy(void) { @@ -239,5 +263,10 @@ static inline bool has_erratum_a005697(void) { return false; } + +static inline bool has_erratum_a004477(void) +{ + return false; +} #endif #endif /*_ASM_FSL_USB_H_ */ -- cgit v1.2.1 From 373762c34cd33b4a445b758090daaa87ccfa3fc6 Mon Sep 17 00:00:00 2001 From: Chunhe Lan Date: Fri, 20 Mar 2015 17:08:54 +0800 Subject: powerpc/t4rdb: Add SD boot support for T4240RDB board This patch adds SD boot support for T4240RDB board. SPL framework is used. PBL initializes the internal RAM and copies SPL to it. Then SPL initializes DDR using SPD and copies u-boot from SD card to DDR, finally SPL transfers control to u-boot. Signed-off-by: Chunhe Lan [York Sun: Fix T4240RDB_SDCARD_defcofig] Reviewed-by: York Sun --- include/configs/T4240RDB.h | 71 ++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 63 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 957a436374..2a222493da 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -21,11 +21,53 @@ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg +#ifndef CONFIG_SDCARD +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#else +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_MMC_BOOT +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif + #endif +#endif /* CONFIG_RAMBOOT_PBL */ #define CONFIG_DDR_ECC @@ -84,7 +126,16 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (512 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -112,7 +163,11 @@ #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ #define CONFIG_MISC_INIT_R @@ -135,7 +190,7 @@ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* Serial Port - controlled on board with jumper J8 @@ -351,7 +406,7 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) +#define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND @@ -617,11 +672,11 @@ unsigned long get_board_ddr_clk(void); #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) -- cgit v1.2.1 From 5066e62847bddf6030262ade2aa3e7bcdc930037 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Thu, 26 Mar 2015 16:13:09 +0800 Subject: T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue T2080QDS PEX1/Slot#1 will down-train from x4 to x2, with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15. Soft reset PCIe can fix this issue. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- include/configs/T208xQDS.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 046aa48baa..6adcb22521 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -575,6 +575,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controler 2 */ #define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_FSL_PCIE_RESET #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -- cgit v1.2.1 From e8a7f1c32b55f48408a10cded2663b3f578d02e2 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 27 Mar 2015 15:48:34 +0800 Subject: powerpc/t1023rdb: Add T1023 RDB board support T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC. T1023RDB board Overview ----------------------- - T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - one 1G RGMII port on-board(RTL8211F PHY) - one 1G SGMII port on-board(RTL8211F PHY) - one 2.5G SGMII port on-board(AQR105 PHY) - PCIe: Two Mini-PCIe connectors on-board. - SerDes: 4 lanes up to 10.3125GHz - NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash - NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash - eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash. - USB: one Type-A USB 2.0 port with internal PHY - eSDHC: support SD/MMC card and eMMC on-board - 256Kbit M24256 I2C EEPROM - RTC: Real-time clock DS1339 on I2C bus - UART: one serial port on-board with RJ45 connector - Debugging: JTAG/COP for T1023 debugging As well updated T1024RDB to add T1023RDB. Signed-off-by: Shengzhou Liu [York Sun: fix defconfig files] Reviewed-by: York Sun --- include/configs/T102xRDB.h | 79 +++++++++++++++++++++++++++++++++++++++------- 1 file changed, 68 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 84e8336a72..deff617ed4 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -11,6 +11,12 @@ #ifndef __T1024RDB_H #define __T1024RDB_H +#if defined(CONFIG_T1023RDB) +#ifdef CONFIG_SPL +#define CONFIG_SYS_NO_FLASH +#endif +#endif + /* High Level Configuration Options */ #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO @@ -35,7 +41,9 @@ #define CONFIG_ENV_OVERWRITE /* support deep sleep */ +#ifdef CONFIG_PPC_T1024 #define CONFIG_DEEP_SLEEP +#endif #if defined(CONFIG_DEEP_SLEEP) #define CONFIG_SILENT_CONSOLE #define CONFIG_BOARD_EARLY_INIT_F @@ -43,7 +51,11 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg +#if defined(CONFIG_T1024RDB) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg +#endif #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT @@ -177,7 +189,11 @@ #define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#if defined(CONFIG_T1024RDB) #define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_T1023RDB) +#define CONFIG_ENV_SECT_SIZE 0x40000 +#endif #elif defined(CONFIG_SDCARD) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_MMC @@ -188,7 +204,11 @@ #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE 0x2000 +#if defined(CONFIG_T1024RDB) #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_T1023RDB) +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#endif #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -209,7 +229,7 @@ unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 66660000 +#define CONFIG_DDR_CLK_FREQ 100000000 /* * These can be toggled for performance analysis, otherwise use default. @@ -224,6 +244,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif +#define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_SYS_ALT_MEMTEST @@ -265,13 +286,18 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_FSL_DDR_INTERACTIVE +#if defined(CONFIG_T1024RDB) #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR3 - #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 - #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_SYS_SDRAM_SIZE 2048 +#endif /* * IFC Definitions @@ -291,7 +317,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ +#if defined(CONFIG_T1024RDB) #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) +#endif #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) @@ -315,6 +346,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#ifdef CONFIG_T1024RDB /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) @@ -336,6 +368,7 @@ unsigned long get_board_ddr_clk(void); FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS2_FTIM3 0x0 +#endif /* NAND Flash on IFC */ #define CONFIG_NAND_FSL_IFC @@ -352,6 +385,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#if defined(CONFIG_T1024RDB) #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ @@ -359,9 +393,17 @@ unsigned long get_board_ddr_clk(void); | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ + | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#endif #define CONFIG_SYS_NAND_ONFI_DETECTION - /* ONFI NAND Flash mode0 Timing Params */ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ @@ -381,8 +423,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) - #if defined(CONFIG_NAND) #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -536,7 +576,11 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_FSL_ESPI #define CONFIG_SPI_FLASH +#if defined(CONFIG_T1024RDB) #define CONFIG_SPI_FLASH_STMICRO +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SPI_FLASH_SPANSION +#endif #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_BAR #define CONFIG_SF_DEFAULT_SPEED 10000000 @@ -736,8 +780,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#if defined(CONFIG_T1024RDB) #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) +#endif #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -762,10 +811,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PHYLIB_10G #define CONFIG_PHY_REALTEK #define CONFIG_PHY_AQUANTIA +#if defined(CONFIG_T1024RDB) #define RGMII_PHY1_ADDR 0x2 #define RGMII_PHY2_ADDR 0x6 -#define SGMII_PHY1_ADDR 0x2 +#define SGMII_AQR_PHY_ADDR 0x2 #define FM1_10GEC1_PHY_ADDR 0x1 +#elif defined(CONFIG_T1023RDB) +#define RGMII_PHY1_ADDR 0x1 +#define SGMII_RTK_PHY_ADDR 0x3 +#define SGMII_AQR_PHY_ADDR 0x2 +#endif #endif #ifdef CONFIG_FMAN_ENET @@ -855,21 +910,23 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 #define __USB_PHY_TYPE utmi #ifdef CONFIG_PPC_T1024 -#define CONFIG_BOARDNAME "t1024rdb" +#define CONFIG_BOARDNAME t1024rdb +#define BANK_INTLV cs0_cs1 #else -#define CONFIG_BOARDNAME "t1023rdb" +#define CONFIG_BOARDNAME t1023rdb +#define BANK_INTLV null #endif #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1\0" \ + "bank_intlv=" __stringify(BANK_INTLV) "\0" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ -- cgit v1.2.1 From 5a8dbdc6b4b8b4b17c807c9bb23807cdc66f6feb Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Wed, 22 Apr 2015 13:57:00 +0800 Subject: mmc: fsl_esdhc: Add adapter card type identification support Add adapter card type identification support by reading FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function, define CONFIG_FSL_ESDHC_ADAPTER_IDENT. Signed-off-by: Yangbo Lu Cc: York Sun Cc: Pantelis Antoniou [York Sun: resolve conflicts in README.fsl-esdhc] Reviewed-by: York Sun --- include/fsl_esdhc.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 41bf05be4c..bec8a0e4cc 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -16,6 +16,10 @@ /* needed for the mmc_cfg definition */ #include +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT +#include "../board/freescale/common/qixis.h" +#endif + /* FSL eSDHC-specific constants */ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x08000000 -- cgit v1.2.1 From b46cf1b178c7e79240dd8ddb700b3394afbb4192 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Wed, 22 Apr 2015 13:57:21 +0800 Subject: powerpc/t2080qds: enable eSDHC adapter card type identification Enable eSDHC adapter card type identification and this will do some corresponding operations and set 'adapter-type' property for device tree according SDHC Card ID. Signed-off-by: Yangbo Lu Cc: York Sun Cc: Pantelis Antoniou Reviewed-by: York Sun --- include/configs/T208xQDS.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 6adcb22521..cdd4510777 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -764,6 +764,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_FSL_ESDHC_ADAPTER_IDENT #endif -- cgit v1.2.1 From 2d9ca2c72c0fce33052f78f02cdc8ad0a5cf4292 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Wed, 22 Apr 2015 13:57:40 +0800 Subject: mmc: fsl_esdhc: Add peripheral clock support The SD clock could be generated by platform clock or peripheral clock for some platforms. This patch adds peripheral clock support for T1024/T1040/T2080. To enable it, define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK. Signed-off-by: Yangbo Lu Cc: York Sun Cc: Pantelis Antoniou Reviewed-by: York Sun --- include/e500.h | 1 + include/fsl_esdhc.h | 4 ++++ 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/include/e500.h b/include/e500.h index 255f46bf1e..1acf7784df 100644 --- a/include/e500.h +++ b/include/e500.h @@ -18,6 +18,7 @@ typedef struct unsigned long freq_ddrbus; unsigned long freq_localbus; unsigned long freq_qe; + unsigned long freq_sdhc; #ifdef CONFIG_SYS_DPAA_FMAN unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; #endif diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index bec8a0e4cc..0d00b7dfdb 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -78,6 +78,9 @@ #define IRQSTATEN_TC (0x00000002) #define IRQSTATEN_CC (0x00000001) +#define ESDHCCTL 0x0002e40c +#define ESDHCCTL_PCS (0x00080000) + #define PRSSTAT 0x0002e024 #define PRSSTAT_DAT0 (0x01000000) #define PRSSTAT_CLSL (0x00800000) @@ -86,6 +89,7 @@ #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BWEN (0x00000400) +#define PRSSTAT_SDSTB (0X00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) #define PRSSTAT_CIDHB (0x00000001) -- cgit v1.2.1 From 3285e6cbcc1b848a99f4113f807812c14ed10dea Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Wed, 22 Apr 2015 13:57:56 +0800 Subject: powerpc/t2080qds: enable eSDHC peripheral clock support Enable eSDHC peripheral clock support. u-boot and linux will use SD clock generated by peripheral clock instead of platform clock. Signed-off-by: Yangbo Lu Cc: York Sun Cc: Pantelis Antoniou Reviewed-by: York Sun --- include/configs/T208xQDS.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index cdd4510777..bad3613b51 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -757,6 +757,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_MMC #define CONFIG_CMD_MMC #define CONFIG_FSL_ESDHC +#define define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -- cgit v1.2.1 From 8b0044ff5942943eaa49935f49d5006b346a60f8 Mon Sep 17 00:00:00 2001 From: Oleksandr G Zhadan Date: Wed, 29 Apr 2015 16:57:39 -0400 Subject: powerpc/mpc85xx: Add board support for ucp1020 New QorIQ p1020 based board support from Arcturus Networks Inc. http://www.arcturusnetworks.com/products/ucp1020/ Signed-off-by: Michael Durrant Signed-off-by: Oleksandr G Zhadan [York Sun: remove patman tags from commit message] Reviewed-by: York Sun --- include/configs/UCP1020.h | 1027 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 1027 insertions(+) create mode 100644 include/configs/UCP1020.h (limited to 'include') diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h new file mode 100644 index 0000000000..57e0c6c747 --- /dev/null +++ b/include/configs/UCP1020.h @@ -0,0 +1,1027 @@ +/* + * Copyright 2013-2015 Arcturus Networks, Inc. + * http://www.arcturusnetworks.com/products/ucp1020/ + * based on include/configs/p1_p2_rdb_pc.h + * original copyright follows: + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * QorIQ uCP1020-xx boards configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_FSL_ELBC +#define CONFIG_PCI +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#if defined(CONFIG_TARTGET_UCP1020T1) + +#define CONFIG_UCP1020_REV_1_3 + +#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" +#define CONFIG_P1020 + +#define CONFIG_TSEC_ENET +#define CONFIG_TSEC1 +#define CONFIG_TSEC3 +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF +#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE +#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD +#define CONFIG_IPADDR 10.80.41.229 +#define CONFIG_SERVERIP 10.80.41.227 +#define CONFIG_NETMASK 255.255.252.0 +#define CONFIG_ETHPRIME "eTSEC3" + +#ifndef CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH y +#endif +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#define CONFIG_MMC +#define CONFIG_SYS_L2_SIZE (256 << 10) + +#define CONFIG_LAST_STAGE_INIT + +#if !defined(CONFIG_DONGLE) +#define CONFIG_SILENT_CONSOLE +#endif + +#endif + +#if defined(CONFIG_TARGET_UCP1020) + +#define CONFIG_UCP1020 +#define CONFIG_UCP1020_REV_1_3 + +#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" +#define CONFIG_P1020 + +#define CONFIG_TSEC_ENET +#define CONFIG_TSEC1 +#define CONFIG_TSEC2 +#define CONFIG_TSEC3 +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF +#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE +#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD +#define CONFIG_IPADDR 192.168.1.81 +#define CONFIG_IPADDR1 192.168.1.82 +#define CONFIG_IPADDR2 192.168.1.83 +#define CONFIG_SERVERIP 192.168.1.80 +#define CONFIG_GATEWAYIP 102.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_ETHPRIME "eTSEC1" + +#ifndef CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH y +#endif +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#define CONFIG_MMC +#define CONFIG_SYS_L2_SIZE (256 << 10) + +#define CONFIG_LAST_STAGE_INIT + +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RAMBOOT_SDCARD +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif +#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 +/* #define CONFIG_MPC85xx */ + +#define CONFIG_MP + +#define CONFIG_FSL_LAW + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_CMD_SATA +#define CONFIG_SATA_SIL +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_LIBATA +#define CONFIG_LBA48 + +#define CONFIG_SYS_CLK_FREQ 66666666 +#define CONFIG_DDR_CLK_FREQ 66666666 + +#define CONFIG_HWCONFIG + +#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ +#define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */ +#define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */ +/* + * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details). + * there will be one entry in this array for each two (dummy) sensors in + * CONFIG_DTT_SENSORS. + * + * For uCP1020 module: + * - only one ADM1021/NCT72 + * - i2c addr 0x41 + * - conversion rate 0x02 = 0.25 conversions/second + * - ALERT output disabled + * - local temp sensor enabled, min set to 0 deg, max set to 85 deg + * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg + */ +#define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \ + 0x02, 0, 1, 0, 85, 1, 0, 85} } + +#define CONFIG_CMD_DTT + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE +#define CONFIG_BTB + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x1fffffff +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k + SPL code*/ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + +/* DDR Setup */ +#define CONFIG_DDR_ECC_ENABLE +#define CONFIG_SYS_FSL_DDR3 +#ifndef CONFIG_DDR_ECC_ENABLE +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_DDR_SPD +#endif +#define CONFIG_SYS_SPD_BUS_NUM 1 +#undef CONFIG_FSL_DDR_INTERACTIVE + +#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +/* Default settings for DDR3 */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 + +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 + +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#ifdef CONFIG_DDR_ECC_ENABLE +#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ +#else +#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ +#endif +#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5 0x03402400 + +#define CONFIG_SYS_DDR_TIMING_3 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0 0x00330004 +#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 +#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF +#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 +#define CONFIG_SYS_DDR_MODE_1 0x40461520 +#define CONFIG_SYS_DDR_MODE_2 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL 0x0C300000 + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable + * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) + * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 + * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable + * (early boot only) + * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * Local Bus Definitions + */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ +#define CONFIG_SYS_FLASH_BASE 0xec000000 + +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ + | BR_PS_16 | BR_V) + +#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +/* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +/* Size of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ + +#define CONFIG_SYS_PMC_BASE 0xff980000 +#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE +#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ + BR_PS_8 | BR_V) +#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ + OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ + OR_GPCM_EAD) + +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#ifdef CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#endif + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } +#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ + +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_RTC_DS1337_NOOSC +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 +#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C +#define CONFIG_SYS_I2C_IDT6V49205B 0x69 + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_HARD_SPI +#define CONFIG_FSL_ESPI + +#define CONFIG_SPI_FLASH_SST 1 +#define CONFIG_SPI_FLASH_STMICRO 1 +#define CONFIG_SPI_FLASH_WINBOND 1 +#define CONFIG_CMD_SF 1 +#define CONFIG_CMD_SPI 1 +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +#if defined(CONFIG_PCI) +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 1, Slot 2, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* + * Environment + */ +#ifdef CONFIG_ENV_FIT_UCBOOT + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ + +#else + +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 + +#ifdef CONFIG_RAMBOOT_SPIFLASH + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x3000 /* 12KB */ +#define CONFIG_ENV_OFFSET 0x2000 /* 8KB */ +#define CONFIG_ENV_SECT_SIZE 0x1000 + +#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#endif + +#elif defined(CONFIG_RAMBOOT_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#elif defined(CONFIG_SYS_RAMBOOT) +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 + +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000) +#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#endif + +#endif + +#endif /* CONFIG_ENV_FIT_UCBOOT */ + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_CRAMFS +#define CONFIG_CRAMFS_CMDLINE + +/* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) +#define CONFIG_USB_EHCI + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#endif +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_MMC_SPI +#define CONFIG_CMD_MMC_SPI +#define CONFIG_GENERIC_MMC +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Misc Extra Settings */ +#define CONFIG_CMD_GPIO 1 +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "B$ " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) + +#if defined(CONFIG_UCP1020_REV_1_2) +#define CONFIG_PHY_MICREL_KSZ9021 +#elif defined(CONFIG_UCP1020_REV_1_3) +#define CONFIG_PHY_MICREL_KSZ9031 +#else +#error "UCP1020 module revision is not defined !!!" +#endif + +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SERVERIP + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 4 +#define TSEC2_PHY_ADDR 0 +#define TSEC2_PHY_ADDR_SGMII 0x00 +#define TSEC3_PHY_ADDR 6 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#endif + +#define CONFIG_HOSTNAME UCP1020 +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +/* + * Autobooting + */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "\x1b" +#define DEBUG_BOOTKEYS 0 +#undef CONFIG_AUTOBOOT_DELAY_STR +#undef CONFIG_BOOTARGS +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ + "press \"\" to stop\n", bootdelay + +#define CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#if defined(CONFIG_DONGLE) + +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ +#define CONFIG_EXTRA_ENV_SETTINGS \ +"bootcmd=run prog_spi_mbrbootcramfs\0" \ +"bootfile=uImage\0" \ +"consoledev=ttyS0\0" \ +"cramfsfile=image.cramfs\0" \ +"dtbaddr=0x00c00000\0" \ +"dtbfile=image.dtb\0" \ +"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ +"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ +"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ +"fileaddr=0x01000000\0" \ +"filesize=0x00080000\0" \ +"flashmbr=sf probe 0; " \ + "tftp $loadaddr $mbr; " \ + "sf erase $mbr_offset +$filesize; " \ + "sf write $loadaddr $mbr_offset $filesize\0" \ +"flashrecovery=tftp $recoveryaddr $cramfsfile; " \ + "protect off $nor_recoveryaddr +$filesize; " \ + "erase $nor_recoveryaddr +$filesize; " \ + "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ + "protect on $nor_recoveryaddr +$filesize\0 " \ +"flashuboot=tftp $ubootaddr $ubootfile; " \ + "protect off $nor_ubootaddr +$filesize; " \ + "erase $nor_ubootaddr +$filesize; " \ + "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ + "protect on $nor_ubootaddr +$filesize\0 " \ +"flashworking=tftp $workingaddr $cramfsfile; " \ + "protect off $nor_workingaddr +$filesize; " \ + "erase $nor_workingaddr +$filesize; " \ + "cp.b $workingaddr $nor_workingaddr $filesize; " \ + "protect on $nor_workingaddr +$filesize\0 " \ +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ +"kerneladdr=0x01100000\0" \ +"kernelfile=uImage\0" \ +"loadaddr=0x01000000\0" \ +"mbr=uCP1020d.mbr\0" \ +"mbr_offset=0x00000000\0" \ +"mmbr=uCP1020Quiet.mbr\0" \ +"mmcpart=0:2\0" \ +"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ + "mmc erase 1 1; " \ + "mmc write $loadaddr 1 1\0" \ +"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ + "mmc erase 0x40 0x400; " \ + "mmc write $loadaddr 0x40 0x400\0" \ +"netdev=eth0\0" \ +"nor_recoveryaddr=0xEC0A0000\0" \ +"nor_ubootaddr=0xEFF80000\0" \ +"nor_workingaddr=0xECFA0000\0" \ +"norbootrecovery=setenv bootargs $recoverybootargs" \ + " console=$consoledev,$baudrate $othbootargs; " \ + "run norloadrecovery; " \ + "bootm $kerneladdr - $dtbaddr\0" \ +"norbootworking=setenv bootargs $workingbootargs" \ + " console=$consoledev,$baudrate $othbootargs; " \ + "run norloadworking; " \ + "bootm $kerneladdr - $dtbaddr\0" \ +"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ + "setenv cramfsaddr $nor_recoveryaddr; " \ + "cramfsload $dtbaddr $dtbfile; " \ + "cramfsload $kerneladdr $kernelfile\0" \ +"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ + "setenv cramfsaddr $nor_workingaddr; " \ + "cramfsload $dtbaddr $dtbfile; " \ + "cramfsload $kerneladdr $kernelfile\0" \ +"prog_spi_mbr=run spi__mbr\0" \ +"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ +"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ + "run spi__cramfs\0" \ +"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ + " console=$consoledev,$baudrate $othbootargs; " \ + "tftp $rootfsaddr $rootfsfile; " \ + "tftp $loadaddr $kernelfile; " \ + "tftp $dtbaddr $dtbfile; " \ + "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ +"ramdisk_size=120000\0" \ +"ramdiskfile=rootfs.ext2.gz.uboot\0" \ +"recoveryaddr=0x02F00000\0" \ +"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ +"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ + "mw.l 0xffe0f008 0x00400000\0" \ +"rootfsaddr=0x02F00000\0" \ +"rootfsfile=rootfs.ext2.gz.uboot\0" \ +"rootpath=/opt/nfsroot\0" \ +"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ + "protect off 0xeC000000 +$filesize; " \ + "erase 0xEC000000 +$filesize; " \ + "cp.b $loadaddr 0xEC000000 $filesize; " \ + "cmp.b $loadaddr 0xEC000000 $filesize; " \ + "protect on 0xeC000000 +$filesize\0" \ +"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ + "protect off 0xeFF80000 +$filesize; " \ + "erase 0xEFF80000 +$filesize; " \ + "cp.b $loadaddr 0xEFF80000 $filesize; " \ + "cmp.b $loadaddr 0xEFF80000 $filesize; " \ + "protect on 0xeFF80000 +$filesize\0" \ +"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ + "sf probe 0; sf erase 0x8000 +$filesize; " \ + "sf write $loadaddr 0x8000 $filesize\0" \ +"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ + "protect off 0xec0a0000 +$filesize; " \ + "erase 0xeC0A0000 +$filesize; " \ + "cp.b $loadaddr 0xeC0A0000 $filesize; " \ + "protect on 0xec0a0000 +$filesize\0" \ +"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ + "sf probe 1; sf erase 0 +$filesize; " \ + "sf write $loadaddr 0 $filesize\0" \ +"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ + "sf probe 0; sf erase 0 +$filesize; " \ + "sf write $loadaddr 0 $filesize\0" \ +"tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ +"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ +"ubootaddr=0x01000000\0" \ +"ubootfile=u-boot.bin\0" \ +"ubootd=u-boot4dongle.bin\0" \ +"upgrade=run flashworking\0" \ +"usb_phy_type=ulpi\0 " \ +"workingaddr=0x02F00000\0" \ +"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" + +#else + +#if defined(CONFIG_UCP1020T1) + +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */ +#define CONFIG_EXTRA_ENV_SETTINGS \ +"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ +"bootfile=uImage\0" \ +"consoledev=ttyS0\0" \ +"cramfsfile=image.cramfs\0" \ +"dtbaddr=0x00c00000\0" \ +"dtbfile=image.dtb\0" \ +"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ +"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ +"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ +"fileaddr=0x01000000\0" \ +"filesize=0x00080000\0" \ +"flashmbr=sf probe 0; " \ + "tftp $loadaddr $mbr; " \ + "sf erase $mbr_offset +$filesize; " \ + "sf write $loadaddr $mbr_offset $filesize\0" \ +"flashrecovery=tftp $recoveryaddr $cramfsfile; " \ + "protect off $nor_recoveryaddr +$filesize; " \ + "erase $nor_recoveryaddr +$filesize; " \ + "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ + "protect on $nor_recoveryaddr +$filesize\0 " \ +"flashuboot=tftp $ubootaddr $ubootfile; " \ + "protect off $nor_ubootaddr +$filesize; " \ + "erase $nor_ubootaddr +$filesize; " \ + "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ + "protect on $nor_ubootaddr +$filesize\0 " \ +"flashworking=tftp $workingaddr $cramfsfile; " \ + "protect off $nor_workingaddr +$filesize; " \ + "erase $nor_workingaddr +$filesize; " \ + "cp.b $workingaddr $nor_workingaddr $filesize; " \ + "protect on $nor_workingaddr +$filesize\0 " \ +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ +"kerneladdr=0x01100000\0" \ +"kernelfile=uImage\0" \ +"loadaddr=0x01000000\0" \ +"mbr=uCP1020.mbr\0" \ +"mbr_offset=0x00000000\0" \ +"netdev=eth0\0" \ +"nor_recoveryaddr=0xEC0A0000\0" \ +"nor_ubootaddr=0xEFF80000\0" \ +"nor_workingaddr=0xECFA0000\0" \ +"norbootrecovery=setenv bootargs $recoverybootargs" \ + " console=$consoledev,$baudrate $othbootargs; " \ + "run norloadrecovery; " \ + "bootm $kerneladdr - $dtbaddr\0" \ +"norbootworking=setenv bootargs $workingbootargs" \ + " console=$consoledev,$baudrate $othbootargs; " \ + "run norloadworking; " \ + "bootm $kerneladdr - $dtbaddr\0" \ +"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ + "setenv cramfsaddr $nor_recoveryaddr; " \ + "cramfsload $dtbaddr $dtbfile; " \ + "cramfsload $kerneladdr $kernelfile\0" \ +"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ + "setenv cramfsaddr $nor_workingaddr; " \ + "cramfsload $dtbaddr $dtbfile; " \ + "cramfsload $kerneladdr $kernelfile\0" \ +"othbootargs=quiet\0" \ +"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ + " console=$consoledev,$baudrate $othbootargs; " \ + "tftp $rootfsaddr $rootfsfile; " \ + "tftp $loadaddr $kernelfile; " \ + "tftp $dtbaddr $dtbfile; " \ + "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ +"ramdisk_size=120000\0" \ +"ramdiskfile=rootfs.ext2.gz.uboot\0" \ +"recoveryaddr=0x02F00000\0" \ +"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ +"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ + "mw.l 0xffe0f008 0x00400000\0" \ +"rootfsaddr=0x02F00000\0" \ +"rootfsfile=rootfs.ext2.gz.uboot\0" \ +"rootpath=/opt/nfsroot\0" \ +"silent=1\0" \ +"tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ +"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ +"ubootaddr=0x01000000\0" \ +"ubootfile=u-boot.bin\0" \ +"upgrade=run flashworking\0" \ +"workingaddr=0x02F00000\0" \ +"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" + +#else /* For Arcturus Modules */ + +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */ +#define CONFIG_EXTRA_ENV_SETTINGS \ +"bootcmd=run norkernel\0" \ +"bootfile=uImage\0" \ +"consoledev=ttyS0\0" \ +"dtbaddr=0x00c00000\0" \ +"dtbfile=image.dtb\0" \ +"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ +"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ +"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ +"fileaddr=0x01000000\0" \ +"filesize=0x00080000\0" \ +"flashmbr=sf probe 0; " \ + "tftp $loadaddr $mbr; " \ + "sf erase $mbr_offset +$filesize; " \ + "sf write $loadaddr $mbr_offset $filesize\0" \ +"flashuboot=tftp $loadaddr $ubootfile; " \ + "protect off $nor_ubootaddr0 +$filesize; " \ + "erase $nor_ubootaddr0 +$filesize; " \ + "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ + "protect on $nor_ubootaddr0 +$filesize; " \ + "protect off $nor_ubootaddr1 +$filesize; " \ + "erase $nor_ubootaddr1 +$filesize; " \ + "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ + "protect on $nor_ubootaddr1 +$filesize\0 " \ +"format0=protect off $part0base +$part0size; " \ + "erase $part0base +$part0size\0" \ +"format1=protect off $part1base +$part1size; " \ + "erase $part1base +$part1size\0" \ +"format2=protect off $part2base +$part2size; " \ + "erase $part2base +$part2size\0" \ +"format3=protect off $part3base +$part3size; " \ + "erase $part3base +$part3size\0" \ +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ +"kerneladdr=0x01100000\0" \ +"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ +"kernelfile=uImage\0" \ +"loadaddr=0x01000000\0" \ +"mbr=uCP1020.mbr\0" \ +"mbr_offset=0x00000000\0" \ +"netdev=eth0\0" \ +"nor_ubootaddr0=0xEC000000\0" \ +"nor_ubootaddr1=0xEFF80000\0" \ +"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ + "run norkernelload; " \ + "bootm $kerneladdr - $dtbaddr\0" \ +"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ + "setenv cramfsaddr $part0base; " \ + "cramfsload $dtbaddr $dtbfile; " \ + "cramfsload $kerneladdr $kernelfile\0" \ +"part0base=0xEC100000\0" \ +"part0size=0x00700000\0" \ +"part1base=0xEC800000\0" \ +"part1size=0x02000000\0" \ +"part2base=0xEE800000\0" \ +"part2size=0x00800000\0" \ +"part3base=0xEF000000\0" \ +"part3size=0x00F80000\0" \ +"partENVbase=0xEC080000\0" \ +"partENVsize=0x00080000\0" \ +"program0=tftp part0-000000.bin; " \ + "protect off $part0base +$filesize; " \ + "erase $part0base +$filesize; " \ + "cp.b $loadaddr $part0base $filesize; " \ + "echo Verifying...; " \ + "cmp.b $loadaddr $part0base $filesize\0" \ +"program1=tftp part1-000000.bin; " \ + "protect off $part1base +$filesize; " \ + "erase $part1base +$filesize; " \ + "cp.b $loadaddr $part1base $filesize; " \ + "echo Verifying...; " \ + "cmp.b $loadaddr $part1base $filesize\0" \ +"program2=tftp part2-000000.bin; " \ + "protect off $part2base +$filesize; " \ + "erase $part2base +$filesize; " \ + "cp.b $loadaddr $part2base $filesize; " \ + "echo Verifying...; " \ + "cmp.b $loadaddr $part2base $filesize\0" \ +"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ + " console=$consoledev,$baudrate $othbootargs; " \ + "tftp $rootfsaddr $rootfsfile; " \ + "tftp $loadaddr $kernelfile; " \ + "tftp $dtbaddr $dtbfile; " \ + "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ +"ramdisk_size=120000\0" \ +"ramdiskfile=rootfs.ext2.gz.uboot\0" \ +"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ + "mw.l 0xffe0f008 0x00400000\0" \ +"rootfsaddr=0x02F00000\0" \ +"rootfsfile=rootfs.ext2.gz.uboot\0" \ +"rootpath=/opt/nfsroot\0" \ +"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ + "sf probe 0; sf erase 0 +$filesize; " \ + "sf write $loadaddr 0 $filesize\0" \ +"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ + "protect off 0xeC000000 +$filesize; " \ + "erase 0xEC000000 +$filesize; " \ + "cp.b $loadaddr 0xEC000000 $filesize; " \ + "cmp.b $loadaddr 0xEC000000 $filesize; " \ + "protect on 0xeC000000 +$filesize\0" \ +"tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ +"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ +"ubootfile=u-boot.bin\0" \ +"upgrade=run flashuboot\0" \ +"usb_phy_type=ulpi\0 " \ +"boot_nfs= " \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr\0" \ +"boot_hd = " \ + "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "usb start;" \ + "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ + "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ + "bootm $loadaddr - $fdtaddr\0" \ +"boot_usb_fat = " \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs " \ + "ramdisk_size=$ramdisk_size;" \ + "usb start;" \ + "fatload usb 0:2 $loadaddr $bootfile;" \ + "fatload usb 0:2 $fdtaddr $fdtfile;" \ + "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ +"boot_usb_ext2 = " \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs " \ + "ramdisk_size=$ramdisk_size;" \ + "usb start;" \ + "ext2load usb 0:4 $loadaddr $bootfile;" \ + "ext2load usb 0:4 $fdtaddr $fdtfile;" \ + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ +"boot_nor = " \ + "setenv bootargs root=/dev/$jffs2nor rw " \ + "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ + "bootm $norbootaddr - $norfdtaddr\0 " \ +"boot_ram = " \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs " \ + "ramdisk_size=$ramdisk_size;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" + +#endif +#endif + +#endif /* __CONFIG_H */ -- cgit v1.2.1