From 3e0529f742e893653848494ffb9f7cd0d91304bf Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 21 Nov 2011 17:10:22 -0600 Subject: powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA controller, so it should be defined in config_mpc85xx.h instead of the various board header files. So now CONFIG_FSL_SATA_V2 is always defined on the P1013, P1022, P2041, P3041, P5010, and P5020. It was already defined for the P1010 and P1014. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- include/configs/P1022DS.h | 1 - include/configs/P2041RDB.h | 5 ++--- include/configs/P3041DS.h | 1 - include/configs/P5020DS.h | 1 - 4 files changed, 2 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 1158fec436..70d751da20 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -345,7 +345,6 @@ /* SATA */ #define CONFIG_LIBATA #define CONFIG_FSL_SATA -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 6d45bb1e8d..f9fe3cf952 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -446,10 +446,9 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_PCI */ /* SATA */ -#define CONFIG_FSL_SATA_V2 -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA #define CONFIG_FSL_SATA +#ifdef CONFIG_FSL_SATA +#define CONFIG_LIBATA #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index 57d5de5b12..98e7a42e5f 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -32,7 +32,6 @@ #define CONFIG_MMC #define CONFIG_NAND_FSL_ELBC -#define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE3 #define CONFIG_PCIE4 #define CONFIG_SYS_DPAA_RMAN diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index a9cee23726..4afc4f16ed 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -32,7 +32,6 @@ #define CONFIG_MMC #define CONFIG_NAND_FSL_ELBC -#define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE3 #define CONFIG_PCIE4 #define CONFIG_SYS_FSL_RAID_ENGINE -- cgit v1.2.1 From f2717b47eac74fe262d89c6d8f6bb5a047a77229 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 22 Nov 2011 09:21:25 -0600 Subject: powerpc/85xx: clean up and document the QE/FMAN microcode macros Several macros are used to identify and locate the microcode binary image that U-boot needs to upload to the QE or Fman. Both the QE and the Fman use the QE Firmware binary format to package their respective microcode data, which is why the same macros are used for both. A given SOC will only have a QE or an Fman, so this is safe. Unfortunately, the current macro definition and usage has inconsistencies. For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address of NAND. There's no way to know by looking at a variable how it's supposed to be used. In the future, the code which uploads QE firmware and Fman firmware will be merged. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- include/configs/MPC8569MDS.h | 3 ++- include/configs/P1023RDS.h | 10 ++++++---- include/configs/P2041RDB.h | 16 ++++++++++------ include/configs/corenet_ds.h | 16 ++++++++++------ include/configs/p1_p2_rdb_pc.h | 5 +++-- 5 files changed, 31 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index ab27b9895a..7a5d86d2b7 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -510,7 +510,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ /* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FW_ADDR 0xfff00000 +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000 /* * BOOTP options diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index 013a6acdca..e057b1f945 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -526,12 +526,14 @@ extern unsigned long get_clock_freq(void); #ifndef CONFIG_NAND /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 #else -#define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000 +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000 #endif -#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index f9fe3cf952..a48055e2c5 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -414,21 +414,25 @@ unsigned long get_board_sys_clk(unsigned long dummy); * env is stored at 0x100000, sector size is 0x10000, ucode is stored after * env, so we got 0x110000. */ -#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000 +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is * about 545KB (1089 blocks), Env is stored after the image, and the env size is * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. */ -#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) #elif defined(CONFIG_NAND) -#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) #else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 #endif -#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index bc0aeebb44..0622b9fcfd 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -474,21 +474,25 @@ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after * env, so we got 0x110000. */ -#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000 +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is * about 545KB (1089 blocks), Env is stored after the image, and the env size is * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. */ -#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) #elif defined(CONFIG_NAND) -#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) #else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 #endif -#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 5a69902f89..8e8fa163b8 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -677,8 +677,9 @@ #ifdef CONFIG_QE /* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FW_ADDR 0xefec0000 -#define CONFIG_SYS_QE_FW_LENGTH 0x10000 +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #endif /* CONFIG_QE */ #ifdef CONFIG_P1025RDB -- cgit v1.2.1 From ae6b03fefc1a8b27d834ef12e0a586f4237fdb1f Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Tue, 22 Nov 2011 16:51:13 +0800 Subject: powerpc/p3060qds: Add board related support for P3060QDS platform The P3060QDS is a Freescale reference board for the six-core P3060 SOC. P3060QDS Board Overview: Memory subsystem: - 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus) - 128M Bytes NOR flash single-chip memory - 16M Bytes SPI flash - 8K Bytes AT24C64 I2C EEPROM for RCW Ethernet: - Eight Ethernet controllers (4x1G + 4x1G/2.5G) - Three VSC8641 PHYs on board (2xRGMII + 1xMII) - Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3 PCIe: Two PCI Express 2.0 controllers/ports USB: Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board I2C: Four I2C controllers UART: Supports two dUARTs up to 115200 bps for console RapidIO: Two RapidIO, sRIO1 and sRIO2 Signed-off-by: Shengzhou Liu Signed-off-by: York Sun Signed-off-by: Kumar Gala --- include/configs/P3060QDS.h | 48 ++++++++++++++++++++++++++++++++++++++++++++ include/configs/corenet_ds.h | 6 +++++- 2 files changed, 53 insertions(+), 1 deletion(-) create mode 100644 include/configs/P3060QDS.h (limited to 'include') diff --git a/include/configs/P3060QDS.h b/include/configs/P3060QDS.h new file mode 100644 index 0000000000..8006547000 --- /dev/null +++ b/include/configs/P3060QDS.h @@ -0,0 +1,48 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * P3060 QDS board configuration file + */ +#define CONFIG_P3060QDS +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_P3060 +#define CONFIG_FSL_QIXIS + +#define CONFIG_NAND_FSL_ELBC + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SPI_FLASH_EON +#define CONFIG_SPI_FLASH_SST + +#include "corenet_ds.h" + +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F + +/* There is a PCA9547 8-channel I2C-bus multiplexer on P3060QDS board */ +#define CONFIG_I2C_MUX +#define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 0622b9fcfd..7925b95838 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -168,7 +168,11 @@ #define CONFIG_DDR_SPD #define CONFIG_FSL_DDR3 +#ifdef CONFIG_P3060QDS +#define CONFIG_SYS_SPD_BUS_NUM 0 +#else #define CONFIG_SYS_SPD_BUS_NUM 1 +#endif #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ @@ -641,7 +645,7 @@ #define CONFIG_BAUDRATE 115200 -#if defined(CONFIG_P4080DS) +#if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS) #define __USB_PHY_TYPE ulpi #else #define __USB_PHY_TYPE utmi -- cgit v1.2.1 From 2f3a71f235f442beb9419cee94ef6888b24f8259 Mon Sep 17 00:00:00 2001 From: "Ira W. Snyder" Date: Mon, 21 Nov 2011 13:20:33 -0800 Subject: mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification Newer JEDEC DDR3 SPD Specifications define several additional values for the DDR3 module_type field which were undefined when this code was written. Update the code to handle the newer module types. Signed-off-by: Ira W. Snyder Cc: York Sun Signed-off-by: Kumar Gala --- include/ddr_spd.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/ddr_spd.h b/include/ddr_spd.h index 40a0463560..a9230b9108 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -325,5 +325,12 @@ extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); #define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04) #define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05) #define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06) +#define DDR3_SPD_MODULETYPE_MINI_CDIMM (0x07) +#define DDR3_SPD_MODULETYPE_72B_SO_UDIMM (0x08) +#define DDR3_SPD_MODULETYPE_72B_SO_RDIMM (0x09) +#define DDR3_SPD_MODULETYPE_72B_SO_CDIMM (0x0A) +#define DDR3_SPD_MODULETYPE_LRDIMM (0x0B) +#define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C) +#define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D) #endif /* _DDR_SPD_H_ */ -- cgit v1.2.1 From 9839709ea3df89f6021034508f48b97cab33ebb8 Mon Sep 17 00:00:00 2001 From: "Ira W. Snyder" Date: Wed, 23 Nov 2011 08:25:58 -0800 Subject: mpc85xx: support for Freescale COM Express P2020 This adds support for the Freescale COM Express P2020 board. This board is similar to the P1_P2_RDB, but has some extra (as well as missing) peripherals. Unlike all other mpc85xx boards, it uses a watchdog timeout to reset. Using the HRESET_REQ register does not work. This board has no NOR flash, and can only be booted via SD or SPI. This procedure is documented in Freescale Document Number AN3659 "Booting from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated Processor Reference Manual" (section 4.5). Signed-off-by: Ira W. Snyder Signed-off-by: Kumar Gala --- include/configs/P2020COME.h | 576 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 576 insertions(+) create mode 100644 include/configs/P2020COME.h (limited to 'include') diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h new file mode 100644 index 0000000000..db88b683ea --- /dev/null +++ b/include/configs/P2020COME.h @@ -0,0 +1,576 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* The P2020COME board is only booted via the Freescale On-Chip ROM */ +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC + +#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc + +#ifdef CONFIG_SDCARD +#define CONFIG_RAMBOOT_SDCARD 1 +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH 1 +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/ +#define CONFIG_P2020 1 +#define CONFIG_P2020COME 1 +#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ +#define CONFIG_MP + +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#if defined(CONFIG_PCI) +#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ +#define CONFIG_PCIE3 1 /* PCIE controller 3 (slot 3) */ + +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#endif /* #if defined(CONFIG_PCI) */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_PCI) +#define CONFIG_E1000 1 /* E1000 pci Ethernet card */ +#endif + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_ddr_clk(unsigned long dummy); +extern unsigned long get_board_sys_clk(unsigned long dummy); +#endif + +/* + * For P2020COME DDRCLK and SYSCLK are from the same oscillator + * For DA phase the SYSCLK is 66MHz + * For EA phase the SYSCLK is 100MHz + */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) + +#define CONFIG_HWCONFIG + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch prediction */ + +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x1fffffff +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + + + + + + + + /* + * Config the L2 Cache as L2 SRAM + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull +#else +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#endif +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR \ + + CONFIG_SYS_L2_SIZE) + +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* DDR Setup */ +#define CONFIG_FSL_DDR3 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD + +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +#define CONFIG_SYS_SDRAM_SIZE 2048ULL /* DDR size on P2020COME */ +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d +#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 +#define CONFIG_SYS_DDR_SBE 0x00ff0000 + +#define CONFIG_SYS_SPD_BUS_NUM 1 +#define SPD_EEPROM_ADDRESS 0x53 + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR3 2G Cacheable + * 0x8000_0000 0x9fff_ffff PCI Express 3 Mem 1G non-cacheable + * 0xa000_0000 0xbfff_ffff PCI Express 2 Mem 1G non-cacheable + * 0xc000_0000 0xdfff_ffff PCI Express 1 Mem 1G non-cacheable + * 0xffc1_0000 0xffc1_ffff PCI Express 3 IO 64K non-cacheable + * 0xffc2_0000 0xffc2_ffff PCI Express 2 IO 64K non-cacheable + * 0xffc3_0000 0xffc3_ffff PCI Express 1 IO 64K non-cacheable + * + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * Local Bus Definitions + */ + +/* There is no NOR Flash on P2020COME */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_HWCONFIG + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* the assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * I2C2 EEPROM + */ +#define CONFIG_ID_EEPROM +#ifdef CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#endif +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR2 0x18 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#if defined(CONFIG_PCI) + +/* controller 3, Slot 3, tgtid 3, Base address 8000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc10000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP +#undef CONFIG_RTL8139 + +#ifdef CONFIG_RTL8139 +/* This macro is used by RTL8139 but not defined in PPC architecture */ +#define KSEG1ADDR(x) (x) +#define _IO_BASE 0x00000000 +#endif + + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 2 +#define TSEC3_PHY_ADDR 1 + +#undef CONFIG_VSC7385_ENET + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#if defined(CONFIG_RAMBOOT_SDCARD) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_RAMBOOT_SPIFLASH) + #define CONFIG_ENV_IS_IN_SPI_FLASH + #define CONFIG_ENV_SPI_BUS 0 + #define CONFIG_ENV_SPI_CS 0 + #define CONFIG_ENV_SPI_MAX_HZ 10000000 + #define CONFIG_ENV_SPI_MODE 0 + #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ + #define CONFIG_ENV_SECT_SIZE 0x10000 + #define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_MMC 1 + +#ifdef CONFIG_MMC +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_FSL_ESDHC +#define CONFIG_GENERIC_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#endif /* CONFIG_MMC */ + +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#define CONFIG_HAS_FSL_DR_USB +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Misc Extra Settings */ +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 +#define CONFIG_CMD_DHCP 1 + +#define CONFIG_CMD_DATE 1 +#define CONFIG_RTC_M41T62 1 +#define CONFIG_SYS_RTC_BUS_NUM 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#endif + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ecc=on\0" \ + "bootcmd=run sdboot\0" \ + "sdboot=setenv bootargs root=/dev/mmcblk0p2 rw " \ + "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\ + "$othbootargs; mmcinfo; " \ + "ext2load mmc 0:2 $loadaddr /boot/$bootfile; " \ + "ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; " \ + "bootm $loadaddr - $fdtaddr\0" \ + "sdfatboot=setenv bootargs root=/dev/ram rw " \ + "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\ + "$othbootargs; mmcinfo; " \ + "fatload mmc 0:1 $loadaddr $bootfile; " \ + "fatload mmc 0:1 $fdtaddr $fdtfile; " \ + "fatload mmc 0:1 $ramdiskaddr $ramdiskfile; " \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + "usbboot=setenv bootargs root=/dev/sda1 rw " \ + "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\ + "$othbootargs; " \ + "usb start; " \ + "ext2load usb 0:1 $loadaddr /boot/$bootfile; " \ + "ext2load usb 0:1 $fdtaddr /boot/$fdtfile; " \ + "bootm $loadaddr - $fdtaddr\0" \ + "usbfatboot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start; " \ + "fatload usb 0:2 $loadaddr $bootfile; " \ + "fatload usb 0:2 $fdtaddr $fdtfile; " \ + "fatload usb 0:2 $ramdiskaddr $ramdiskfile; " \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + "usbext2boot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start; " \ + "ext2load usb 0:4 $loadaddr $bootfile; " \ + "ext2load usb 0:4 $fdtaddr $fdtfile; " \ + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile; " \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + "upgradespi=sf probe 0; " \ + "setenv startaddr 0; " \ + "setenv erasesize a0000; " \ + "tftp 1000000 $tftppath/$uboot_spi; " \ + "sf erase $startaddr $erasesize; " \ + "sf write 1000000 $startaddr $filesize; " \ + "sf erase 100000 120000\0" \ + "clearspienv=sf probe 0;sf erase 100000 20000\0" \ + "othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0" \ + "netdev=eth0\0" \ + "rootdelaysecond=15\0" \ + "uboot_nor=u-boot-nor.bin\0" \ + "uboot_spi=u-boot-p2020.spi\0" \ + "uboot_sd=u-boot-p2020.bin\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs-dev.ext2.img\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=uImage-2.6.32-p2020.dtb\0" \ + "tftppath=p2020\0" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "usb start;" \ + "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ + "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $tftppath/$bootfile;" \ + "tftp $fdtaddr $tftppath/$fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $tftppath/$ramdiskfile;" \ + "tftp $loadaddr $tftppath/$bootfile;" \ + "tftp $fdtaddr $tftppath/$fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#endif /* __CONFIG_H */ -- cgit v1.2.1