From ace3be4f15875d74344336b9754c14274f940969 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 27 May 2016 14:28:04 +0100 Subject: MIPS: Move cache sizes to Kconfig Move details of the L1 cache line sizes & total sizes into Kconfig, defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is introduced to allow platforms to select auto-detection of cache sizes, and it defaults to being enabled if none of the cache sizes are set by the configuration (ie. sizes are all the default 0), and code is adjusted to #ifdef on that rather than on the definition of the sizes (which will always be defined even if 0). Signed-off-by: Paul Burton --- include/configs/ap121.h | 5 ----- include/configs/ap143.h | 5 ----- include/configs/dbau1x00.h | 7 ------- include/configs/pb1x00.h | 6 ------ include/configs/qemu-mips.h | 7 ------- include/configs/qemu-mips64.h | 7 ------- include/configs/tplink_wdr4300.h | 5 ----- include/configs/vct.h | 7 ------- 8 files changed, 49 deletions(-) (limited to 'include') diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 6f69f31503..f069d50130 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -15,11 +15,6 @@ #define CONFIG_SYS_MHZ 200 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 0x8000 -#define CONFIG_SYS_ICACHE_SIZE 0x10000 -#define CONFIG_SYS_CACHELINE_SIZE 32 - #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MALLOC_LEN 0x40000 diff --git a/include/configs/ap143.h b/include/configs/ap143.h index f907c02af9..e45f743936 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -15,11 +15,6 @@ #define CONFIG_SYS_MHZ 325 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 0x8000 -#define CONFIG_SYS_ICACHE_SIZE 0x10000 -#define CONFIG_SYS_CACHELINE_SIZE 32 - #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MALLOC_LEN 0x40000 diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index 68d9e36b19..68ff02509b 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -202,11 +202,4 @@ #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 #endif /* CONFIG_DBAU1550 */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 - #endif /* __CONFIG_H */ diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 869768add0..b907419a59 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -144,12 +144,6 @@ #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 #endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 /* * BOOTP options diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index 246ee0173a..f58fc4c377 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -132,11 +132,4 @@ #define CONFIG_LZMA -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 - #endif /* __CONFIG_H */ diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index 60a3a71fbd..2190d16200 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -132,11 +132,4 @@ #define CONFIG_LZMA -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 - #endif /* __CONFIG_H */ diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 09a69fec09..6273711b1d 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -15,11 +15,6 @@ #define CONFIG_SYS_MHZ 280 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 0x8000 -#define CONFIG_SYS_ICACHE_SIZE 0x10000 -#define CONFIG_SYS_CACHELINE_SIZE 32 - #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MALLOC_LEN 0x40000 diff --git a/include/configs/vct.h b/include/configs/vct.h index 68eb089394..cc5e3546b0 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -203,13 +203,6 @@ #define CONFIG_ENV_SIZE (128 << 10) /* erase size */ #endif /* CONFIG_VCT_ONENAND */ -/* - * Cache Configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 - /* * I2C/EEPROM */ -- cgit v1.2.1