From d5e2d625c74c84aa419ba7fa0c81bad93fc69a60 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Sat, 24 Oct 2009 14:48:33 -0500 Subject: ARM Update mach-types.h From http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm Commit id 0996391139f43d032335b5360db11da62a2cbb39 Signed-off-by: Tom Rix --- include/asm-arm/mach-types.h | 282 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 263 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index 6c1f5ac4e6..bfe8af625f 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -1,9 +1,6 @@ /* - * This was automagically generated from mach-types! + * This was automagically generated from arch/arm/tools/mach-types! * Do NOT edit - * - * Last update: Fri Sep 4 22:16:22 2009 - * */ #ifndef __ASM_ARM_MACH_TYPE_H @@ -1637,7 +1634,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_AML_M8050 1644 #define MACH_TYPE_MX35_3DS 1645 #define MACH_TYPE_MARS 1646 -#define MACH_TYPE_NTOSD_644XA 1647 +#define MACH_TYPE_NEUROS_OSD2 1647 #define MACH_TYPE_BADGER 1648 #define MACH_TYPE_TRIZEPS4WL 1649 #define MACH_TYPE_TRIZEPS5 1650 @@ -1653,7 +1650,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_ZORAN43XX 1660 #define MACH_TYPE_SONIX926 1661 #define MACH_TYPE_CELESTIALSEMI 1662 -#define MACH_TYPE_CC9M2443 1663 +#define MACH_TYPE_CC9M2443JS 1663 #define MACH_TYPE_TW5334 1664 #define MACH_TYPE_HTCARTEMIS 1665 #define MACH_TYPE_NAL_HLITE 1666 @@ -1801,7 +1798,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_RD88F5181L_GE 1812 #define MACH_TYPE_SIFMAIN 1813 #define MACH_TYPE_SAM9_L9261 1814 -#define MACH_TYPE_CC9M2443JS 1815 +#define MACH_TYPE_CC9M2443 1815 #define MACH_TYPE_XARIA300 1816 #define MACH_TYPE_IT9200 1817 #define MACH_TYPE_RD88F5181L_FXO 1818 @@ -2401,6 +2398,25 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_MULTIBUS_MASTER 2416 #define MACH_TYPE_MULTIBUS_PBK 2417 #define MACH_TYPE_TNETV107X 2418 +#define MACH_TYPE_SNAKE 2419 +#define MACH_TYPE_CWMX27 2420 +#define MACH_TYPE_SCH_M480 2421 +#define MACH_TYPE_PLATYPUS 2422 +#define MACH_TYPE_PSS2 2423 +#define MACH_TYPE_DAVINCI_APM150 2424 +#define MACH_TYPE_STR9100 2425 +#define MACH_TYPE_NET5BIG 2426 +#define MACH_TYPE_SEABED9263 2427 +#define MACH_TYPE_MX51_M2ID 2428 +#define MACH_TYPE_OCTVOCPLUS_EB 2429 +#define MACH_TYPE_KLK_FIREFOX 2430 +#define MACH_TYPE_KLK_WIRMA_MODULE 2431 +#define MACH_TYPE_KLK_WIRMA_MMI 2432 +#define MACH_TYPE_SUPERSONIC 2433 +#define MACH_TYPE_LIBERTY 2434 +#define MACH_TYPE_MH355 2435 +#define MACH_TYPE_PC7802 2436 +#define MACH_TYPE_GNET_SGC 2437 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -21866,16 +21882,16 @@ extern unsigned int __machine_arch_type; # define machine_is_mars() (0) #endif -#ifdef CONFIG_MACH_NTOSD_644XA +#ifdef CONFIG_MACH_NEUROS_OSD2 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_NTOSD_644XA +# define machine_arch_type MACH_TYPE_NEUROS_OSD2 # endif -# define machine_is_ntosd_644xa() (machine_arch_type == MACH_TYPE_NTOSD_644XA) +# define machine_is_neuros_osd2() (machine_arch_type == MACH_TYPE_NEUROS_OSD2) #else -# define machine_is_ntosd_644xa() (0) +# define machine_is_neuros_osd2() (0) #endif #ifdef CONFIG_MACH_BADGER @@ -22058,16 +22074,16 @@ extern unsigned int __machine_arch_type; # define machine_is_celestialsemi() (0) #endif -#ifdef CONFIG_MACH_CC9M2443 +#ifdef CONFIG_MACH_CC9M2443JS # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_CC9M2443 +# define machine_arch_type MACH_TYPE_CC9M2443JS # endif -# define machine_is_cc9m2443() (machine_arch_type == MACH_TYPE_CC9M2443) +# define machine_is_cc9m2443js() (machine_arch_type == MACH_TYPE_CC9M2443JS) #else -# define machine_is_cc9m2443() (0) +# define machine_is_cc9m2443js() (0) #endif #ifdef CONFIG_MACH_TW5334 @@ -23834,16 +23850,16 @@ extern unsigned int __machine_arch_type; # define machine_is_sam9_l9261() (0) #endif -#ifdef CONFIG_MACH_CC9M2443JS +#ifdef CONFIG_MACH_CC9M2443 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_CC9M2443JS +# define machine_arch_type MACH_TYPE_CC9M2443 # endif -# define machine_is_cc9m2443js() (machine_arch_type == MACH_TYPE_CC9M2443JS) +# define machine_is_cc9m2443() (machine_arch_type == MACH_TYPE_CC9M2443) #else -# define machine_is_cc9m2443js() (0) +# define machine_is_cc9m2443() (0) #endif #ifdef CONFIG_MACH_XARIA300 @@ -31034,6 +31050,234 @@ extern unsigned int __machine_arch_type; # define machine_is_tnetv107x() (0) #endif +#ifdef CONFIG_MACH_SNAKE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAKE +# endif +# define machine_is_snake() (machine_arch_type == MACH_TYPE_SNAKE) +#else +# define machine_is_snake() (0) +#endif + +#ifdef CONFIG_MACH_CWMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CWMX27 +# endif +# define machine_is_cwmx27() (machine_arch_type == MACH_TYPE_CWMX27) +#else +# define machine_is_cwmx27() (0) +#endif + +#ifdef CONFIG_MACH_SCH_M480 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCH_M480 +# endif +# define machine_is_sch_m480() (machine_arch_type == MACH_TYPE_SCH_M480) +#else +# define machine_is_sch_m480() (0) +#endif + +#ifdef CONFIG_MACH_PLATYPUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PLATYPUS +# endif +# define machine_is_platypus() (machine_arch_type == MACH_TYPE_PLATYPUS) +#else +# define machine_is_platypus() (0) +#endif + +#ifdef CONFIG_MACH_PSS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PSS2 +# endif +# define machine_is_pss2() (machine_arch_type == MACH_TYPE_PSS2) +#else +# define machine_is_pss2() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_APM150 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_APM150 +# endif +# define machine_is_davinci_apm150() (machine_arch_type == MACH_TYPE_DAVINCI_APM150) +#else +# define machine_is_davinci_apm150() (0) +#endif + +#ifdef CONFIG_MACH_STR9100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STR9100 +# endif +# define machine_is_str9100() (machine_arch_type == MACH_TYPE_STR9100) +#else +# define machine_is_str9100() (0) +#endif + +#ifdef CONFIG_MACH_NET5BIG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET5BIG +# endif +# define machine_is_net5big() (machine_arch_type == MACH_TYPE_NET5BIG) +#else +# define machine_is_net5big() (0) +#endif + +#ifdef CONFIG_MACH_SEABED9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SEABED9263 +# endif +# define machine_is_seabed9263() (machine_arch_type == MACH_TYPE_SEABED9263) +#else +# define machine_is_seabed9263() (0) +#endif + +#ifdef CONFIG_MACH_MX51_M2ID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_M2ID +# endif +# define machine_is_mx51_m2id() (machine_arch_type == MACH_TYPE_MX51_M2ID) +#else +# define machine_is_mx51_m2id() (0) +#endif + +#ifdef CONFIG_MACH_OCTVOCPLUS_EB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OCTVOCPLUS_EB +# endif +# define machine_is_octvocplus_eb() (machine_arch_type == MACH_TYPE_OCTVOCPLUS_EB) +#else +# define machine_is_octvocplus_eb() (0) +#endif + +#ifdef CONFIG_MACH_KLK_FIREFOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KLK_FIREFOX +# endif +# define machine_is_klk_firefox() (machine_arch_type == MACH_TYPE_KLK_FIREFOX) +#else +# define machine_is_klk_firefox() (0) +#endif + +#ifdef CONFIG_MACH_KLK_WIRMA_MODULE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KLK_WIRMA_MODULE +# endif +# define machine_is_klk_wirma_module() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MODULE) +#else +# define machine_is_klk_wirma_module() (0) +#endif + +#ifdef CONFIG_MACH_KLK_WIRMA_MMI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KLK_WIRMA_MMI +# endif +# define machine_is_klk_wirma_mmi() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MMI) +#else +# define machine_is_klk_wirma_mmi() (0) +#endif + +#ifdef CONFIG_MACH_SUPERSONIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUPERSONIC +# endif +# define machine_is_supersonic() (machine_arch_type == MACH_TYPE_SUPERSONIC) +#else +# define machine_is_supersonic() (0) +#endif + +#ifdef CONFIG_MACH_LIBERTY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIBERTY +# endif +# define machine_is_liberty() (machine_arch_type == MACH_TYPE_LIBERTY) +#else +# define machine_is_liberty() (0) +#endif + +#ifdef CONFIG_MACH_MH355 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MH355 +# endif +# define machine_is_mh355() (machine_arch_type == MACH_TYPE_MH355) +#else +# define machine_is_mh355() (0) +#endif + +#ifdef CONFIG_MACH_PC7802 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC7802 +# endif +# define machine_is_pc7802() (machine_arch_type == MACH_TYPE_PC7802) +#else +# define machine_is_pc7802() (0) +#endif + +#ifdef CONFIG_MACH_GNET_SGC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_SGC +# endif +# define machine_is_gnet_sgc() (machine_arch_type == MACH_TYPE_GNET_SGC) +#else +# define machine_is_gnet_sgc() (0) +#endif + /* * These have not yet been registered */ -- cgit v1.2.1 From 2d251ccaa90997012e0b1f13bf791df2bf03a144 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Sun, 15 Nov 2009 10:58:06 -0600 Subject: ARM Update mach-types Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit 156171c71a0dc4bce12b4408bb1591f8fe32dc1a Signed-off-by: Tom Rix --- include/asm-arm/mach-types.h | 1213 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 1211 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index bfe8af625f..c7ee24d018 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -2417,6 +2417,99 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_MH355 2435 #define MACH_TYPE_PC7802 2436 #define MACH_TYPE_GNET_SGC 2437 +#define MACH_TYPE_EINSTEIN15 2438 +#define MACH_TYPE_CMPD 2439 +#define MACH_TYPE_DAVINCI_HASE1 2440 +#define MACH_TYPE_LGEINCITEPHONE 2441 +#define MACH_TYPE_EA313X 2442 +#define MACH_TYPE_FWBD_39064 2443 +#define MACH_TYPE_FWBD_390128 2444 +#define MACH_TYPE_PELCO_MOE 2445 +#define MACH_TYPE_MINIMIX27 2446 +#define MACH_TYPE_OMAP3_THUNDER 2447 +#define MACH_TYPE_PASSIONC 2448 +#define MACH_TYPE_MX27AMATA 2449 +#define MACH_TYPE_BGAT1 2450 +#define MACH_TYPE_BUZZ 2451 +#define MACH_TYPE_MB9G20 2452 +#define MACH_TYPE_YUSHAN 2453 +#define MACH_TYPE_LIZARD 2454 +#define MACH_TYPE_OMAP3POLYCOM 2455 +#define MACH_TYPE_SMDKV210 2456 +#define MACH_TYPE_BRAVO 2457 +#define MACH_TYPE_SIOGENTOO1 2458 +#define MACH_TYPE_SIOGENTOO2 2459 +#define MACH_TYPE_SM3K 2460 +#define MACH_TYPE_ACER_TEMPO_F900 2461 +#define MACH_TYPE_SST61VC010_DEV 2462 +#define MACH_TYPE_GLITTERTIND 2463 +#define MACH_TYPE_OMAP_ZOOM3 2464 +#define MACH_TYPE_OMAP_3630SDP 2465 +#define MACH_TYPE_CYBOOK2440 2466 +#define MACH_TYPE_TORINO_S 2467 +#define MACH_TYPE_HAVANA 2468 +#define MACH_TYPE_BEAUMONT_11 2469 +#define MACH_TYPE_VANGUARD 2470 +#define MACH_TYPE_S5PC110_DRACO 2471 +#define MACH_TYPE_CARTESIO_TWO 2472 +#define MACH_TYPE_ASTER 2473 +#define MACH_TYPE_VOGUESV210 2474 +#define MACH_TYPE_ACM500X 2475 +#define MACH_TYPE_KM9260 2476 +#define MACH_TYPE_NIDEFLEXG1 2477 +#define MACH_TYPE_CTERA_PLUG_IO 2478 +#define MACH_TYPE_SMARTQ7 2479 +#define MACH_TYPE_AT91SAM9G10EK2 2480 +#define MACH_TYPE_ASUSP527 2481 +#define MACH_TYPE_AT91SAM9G20MPM2 2482 +#define MACH_TYPE_TOPASA900 2483 +#define MACH_TYPE_ELECTRUM_100 2484 +#define MACH_TYPE_MX51GRB 2485 +#define MACH_TYPE_XEA300 2486 +#define MACH_TYPE_HTCSTARTREK 2487 +#define MACH_TYPE_LIMA 2488 +#define MACH_TYPE_CSB740 2489 +#define MACH_TYPE_USB_S8815 2490 +#define MACH_TYPE_WATSON_EFM_PLUGIN 2491 +#define MACH_TYPE_MILKYWAY 2492 +#define MACH_TYPE_G4EVM 2493 +#define MACH_TYPE_PICOMOD6 2494 +#define MACH_TYPE_OMAPL138_HAWKBOARD 2495 +#define MACH_TYPE_IP6000 2496 +#define MACH_TYPE_IP6010 2497 +#define MACH_TYPE_UTM400 2498 +#define MACH_TYPE_OMAP3_ZYBEX 2499 +#define MACH_TYPE_WIRELESS_SPACE 2500 +#define MACH_TYPE_SX560 2501 +#define MACH_TYPE_TS41X 2502 +#define MACH_TYPE_ELPHEL10373 2503 +#define MACH_TYPE_RHOBOT 2504 +#define MACH_TYPE_MX51_REFRESH 2505 +#define MACH_TYPE_LS9260 2506 +#define MACH_TYPE_SHANK 2507 +#define MACH_TYPE_QSD8X50_ST1 2508 +#define MACH_TYPE_AT91SAM9M10EKES 2509 +#define MACH_TYPE_HIRAM 2510 +#define MACH_TYPE_PHY3250 2511 +#define MACH_TYPE_EA3250 2512 +#define MACH_TYPE_FDI3250 2513 +#define MACH_TYPE_WHITESTONE 2514 +#define MACH_TYPE_AT91SAM9263NIT 2515 +#define MACH_TYPE_CCMX51 2516 +#define MACH_TYPE_CCMX51JS 2517 +#define MACH_TYPE_CCWMX51 2518 +#define MACH_TYPE_CCWMX51JS 2519 +#define MACH_TYPE_MINI6410 2520 +#define MACH_TYPE_TINY6410 2521 +#define MACH_TYPE_NANO6410 2522 +#define MACH_TYPE_AT572D940HFNLDB 2523 +#define MACH_TYPE_HTCLEO 2524 +#define MACH_TYPE_AVP13 2525 +#define MACH_TYPE_XXSVIDEOD 2526 +#define MACH_TYPE_VPNEXT 2527 +#define MACH_TYPE_SWARCO_ITC3 2528 +#define MACH_TYPE_TX51 2529 +#define MACH_TYPE_DOLBY_CAT1021 2530 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -13369,9 +13462,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_REA_2D # endif -# define machine_is_rea_2d() (machine_arch_type == MACH_TYPE_REA_2D) +# define machine_is_rea_cpu2() (machine_arch_type == MACH_TYPE_REA_2D) #else -# define machine_is_rea_2d() (0) +# define machine_is_rea_cpu2() (0) #endif #ifdef CONFIG_MACH_TI3E524 @@ -31278,6 +31371,1122 @@ extern unsigned int __machine_arch_type; # define machine_is_gnet_sgc() (0) #endif +#ifdef CONFIG_MACH_EINSTEIN15 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EINSTEIN15 +# endif +# define machine_is_einstein15() (machine_arch_type == MACH_TYPE_EINSTEIN15) +#else +# define machine_is_einstein15() (0) +#endif + +#ifdef CONFIG_MACH_CMPD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CMPD +# endif +# define machine_is_cmpd() (machine_arch_type == MACH_TYPE_CMPD) +#else +# define machine_is_cmpd() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_HASE1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_HASE1 +# endif +# define machine_is_davinci_hase1() (machine_arch_type == MACH_TYPE_DAVINCI_HASE1) +#else +# define machine_is_davinci_hase1() (0) +#endif + +#ifdef CONFIG_MACH_LGEINCITEPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LGEINCITEPHONE +# endif +# define machine_is_lgeincitephone() (machine_arch_type == MACH_TYPE_LGEINCITEPHONE) +#else +# define machine_is_lgeincitephone() (0) +#endif + +#ifdef CONFIG_MACH_EA313X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EA313X +# endif +# define machine_is_ea313x() (machine_arch_type == MACH_TYPE_EA313X) +#else +# define machine_is_ea313x() (0) +#endif + +#ifdef CONFIG_MACH_FWBD_39064 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FWBD_39064 +# endif +# define machine_is_fwbd_39064() (machine_arch_type == MACH_TYPE_FWBD_39064) +#else +# define machine_is_fwbd_39064() (0) +#endif + +#ifdef CONFIG_MACH_FWBD_390128 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FWBD_390128 +# endif +# define machine_is_fwbd_390128() (machine_arch_type == MACH_TYPE_FWBD_390128) +#else +# define machine_is_fwbd_390128() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_MOE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_MOE +# endif +# define machine_is_pelco_moe() (machine_arch_type == MACH_TYPE_PELCO_MOE) +#else +# define machine_is_pelco_moe() (0) +#endif + +#ifdef CONFIG_MACH_MINIMIX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINIMIX27 +# endif +# define machine_is_minimix27() (machine_arch_type == MACH_TYPE_MINIMIX27) +#else +# define machine_is_minimix27() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_THUNDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_THUNDER +# endif +# define machine_is_omap3_thunder() (machine_arch_type == MACH_TYPE_OMAP3_THUNDER) +#else +# define machine_is_omap3_thunder() (0) +#endif + +#ifdef CONFIG_MACH_PASSIONC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PASSIONC +# endif +# define machine_is_passionc() (machine_arch_type == MACH_TYPE_PASSIONC) +#else +# define machine_is_passionc() (0) +#endif + +#ifdef CONFIG_MACH_MX27AMATA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX27AMATA +# endif +# define machine_is_mx27amata() (machine_arch_type == MACH_TYPE_MX27AMATA) +#else +# define machine_is_mx27amata() (0) +#endif + +#ifdef CONFIG_MACH_BGAT1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BGAT1 +# endif +# define machine_is_bgat1() (machine_arch_type == MACH_TYPE_BGAT1) +#else +# define machine_is_bgat1() (0) +#endif + +#ifdef CONFIG_MACH_BUZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUZZ +# endif +# define machine_is_buzz() (machine_arch_type == MACH_TYPE_BUZZ) +#else +# define machine_is_buzz() (0) +#endif + +#ifdef CONFIG_MACH_MB9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MB9G20 +# endif +# define machine_is_mb9g20() (machine_arch_type == MACH_TYPE_MB9G20) +#else +# define machine_is_mb9g20() (0) +#endif + +#ifdef CONFIG_MACH_YUSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YUSHAN +# endif +# define machine_is_yushan() (machine_arch_type == MACH_TYPE_YUSHAN) +#else +# define machine_is_yushan() (0) +#endif + +#ifdef CONFIG_MACH_LIZARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIZARD +# endif +# define machine_is_lizard() (machine_arch_type == MACH_TYPE_LIZARD) +#else +# define machine_is_lizard() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3POLYCOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3POLYCOM +# endif +# define machine_is_omap3polycom() (machine_arch_type == MACH_TYPE_OMAP3POLYCOM) +#else +# define machine_is_omap3polycom() (0) +#endif + +#ifdef CONFIG_MACH_SMDKV210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKV210 +# endif +# define machine_is_smdkv210() (machine_arch_type == MACH_TYPE_SMDKV210) +#else +# define machine_is_smdkv210() (0) +#endif + +#ifdef CONFIG_MACH_BRAVO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BRAVO +# endif +# define machine_is_bravo() (machine_arch_type == MACH_TYPE_BRAVO) +#else +# define machine_is_bravo() (0) +#endif + +#ifdef CONFIG_MACH_SIOGENTOO1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIOGENTOO1 +# endif +# define machine_is_siogentoo1() (machine_arch_type == MACH_TYPE_SIOGENTOO1) +#else +# define machine_is_siogentoo1() (0) +#endif + +#ifdef CONFIG_MACH_SIOGENTOO2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIOGENTOO2 +# endif +# define machine_is_siogentoo2() (machine_arch_type == MACH_TYPE_SIOGENTOO2) +#else +# define machine_is_siogentoo2() (0) +#endif + +#ifdef CONFIG_MACH_SM3K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SM3K +# endif +# define machine_is_sm3k() (machine_arch_type == MACH_TYPE_SM3K) +#else +# define machine_is_sm3k() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_F900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_F900 +# endif +# define machine_is_acer_tempo_f900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_F900) +#else +# define machine_is_acer_tempo_f900() (0) +#endif + +#ifdef CONFIG_MACH_SST61VC010_DEV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SST61VC010_DEV +# endif +# define machine_is_sst61vc010_dev() (machine_arch_type == MACH_TYPE_SST61VC010_DEV) +#else +# define machine_is_sst61vc010_dev() (0) +#endif + +#ifdef CONFIG_MACH_GLITTERTIND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GLITTERTIND +# endif +# define machine_is_glittertind() (machine_arch_type == MACH_TYPE_GLITTERTIND) +#else +# define machine_is_glittertind() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_ZOOM3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_ZOOM3 +# endif +# define machine_is_omap_zoom3() (machine_arch_type == MACH_TYPE_OMAP_ZOOM3) +#else +# define machine_is_omap_zoom3() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_3630SDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_3630SDP +# endif +# define machine_is_omap_3630sdp() (machine_arch_type == MACH_TYPE_OMAP_3630SDP) +#else +# define machine_is_omap_3630sdp() (0) +#endif + +#ifdef CONFIG_MACH_CYBOOK2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBOOK2440 +# endif +# define machine_is_cybook2440() (machine_arch_type == MACH_TYPE_CYBOOK2440) +#else +# define machine_is_cybook2440() (0) +#endif + +#ifdef CONFIG_MACH_TORINO_S +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TORINO_S +# endif +# define machine_is_torino_s() (machine_arch_type == MACH_TYPE_TORINO_S) +#else +# define machine_is_torino_s() (0) +#endif + +#ifdef CONFIG_MACH_HAVANA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HAVANA +# endif +# define machine_is_havana() (machine_arch_type == MACH_TYPE_HAVANA) +#else +# define machine_is_havana() (0) +#endif + +#ifdef CONFIG_MACH_BEAUMONT_11 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BEAUMONT_11 +# endif +# define machine_is_beaumont_11() (machine_arch_type == MACH_TYPE_BEAUMONT_11) +#else +# define machine_is_beaumont_11() (0) +#endif + +#ifdef CONFIG_MACH_VANGUARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VANGUARD +# endif +# define machine_is_vanguard() (machine_arch_type == MACH_TYPE_VANGUARD) +#else +# define machine_is_vanguard() (0) +#endif + +#ifdef CONFIG_MACH_S5PC110_DRACO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5PC110_DRACO +# endif +# define machine_is_s5pc110_draco() (machine_arch_type == MACH_TYPE_S5PC110_DRACO) +#else +# define machine_is_s5pc110_draco() (0) +#endif + +#ifdef CONFIG_MACH_CARTESIO_TWO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CARTESIO_TWO +# endif +# define machine_is_cartesio_two() (machine_arch_type == MACH_TYPE_CARTESIO_TWO) +#else +# define machine_is_cartesio_two() (0) +#endif + +#ifdef CONFIG_MACH_ASTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASTER +# endif +# define machine_is_aster() (machine_arch_type == MACH_TYPE_ASTER) +#else +# define machine_is_aster() (0) +#endif + +#ifdef CONFIG_MACH_VOGUESV210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VOGUESV210 +# endif +# define machine_is_voguesv210() (machine_arch_type == MACH_TYPE_VOGUESV210) +#else +# define machine_is_voguesv210() (0) +#endif + +#ifdef CONFIG_MACH_ACM500X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACM500X +# endif +# define machine_is_acm500x() (machine_arch_type == MACH_TYPE_ACM500X) +#else +# define machine_is_acm500x() (0) +#endif + +#ifdef CONFIG_MACH_KM9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KM9260 +# endif +# define machine_is_km9260() (machine_arch_type == MACH_TYPE_KM9260) +#else +# define machine_is_km9260() (0) +#endif + +#ifdef CONFIG_MACH_NIDEFLEXG1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIDEFLEXG1 +# endif +# define machine_is_nideflexg1() (machine_arch_type == MACH_TYPE_NIDEFLEXG1) +#else +# define machine_is_nideflexg1() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_PLUG_IO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_PLUG_IO +# endif +# define machine_is_ctera_plug_io() (machine_arch_type == MACH_TYPE_CTERA_PLUG_IO) +#else +# define machine_is_ctera_plug_io() (0) +#endif + +#ifdef CONFIG_MACH_SMARTQ7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTQ7 +# endif +# define machine_is_smartq7() (machine_arch_type == MACH_TYPE_SMARTQ7) +#else +# define machine_is_smartq7() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G10EK2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G10EK2 +# endif +# define machine_is_at91sam9g10ek2() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK2) +#else +# define machine_is_at91sam9g10ek2() (0) +#endif + +#ifdef CONFIG_MACH_ASUSP527 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASUSP527 +# endif +# define machine_is_asusp527() (machine_arch_type == MACH_TYPE_ASUSP527) +#else +# define machine_is_asusp527() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G20MPM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G20MPM2 +# endif +# define machine_is_at91sam9g20mpm2() (machine_arch_type == MACH_TYPE_AT91SAM9G20MPM2) +#else +# define machine_is_at91sam9g20mpm2() (0) +#endif + +#ifdef CONFIG_MACH_TOPASA900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOPASA900 +# endif +# define machine_is_topasa900() (machine_arch_type == MACH_TYPE_TOPASA900) +#else +# define machine_is_topasa900() (0) +#endif + +#ifdef CONFIG_MACH_ELECTRUM_100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELECTRUM_100 +# endif +# define machine_is_electrum_100() (machine_arch_type == MACH_TYPE_ELECTRUM_100) +#else +# define machine_is_electrum_100() (0) +#endif + +#ifdef CONFIG_MACH_MX51GRB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51GRB +# endif +# define machine_is_mx51grb() (machine_arch_type == MACH_TYPE_MX51GRB) +#else +# define machine_is_mx51grb() (0) +#endif + +#ifdef CONFIG_MACH_XEA300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XEA300 +# endif +# define machine_is_xea300() (machine_arch_type == MACH_TYPE_XEA300) +#else +# define machine_is_xea300() (0) +#endif + +#ifdef CONFIG_MACH_HTCSTARTREK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCSTARTREK +# endif +# define machine_is_htcstartrek() (machine_arch_type == MACH_TYPE_HTCSTARTREK) +#else +# define machine_is_htcstartrek() (0) +#endif + +#ifdef CONFIG_MACH_LIMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIMA +# endif +# define machine_is_lima() (machine_arch_type == MACH_TYPE_LIMA) +#else +# define machine_is_lima() (0) +#endif + +#ifdef CONFIG_MACH_CSB740 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB740 +# endif +# define machine_is_csb740() (machine_arch_type == MACH_TYPE_CSB740) +#else +# define machine_is_csb740() (0) +#endif + +#ifdef CONFIG_MACH_USB_S8815 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_USB_S8815 +# endif +# define machine_is_usb_s8815() (machine_arch_type == MACH_TYPE_USB_S8815) +#else +# define machine_is_usb_s8815() (0) +#endif + +#ifdef CONFIG_MACH_WATSON_EFM_PLUGIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WATSON_EFM_PLUGIN +# endif +# define machine_is_watson_efm_plugin() (machine_arch_type == MACH_TYPE_WATSON_EFM_PLUGIN) +#else +# define machine_is_watson_efm_plugin() (0) +#endif + +#ifdef CONFIG_MACH_MILKYWAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MILKYWAY +# endif +# define machine_is_milkyway() (machine_arch_type == MACH_TYPE_MILKYWAY) +#else +# define machine_is_milkyway() (0) +#endif + +#ifdef CONFIG_MACH_G4EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G4EVM +# endif +# define machine_is_g4evm() (machine_arch_type == MACH_TYPE_G4EVM) +#else +# define machine_is_g4evm() (0) +#endif + +#ifdef CONFIG_MACH_PICOMOD6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PICOMOD6 +# endif +# define machine_is_picomod6() (machine_arch_type == MACH_TYPE_PICOMOD6) +#else +# define machine_is_picomod6() (0) +#endif + +#ifdef CONFIG_MACH_OMAPL138_HAWKBOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAPL138_HAWKBOARD +# endif +# define machine_is_omapl138_hawkboard() (machine_arch_type == MACH_TYPE_OMAPL138_HAWKBOARD) +#else +# define machine_is_omapl138_hawkboard() (0) +#endif + +#ifdef CONFIG_MACH_IP6000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IP6000 +# endif +# define machine_is_ip6000() (machine_arch_type == MACH_TYPE_IP6000) +#else +# define machine_is_ip6000() (0) +#endif + +#ifdef CONFIG_MACH_IP6010 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IP6010 +# endif +# define machine_is_ip6010() (machine_arch_type == MACH_TYPE_IP6010) +#else +# define machine_is_ip6010() (0) +#endif + +#ifdef CONFIG_MACH_UTM400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UTM400 +# endif +# define machine_is_utm400() (machine_arch_type == MACH_TYPE_UTM400) +#else +# define machine_is_utm400() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_ZYBEX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_ZYBEX +# endif +# define machine_is_omap3_zybex() (machine_arch_type == MACH_TYPE_OMAP3_ZYBEX) +#else +# define machine_is_omap3_zybex() (0) +#endif + +#ifdef CONFIG_MACH_WIRELESS_SPACE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WIRELESS_SPACE +# endif +# define machine_is_wireless_space() (machine_arch_type == MACH_TYPE_WIRELESS_SPACE) +#else +# define machine_is_wireless_space() (0) +#endif + +#ifdef CONFIG_MACH_SX560 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SX560 +# endif +# define machine_is_sx560() (machine_arch_type == MACH_TYPE_SX560) +#else +# define machine_is_sx560() (0) +#endif + +#ifdef CONFIG_MACH_TS41X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS41X +# endif +# define machine_is_ts41x() (machine_arch_type == MACH_TYPE_TS41X) +#else +# define machine_is_ts41x() (0) +#endif + +#ifdef CONFIG_MACH_ELPHEL10373 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELPHEL10373 +# endif +# define machine_is_elphel10373() (machine_arch_type == MACH_TYPE_ELPHEL10373) +#else +# define machine_is_elphel10373() (0) +#endif + +#ifdef CONFIG_MACH_RHOBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RHOBOT +# endif +# define machine_is_rhobot() (machine_arch_type == MACH_TYPE_RHOBOT) +#else +# define machine_is_rhobot() (0) +#endif + +#ifdef CONFIG_MACH_MX51_REFRESH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_REFRESH +# endif +# define machine_is_mx51_refresh() (machine_arch_type == MACH_TYPE_MX51_REFRESH) +#else +# define machine_is_mx51_refresh() (0) +#endif + +#ifdef CONFIG_MACH_LS9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LS9260 +# endif +# define machine_is_ls9260() (machine_arch_type == MACH_TYPE_LS9260) +#else +# define machine_is_ls9260() (0) +#endif + +#ifdef CONFIG_MACH_SHANK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHANK +# endif +# define machine_is_shank() (machine_arch_type == MACH_TYPE_SHANK) +#else +# define machine_is_shank() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_ST1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_ST1 +# endif +# define machine_is_qsd8x50_st1() (machine_arch_type == MACH_TYPE_QSD8X50_ST1) +#else +# define machine_is_qsd8x50_st1() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9M10EKES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9M10EKES +# endif +# define machine_is_at91sam9m10ekes() (machine_arch_type == MACH_TYPE_AT91SAM9M10EKES) +#else +# define machine_is_at91sam9m10ekes() (0) +#endif + +#ifdef CONFIG_MACH_HIRAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HIRAM +# endif +# define machine_is_hiram() (machine_arch_type == MACH_TYPE_HIRAM) +#else +# define machine_is_hiram() (0) +#endif + +#ifdef CONFIG_MACH_PHY3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHY3250 +# endif +# define machine_is_phy3250() (machine_arch_type == MACH_TYPE_PHY3250) +#else +# define machine_is_phy3250() (0) +#endif + +#ifdef CONFIG_MACH_EA3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EA3250 +# endif +# define machine_is_ea3250() (machine_arch_type == MACH_TYPE_EA3250) +#else +# define machine_is_ea3250() (0) +#endif + +#ifdef CONFIG_MACH_FDI3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FDI3250 +# endif +# define machine_is_fdi3250() (machine_arch_type == MACH_TYPE_FDI3250) +#else +# define machine_is_fdi3250() (0) +#endif + +#ifdef CONFIG_MACH_WHITESTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WHITESTONE +# endif +# define machine_is_whitestone() (machine_arch_type == MACH_TYPE_WHITESTONE) +#else +# define machine_is_whitestone() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9263NIT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9263NIT +# endif +# define machine_is_at91sam9263nit() (machine_arch_type == MACH_TYPE_AT91SAM9263NIT) +#else +# define machine_is_at91sam9263nit() (0) +#endif + +#ifdef CONFIG_MACH_CCMX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCMX51 +# endif +# define machine_is_ccmx51() (machine_arch_type == MACH_TYPE_CCMX51) +#else +# define machine_is_ccmx51() (0) +#endif + +#ifdef CONFIG_MACH_CCMX51JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCMX51JS +# endif +# define machine_is_ccmx51js() (machine_arch_type == MACH_TYPE_CCMX51JS) +#else +# define machine_is_ccmx51js() (0) +#endif + +#ifdef CONFIG_MACH_CCWMX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCWMX51 +# endif +# define machine_is_ccwmx51() (machine_arch_type == MACH_TYPE_CCWMX51) +#else +# define machine_is_ccwmx51() (0) +#endif + +#ifdef CONFIG_MACH_CCWMX51JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCWMX51JS +# endif +# define machine_is_ccwmx51js() (machine_arch_type == MACH_TYPE_CCWMX51JS) +#else +# define machine_is_ccwmx51js() (0) +#endif + +#ifdef CONFIG_MACH_MINI6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINI6410 +# endif +# define machine_is_mini6410() (machine_arch_type == MACH_TYPE_MINI6410) +#else +# define machine_is_mini6410() (0) +#endif + +#ifdef CONFIG_MACH_TINY6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TINY6410 +# endif +# define machine_is_tiny6410() (machine_arch_type == MACH_TYPE_TINY6410) +#else +# define machine_is_tiny6410() (0) +#endif + +#ifdef CONFIG_MACH_NANO6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NANO6410 +# endif +# define machine_is_nano6410() (machine_arch_type == MACH_TYPE_NANO6410) +#else +# define machine_is_nano6410() (0) +#endif + +#ifdef CONFIG_MACH_AT572D940HFNLDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT572D940HFNLDB +# endif +# define machine_is_at572d940hfnldb() (machine_arch_type == MACH_TYPE_AT572D940HFNLDB) +#else +# define machine_is_at572d940hfnldb() (0) +#endif + +#ifdef CONFIG_MACH_HTCLEO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCLEO +# endif +# define machine_is_htcleo() (machine_arch_type == MACH_TYPE_HTCLEO) +#else +# define machine_is_htcleo() (0) +#endif + +#ifdef CONFIG_MACH_AVP13 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AVP13 +# endif +# define machine_is_avp13() (machine_arch_type == MACH_TYPE_AVP13) +#else +# define machine_is_avp13() (0) +#endif + +#ifdef CONFIG_MACH_XXSVIDEOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XXSVIDEOD +# endif +# define machine_is_xxsvideod() (machine_arch_type == MACH_TYPE_XXSVIDEOD) +#else +# define machine_is_xxsvideod() (0) +#endif + +#ifdef CONFIG_MACH_VPNEXT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPNEXT +# endif +# define machine_is_vpnext() (machine_arch_type == MACH_TYPE_VPNEXT) +#else +# define machine_is_vpnext() (0) +#endif + +#ifdef CONFIG_MACH_SWARCO_ITC3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWARCO_ITC3 +# endif +# define machine_is_swarco_itc3() (machine_arch_type == MACH_TYPE_SWARCO_ITC3) +#else +# define machine_is_swarco_itc3() (0) +#endif + +#ifdef CONFIG_MACH_TX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TX51 +# endif +# define machine_is_tx51() (machine_arch_type == MACH_TYPE_TX51) +#else +# define machine_is_tx51() (0) +#endif + +#ifdef CONFIG_MACH_DOLBY_CAT1021 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOLBY_CAT1021 +# endif +# define machine_is_dolby_cat1021() (machine_arch_type == MACH_TYPE_DOLBY_CAT1021) +#else +# define machine_is_dolby_cat1021() (0) +#endif + /* * These have not yet been registered */ -- cgit v1.2.1 From 492fb1fdbcdd5e21be0b6742c15f76c648f0653b Mon Sep 17 00:00:00 2001 From: "kevin.morfitt@fearnside-systems.co.uk" Date: Tue, 3 Nov 2009 18:08:41 +0900 Subject: Move s3c24x0 header files to asm-arm/arch-s3c24x0/ This patch moves the s3c24x0 header files from include/ to include/asm-arm/arch-s3c24x0/. checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due to a non-UTF8 character in David M?ller's name: ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8 #489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3: + * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch As David's name correctly contains a non-UTF8 character I haven't fixed these errors. The 3 warnings were all because of the use of 'volatile' in s3c24x0.h: WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt #673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35: +typedef volatile u8 S3C24X0_REG8; +typedef volatile u16 S3C24X0_REG16; +typedef volatile u32 S3C24X0_REG32; I'll fix these errors in another patch. Tested by running MAKEALL for ARM8 targets and ensuring there were no new errors or warnings. Signed-off-by: Kevin Morfitt Signed-off-by: Minkyu Kang --- include/asm-arm/arch-s3c24x0/s3c2400.h | 136 +++++++ include/asm-arm/arch-s3c24x0/s3c2410.h | 146 ++++++++ include/asm-arm/arch-s3c24x0/s3c24x0.h | 656 +++++++++++++++++++++++++++++++++ include/s3c2400.h | 136 ------- include/s3c2410.h | 146 -------- include/s3c24x0.h | 656 --------------------------------- 6 files changed, 938 insertions(+), 938 deletions(-) create mode 100644 include/asm-arm/arch-s3c24x0/s3c2400.h create mode 100644 include/asm-arm/arch-s3c24x0/s3c2410.h create mode 100644 include/asm-arm/arch-s3c24x0/s3c24x0.h delete mode 100644 include/s3c2400.h delete mode 100644 include/s3c2410.h delete mode 100644 include/s3c24x0.h (limited to 'include') diff --git a/include/asm-arm/arch-s3c24x0/s3c2400.h b/include/asm-arm/arch-s3c24x0/s3c2400.h new file mode 100644 index 0000000000..26bd4e49a1 --- /dev/null +++ b/include/asm-arm/arch-s3c24x0/s3c2400.h @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2003 + * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : s3c2400.h + * Version : 31.3.2003 + * + * Based on S3C2400X User's manual Rev 1.1 + ************************************************/ + +#ifndef __S3C2400_H__ +#define __S3C2400_H__ + +#define S3C24X0_UART_CHANNELS 2 +#define S3C24X0_SPI_CHANNELS 1 +#define PALETTE (0x14A00400) /* SJS */ + +enum s3c24x0_uarts_nr { + S3C24X0_UART0, + S3C24X0_UART1, +}; + +/*S3C2400 device base addresses */ +#define S3C24X0_MEMCTL_BASE 0x14000000 +#define S3C24X0_USB_HOST_BASE 0x14200000 +#define S3C24X0_INTERRUPT_BASE 0x14400000 +#define S3C24X0_DMA_BASE 0x14600000 +#define S3C24X0_CLOCK_POWER_BASE 0x14800000 +#define S3C24X0_LCD_BASE 0x14A00000 +#define S3C24X0_UART_BASE 0x15000000 +#define S3C24X0_TIMER_BASE 0x15100000 +#define S3C24X0_USB_DEVICE_BASE 0x15200140 +#define S3C24X0_WATCHDOG_BASE 0x15300000 +#define S3C24X0_I2C_BASE 0x15400000 +#define S3C24X0_I2S_BASE 0x15508000 +#define S3C24X0_GPIO_BASE 0x15600000 +#define S3C24X0_RTC_BASE 0x15700000 +#define S3C24X0_ADC_BASE 0x15800000 +#define S3C24X0_SPI_BASE 0x15900000 +#define S3C2400_MMC_BASE 0x15A00000 + +/* include common stuff */ +#include + + +static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) +{ + return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; +} +static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) +{ + return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; +} +static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) +{ + return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; +} +static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) +{ + return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; +} +static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) +{ + return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; +} +static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) +{ + return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; +} +static inline struct s3c24x0_uart + *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) +{ + return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); +} +static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) +{ + return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; +} +static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) +{ + return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; +} +static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) +{ + return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; +} +static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) +{ + return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; +} +static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) +{ + return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; +} +static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) +{ + return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; +} +static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) +{ + return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; +} +static inline struct s3c2400_adc *s3c2400_get_base_adc(void) +{ + return (struct s3c2400_adc *)S3C24X0_ADC_BASE; +} +static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) +{ + return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; +} +static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void) +{ + return (struct s3c2400_mmc *)S3C2400_MMC_BASE; +} + +#endif /*__S3C2400_H__*/ diff --git a/include/asm-arm/arch-s3c24x0/s3c2410.h b/include/asm-arm/arch-s3c24x0/s3c2410.h new file mode 100644 index 0000000000..be2e76e5f2 --- /dev/null +++ b/include/asm-arm/arch-s3c24x0/s3c2410.h @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2003 + * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : s3c2410.h + * Version : 31.3.2003 + * + * Based on S3C2410X User's manual Rev 1.1 + ************************************************/ + +#ifndef __S3C2410_H__ +#define __S3C2410_H__ + +#define S3C24X0_UART_CHANNELS 3 +#define S3C24X0_SPI_CHANNELS 2 + +/* S3C2410 only supports 512 Byte HW ECC */ +#define S3C2410_ECCSIZE 512 +#define S3C2410_ECCBYTES 3 + +enum s3c24x0_uarts_nr { + S3C24X0_UART0, + S3C24X0_UART1, + S3C24X0_UART2 +}; + +/* S3C2410 device base addresses */ +#define S3C24X0_MEMCTL_BASE 0x48000000 +#define S3C24X0_USB_HOST_BASE 0x49000000 +#define S3C24X0_INTERRUPT_BASE 0x4A000000 +#define S3C24X0_DMA_BASE 0x4B000000 +#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 +#define S3C24X0_LCD_BASE 0x4D000000 +#define S3C2410_NAND_BASE 0x4E000000 +#define S3C24X0_UART_BASE 0x50000000 +#define S3C24X0_TIMER_BASE 0x51000000 +#define S3C24X0_USB_DEVICE_BASE 0x52000140 +#define S3C24X0_WATCHDOG_BASE 0x53000000 +#define S3C24X0_I2C_BASE 0x54000000 +#define S3C24X0_I2S_BASE 0x55000000 +#define S3C24X0_GPIO_BASE 0x56000000 +#define S3C24X0_RTC_BASE 0x57000000 +#define S3C2410_ADC_BASE 0x58000000 +#define S3C24X0_SPI_BASE 0x59000000 +#define S3C2410_SDI_BASE 0x5A000000 + + +/* include common stuff */ +#include + + +static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) +{ + return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; +} +static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) +{ + return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; +} +static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) +{ + return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; +} +static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) +{ + return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; +} +static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) +{ + return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; +} +static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) +{ + return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; +} +static inline struct s3c2410_nand *s3c2410_get_base_nand(void) +{ + return (struct s3c2410_nand *)S3C2410_NAND_BASE; +} +static inline struct s3c24x0_uart + *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) +{ + return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); +} +static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) +{ + return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; +} +static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) +{ + return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; +} +static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) +{ + return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; +} +static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) +{ + return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; +} +static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) +{ + return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; +} +static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) +{ + return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; +} +static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) +{ + return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; +} +static inline struct s3c2410_adc *s3c2410_get_base_adc(void) +{ + return (struct s3c2410_adc *)S3C2410_ADC_BASE; +} +static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) +{ + return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; +} +static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void) +{ + return (struct s3c2410_sdi *)S3C2410_SDI_BASE; +} + +#endif /*__S3C2410_H__*/ diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0.h b/include/asm-arm/arch-s3c24x0/s3c24x0.h new file mode 100644 index 0000000000..56a551aeb4 --- /dev/null +++ b/include/asm-arm/arch-s3c24x0/s3c24x0.h @@ -0,0 +1,656 @@ +/* + * (C) Copyright 2003 + * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : s3c24x0.h + * Version : 31.3.2003 + * + * common stuff for SAMSUNG S3C24X0 SoC + ************************************************/ + +#ifndef __S3C24X0_H__ +#define __S3C24X0_H__ + +typedef volatile u8 S3C24X0_REG8; +typedef volatile u16 S3C24X0_REG16; +typedef volatile u32 S3C24X0_REG32; + +/* Memory controller (see manual chapter 5) */ +struct s3c24x0_memctl { + S3C24X0_REG32 BWSCON; + S3C24X0_REG32 BANKCON[8]; + S3C24X0_REG32 REFRESH; + S3C24X0_REG32 BANKSIZE; + S3C24X0_REG32 MRSRB6; + S3C24X0_REG32 MRSRB7; +}; + + +/* USB HOST (see manual chapter 12) */ +struct s3c24x0_usb_host { + S3C24X0_REG32 HcRevision; + S3C24X0_REG32 HcControl; + S3C24X0_REG32 HcCommonStatus; + S3C24X0_REG32 HcInterruptStatus; + S3C24X0_REG32 HcInterruptEnable; + S3C24X0_REG32 HcInterruptDisable; + S3C24X0_REG32 HcHCCA; + S3C24X0_REG32 HcPeriodCuttendED; + S3C24X0_REG32 HcControlHeadED; + S3C24X0_REG32 HcControlCurrentED; + S3C24X0_REG32 HcBulkHeadED; + S3C24X0_REG32 HcBuldCurrentED; + S3C24X0_REG32 HcDoneHead; + S3C24X0_REG32 HcRmInterval; + S3C24X0_REG32 HcFmRemaining; + S3C24X0_REG32 HcFmNumber; + S3C24X0_REG32 HcPeriodicStart; + S3C24X0_REG32 HcLSThreshold; + S3C24X0_REG32 HcRhDescriptorA; + S3C24X0_REG32 HcRhDescriptorB; + S3C24X0_REG32 HcRhStatus; + S3C24X0_REG32 HcRhPortStatus1; + S3C24X0_REG32 HcRhPortStatus2; +}; + + +/* INTERRUPT (see manual chapter 14) */ +struct s3c24x0_interrupt { + S3C24X0_REG32 SRCPND; + S3C24X0_REG32 INTMOD; + S3C24X0_REG32 INTMSK; + S3C24X0_REG32 PRIORITY; + S3C24X0_REG32 INTPND; + S3C24X0_REG32 INTOFFSET; +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 SUBSRCPND; + S3C24X0_REG32 INTSUBMSK; +#endif +}; + + +/* DMAS (see manual chapter 8) */ +struct s3c24x0_dma { + S3C24X0_REG32 DISRC; +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 DISRCC; +#endif + S3C24X0_REG32 DIDST; +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 DIDSTC; +#endif + S3C24X0_REG32 DCON; + S3C24X0_REG32 DSTAT; + S3C24X0_REG32 DCSRC; + S3C24X0_REG32 DCDST; + S3C24X0_REG32 DMASKTRIG; +#ifdef CONFIG_S3C2400 + S3C24X0_REG32 res[1]; +#endif +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 res[7]; +#endif +}; + +struct s3c24x0_dmas { + struct s3c24x0_dma dma[4]; +}; + + +/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ +/* (see S3C2410 manual chapter 7) */ +struct s3c24x0_clock_power { + S3C24X0_REG32 LOCKTIME; + S3C24X0_REG32 MPLLCON; + S3C24X0_REG32 UPLLCON; + S3C24X0_REG32 CLKCON; + S3C24X0_REG32 CLKSLOW; + S3C24X0_REG32 CLKDIVN; +}; + + +/* LCD CONTROLLER (see manual chapter 15) */ +struct s3c24x0_lcd { + S3C24X0_REG32 LCDCON1; + S3C24X0_REG32 LCDCON2; + S3C24X0_REG32 LCDCON3; + S3C24X0_REG32 LCDCON4; + S3C24X0_REG32 LCDCON5; + S3C24X0_REG32 LCDSADDR1; + S3C24X0_REG32 LCDSADDR2; + S3C24X0_REG32 LCDSADDR3; + S3C24X0_REG32 REDLUT; + S3C24X0_REG32 GREENLUT; + S3C24X0_REG32 BLUELUT; + S3C24X0_REG32 res[8]; + S3C24X0_REG32 DITHMODE; + S3C24X0_REG32 TPAL; +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 LCDINTPND; + S3C24X0_REG32 LCDSRCPND; + S3C24X0_REG32 LCDINTMSK; + S3C24X0_REG32 LPCSEL; +#endif +}; + + +/* NAND FLASH (see S3C2410 manual chapter 6) */ +struct s3c2410_nand { + S3C24X0_REG32 NFCONF; + S3C24X0_REG32 NFCMD; + S3C24X0_REG32 NFADDR; + S3C24X0_REG32 NFDATA; + S3C24X0_REG32 NFSTAT; + S3C24X0_REG32 NFECC; +}; + + +/* UART (see manual chapter 11) */ +struct s3c24x0_uart { + S3C24X0_REG32 ULCON; + S3C24X0_REG32 UCON; + S3C24X0_REG32 UFCON; + S3C24X0_REG32 UMCON; + S3C24X0_REG32 UTRSTAT; + S3C24X0_REG32 UERSTAT; + S3C24X0_REG32 UFSTAT; + S3C24X0_REG32 UMSTAT; +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 UTXH; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 URXH; +#else /* Little Endian */ + S3C24X0_REG8 UTXH; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 URXH; + S3C24X0_REG8 res2[3]; +#endif + S3C24X0_REG32 UBRDIV; +}; + + +/* PWM TIMER (see manual chapter 10) */ +struct s3c24x0_timer { + S3C24X0_REG32 TCNTB; + S3C24X0_REG32 TCMPB; + S3C24X0_REG32 TCNTO; +}; + +struct s3c24x0_timers { + S3C24X0_REG32 TCFG0; + S3C24X0_REG32 TCFG1; + S3C24X0_REG32 TCON; + struct s3c24x0_timer ch[4]; + S3C24X0_REG32 TCNTB4; + S3C24X0_REG32 TCNTO4; +}; + + +/* USB DEVICE (see manual chapter 13) */ +struct s3c24x0_usb_dev_fifos { +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res[3]; + S3C24X0_REG8 EP_FIFO_REG; +#else /* little endian */ + S3C24X0_REG8 EP_FIFO_REG; + S3C24X0_REG8 res[3]; +#endif +}; + +struct s3c24x0_usb_dev_dmas { +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 EP_DMA_CON; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 EP_DMA_UNIT; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 EP_DMA_FIFO; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 EP_DMA_TTC_L; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 EP_DMA_TTC_M; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 EP_DMA_TTC_H; +#else /* little endian */ + S3C24X0_REG8 EP_DMA_CON; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 EP_DMA_UNIT; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 EP_DMA_FIFO; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 EP_DMA_TTC_L; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 EP_DMA_TTC_M; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 EP_DMA_TTC_H; + S3C24X0_REG8 res6[3]; +#endif +}; + +struct s3c24x0_usb_device { +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 FUNC_ADDR_REG; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 PWR_REG; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 EP_INT_REG; + S3C24X0_REG8 res4[15]; + S3C24X0_REG8 USB_INT_REG; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 EP_INT_EN_REG; + S3C24X0_REG8 res6[15]; + S3C24X0_REG8 USB_INT_EN_REG; + S3C24X0_REG8 res7[3]; + S3C24X0_REG8 FRAME_NUM1_REG; + S3C24X0_REG8 res8[3]; + S3C24X0_REG8 FRAME_NUM2_REG; + S3C24X0_REG8 res9[3]; + S3C24X0_REG8 INDEX_REG; + S3C24X0_REG8 res10[7]; + S3C24X0_REG8 MAXP_REG; + S3C24X0_REG8 res11[3]; + S3C24X0_REG8 EP0_CSR_IN_CSR1_REG; + S3C24X0_REG8 res12[3]; + S3C24X0_REG8 IN_CSR2_REG; + S3C24X0_REG8 res13[7]; + S3C24X0_REG8 OUT_CSR1_REG; + S3C24X0_REG8 res14[3]; + S3C24X0_REG8 OUT_CSR2_REG; + S3C24X0_REG8 res15[3]; + S3C24X0_REG8 OUT_FIFO_CNT1_REG; + S3C24X0_REG8 res16[3]; + S3C24X0_REG8 OUT_FIFO_CNT2_REG; +#else /* little endian */ + S3C24X0_REG8 FUNC_ADDR_REG; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 PWR_REG; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 EP_INT_REG; + S3C24X0_REG8 res3[15]; + S3C24X0_REG8 USB_INT_REG; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 EP_INT_EN_REG; + S3C24X0_REG8 res5[15]; + S3C24X0_REG8 USB_INT_EN_REG; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 FRAME_NUM1_REG; + S3C24X0_REG8 res7[3]; + S3C24X0_REG8 FRAME_NUM2_REG; + S3C24X0_REG8 res8[3]; + S3C24X0_REG8 INDEX_REG; + S3C24X0_REG8 res9[7]; + S3C24X0_REG8 MAXP_REG; + S3C24X0_REG8 res10[7]; + S3C24X0_REG8 EP0_CSR_IN_CSR1_REG; + S3C24X0_REG8 res11[3]; + S3C24X0_REG8 IN_CSR2_REG; + S3C24X0_REG8 res12[3]; + S3C24X0_REG8 OUT_CSR1_REG; + S3C24X0_REG8 res13[7]; + S3C24X0_REG8 OUT_CSR2_REG; + S3C24X0_REG8 res14[3]; + S3C24X0_REG8 OUT_FIFO_CNT1_REG; + S3C24X0_REG8 res15[3]; + S3C24X0_REG8 OUT_FIFO_CNT2_REG; + S3C24X0_REG8 res16[3]; +#endif /* __BIG_ENDIAN */ + struct s3c24x0_usb_dev_fifos fifo[5]; + struct s3c24x0_usb_dev_dmas dma[5]; +}; + + +/* WATCH DOG TIMER (see manual chapter 18) */ +struct s3c24x0_watchdog { + S3C24X0_REG32 WTCON; + S3C24X0_REG32 WTDAT; + S3C24X0_REG32 WTCNT; +}; + + +/* IIC (see manual chapter 20) */ +struct s3c24x0_i2c { + S3C24X0_REG32 IICCON; + S3C24X0_REG32 IICSTAT; + S3C24X0_REG32 IICADD; + S3C24X0_REG32 IICDS; +}; + + +/* IIS (see manual chapter 21) */ +struct s3c24x0_i2s { +#ifdef __BIG_ENDIAN + S3C24X0_REG16 res1; + S3C24X0_REG16 IISCON; + S3C24X0_REG16 res2; + S3C24X0_REG16 IISMOD; + S3C24X0_REG16 res3; + S3C24X0_REG16 IISPSR; + S3C24X0_REG16 res4; + S3C24X0_REG16 IISFCON; + S3C24X0_REG16 res5; + S3C24X0_REG16 IISFIFO; +#else /* little endian */ + S3C24X0_REG16 IISCON; + S3C24X0_REG16 res1; + S3C24X0_REG16 IISMOD; + S3C24X0_REG16 res2; + S3C24X0_REG16 IISPSR; + S3C24X0_REG16 res3; + S3C24X0_REG16 IISFCON; + S3C24X0_REG16 res4; + S3C24X0_REG16 IISFIFO; + S3C24X0_REG16 res5; +#endif +}; + + +/* I/O PORT (see manual chapter 9) */ +struct s3c24x0_gpio { +#ifdef CONFIG_S3C2400 + S3C24X0_REG32 PACON; + S3C24X0_REG32 PADAT; + + S3C24X0_REG32 PBCON; + S3C24X0_REG32 PBDAT; + S3C24X0_REG32 PBUP; + + S3C24X0_REG32 PCCON; + S3C24X0_REG32 PCDAT; + S3C24X0_REG32 PCUP; + + S3C24X0_REG32 PDCON; + S3C24X0_REG32 PDDAT; + S3C24X0_REG32 PDUP; + + S3C24X0_REG32 PECON; + S3C24X0_REG32 PEDAT; + S3C24X0_REG32 PEUP; + + S3C24X0_REG32 PFCON; + S3C24X0_REG32 PFDAT; + S3C24X0_REG32 PFUP; + + S3C24X0_REG32 PGCON; + S3C24X0_REG32 PGDAT; + S3C24X0_REG32 PGUP; + + S3C24X0_REG32 OPENCR; + + S3C24X0_REG32 MISCCR; + S3C24X0_REG32 EXTINT; +#endif +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 GPACON; + S3C24X0_REG32 GPADAT; + S3C24X0_REG32 res1[2]; + S3C24X0_REG32 GPBCON; + S3C24X0_REG32 GPBDAT; + S3C24X0_REG32 GPBUP; + S3C24X0_REG32 res2; + S3C24X0_REG32 GPCCON; + S3C24X0_REG32 GPCDAT; + S3C24X0_REG32 GPCUP; + S3C24X0_REG32 res3; + S3C24X0_REG32 GPDCON; + S3C24X0_REG32 GPDDAT; + S3C24X0_REG32 GPDUP; + S3C24X0_REG32 res4; + S3C24X0_REG32 GPECON; + S3C24X0_REG32 GPEDAT; + S3C24X0_REG32 GPEUP; + S3C24X0_REG32 res5; + S3C24X0_REG32 GPFCON; + S3C24X0_REG32 GPFDAT; + S3C24X0_REG32 GPFUP; + S3C24X0_REG32 res6; + S3C24X0_REG32 GPGCON; + S3C24X0_REG32 GPGDAT; + S3C24X0_REG32 GPGUP; + S3C24X0_REG32 res7; + S3C24X0_REG32 GPHCON; + S3C24X0_REG32 GPHDAT; + S3C24X0_REG32 GPHUP; + S3C24X0_REG32 res8; + + S3C24X0_REG32 MISCCR; + S3C24X0_REG32 DCLKCON; + S3C24X0_REG32 EXTINT0; + S3C24X0_REG32 EXTINT1; + S3C24X0_REG32 EXTINT2; + S3C24X0_REG32 EINTFLT0; + S3C24X0_REG32 EINTFLT1; + S3C24X0_REG32 EINTFLT2; + S3C24X0_REG32 EINTFLT3; + S3C24X0_REG32 EINTMASK; + S3C24X0_REG32 EINTPEND; + S3C24X0_REG32 GSTATUS0; + S3C24X0_REG32 GSTATUS1; + S3C24X0_REG32 GSTATUS2; + S3C24X0_REG32 GSTATUS3; + S3C24X0_REG32 GSTATUS4; +#endif +}; + + +/* RTC (see manual chapter 17) */ +struct s3c24x0_rtc { +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res1[67]; + S3C24X0_REG8 RTCCON; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 TICNT; + S3C24X0_REG8 res3[11]; + S3C24X0_REG8 RTCALM; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 ALMSEC; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 ALMMIN; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 ALMHOUR; + S3C24X0_REG8 res7[3]; + S3C24X0_REG8 ALMDATE; + S3C24X0_REG8 res8[3]; + S3C24X0_REG8 ALMMON; + S3C24X0_REG8 res9[3]; + S3C24X0_REG8 ALMYEAR; + S3C24X0_REG8 res10[3]; + S3C24X0_REG8 RTCRST; + S3C24X0_REG8 res11[3]; + S3C24X0_REG8 BCDSEC; + S3C24X0_REG8 res12[3]; + S3C24X0_REG8 BCDMIN; + S3C24X0_REG8 res13[3]; + S3C24X0_REG8 BCDHOUR; + S3C24X0_REG8 res14[3]; + S3C24X0_REG8 BCDDATE; + S3C24X0_REG8 res15[3]; + S3C24X0_REG8 BCDDAY; + S3C24X0_REG8 res16[3]; + S3C24X0_REG8 BCDMON; + S3C24X0_REG8 res17[3]; + S3C24X0_REG8 BCDYEAR; +#else /* little endian */ + S3C24X0_REG8 res0[64]; + S3C24X0_REG8 RTCCON; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 TICNT; + S3C24X0_REG8 res2[11]; + S3C24X0_REG8 RTCALM; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 ALMSEC; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 ALMMIN; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 ALMHOUR; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 ALMDATE; + S3C24X0_REG8 res7[3]; + S3C24X0_REG8 ALMMON; + S3C24X0_REG8 res8[3]; + S3C24X0_REG8 ALMYEAR; + S3C24X0_REG8 res9[3]; + S3C24X0_REG8 RTCRST; + S3C24X0_REG8 res10[3]; + S3C24X0_REG8 BCDSEC; + S3C24X0_REG8 res11[3]; + S3C24X0_REG8 BCDMIN; + S3C24X0_REG8 res12[3]; + S3C24X0_REG8 BCDHOUR; + S3C24X0_REG8 res13[3]; + S3C24X0_REG8 BCDDATE; + S3C24X0_REG8 res14[3]; + S3C24X0_REG8 BCDDAY; + S3C24X0_REG8 res15[3]; + S3C24X0_REG8 BCDMON; + S3C24X0_REG8 res16[3]; + S3C24X0_REG8 BCDYEAR; + S3C24X0_REG8 res17[3]; +#endif +}; + + +/* ADC (see manual chapter 16) */ +struct s3c2400_adc { + S3C24X0_REG32 ADCCON; + S3C24X0_REG32 ADCDAT; +}; + + +/* ADC (see manual chapter 16) */ +struct s3c2410_adc { + S3C24X0_REG32 ADCCON; + S3C24X0_REG32 ADCTSC; + S3C24X0_REG32 ADCDLY; + S3C24X0_REG32 ADCDAT0; + S3C24X0_REG32 ADCDAT1; +}; + + +/* SPI (see manual chapter 22) */ +struct s3c24x0_spi_channel { + S3C24X0_REG8 SPCON; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 SPSTA; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 SPPIN; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 SPPRE; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 SPTDAT; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 SPRDAT; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 res7[16]; +}; + +struct s3c24x0_spi { + struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS]; +}; + + +/* MMC INTERFACE (see S3C2400 manual chapter 19) */ +struct s3c2400_mmc { +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 MMCON; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 MMCRR; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 MMFCON; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 MMSTA; + S3C24X0_REG16 res5; + S3C24X0_REG16 MMFSTA; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 MMPRE; + S3C24X0_REG16 res7; + S3C24X0_REG16 MMLEN; + S3C24X0_REG8 res8[3]; + S3C24X0_REG8 MMCR7; + S3C24X0_REG32 MMRSP[4]; + S3C24X0_REG8 res9[3]; + S3C24X0_REG8 MMCMD0; + S3C24X0_REG32 MMCMD1; + S3C24X0_REG16 res10; + S3C24X0_REG16 MMCR16; + S3C24X0_REG8 res11[3]; + S3C24X0_REG8 MMDAT; +#else + S3C24X0_REG8 MMCON; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 MMCRR; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 MMFCON; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 MMSTA; + S3C24X0_REG8 res4[3]; + S3C24X0_REG16 MMFSTA; + S3C24X0_REG16 res5; + S3C24X0_REG8 MMPRE; + S3C24X0_REG8 res6[3]; + S3C24X0_REG16 MMLEN; + S3C24X0_REG16 res7; + S3C24X0_REG8 MMCR7; + S3C24X0_REG8 res8[3]; + S3C24X0_REG32 MMRSP[4]; + S3C24X0_REG8 MMCMD0; + S3C24X0_REG8 res9[3]; + S3C24X0_REG32 MMCMD1; + S3C24X0_REG16 MMCR16; + S3C24X0_REG16 res10; + S3C24X0_REG8 MMDAT; + S3C24X0_REG8 res11[3]; +#endif +}; + + +/* SD INTERFACE (see S3C2410 manual chapter 19) */ +struct s3c2410_sdi { + S3C24X0_REG32 SDICON; + S3C24X0_REG32 SDIPRE; + S3C24X0_REG32 SDICARG; + S3C24X0_REG32 SDICCON; + S3C24X0_REG32 SDICSTA; + S3C24X0_REG32 SDIRSP0; + S3C24X0_REG32 SDIRSP1; + S3C24X0_REG32 SDIRSP2; + S3C24X0_REG32 SDIRSP3; + S3C24X0_REG32 SDIDTIMER; + S3C24X0_REG32 SDIBSIZE; + S3C24X0_REG32 SDIDCON; + S3C24X0_REG32 SDIDCNT; + S3C24X0_REG32 SDIDSTA; + S3C24X0_REG32 SDIFSTA; +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res[3]; + S3C24X0_REG8 SDIDAT; +#else + S3C24X0_REG8 SDIDAT; + S3C24X0_REG8 res[3]; +#endif + S3C24X0_REG32 SDIIMSK; +}; + +#endif /*__S3C24X0_H__*/ diff --git a/include/s3c2400.h b/include/s3c2400.h deleted file mode 100644 index 062259d102..0000000000 --- a/include/s3c2400.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : s3c2400.h - * Version : 31.3.2003 - * - * Based on S3C2400X User's manual Rev 1.1 - ************************************************/ - -#ifndef __S3C2400_H__ -#define __S3C2400_H__ - -#define S3C24X0_UART_CHANNELS 2 -#define S3C24X0_SPI_CHANNELS 1 -#define PALETTE (0x14A00400) /* SJS */ - -enum s3c24x0_uarts_nr { - S3C24X0_UART0, - S3C24X0_UART1, -}; - -/*S3C2400 device base addresses */ -#define S3C24X0_MEMCTL_BASE 0x14000000 -#define S3C24X0_USB_HOST_BASE 0x14200000 -#define S3C24X0_INTERRUPT_BASE 0x14400000 -#define S3C24X0_DMA_BASE 0x14600000 -#define S3C24X0_CLOCK_POWER_BASE 0x14800000 -#define S3C24X0_LCD_BASE 0x14A00000 -#define S3C24X0_UART_BASE 0x15000000 -#define S3C24X0_TIMER_BASE 0x15100000 -#define S3C24X0_USB_DEVICE_BASE 0x15200140 -#define S3C24X0_WATCHDOG_BASE 0x15300000 -#define S3C24X0_I2C_BASE 0x15400000 -#define S3C24X0_I2S_BASE 0x15508000 -#define S3C24X0_GPIO_BASE 0x15600000 -#define S3C24X0_RTC_BASE 0x15700000 -#define S3C24X0_ADC_BASE 0x15800000 -#define S3C24X0_SPI_BASE 0x15900000 -#define S3C2400_MMC_BASE 0x15A00000 - -/* include common stuff */ -#include - - -static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) -{ - return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; -} -static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) -{ - return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; -} -static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) -{ - return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; -} -static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) -{ - return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; -} -static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) -{ - return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; -} -static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) -{ - return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; -} -static inline struct s3c24x0_uart - *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) -{ - return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); -} -static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) -{ - return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; -} -static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) -{ - return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; -} -static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) -{ - return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; -} -static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) -{ - return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; -} -static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) -{ - return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; -} -static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) -{ - return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; -} -static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) -{ - return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; -} -static inline struct s3c2400_adc *s3c2400_get_base_adc(void) -{ - return (struct s3c2400_adc *)S3C24X0_ADC_BASE; -} -static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) -{ - return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; -} -static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void) -{ - return (struct s3c2400_mmc *)S3C2400_MMC_BASE; -} - -#endif /*__S3C2400_H__*/ diff --git a/include/s3c2410.h b/include/s3c2410.h deleted file mode 100644 index 03b33b4924..0000000000 --- a/include/s3c2410.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : s3c2410.h - * Version : 31.3.2003 - * - * Based on S3C2410X User's manual Rev 1.1 - ************************************************/ - -#ifndef __S3C2410_H__ -#define __S3C2410_H__ - -#define S3C24X0_UART_CHANNELS 3 -#define S3C24X0_SPI_CHANNELS 2 - -/* S3C2410 only supports 512 Byte HW ECC */ -#define S3C2410_ECCSIZE 512 -#define S3C2410_ECCBYTES 3 - -enum s3c24x0_uarts_nr { - S3C24X0_UART0, - S3C24X0_UART1, - S3C24X0_UART2 -}; - -/* S3C2410 device base addresses */ -#define S3C24X0_MEMCTL_BASE 0x48000000 -#define S3C24X0_USB_HOST_BASE 0x49000000 -#define S3C24X0_INTERRUPT_BASE 0x4A000000 -#define S3C24X0_DMA_BASE 0x4B000000 -#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 -#define S3C24X0_LCD_BASE 0x4D000000 -#define S3C2410_NAND_BASE 0x4E000000 -#define S3C24X0_UART_BASE 0x50000000 -#define S3C24X0_TIMER_BASE 0x51000000 -#define S3C24X0_USB_DEVICE_BASE 0x52000140 -#define S3C24X0_WATCHDOG_BASE 0x53000000 -#define S3C24X0_I2C_BASE 0x54000000 -#define S3C24X0_I2S_BASE 0x55000000 -#define S3C24X0_GPIO_BASE 0x56000000 -#define S3C24X0_RTC_BASE 0x57000000 -#define S3C2410_ADC_BASE 0x58000000 -#define S3C24X0_SPI_BASE 0x59000000 -#define S3C2410_SDI_BASE 0x5A000000 - - -/* include common stuff */ -#include - - -static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) -{ - return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; -} -static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) -{ - return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; -} -static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) -{ - return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; -} -static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) -{ - return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; -} -static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) -{ - return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; -} -static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) -{ - return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; -} -static inline struct s3c2410_nand *s3c2410_get_base_nand(void) -{ - return (struct s3c2410_nand *)S3C2410_NAND_BASE; -} -static inline struct s3c24x0_uart - *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) -{ - return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); -} -static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) -{ - return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; -} -static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) -{ - return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; -} -static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) -{ - return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; -} -static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) -{ - return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; -} -static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) -{ - return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; -} -static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) -{ - return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; -} -static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) -{ - return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; -} -static inline struct s3c2410_adc *s3c2410_get_base_adc(void) -{ - return (struct s3c2410_adc *)S3C2410_ADC_BASE; -} -static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) -{ - return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; -} -static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void) -{ - return (struct s3c2410_sdi *)S3C2410_SDI_BASE; -} - -#endif /*__S3C2410_H__*/ diff --git a/include/s3c24x0.h b/include/s3c24x0.h deleted file mode 100644 index 56a551aeb4..0000000000 --- a/include/s3c24x0.h +++ /dev/null @@ -1,656 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : s3c24x0.h - * Version : 31.3.2003 - * - * common stuff for SAMSUNG S3C24X0 SoC - ************************************************/ - -#ifndef __S3C24X0_H__ -#define __S3C24X0_H__ - -typedef volatile u8 S3C24X0_REG8; -typedef volatile u16 S3C24X0_REG16; -typedef volatile u32 S3C24X0_REG32; - -/* Memory controller (see manual chapter 5) */ -struct s3c24x0_memctl { - S3C24X0_REG32 BWSCON; - S3C24X0_REG32 BANKCON[8]; - S3C24X0_REG32 REFRESH; - S3C24X0_REG32 BANKSIZE; - S3C24X0_REG32 MRSRB6; - S3C24X0_REG32 MRSRB7; -}; - - -/* USB HOST (see manual chapter 12) */ -struct s3c24x0_usb_host { - S3C24X0_REG32 HcRevision; - S3C24X0_REG32 HcControl; - S3C24X0_REG32 HcCommonStatus; - S3C24X0_REG32 HcInterruptStatus; - S3C24X0_REG32 HcInterruptEnable; - S3C24X0_REG32 HcInterruptDisable; - S3C24X0_REG32 HcHCCA; - S3C24X0_REG32 HcPeriodCuttendED; - S3C24X0_REG32 HcControlHeadED; - S3C24X0_REG32 HcControlCurrentED; - S3C24X0_REG32 HcBulkHeadED; - S3C24X0_REG32 HcBuldCurrentED; - S3C24X0_REG32 HcDoneHead; - S3C24X0_REG32 HcRmInterval; - S3C24X0_REG32 HcFmRemaining; - S3C24X0_REG32 HcFmNumber; - S3C24X0_REG32 HcPeriodicStart; - S3C24X0_REG32 HcLSThreshold; - S3C24X0_REG32 HcRhDescriptorA; - S3C24X0_REG32 HcRhDescriptorB; - S3C24X0_REG32 HcRhStatus; - S3C24X0_REG32 HcRhPortStatus1; - S3C24X0_REG32 HcRhPortStatus2; -}; - - -/* INTERRUPT (see manual chapter 14) */ -struct s3c24x0_interrupt { - S3C24X0_REG32 SRCPND; - S3C24X0_REG32 INTMOD; - S3C24X0_REG32 INTMSK; - S3C24X0_REG32 PRIORITY; - S3C24X0_REG32 INTPND; - S3C24X0_REG32 INTOFFSET; -#ifdef CONFIG_S3C2410 - S3C24X0_REG32 SUBSRCPND; - S3C24X0_REG32 INTSUBMSK; -#endif -}; - - -/* DMAS (see manual chapter 8) */ -struct s3c24x0_dma { - S3C24X0_REG32 DISRC; -#ifdef CONFIG_S3C2410 - S3C24X0_REG32 DISRCC; -#endif - S3C24X0_REG32 DIDST; -#ifdef CONFIG_S3C2410 - S3C24X0_REG32 DIDSTC; -#endif - S3C24X0_REG32 DCON; - S3C24X0_REG32 DSTAT; - S3C24X0_REG32 DCSRC; - S3C24X0_REG32 DCDST; - S3C24X0_REG32 DMASKTRIG; -#ifdef CONFIG_S3C2400 - S3C24X0_REG32 res[1]; -#endif -#ifdef CONFIG_S3C2410 - S3C24X0_REG32 res[7]; -#endif -}; - -struct s3c24x0_dmas { - struct s3c24x0_dma dma[4]; -}; - - -/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ -/* (see S3C2410 manual chapter 7) */ -struct s3c24x0_clock_power { - S3C24X0_REG32 LOCKTIME; - S3C24X0_REG32 MPLLCON; - S3C24X0_REG32 UPLLCON; - S3C24X0_REG32 CLKCON; - S3C24X0_REG32 CLKSLOW; - S3C24X0_REG32 CLKDIVN; -}; - - -/* LCD CONTROLLER (see manual chapter 15) */ -struct s3c24x0_lcd { - S3C24X0_REG32 LCDCON1; - S3C24X0_REG32 LCDCON2; - S3C24X0_REG32 LCDCON3; - S3C24X0_REG32 LCDCON4; - S3C24X0_REG32 LCDCON5; - S3C24X0_REG32 LCDSADDR1; - S3C24X0_REG32 LCDSADDR2; - S3C24X0_REG32 LCDSADDR3; - S3C24X0_REG32 REDLUT; - S3C24X0_REG32 GREENLUT; - S3C24X0_REG32 BLUELUT; - S3C24X0_REG32 res[8]; - S3C24X0_REG32 DITHMODE; - S3C24X0_REG32 TPAL; -#ifdef CONFIG_S3C2410 - S3C24X0_REG32 LCDINTPND; - S3C24X0_REG32 LCDSRCPND; - S3C24X0_REG32 LCDINTMSK; - S3C24X0_REG32 LPCSEL; -#endif -}; - - -/* NAND FLASH (see S3C2410 manual chapter 6) */ -struct s3c2410_nand { - S3C24X0_REG32 NFCONF; - S3C24X0_REG32 NFCMD; - S3C24X0_REG32 NFADDR; - S3C24X0_REG32 NFDATA; - S3C24X0_REG32 NFSTAT; - S3C24X0_REG32 NFECC; -}; - - -/* UART (see manual chapter 11) */ -struct s3c24x0_uart { - S3C24X0_REG32 ULCON; - S3C24X0_REG32 UCON; - S3C24X0_REG32 UFCON; - S3C24X0_REG32 UMCON; - S3C24X0_REG32 UTRSTAT; - S3C24X0_REG32 UERSTAT; - S3C24X0_REG32 UFSTAT; - S3C24X0_REG32 UMSTAT; -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 UTXH; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 URXH; -#else /* Little Endian */ - S3C24X0_REG8 UTXH; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 URXH; - S3C24X0_REG8 res2[3]; -#endif - S3C24X0_REG32 UBRDIV; -}; - - -/* PWM TIMER (see manual chapter 10) */ -struct s3c24x0_timer { - S3C24X0_REG32 TCNTB; - S3C24X0_REG32 TCMPB; - S3C24X0_REG32 TCNTO; -}; - -struct s3c24x0_timers { - S3C24X0_REG32 TCFG0; - S3C24X0_REG32 TCFG1; - S3C24X0_REG32 TCON; - struct s3c24x0_timer ch[4]; - S3C24X0_REG32 TCNTB4; - S3C24X0_REG32 TCNTO4; -}; - - -/* USB DEVICE (see manual chapter 13) */ -struct s3c24x0_usb_dev_fifos { -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res[3]; - S3C24X0_REG8 EP_FIFO_REG; -#else /* little endian */ - S3C24X0_REG8 EP_FIFO_REG; - S3C24X0_REG8 res[3]; -#endif -}; - -struct s3c24x0_usb_dev_dmas { -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 EP_DMA_CON; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 EP_DMA_UNIT; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 EP_DMA_FIFO; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 EP_DMA_TTC_L; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 EP_DMA_TTC_M; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 EP_DMA_TTC_H; -#else /* little endian */ - S3C24X0_REG8 EP_DMA_CON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 EP_DMA_UNIT; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 EP_DMA_FIFO; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 EP_DMA_TTC_L; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 EP_DMA_TTC_M; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 EP_DMA_TTC_H; - S3C24X0_REG8 res6[3]; -#endif -}; - -struct s3c24x0_usb_device { -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 FUNC_ADDR_REG; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 PWR_REG; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 EP_INT_REG; - S3C24X0_REG8 res4[15]; - S3C24X0_REG8 USB_INT_REG; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 EP_INT_EN_REG; - S3C24X0_REG8 res6[15]; - S3C24X0_REG8 USB_INT_EN_REG; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 FRAME_NUM1_REG; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 FRAME_NUM2_REG; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 INDEX_REG; - S3C24X0_REG8 res10[7]; - S3C24X0_REG8 MAXP_REG; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 EP0_CSR_IN_CSR1_REG; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 IN_CSR2_REG; - S3C24X0_REG8 res13[7]; - S3C24X0_REG8 OUT_CSR1_REG; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 OUT_CSR2_REG; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 OUT_FIFO_CNT1_REG; - S3C24X0_REG8 res16[3]; - S3C24X0_REG8 OUT_FIFO_CNT2_REG; -#else /* little endian */ - S3C24X0_REG8 FUNC_ADDR_REG; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 PWR_REG; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 EP_INT_REG; - S3C24X0_REG8 res3[15]; - S3C24X0_REG8 USB_INT_REG; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 EP_INT_EN_REG; - S3C24X0_REG8 res5[15]; - S3C24X0_REG8 USB_INT_EN_REG; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 FRAME_NUM1_REG; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 FRAME_NUM2_REG; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 INDEX_REG; - S3C24X0_REG8 res9[7]; - S3C24X0_REG8 MAXP_REG; - S3C24X0_REG8 res10[7]; - S3C24X0_REG8 EP0_CSR_IN_CSR1_REG; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 IN_CSR2_REG; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 OUT_CSR1_REG; - S3C24X0_REG8 res13[7]; - S3C24X0_REG8 OUT_CSR2_REG; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 OUT_FIFO_CNT1_REG; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 OUT_FIFO_CNT2_REG; - S3C24X0_REG8 res16[3]; -#endif /* __BIG_ENDIAN */ - struct s3c24x0_usb_dev_fifos fifo[5]; - struct s3c24x0_usb_dev_dmas dma[5]; -}; - - -/* WATCH DOG TIMER (see manual chapter 18) */ -struct s3c24x0_watchdog { - S3C24X0_REG32 WTCON; - S3C24X0_REG32 WTDAT; - S3C24X0_REG32 WTCNT; -}; - - -/* IIC (see manual chapter 20) */ -struct s3c24x0_i2c { - S3C24X0_REG32 IICCON; - S3C24X0_REG32 IICSTAT; - S3C24X0_REG32 IICADD; - S3C24X0_REG32 IICDS; -}; - - -/* IIS (see manual chapter 21) */ -struct s3c24x0_i2s { -#ifdef __BIG_ENDIAN - S3C24X0_REG16 res1; - S3C24X0_REG16 IISCON; - S3C24X0_REG16 res2; - S3C24X0_REG16 IISMOD; - S3C24X0_REG16 res3; - S3C24X0_REG16 IISPSR; - S3C24X0_REG16 res4; - S3C24X0_REG16 IISFCON; - S3C24X0_REG16 res5; - S3C24X0_REG16 IISFIFO; -#else /* little endian */ - S3C24X0_REG16 IISCON; - S3C24X0_REG16 res1; - S3C24X0_REG16 IISMOD; - S3C24X0_REG16 res2; - S3C24X0_REG16 IISPSR; - S3C24X0_REG16 res3; - S3C24X0_REG16 IISFCON; - S3C24X0_REG16 res4; - S3C24X0_REG16 IISFIFO; - S3C24X0_REG16 res5; -#endif -}; - - -/* I/O PORT (see manual chapter 9) */ -struct s3c24x0_gpio { -#ifdef CONFIG_S3C2400 - S3C24X0_REG32 PACON; - S3C24X0_REG32 PADAT; - - S3C24X0_REG32 PBCON; - S3C24X0_REG32 PBDAT; - S3C24X0_REG32 PBUP; - - S3C24X0_REG32 PCCON; - S3C24X0_REG32 PCDAT; - S3C24X0_REG32 PCUP; - - S3C24X0_REG32 PDCON; - S3C24X0_REG32 PDDAT; - S3C24X0_REG32 PDUP; - - S3C24X0_REG32 PECON; - S3C24X0_REG32 PEDAT; - S3C24X0_REG32 PEUP; - - S3C24X0_REG32 PFCON; - S3C24X0_REG32 PFDAT; - S3C24X0_REG32 PFUP; - - S3C24X0_REG32 PGCON; - S3C24X0_REG32 PGDAT; - S3C24X0_REG32 PGUP; - - S3C24X0_REG32 OPENCR; - - S3C24X0_REG32 MISCCR; - S3C24X0_REG32 EXTINT; -#endif -#ifdef CONFIG_S3C2410 - S3C24X0_REG32 GPACON; - S3C24X0_REG32 GPADAT; - S3C24X0_REG32 res1[2]; - S3C24X0_REG32 GPBCON; - S3C24X0_REG32 GPBDAT; - S3C24X0_REG32 GPBUP; - S3C24X0_REG32 res2; - S3C24X0_REG32 GPCCON; - S3C24X0_REG32 GPCDAT; - S3C24X0_REG32 GPCUP; - S3C24X0_REG32 res3; - S3C24X0_REG32 GPDCON; - S3C24X0_REG32 GPDDAT; - S3C24X0_REG32 GPDUP; - S3C24X0_REG32 res4; - S3C24X0_REG32 GPECON; - S3C24X0_REG32 GPEDAT; - S3C24X0_REG32 GPEUP; - S3C24X0_REG32 res5; - S3C24X0_REG32 GPFCON; - S3C24X0_REG32 GPFDAT; - S3C24X0_REG32 GPFUP; - S3C24X0_REG32 res6; - S3C24X0_REG32 GPGCON; - S3C24X0_REG32 GPGDAT; - S3C24X0_REG32 GPGUP; - S3C24X0_REG32 res7; - S3C24X0_REG32 GPHCON; - S3C24X0_REG32 GPHDAT; - S3C24X0_REG32 GPHUP; - S3C24X0_REG32 res8; - - S3C24X0_REG32 MISCCR; - S3C24X0_REG32 DCLKCON; - S3C24X0_REG32 EXTINT0; - S3C24X0_REG32 EXTINT1; - S3C24X0_REG32 EXTINT2; - S3C24X0_REG32 EINTFLT0; - S3C24X0_REG32 EINTFLT1; - S3C24X0_REG32 EINTFLT2; - S3C24X0_REG32 EINTFLT3; - S3C24X0_REG32 EINTMASK; - S3C24X0_REG32 EINTPEND; - S3C24X0_REG32 GSTATUS0; - S3C24X0_REG32 GSTATUS1; - S3C24X0_REG32 GSTATUS2; - S3C24X0_REG32 GSTATUS3; - S3C24X0_REG32 GSTATUS4; -#endif -}; - - -/* RTC (see manual chapter 17) */ -struct s3c24x0_rtc { -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[67]; - S3C24X0_REG8 RTCCON; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 TICNT; - S3C24X0_REG8 res3[11]; - S3C24X0_REG8 RTCALM; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 ALMSEC; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 ALMMIN; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 ALMHOUR; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 ALMDATE; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 ALMMON; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 ALMYEAR; - S3C24X0_REG8 res10[3]; - S3C24X0_REG8 RTCRST; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 BCDSEC; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 BCDMIN; - S3C24X0_REG8 res13[3]; - S3C24X0_REG8 BCDHOUR; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 BCDDATE; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 BCDDAY; - S3C24X0_REG8 res16[3]; - S3C24X0_REG8 BCDMON; - S3C24X0_REG8 res17[3]; - S3C24X0_REG8 BCDYEAR; -#else /* little endian */ - S3C24X0_REG8 res0[64]; - S3C24X0_REG8 RTCCON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 TICNT; - S3C24X0_REG8 res2[11]; - S3C24X0_REG8 RTCALM; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 ALMSEC; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 ALMMIN; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 ALMHOUR; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 ALMDATE; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 ALMMON; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 ALMYEAR; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 RTCRST; - S3C24X0_REG8 res10[3]; - S3C24X0_REG8 BCDSEC; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 BCDMIN; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 BCDHOUR; - S3C24X0_REG8 res13[3]; - S3C24X0_REG8 BCDDATE; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 BCDDAY; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 BCDMON; - S3C24X0_REG8 res16[3]; - S3C24X0_REG8 BCDYEAR; - S3C24X0_REG8 res17[3]; -#endif -}; - - -/* ADC (see manual chapter 16) */ -struct s3c2400_adc { - S3C24X0_REG32 ADCCON; - S3C24X0_REG32 ADCDAT; -}; - - -/* ADC (see manual chapter 16) */ -struct s3c2410_adc { - S3C24X0_REG32 ADCCON; - S3C24X0_REG32 ADCTSC; - S3C24X0_REG32 ADCDLY; - S3C24X0_REG32 ADCDAT0; - S3C24X0_REG32 ADCDAT1; -}; - - -/* SPI (see manual chapter 22) */ -struct s3c24x0_spi_channel { - S3C24X0_REG8 SPCON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 SPSTA; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 SPPIN; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 SPPRE; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 SPTDAT; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 SPRDAT; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 res7[16]; -}; - -struct s3c24x0_spi { - struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS]; -}; - - -/* MMC INTERFACE (see S3C2400 manual chapter 19) */ -struct s3c2400_mmc { -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 MMCON; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 MMCRR; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 MMFCON; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 MMSTA; - S3C24X0_REG16 res5; - S3C24X0_REG16 MMFSTA; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 MMPRE; - S3C24X0_REG16 res7; - S3C24X0_REG16 MMLEN; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 MMCR7; - S3C24X0_REG32 MMRSP[4]; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 MMCMD0; - S3C24X0_REG32 MMCMD1; - S3C24X0_REG16 res10; - S3C24X0_REG16 MMCR16; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 MMDAT; -#else - S3C24X0_REG8 MMCON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 MMCRR; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 MMFCON; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 MMSTA; - S3C24X0_REG8 res4[3]; - S3C24X0_REG16 MMFSTA; - S3C24X0_REG16 res5; - S3C24X0_REG8 MMPRE; - S3C24X0_REG8 res6[3]; - S3C24X0_REG16 MMLEN; - S3C24X0_REG16 res7; - S3C24X0_REG8 MMCR7; - S3C24X0_REG8 res8[3]; - S3C24X0_REG32 MMRSP[4]; - S3C24X0_REG8 MMCMD0; - S3C24X0_REG8 res9[3]; - S3C24X0_REG32 MMCMD1; - S3C24X0_REG16 MMCR16; - S3C24X0_REG16 res10; - S3C24X0_REG8 MMDAT; - S3C24X0_REG8 res11[3]; -#endif -}; - - -/* SD INTERFACE (see S3C2410 manual chapter 19) */ -struct s3c2410_sdi { - S3C24X0_REG32 SDICON; - S3C24X0_REG32 SDIPRE; - S3C24X0_REG32 SDICARG; - S3C24X0_REG32 SDICCON; - S3C24X0_REG32 SDICSTA; - S3C24X0_REG32 SDIRSP0; - S3C24X0_REG32 SDIRSP1; - S3C24X0_REG32 SDIRSP2; - S3C24X0_REG32 SDIRSP3; - S3C24X0_REG32 SDIDTIMER; - S3C24X0_REG32 SDIBSIZE; - S3C24X0_REG32 SDIDCON; - S3C24X0_REG32 SDIDCNT; - S3C24X0_REG32 SDIDSTA; - S3C24X0_REG32 SDIFSTA; -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res[3]; - S3C24X0_REG8 SDIDAT; -#else - S3C24X0_REG8 SDIDAT; - S3C24X0_REG8 res[3]; -#endif - S3C24X0_REG32 SDIIMSK; -}; - -#endif /*__S3C24X0_H__*/ -- cgit v1.2.1 From 47e801bec360e69e4b087a141d015b318e1b0212 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Wed, 4 Nov 2009 16:07:59 +0900 Subject: s3c64xx: move s3c64xx header files to asm-arm/arch-s3c64xx This patch moves the s3c64xx header files from include/ to include/asm-arm/arch-s3c64xx Signed-off-by: Minkyu Kang --- include/asm-arm/arch-s3c64xx/s3c6400.h | 895 +++++++++++++++++++++++++++++++++ include/asm-arm/arch-s3c64xx/s3c64x0.h | 90 ++++ include/s3c6400.h | 895 --------------------------------- include/s3c64x0.h | 90 ---- 4 files changed, 985 insertions(+), 985 deletions(-) create mode 100644 include/asm-arm/arch-s3c64xx/s3c6400.h create mode 100644 include/asm-arm/arch-s3c64xx/s3c64x0.h delete mode 100644 include/s3c6400.h delete mode 100644 include/s3c64x0.h (limited to 'include') diff --git a/include/asm-arm/arch-s3c64xx/s3c6400.h b/include/asm-arm/arch-s3c64xx/s3c6400.h new file mode 100644 index 0000000000..e527c08b18 --- /dev/null +++ b/include/asm-arm/arch-s3c64xx/s3c6400.h @@ -0,0 +1,895 @@ +/* + * (C) Copyright 2007 + * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com. + * - only support for S3C6400 + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : s3c6400.h + * + * Based on S3C6400 User's manual Rev 0.0 + ************************************************/ + +#ifndef __S3C6400_H__ +#define __S3C6400_H__ + +#define S3C64XX_UART_CHANNELS 3 +#define S3C64XX_SPI_CHANNELS 2 + +#include + +#define ELFIN_CLOCK_POWER_BASE 0x7e00f000 + +/* Clock & Power Controller for mDirac3*/ +#define APLL_LOCK_OFFSET 0x00 +#define MPLL_LOCK_OFFSET 0x04 +#define EPLL_LOCK_OFFSET 0x08 +#define APLL_CON_OFFSET 0x0C +#define MPLL_CON_OFFSET 0x10 +#define EPLL_CON0_OFFSET 0x14 +#define EPLL_CON1_OFFSET 0x18 +#define CLK_SRC_OFFSET 0x1C +#define CLK_DIV0_OFFSET 0x20 +#define CLK_DIV1_OFFSET 0x24 +#define CLK_DIV2_OFFSET 0x28 +#define CLK_OUT_OFFSET 0x2C +#define HCLK_GATE_OFFSET 0x30 +#define PCLK_GATE_OFFSET 0x34 +#define SCLK_GATE_OFFSET 0x38 +#define AHB_CON0_OFFSET 0x100 +#define AHB_CON1_OFFSET 0x104 +#define AHB_CON2_OFFSET 0x108 +#define SELECT_DMA_OFFSET 0x110 +#define SW_RST_OFFSET 0x114 +#define SYS_ID_OFFSET 0x118 +#define MEM_SYS_CFG_OFFSET 0x120 +#define QOS_OVERRIDE0_OFFSET 0x124 +#define QOS_OVERRIDE1_OFFSET 0x128 +#define MEM_CFG_STAT_OFFSET 0x12C +#define PWR_CFG_OFFSET 0x804 +#define EINT_MASK_OFFSET 0x808 +#define NOR_CFG_OFFSET 0x810 +#define STOP_CFG_OFFSET 0x814 +#define SLEEP_CFG_OFFSET 0x818 +#define OSC_FREQ_OFFSET 0x820 +#define OSC_STABLE_OFFSET 0x824 +#define PWR_STABLE_OFFSET 0x828 +#define FPC_STABLE_OFFSET 0x82C +#define MTC_STABLE_OFFSET 0x830 +#define OTHERS_OFFSET 0x900 +#define RST_STAT_OFFSET 0x904 +#define WAKEUP_STAT_OFFSET 0x908 +#define BLK_PWR_STAT_OFFSET 0x90C +#define INF_REG0_OFFSET 0xA00 +#define INF_REG1_OFFSET 0xA04 +#define INF_REG2_OFFSET 0xA08 +#define INF_REG3_OFFSET 0xA0C +#define INF_REG4_OFFSET 0xA10 +#define INF_REG5_OFFSET 0xA14 +#define INF_REG6_OFFSET 0xA18 +#define INF_REG7_OFFSET 0xA1C + +#define OSC_CNT_VAL_OFFSET 0x824 +#define PWR_CNT_VAL_OFFSET 0x828 +#define FPC_CNT_VAL_OFFSET 0x82C +#define MTC_CNT_VAL_OFFSET 0x830 + +#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) +#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) +#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) +#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) +#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) +#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) +#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) +#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) +#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) +#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) +#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) +#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) +#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) +#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) +#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) +#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) +#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) +#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) +#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + SELECT_DMA_OFFSET) +#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) +#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) +#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + MEM_SYS_CFG_OFFSET) +#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + QOS_OVERRIDE0_OFFSET) +#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + QOS_OVERRIDE1_OFFSET) +#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + MEM_CFG_STAT_OFFSET) +#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) +#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) +#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) +#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) +#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) +#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) +#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + OSC_CNT_VAL_OFFSET) +#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + PWR_CNT_VAL_OFFSET) +#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + FPC_CNT_VAL_OFFSET) +#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + MTC_CNT_VAL_OFFSET) +#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) +#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) +#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + WAKEUP_STAT_OFFSET) +#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + BLK_PWR_STAT_OFFSET) +#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) +#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) +#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) +#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) +#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) +#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) +#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) +#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) + +#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) +#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) +#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) +#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) +#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) +#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) +#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) +#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) +#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) +#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) +#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) +#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) +#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) +#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) +#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) +#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) +#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) +#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) +#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET) +#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) +#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) +#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET) +#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET) +#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET) +#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET) +#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) +#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) +#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) +#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) +#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) +#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) +#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET) +#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET) +#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET) +#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET) +#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) +#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) +#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET) +#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET) +#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) +#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) +#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) +#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) +#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) +#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) +#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) +#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) + + +/* + * GPIO + */ +#define ELFIN_GPIO_BASE 0x7f008000 + +#define GPACON_OFFSET 0x00 +#define GPADAT_OFFSET 0x04 +#define GPAPUD_OFFSET 0x08 +#define GPACONSLP_OFFSET 0x0C +#define GPAPUDSLP_OFFSET 0x10 +#define GPBCON_OFFSET 0x20 +#define GPBDAT_OFFSET 0x24 +#define GPBPUD_OFFSET 0x28 +#define GPBCONSLP_OFFSET 0x2C +#define GPBPUDSLP_OFFSET 0x30 +#define GPCCON_OFFSET 0x40 +#define GPCDAT_OFFSET 0x44 +#define GPCPUD_OFFSET 0x48 +#define GPCCONSLP_OFFSET 0x4C +#define GPCPUDSLP_OFFSET 0x50 +#define GPDCON_OFFSET 0x60 +#define GPDDAT_OFFSET 0x64 +#define GPDPUD_OFFSET 0x68 +#define GPDCONSLP_OFFSET 0x6C +#define GPDPUDSLP_OFFSET 0x70 +#define GPECON_OFFSET 0x80 +#define GPEDAT_OFFSET 0x84 +#define GPEPUD_OFFSET 0x88 +#define GPECONSLP_OFFSET 0x8C +#define GPEPUDSLP_OFFSET 0x90 +#define GPFCON_OFFSET 0xA0 +#define GPFDAT_OFFSET 0xA4 +#define GPFPUD_OFFSET 0xA8 +#define GPFCONSLP_OFFSET 0xAC +#define GPFPUDSLP_OFFSET 0xB0 +#define GPGCON_OFFSET 0xC0 +#define GPGDAT_OFFSET 0xC4 +#define GPGPUD_OFFSET 0xC8 +#define GPGCONSLP_OFFSET 0xCC +#define GPGPUDSLP_OFFSET 0xD0 +#define GPHCON0_OFFSET 0xE0 +#define GPHCON1_OFFSET 0xE4 +#define GPHDAT_OFFSET 0xE8 +#define GPHPUD_OFFSET 0xEC +#define GPHCONSLP_OFFSET 0xF0 +#define GPHPUDSLP_OFFSET 0xF4 +#define GPICON_OFFSET 0x100 +#define GPIDAT_OFFSET 0x104 +#define GPIPUD_OFFSET 0x108 +#define GPICONSLP_OFFSET 0x10C +#define GPIPUDSLP_OFFSET 0x110 +#define GPJCON_OFFSET 0x120 +#define GPJDAT_OFFSET 0x124 +#define GPJPUD_OFFSET 0x128 +#define GPJCONSLP_OFFSET 0x12C +#define GPJPUDSLP_OFFSET 0x130 +#define MEM0DRVCON_OFFSET 0x1D0 +#define MEM1DRVCON_OFFSET 0x1D4 +#define GPKCON0_OFFSET 0x800 +#define GPKCON1_OFFSET 0x804 +#define GPKDAT_OFFSET 0x808 +#define GPKPUD_OFFSET 0x80C +#define GPLCON0_OFFSET 0x810 +#define GPLCON1_OFFSET 0x814 +#define GPLDAT_OFFSET 0x818 +#define GPLPUD_OFFSET 0x81C +#define GPMCON_OFFSET 0x820 +#define GPMDAT_OFFSET 0x824 +#define GPMPUD_OFFSET 0x828 +#define GPNCON_OFFSET 0x830 +#define GPNDAT_OFFSET 0x834 +#define GPNPUD_OFFSET 0x838 +#define GPOCON_OFFSET 0x140 +#define GPODAT_OFFSET 0x144 +#define GPOPUD_OFFSET 0x148 +#define GPOCONSLP_OFFSET 0x14C +#define GPOPUDSLP_OFFSET 0x150 +#define GPPCON_OFFSET 0x160 +#define GPPDAT_OFFSET 0x164 +#define GPPPUD_OFFSET 0x168 +#define GPPCONSLP_OFFSET 0x16C +#define GPPPUDSLP_OFFSET 0x170 +#define GPQCON_OFFSET 0x180 +#define GPQDAT_OFFSET 0x184 +#define GPQPUD_OFFSET 0x188 +#define GPQCONSLP_OFFSET 0x18C +#define GPQPUDSLP_OFFSET 0x190 + +#define EINTPEND_OFFSET 0x924 + +#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET) +#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET) +#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET) +#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET) +#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) +#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET) +#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET) +#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET) +#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) +#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) +#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET) +#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET) +#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET) +#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) +#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) +#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET) +#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET) +#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET) +#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) +#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) +#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET) +#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET) +#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET) +#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET) +#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) +#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET) +#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET) +#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET) +#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) +#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) +#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET) +#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET) +#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET) +#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) +#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) +#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET) +#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET) +#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET) +#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET) +#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) +#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) +#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET) +#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET) +#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET) +#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET) +#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) +#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET) +#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET) +#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET) +#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) +#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) +#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET) +#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET) +#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET) +#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET) +#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET) +#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET) +#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET) +#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET) +#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET) +#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET) +#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET) +#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET) +#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET) +#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET) +#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET) +#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET) +#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET) +#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) +#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) +#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET) +#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET) +#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET) +#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) +#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) +#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET) +#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET) +#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET) +#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) +#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) + +/* + * Bus Matrix + */ +#define ELFIN_MEM_SYS_CFG 0x7e00f120 + +#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12) + +#define S3C64XX_MEM_SYS_CFG_NAND 0x0008 +#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT + +#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET) +#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET) +#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET) +#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET) +#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) +#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET) +#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET) +#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET) +#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) +#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) +#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET) +#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET) +#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET) +#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) +#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) +#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET) +#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET) +#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET) +#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) +#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) +#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET) +#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET) +#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET) +#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET) +#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) +#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET) +#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET) +#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET) +#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) +#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) +#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET) +#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET) +#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET) +#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) +#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) +#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET) +#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET) +#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET) +#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET) +#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) +#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) +#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET) +#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET) +#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET) +#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET) +#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) +#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET) +#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET) +#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET) +#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) +#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) +#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET) +#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET) +#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET) +#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET) +#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET) +#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET) +#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET) +#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET) +#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET) +#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET) +#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET) +#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET) +#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET) +#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET) +#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET) +#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET) +#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET) +#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) +#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) +#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET) +#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET) +#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET) +#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) +#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) +#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET) +#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET) +#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET) +#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) +#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) + +/* + * Memory controller + */ +#define ELFIN_SROM_BASE 0x70000000 + +#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0) +#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4) +#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8) +#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC) +#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10) +#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14) +#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18) + +/* + * SDRAM Controller + */ +#define ELFIN_DMC0_BASE 0x7e000000 +#define ELFIN_DMC1_BASE 0x7e001000 + +#define INDEX_DMC_MEMC_STATUS 0x00 +#define INDEX_DMC_MEMC_CMD 0x04 +#define INDEX_DMC_DIRECT_CMD 0x08 +#define INDEX_DMC_MEMORY_CFG 0x0C +#define INDEX_DMC_REFRESH_PRD 0x10 +#define INDEX_DMC_CAS_LATENCY 0x14 +#define INDEX_DMC_T_DQSS 0x18 +#define INDEX_DMC_T_MRD 0x1C +#define INDEX_DMC_T_RAS 0x20 +#define INDEX_DMC_T_RC 0x24 +#define INDEX_DMC_T_RCD 0x28 +#define INDEX_DMC_T_RFC 0x2C +#define INDEX_DMC_T_RP 0x30 +#define INDEX_DMC_T_RRD 0x34 +#define INDEX_DMC_T_WR 0x38 +#define INDEX_DMC_T_WTR 0x3C +#define INDEX_DMC_T_XP 0x40 +#define INDEX_DMC_T_XSR 0x44 +#define INDEX_DMC_T_ESR 0x48 +#define INDEX_DMC_MEMORY_CFG2 0x4C +#define INDEX_DMC_CHIP_0_CFG 0x200 +#define INDEX_DMC_CHIP_1_CFG 0x204 +#define INDEX_DMC_CHIP_2_CFG 0x208 +#define INDEX_DMC_CHIP_3_CFG 0x20C +#define INDEX_DMC_USER_STATUS 0x300 +#define INDEX_DMC_USER_CONFIG 0x304 + +/* + * Memory Chip direct command + */ +#define DMC_NOP0 0x0c0000 +#define DMC_NOP1 0x1c0000 +#define DMC_PA0 0x000000 /* Precharge all */ +#define DMC_PA1 0x100000 +#define DMC_AR0 0x040000 /* Autorefresh */ +#define DMC_AR1 0x140000 +#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */ +#define DMC_SDR_MR1 0x180032 +#define DMC_DDR_MR0 0x080162 +#define DMC_DDR_MR1 0x180162 +#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */ +#define DMC_mDDR_MR1 0x180032 +#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */ +#define DMC_mSDR_EMR1 0x1a0000 +#define DMC_DDR_EMR0 0x090000 +#define DMC_DDR_EMR1 0x190000 +#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */ +#define DMC_mDDR_EMR1 0x1a0000 + +/* + * Definitions for memory configuration + * Set memory configuration + * active_chips = 1'b0 (1 chip) + * qos_master_chip = 3'b000(ARID[3:0]) + * memory burst = 3'b010(burst 4) + * stop_mem_clock = 1'b0(disable dynamical stop) + * auto_power_down = 1'b0(disable auto power-down mode) + * power_down_prd = 6'b00_0000(0 cycle for auto power-down) + * ap_bit = 1'b0 (bit position of auto-precharge is 10) + * row_bits = 3'b010(# row address 13) + * column_bits = 3'b010(# column address 10 ) + * + * Set user configuration + * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR + * + * Set chip select for chip [n] + * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff + * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24] + */ + +/* + * Nand flash controller + */ +#define ELFIN_NAND_BASE 0x70200000 + +#define NFCONF_OFFSET 0x00 +#define NFCONT_OFFSET 0x04 +#define NFCMMD_OFFSET 0x08 +#define NFADDR_OFFSET 0x0c +#define NFDATA_OFFSET 0x10 +#define NFMECCDATA0_OFFSET 0x14 +#define NFMECCDATA1_OFFSET 0x18 +#define NFSECCDATA0_OFFSET 0x1c +#define NFSBLK_OFFSET 0x20 +#define NFEBLK_OFFSET 0x24 +#define NFSTAT_OFFSET 0x28 +#define NFESTAT0_OFFSET 0x2c +#define NFESTAT1_OFFSET 0x30 +#define NFMECC0_OFFSET 0x34 +#define NFMECC1_OFFSET 0x38 +#define NFSECC_OFFSET 0x3c +#define NFMLCBITPT_OFFSET 0x40 + +#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET) +#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET) +#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET) +#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET) +#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET) +#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) +#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) +#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) +#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET) +#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET) +#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET) +#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET) +#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET) +#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET) +#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET) +#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET) +#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) + +#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET) +#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET) +#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET) +#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET) +#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET) +#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET) +#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) +#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) +#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) +#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET) +#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET) +#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET) +#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET) +#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET) +#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET) +#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET) +#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET) +#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) + +#define NFCONF_ECC_4BIT (1<<24) + +#define NFCONT_ECC_ENC (1<<18) +#define NFCONT_WP (1<<16) +#define NFCONT_MECCLOCK (1<<7) +#define NFCONT_SECCLOCK (1<<6) +#define NFCONT_INITMECC (1<<5) +#define NFCONT_INITSECC (1<<4) +#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC) +#define NFCONT_CS_ALT (1<<2) +#define NFCONT_CS (1<<1) +#define NFCONT_ENABLE (1<<0) + +#define NFSTAT_ECCENCDONE (1<<7) +#define NFSTAT_ECCDECDONE (1<<6) +#define NFSTAT_RnB (1<<0) + +#define NFESTAT0_ECCBUSY (1<<31) + +/* + * Interrupt + */ +#define ELFIN_VIC0_BASE_ADDR 0x71200000 +#define ELFIN_VIC1_BASE_ADDR 0x71300000 +#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */ +#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */ +#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */ +#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */ +#define oVECTADDR 0xF00 /* VIC ADDRESS */ + +/* + * Watchdog timer + */ +#define ELFIN_WATCHDOG_BASE 0x7E004000 + +#define WTCON_REG __REG(0x7E004004) +#define WTDAT_REG __REG(0x7E004008) +#define WTCNT_REG __REG(0x7E00400C) + + +/* + * UART + */ +#define ELFIN_UART_BASE 0x7F005000 + +#define ELFIN_UART0_OFFSET 0x0000 +#define ELFIN_UART1_OFFSET 0x0400 +#define ELFIN_UART2_OFFSET 0x0800 + +#define ULCON_OFFSET 0x00 +#define UCON_OFFSET 0x04 +#define UFCON_OFFSET 0x08 +#define UMCON_OFFSET 0x0C +#define UTRSTAT_OFFSET 0x10 +#define UERSTAT_OFFSET 0x14 +#define UFSTAT_OFFSET 0x18 +#define UMSTAT_OFFSET 0x1C +#define UTXH_OFFSET 0x20 +#define URXH_OFFSET 0x24 +#define UBRDIV_OFFSET 0x28 +#define UDIVSLOT_OFFSET 0x2C +#define UINTP_OFFSET 0x30 +#define UINTSP_OFFSET 0x34 +#define UINTM_OFFSET 0x38 + +#define ULCON0_REG __REG(0x7F005000) +#define UCON0_REG __REG(0x7F005004) +#define UFCON0_REG __REG(0x7F005008) +#define UMCON0_REG __REG(0x7F00500C) +#define UTRSTAT0_REG __REG(0x7F005010) +#define UERSTAT0_REG __REG(0x7F005014) +#define UFSTAT0_REG __REG(0x7F005018) +#define UMSTAT0_REG __REG(0x7F00501c) +#define UTXH0_REG __REG(0x7F005020) +#define URXH0_REG __REG(0x7F005024) +#define UBRDIV0_REG __REG(0x7F005028) +#define UDIVSLOT0_REG __REG(0x7F00502c) +#define UINTP0_REG __REG(0x7F005030) +#define UINTSP0_REG __REG(0x7F005034) +#define UINTM0_REG __REG(0x7F005038) + +#define ULCON1_REG __REG(0x7F005400) +#define UCON1_REG __REG(0x7F005404) +#define UFCON1_REG __REG(0x7F005408) +#define UMCON1_REG __REG(0x7F00540C) +#define UTRSTAT1_REG __REG(0x7F005410) +#define UERSTAT1_REG __REG(0x7F005414) +#define UFSTAT1_REG __REG(0x7F005418) +#define UMSTAT1_REG __REG(0x7F00541c) +#define UTXH1_REG __REG(0x7F005420) +#define URXH1_REG __REG(0x7F005424) +#define UBRDIV1_REG __REG(0x7F005428) +#define UDIVSLOT1_REG __REG(0x7F00542c) +#define UINTP1_REG __REG(0x7F005430) +#define UINTSP1_REG __REG(0x7F005434) +#define UINTM1_REG __REG(0x7F005438) + +#define UTRSTAT_TX_EMPTY (1 << 2) +#define UTRSTAT_RX_READY (1 << 0) +#define UART_ERR_MASK 0xF + +/* + * PWM timer + */ +#define ELFIN_TIMER_BASE 0x7F006000 + +#define TCFG0_REG __REG(0x7F006000) +#define TCFG1_REG __REG(0x7F006004) +#define TCON_REG __REG(0x7F006008) +#define TCNTB0_REG __REG(0x7F00600c) +#define TCMPB0_REG __REG(0x7F006010) +#define TCNTO0_REG __REG(0x7F006014) +#define TCNTB1_REG __REG(0x7F006018) +#define TCMPB1_REG __REG(0x7F00601c) +#define TCNTO1_REG __REG(0x7F006020) +#define TCNTB2_REG __REG(0x7F006024) +#define TCMPB2_REG __REG(0x7F006028) +#define TCNTO2_REG __REG(0x7F00602c) +#define TCNTB3_REG __REG(0x7F006030) +#define TCMPB3_REG __REG(0x7F006034) +#define TCNTO3_REG __REG(0x7F006038) +#define TCNTB4_REG __REG(0x7F00603c) +#define TCNTO4_REG __REG(0x7F006040) + +/* Fields */ +#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */ +#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */ +#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */ +#define fTCFG1_MUX4 Fld(4, 16) +/* bits */ +#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE) +#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1) +#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0) +#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */ +#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */ +#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */ +#define COUNT_4_ON (TCON_4_ONOFF * 1) +#define COUNT_4_OFF (TCON_4_ONOFF * 0) +#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */ +#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1) +#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO) +#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */ +#define TIMER3_IVT_ON (TCON_3_INVERT * 1) +#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT)) +#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */ +#define TIMER3_MANUP (TCON_3_MAN*1) +#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN)) +#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */ +#define TIMER3_ON (TCON_3_ONOFF * 1) +#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF)) + +#if defined(CONFIG_CLK_400_100_50) +#define STARTUP_AMDIV 400 +#define STARTUP_MDIV 400 +#define STARTUP_PDIV 6 +#define STARTUP_SDIV 1 +#elif defined(CONFIG_CLK_400_133_66) +#define STARTUP_AMDIV 400 +#define STARTUP_MDIV 533 +#define STARTUP_PDIV 6 +#define STARTUP_SDIV 1 +#elif defined(CONFIG_CLK_533_133_66) +#define STARTUP_AMDIV 533 +#define STARTUP_MDIV 533 +#define STARTUP_PDIV 6 +#define STARTUP_SDIV 1 +#elif defined(CONFIG_CLK_667_133_66) +#define STARTUP_AMDIV 667 +#define STARTUP_MDIV 533 +#define STARTUP_PDIV 6 +#define STARTUP_SDIV 1 +#endif + +#define STARTUP_PCLKDIV 3 +#define STARTUP_HCLKX2DIV 1 +#define STARTUP_HCLKDIV 1 +#define STARTUP_MPLLDIV 1 +#define STARTUP_APLLDIV 0 + +#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \ + (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV) +#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ + (STARTUP_PDIV << 8) | STARTUP_SDIV) +#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ + STARTUP_PDIV) * STARTUP_MDIV) + +#if defined(CONFIG_SYNC_MODE) +#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ + (STARTUP_PDIV << 8) | STARTUP_SDIV) +#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ + STARTUP_PDIV) * STARTUP_MDIV) +#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ + (STARTUP_HCLKDIV + 1)) +#else +#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \ + (STARTUP_PDIV << 8) | STARTUP_SDIV) +#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ + STARTUP_PDIV) * STARTUP_AMDIV) +#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ + (STARTUP_HCLKDIV + 1)) +#endif + + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ +#define DMC1_MEM_CFG2 0xB45 +#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */ +#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ + +/* Memory Parameters */ +/* DDR Parameters */ +#define DDR_tREFRESH 7800 /* ns */ +#define DDR_tRAS 45 /* ns (min: 45ns)*/ +#define DDR_tRC 68 /* ns (min: 67.5ns)*/ +#define DDR_tRCD 23 /* ns (min: 22.5ns)*/ +#define DDR_tRFC 80 /* ns (min: 80ns)*/ +#define DDR_tRP 23 /* ns (min: 22.5ns)*/ +#define DDR_tRRD 15 /* ns (min: 15ns)*/ +#define DDR_tWR 15 /* ns (min: 15ns)*/ +#define DDR_tXSR 120 /* ns (min: 120ns)*/ +#define DDR_CASL 3 /* CAS Latency 3 */ + +/* + * mDDR memory configuration + */ + +#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000) + +#define DMC_DDR_BA_EMRS 2 +#define DMC_DDR_MEM_CASLAT 3 +/* 6 Set Cas Latency to 3 */ +#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1) +/* Min 0.75 ~ 1.25 */ +#define DMC_DDR_t_DQSS 1 +/* Min 2 tck */ +#define DMC_DDR_t_MRD 2 +/* 7, Min 45ns */ +#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1) +/* 10, Min 67.5ns */ +#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1) +/* 4,5(TRM), Min 22.5ns */ +#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1) +#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3) +/* 11,18(TRM) Min 80ns */ +#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1) +#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5) +/* 4, 5(TRM) Min 22.5ns */ +#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1) +#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3) +/* 3, Min 15ns */ +#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1) +/* Min 15ns */ +#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1) +#define DMC_DDR_t_WTR 2 +/* 1tck + tIS(1.5ns) */ +#define DMC_DDR_t_XP 2 +/* 17, Min 120ns */ +#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1) +#define DMC_DDR_t_ESR DMC_DDR_t_XSR +/* TRM 2656 */ +#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH)) +/* 2b01 : mDDR */ +#define DMC_DDR_USER_CONFIG 1 + +#ifndef __ASSEMBLY__ +enum s3c64xx_uarts_nr { + S3C64XX_UART0, + S3C64XX_UART1, + S3C64XX_UART2, +}; + +#include "s3c64x0.h" + +static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr) +{ + return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400)); +} +#endif + +#endif /*__S3C6400_H__*/ diff --git a/include/asm-arm/arch-s3c64xx/s3c64x0.h b/include/asm-arm/arch-s3c64xx/s3c64x0.h new file mode 100644 index 0000000000..0bbf1d0c43 --- /dev/null +++ b/include/asm-arm/arch-s3c64xx/s3c64x0.h @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2003 + * David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : S3C64XX.h + * Version : 31.3.2003 + * + * common stuff for SAMSUNG S3C64XX SoC + ************************************************/ + +#ifndef __S3C64XX_H__ +#define __S3C64XX_H__ + +#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400) +#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration! +#endif + +#include + +/* UART (see manual chapter 11) */ +typedef struct { + volatile u32 ULCON; + volatile u32 UCON; + volatile u32 UFCON; + volatile u32 UMCON; + volatile u32 UTRSTAT; + volatile u32 UERSTAT; + volatile u32 UFSTAT; + volatile u32 UMSTAT; +#ifdef __BIG_ENDIAN + volatile u8 res1[3]; + volatile u8 UTXH; + volatile u8 res2[3]; + volatile u8 URXH; +#else /* Little Endian */ + volatile u8 UTXH; + volatile u8 res1[3]; + volatile u8 URXH; + volatile u8 res2[3]; +#endif + volatile u32 UBRDIV; +#ifdef __BIG_ENDIAN + volatile u8 res3[2]; + volatile u16 UDIVSLOT; +#else + volatile u16 UDIVSLOT; + volatile u8 res3[2]; +#endif +} s3c64xx_uart; + +/* PWM TIMER (see manual chapter 10) */ +typedef struct { + volatile u32 TCNTB; + volatile u32 TCMPB; + volatile u32 TCNTO; +} s3c64xx_timer; + +typedef struct { + volatile u32 TCFG0; + volatile u32 TCFG1; + volatile u32 TCON; + s3c64xx_timer ch[4]; + volatile u32 TCNTB4; + volatile u32 TCNTO4; +} s3c64xx_timers; + +#endif /*__S3C64XX_H__*/ diff --git a/include/s3c6400.h b/include/s3c6400.h deleted file mode 100644 index e527c08b18..0000000000 --- a/include/s3c6400.h +++ /dev/null @@ -1,895 +0,0 @@ -/* - * (C) Copyright 2007 - * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com. - * - only support for S3C6400 - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : s3c6400.h - * - * Based on S3C6400 User's manual Rev 0.0 - ************************************************/ - -#ifndef __S3C6400_H__ -#define __S3C6400_H__ - -#define S3C64XX_UART_CHANNELS 3 -#define S3C64XX_SPI_CHANNELS 2 - -#include - -#define ELFIN_CLOCK_POWER_BASE 0x7e00f000 - -/* Clock & Power Controller for mDirac3*/ -#define APLL_LOCK_OFFSET 0x00 -#define MPLL_LOCK_OFFSET 0x04 -#define EPLL_LOCK_OFFSET 0x08 -#define APLL_CON_OFFSET 0x0C -#define MPLL_CON_OFFSET 0x10 -#define EPLL_CON0_OFFSET 0x14 -#define EPLL_CON1_OFFSET 0x18 -#define CLK_SRC_OFFSET 0x1C -#define CLK_DIV0_OFFSET 0x20 -#define CLK_DIV1_OFFSET 0x24 -#define CLK_DIV2_OFFSET 0x28 -#define CLK_OUT_OFFSET 0x2C -#define HCLK_GATE_OFFSET 0x30 -#define PCLK_GATE_OFFSET 0x34 -#define SCLK_GATE_OFFSET 0x38 -#define AHB_CON0_OFFSET 0x100 -#define AHB_CON1_OFFSET 0x104 -#define AHB_CON2_OFFSET 0x108 -#define SELECT_DMA_OFFSET 0x110 -#define SW_RST_OFFSET 0x114 -#define SYS_ID_OFFSET 0x118 -#define MEM_SYS_CFG_OFFSET 0x120 -#define QOS_OVERRIDE0_OFFSET 0x124 -#define QOS_OVERRIDE1_OFFSET 0x128 -#define MEM_CFG_STAT_OFFSET 0x12C -#define PWR_CFG_OFFSET 0x804 -#define EINT_MASK_OFFSET 0x808 -#define NOR_CFG_OFFSET 0x810 -#define STOP_CFG_OFFSET 0x814 -#define SLEEP_CFG_OFFSET 0x818 -#define OSC_FREQ_OFFSET 0x820 -#define OSC_STABLE_OFFSET 0x824 -#define PWR_STABLE_OFFSET 0x828 -#define FPC_STABLE_OFFSET 0x82C -#define MTC_STABLE_OFFSET 0x830 -#define OTHERS_OFFSET 0x900 -#define RST_STAT_OFFSET 0x904 -#define WAKEUP_STAT_OFFSET 0x908 -#define BLK_PWR_STAT_OFFSET 0x90C -#define INF_REG0_OFFSET 0xA00 -#define INF_REG1_OFFSET 0xA04 -#define INF_REG2_OFFSET 0xA08 -#define INF_REG3_OFFSET 0xA0C -#define INF_REG4_OFFSET 0xA10 -#define INF_REG5_OFFSET 0xA14 -#define INF_REG6_OFFSET 0xA18 -#define INF_REG7_OFFSET 0xA1C - -#define OSC_CNT_VAL_OFFSET 0x824 -#define PWR_CNT_VAL_OFFSET 0x828 -#define FPC_CNT_VAL_OFFSET 0x82C -#define MTC_CNT_VAL_OFFSET 0x830 - -#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) -#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) -#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) -#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) -#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) -#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) -#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) -#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) -#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) -#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) -#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) -#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) -#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) -#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) -#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) -#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) -#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) -#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) -#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - SELECT_DMA_OFFSET) -#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) -#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) -#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MEM_SYS_CFG_OFFSET) -#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - QOS_OVERRIDE0_OFFSET) -#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - QOS_OVERRIDE1_OFFSET) -#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MEM_CFG_STAT_OFFSET) -#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) -#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) -#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) -#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) -#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) -#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) -#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - OSC_CNT_VAL_OFFSET) -#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - PWR_CNT_VAL_OFFSET) -#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - FPC_CNT_VAL_OFFSET) -#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MTC_CNT_VAL_OFFSET) -#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) -#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) -#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - WAKEUP_STAT_OFFSET) -#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - BLK_PWR_STAT_OFFSET) -#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) -#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) -#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) -#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) -#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) -#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) -#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) -#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) - -#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) -#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) -#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) -#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) -#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) -#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) -#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) -#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) -#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) -#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) -#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) -#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) -#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) -#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) -#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) -#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) -#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) -#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) -#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET) -#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) -#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) -#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET) -#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET) -#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET) -#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET) -#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) -#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) -#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) -#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) -#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) -#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) -#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET) -#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET) -#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET) -#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET) -#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) -#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) -#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET) -#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET) -#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) -#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) -#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) -#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) -#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) -#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) -#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) -#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) - - -/* - * GPIO - */ -#define ELFIN_GPIO_BASE 0x7f008000 - -#define GPACON_OFFSET 0x00 -#define GPADAT_OFFSET 0x04 -#define GPAPUD_OFFSET 0x08 -#define GPACONSLP_OFFSET 0x0C -#define GPAPUDSLP_OFFSET 0x10 -#define GPBCON_OFFSET 0x20 -#define GPBDAT_OFFSET 0x24 -#define GPBPUD_OFFSET 0x28 -#define GPBCONSLP_OFFSET 0x2C -#define GPBPUDSLP_OFFSET 0x30 -#define GPCCON_OFFSET 0x40 -#define GPCDAT_OFFSET 0x44 -#define GPCPUD_OFFSET 0x48 -#define GPCCONSLP_OFFSET 0x4C -#define GPCPUDSLP_OFFSET 0x50 -#define GPDCON_OFFSET 0x60 -#define GPDDAT_OFFSET 0x64 -#define GPDPUD_OFFSET 0x68 -#define GPDCONSLP_OFFSET 0x6C -#define GPDPUDSLP_OFFSET 0x70 -#define GPECON_OFFSET 0x80 -#define GPEDAT_OFFSET 0x84 -#define GPEPUD_OFFSET 0x88 -#define GPECONSLP_OFFSET 0x8C -#define GPEPUDSLP_OFFSET 0x90 -#define GPFCON_OFFSET 0xA0 -#define GPFDAT_OFFSET 0xA4 -#define GPFPUD_OFFSET 0xA8 -#define GPFCONSLP_OFFSET 0xAC -#define GPFPUDSLP_OFFSET 0xB0 -#define GPGCON_OFFSET 0xC0 -#define GPGDAT_OFFSET 0xC4 -#define GPGPUD_OFFSET 0xC8 -#define GPGCONSLP_OFFSET 0xCC -#define GPGPUDSLP_OFFSET 0xD0 -#define GPHCON0_OFFSET 0xE0 -#define GPHCON1_OFFSET 0xE4 -#define GPHDAT_OFFSET 0xE8 -#define GPHPUD_OFFSET 0xEC -#define GPHCONSLP_OFFSET 0xF0 -#define GPHPUDSLP_OFFSET 0xF4 -#define GPICON_OFFSET 0x100 -#define GPIDAT_OFFSET 0x104 -#define GPIPUD_OFFSET 0x108 -#define GPICONSLP_OFFSET 0x10C -#define GPIPUDSLP_OFFSET 0x110 -#define GPJCON_OFFSET 0x120 -#define GPJDAT_OFFSET 0x124 -#define GPJPUD_OFFSET 0x128 -#define GPJCONSLP_OFFSET 0x12C -#define GPJPUDSLP_OFFSET 0x130 -#define MEM0DRVCON_OFFSET 0x1D0 -#define MEM1DRVCON_OFFSET 0x1D4 -#define GPKCON0_OFFSET 0x800 -#define GPKCON1_OFFSET 0x804 -#define GPKDAT_OFFSET 0x808 -#define GPKPUD_OFFSET 0x80C -#define GPLCON0_OFFSET 0x810 -#define GPLCON1_OFFSET 0x814 -#define GPLDAT_OFFSET 0x818 -#define GPLPUD_OFFSET 0x81C -#define GPMCON_OFFSET 0x820 -#define GPMDAT_OFFSET 0x824 -#define GPMPUD_OFFSET 0x828 -#define GPNCON_OFFSET 0x830 -#define GPNDAT_OFFSET 0x834 -#define GPNPUD_OFFSET 0x838 -#define GPOCON_OFFSET 0x140 -#define GPODAT_OFFSET 0x144 -#define GPOPUD_OFFSET 0x148 -#define GPOCONSLP_OFFSET 0x14C -#define GPOPUDSLP_OFFSET 0x150 -#define GPPCON_OFFSET 0x160 -#define GPPDAT_OFFSET 0x164 -#define GPPPUD_OFFSET 0x168 -#define GPPCONSLP_OFFSET 0x16C -#define GPPPUDSLP_OFFSET 0x170 -#define GPQCON_OFFSET 0x180 -#define GPQDAT_OFFSET 0x184 -#define GPQPUD_OFFSET 0x188 -#define GPQCONSLP_OFFSET 0x18C -#define GPQPUDSLP_OFFSET 0x190 - -#define EINTPEND_OFFSET 0x924 - -#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET) -#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET) -#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET) -#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET) -#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) -#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET) -#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET) -#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET) -#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) -#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) -#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET) -#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET) -#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET) -#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) -#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) -#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET) -#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET) -#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET) -#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) -#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) -#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET) -#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET) -#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET) -#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET) -#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) -#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET) -#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET) -#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET) -#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) -#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) -#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET) -#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET) -#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET) -#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) -#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) -#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET) -#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET) -#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET) -#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET) -#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) -#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) -#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET) -#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET) -#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET) -#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET) -#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) -#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET) -#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET) -#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET) -#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) -#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) -#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET) -#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET) -#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET) -#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET) -#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET) -#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET) -#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET) -#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET) -#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET) -#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET) -#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET) -#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET) -#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET) -#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET) -#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET) -#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET) -#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET) -#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) -#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) -#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET) -#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET) -#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET) -#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) -#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) -#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET) -#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET) -#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET) -#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) -#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) - -/* - * Bus Matrix - */ -#define ELFIN_MEM_SYS_CFG 0x7e00f120 - -#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12) - -#define S3C64XX_MEM_SYS_CFG_NAND 0x0008 -#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT - -#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET) -#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET) -#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET) -#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET) -#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) -#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET) -#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET) -#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET) -#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) -#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) -#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET) -#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET) -#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET) -#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) -#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) -#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET) -#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET) -#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET) -#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) -#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) -#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET) -#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET) -#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET) -#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET) -#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) -#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET) -#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET) -#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET) -#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) -#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) -#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET) -#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET) -#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET) -#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) -#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) -#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET) -#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET) -#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET) -#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET) -#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) -#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) -#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET) -#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET) -#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET) -#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET) -#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) -#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET) -#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET) -#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET) -#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) -#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) -#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET) -#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET) -#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET) -#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET) -#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET) -#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET) -#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET) -#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET) -#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET) -#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET) -#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET) -#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET) -#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET) -#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET) -#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET) -#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET) -#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET) -#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) -#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) -#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET) -#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET) -#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET) -#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) -#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) -#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET) -#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET) -#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET) -#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) -#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) - -/* - * Memory controller - */ -#define ELFIN_SROM_BASE 0x70000000 - -#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0) -#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4) -#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8) -#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC) -#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10) -#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14) -#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18) - -/* - * SDRAM Controller - */ -#define ELFIN_DMC0_BASE 0x7e000000 -#define ELFIN_DMC1_BASE 0x7e001000 - -#define INDEX_DMC_MEMC_STATUS 0x00 -#define INDEX_DMC_MEMC_CMD 0x04 -#define INDEX_DMC_DIRECT_CMD 0x08 -#define INDEX_DMC_MEMORY_CFG 0x0C -#define INDEX_DMC_REFRESH_PRD 0x10 -#define INDEX_DMC_CAS_LATENCY 0x14 -#define INDEX_DMC_T_DQSS 0x18 -#define INDEX_DMC_T_MRD 0x1C -#define INDEX_DMC_T_RAS 0x20 -#define INDEX_DMC_T_RC 0x24 -#define INDEX_DMC_T_RCD 0x28 -#define INDEX_DMC_T_RFC 0x2C -#define INDEX_DMC_T_RP 0x30 -#define INDEX_DMC_T_RRD 0x34 -#define INDEX_DMC_T_WR 0x38 -#define INDEX_DMC_T_WTR 0x3C -#define INDEX_DMC_T_XP 0x40 -#define INDEX_DMC_T_XSR 0x44 -#define INDEX_DMC_T_ESR 0x48 -#define INDEX_DMC_MEMORY_CFG2 0x4C -#define INDEX_DMC_CHIP_0_CFG 0x200 -#define INDEX_DMC_CHIP_1_CFG 0x204 -#define INDEX_DMC_CHIP_2_CFG 0x208 -#define INDEX_DMC_CHIP_3_CFG 0x20C -#define INDEX_DMC_USER_STATUS 0x300 -#define INDEX_DMC_USER_CONFIG 0x304 - -/* - * Memory Chip direct command - */ -#define DMC_NOP0 0x0c0000 -#define DMC_NOP1 0x1c0000 -#define DMC_PA0 0x000000 /* Precharge all */ -#define DMC_PA1 0x100000 -#define DMC_AR0 0x040000 /* Autorefresh */ -#define DMC_AR1 0x140000 -#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */ -#define DMC_SDR_MR1 0x180032 -#define DMC_DDR_MR0 0x080162 -#define DMC_DDR_MR1 0x180162 -#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */ -#define DMC_mDDR_MR1 0x180032 -#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */ -#define DMC_mSDR_EMR1 0x1a0000 -#define DMC_DDR_EMR0 0x090000 -#define DMC_DDR_EMR1 0x190000 -#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */ -#define DMC_mDDR_EMR1 0x1a0000 - -/* - * Definitions for memory configuration - * Set memory configuration - * active_chips = 1'b0 (1 chip) - * qos_master_chip = 3'b000(ARID[3:0]) - * memory burst = 3'b010(burst 4) - * stop_mem_clock = 1'b0(disable dynamical stop) - * auto_power_down = 1'b0(disable auto power-down mode) - * power_down_prd = 6'b00_0000(0 cycle for auto power-down) - * ap_bit = 1'b0 (bit position of auto-precharge is 10) - * row_bits = 3'b010(# row address 13) - * column_bits = 3'b010(# column address 10 ) - * - * Set user configuration - * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR - * - * Set chip select for chip [n] - * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff - * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24] - */ - -/* - * Nand flash controller - */ -#define ELFIN_NAND_BASE 0x70200000 - -#define NFCONF_OFFSET 0x00 -#define NFCONT_OFFSET 0x04 -#define NFCMMD_OFFSET 0x08 -#define NFADDR_OFFSET 0x0c -#define NFDATA_OFFSET 0x10 -#define NFMECCDATA0_OFFSET 0x14 -#define NFMECCDATA1_OFFSET 0x18 -#define NFSECCDATA0_OFFSET 0x1c -#define NFSBLK_OFFSET 0x20 -#define NFEBLK_OFFSET 0x24 -#define NFSTAT_OFFSET 0x28 -#define NFESTAT0_OFFSET 0x2c -#define NFESTAT1_OFFSET 0x30 -#define NFMECC0_OFFSET 0x34 -#define NFMECC1_OFFSET 0x38 -#define NFSECC_OFFSET 0x3c -#define NFMLCBITPT_OFFSET 0x40 - -#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET) -#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET) -#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET) -#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET) -#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) -#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) -#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) -#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET) -#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET) -#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET) -#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET) -#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET) -#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET) -#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET) -#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET) -#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) - -#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET) -#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET) -#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET) -#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET) -#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) -#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) -#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) -#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET) -#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET) -#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET) -#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET) -#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET) -#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET) -#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET) -#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET) -#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) - -#define NFCONF_ECC_4BIT (1<<24) - -#define NFCONT_ECC_ENC (1<<18) -#define NFCONT_WP (1<<16) -#define NFCONT_MECCLOCK (1<<7) -#define NFCONT_SECCLOCK (1<<6) -#define NFCONT_INITMECC (1<<5) -#define NFCONT_INITSECC (1<<4) -#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC) -#define NFCONT_CS_ALT (1<<2) -#define NFCONT_CS (1<<1) -#define NFCONT_ENABLE (1<<0) - -#define NFSTAT_ECCENCDONE (1<<7) -#define NFSTAT_ECCDECDONE (1<<6) -#define NFSTAT_RnB (1<<0) - -#define NFESTAT0_ECCBUSY (1<<31) - -/* - * Interrupt - */ -#define ELFIN_VIC0_BASE_ADDR 0x71200000 -#define ELFIN_VIC1_BASE_ADDR 0x71300000 -#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */ -#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */ -#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */ -#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */ -#define oVECTADDR 0xF00 /* VIC ADDRESS */ - -/* - * Watchdog timer - */ -#define ELFIN_WATCHDOG_BASE 0x7E004000 - -#define WTCON_REG __REG(0x7E004004) -#define WTDAT_REG __REG(0x7E004008) -#define WTCNT_REG __REG(0x7E00400C) - - -/* - * UART - */ -#define ELFIN_UART_BASE 0x7F005000 - -#define ELFIN_UART0_OFFSET 0x0000 -#define ELFIN_UART1_OFFSET 0x0400 -#define ELFIN_UART2_OFFSET 0x0800 - -#define ULCON_OFFSET 0x00 -#define UCON_OFFSET 0x04 -#define UFCON_OFFSET 0x08 -#define UMCON_OFFSET 0x0C -#define UTRSTAT_OFFSET 0x10 -#define UERSTAT_OFFSET 0x14 -#define UFSTAT_OFFSET 0x18 -#define UMSTAT_OFFSET 0x1C -#define UTXH_OFFSET 0x20 -#define URXH_OFFSET 0x24 -#define UBRDIV_OFFSET 0x28 -#define UDIVSLOT_OFFSET 0x2C -#define UINTP_OFFSET 0x30 -#define UINTSP_OFFSET 0x34 -#define UINTM_OFFSET 0x38 - -#define ULCON0_REG __REG(0x7F005000) -#define UCON0_REG __REG(0x7F005004) -#define UFCON0_REG __REG(0x7F005008) -#define UMCON0_REG __REG(0x7F00500C) -#define UTRSTAT0_REG __REG(0x7F005010) -#define UERSTAT0_REG __REG(0x7F005014) -#define UFSTAT0_REG __REG(0x7F005018) -#define UMSTAT0_REG __REG(0x7F00501c) -#define UTXH0_REG __REG(0x7F005020) -#define URXH0_REG __REG(0x7F005024) -#define UBRDIV0_REG __REG(0x7F005028) -#define UDIVSLOT0_REG __REG(0x7F00502c) -#define UINTP0_REG __REG(0x7F005030) -#define UINTSP0_REG __REG(0x7F005034) -#define UINTM0_REG __REG(0x7F005038) - -#define ULCON1_REG __REG(0x7F005400) -#define UCON1_REG __REG(0x7F005404) -#define UFCON1_REG __REG(0x7F005408) -#define UMCON1_REG __REG(0x7F00540C) -#define UTRSTAT1_REG __REG(0x7F005410) -#define UERSTAT1_REG __REG(0x7F005414) -#define UFSTAT1_REG __REG(0x7F005418) -#define UMSTAT1_REG __REG(0x7F00541c) -#define UTXH1_REG __REG(0x7F005420) -#define URXH1_REG __REG(0x7F005424) -#define UBRDIV1_REG __REG(0x7F005428) -#define UDIVSLOT1_REG __REG(0x7F00542c) -#define UINTP1_REG __REG(0x7F005430) -#define UINTSP1_REG __REG(0x7F005434) -#define UINTM1_REG __REG(0x7F005438) - -#define UTRSTAT_TX_EMPTY (1 << 2) -#define UTRSTAT_RX_READY (1 << 0) -#define UART_ERR_MASK 0xF - -/* - * PWM timer - */ -#define ELFIN_TIMER_BASE 0x7F006000 - -#define TCFG0_REG __REG(0x7F006000) -#define TCFG1_REG __REG(0x7F006004) -#define TCON_REG __REG(0x7F006008) -#define TCNTB0_REG __REG(0x7F00600c) -#define TCMPB0_REG __REG(0x7F006010) -#define TCNTO0_REG __REG(0x7F006014) -#define TCNTB1_REG __REG(0x7F006018) -#define TCMPB1_REG __REG(0x7F00601c) -#define TCNTO1_REG __REG(0x7F006020) -#define TCNTB2_REG __REG(0x7F006024) -#define TCMPB2_REG __REG(0x7F006028) -#define TCNTO2_REG __REG(0x7F00602c) -#define TCNTB3_REG __REG(0x7F006030) -#define TCMPB3_REG __REG(0x7F006034) -#define TCNTO3_REG __REG(0x7F006038) -#define TCNTB4_REG __REG(0x7F00603c) -#define TCNTO4_REG __REG(0x7F006040) - -/* Fields */ -#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */ -#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */ -#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */ -#define fTCFG1_MUX4 Fld(4, 16) -/* bits */ -#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE) -#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1) -#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0) -#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */ -#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */ -#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */ -#define COUNT_4_ON (TCON_4_ONOFF * 1) -#define COUNT_4_OFF (TCON_4_ONOFF * 0) -#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */ -#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1) -#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO) -#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */ -#define TIMER3_IVT_ON (TCON_3_INVERT * 1) -#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT)) -#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */ -#define TIMER3_MANUP (TCON_3_MAN*1) -#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN)) -#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */ -#define TIMER3_ON (TCON_3_ONOFF * 1) -#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF)) - -#if defined(CONFIG_CLK_400_100_50) -#define STARTUP_AMDIV 400 -#define STARTUP_MDIV 400 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_400_133_66) -#define STARTUP_AMDIV 400 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_533_133_66) -#define STARTUP_AMDIV 533 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_667_133_66) -#define STARTUP_AMDIV 667 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#endif - -#define STARTUP_PCLKDIV 3 -#define STARTUP_HCLKX2DIV 1 -#define STARTUP_HCLKDIV 1 -#define STARTUP_MPLLDIV 1 -#define STARTUP_APLLDIV 0 - -#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \ - (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV) -#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_MDIV) - -#if defined(CONFIG_SYNC_MODE) -#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_MDIV) -#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ - (STARTUP_HCLKDIV + 1)) -#else -#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_AMDIV) -#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ - (STARTUP_HCLKDIV + 1)) -#endif - - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ -#define DMC1_MEM_CFG2 0xB45 -#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */ -#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ - -/* Memory Parameters */ -/* DDR Parameters */ -#define DDR_tREFRESH 7800 /* ns */ -#define DDR_tRAS 45 /* ns (min: 45ns)*/ -#define DDR_tRC 68 /* ns (min: 67.5ns)*/ -#define DDR_tRCD 23 /* ns (min: 22.5ns)*/ -#define DDR_tRFC 80 /* ns (min: 80ns)*/ -#define DDR_tRP 23 /* ns (min: 22.5ns)*/ -#define DDR_tRRD 15 /* ns (min: 15ns)*/ -#define DDR_tWR 15 /* ns (min: 15ns)*/ -#define DDR_tXSR 120 /* ns (min: 120ns)*/ -#define DDR_CASL 3 /* CAS Latency 3 */ - -/* - * mDDR memory configuration - */ - -#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000) - -#define DMC_DDR_BA_EMRS 2 -#define DMC_DDR_MEM_CASLAT 3 -/* 6 Set Cas Latency to 3 */ -#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1) -/* Min 0.75 ~ 1.25 */ -#define DMC_DDR_t_DQSS 1 -/* Min 2 tck */ -#define DMC_DDR_t_MRD 2 -/* 7, Min 45ns */ -#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1) -/* 10, Min 67.5ns */ -#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1) -/* 4,5(TRM), Min 22.5ns */ -#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1) -#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3) -/* 11,18(TRM) Min 80ns */ -#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1) -#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5) -/* 4, 5(TRM) Min 22.5ns */ -#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1) -#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3) -/* 3, Min 15ns */ -#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1) -/* Min 15ns */ -#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1) -#define DMC_DDR_t_WTR 2 -/* 1tck + tIS(1.5ns) */ -#define DMC_DDR_t_XP 2 -/* 17, Min 120ns */ -#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1) -#define DMC_DDR_t_ESR DMC_DDR_t_XSR -/* TRM 2656 */ -#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH)) -/* 2b01 : mDDR */ -#define DMC_DDR_USER_CONFIG 1 - -#ifndef __ASSEMBLY__ -enum s3c64xx_uarts_nr { - S3C64XX_UART0, - S3C64XX_UART1, - S3C64XX_UART2, -}; - -#include "s3c64x0.h" - -static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr) -{ - return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400)); -} -#endif - -#endif /*__S3C6400_H__*/ diff --git a/include/s3c64x0.h b/include/s3c64x0.h deleted file mode 100644 index 0bbf1d0c43..0000000000 --- a/include/s3c64x0.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * (C) Copyright 2003 - * David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : S3C64XX.h - * Version : 31.3.2003 - * - * common stuff for SAMSUNG S3C64XX SoC - ************************************************/ - -#ifndef __S3C64XX_H__ -#define __S3C64XX_H__ - -#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400) -#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration! -#endif - -#include - -/* UART (see manual chapter 11) */ -typedef struct { - volatile u32 ULCON; - volatile u32 UCON; - volatile u32 UFCON; - volatile u32 UMCON; - volatile u32 UTRSTAT; - volatile u32 UERSTAT; - volatile u32 UFSTAT; - volatile u32 UMSTAT; -#ifdef __BIG_ENDIAN - volatile u8 res1[3]; - volatile u8 UTXH; - volatile u8 res2[3]; - volatile u8 URXH; -#else /* Little Endian */ - volatile u8 UTXH; - volatile u8 res1[3]; - volatile u8 URXH; - volatile u8 res2[3]; -#endif - volatile u32 UBRDIV; -#ifdef __BIG_ENDIAN - volatile u8 res3[2]; - volatile u16 UDIVSLOT; -#else - volatile u16 UDIVSLOT; - volatile u8 res3[2]; -#endif -} s3c64xx_uart; - -/* PWM TIMER (see manual chapter 10) */ -typedef struct { - volatile u32 TCNTB; - volatile u32 TCMPB; - volatile u32 TCNTO; -} s3c64xx_timer; - -typedef struct { - volatile u32 TCFG0; - volatile u32 TCFG1; - volatile u32 TCON; - s3c64xx_timer ch[4]; - volatile u32 TCNTB4; - volatile u32 TCNTO4; -} s3c64xx_timers; - -#endif /*__S3C64XX_H__*/ -- cgit v1.2.1 From 9ebfdc202275bcd9eb4af56e32bfb4253ff1b781 Mon Sep 17 00:00:00 2001 From: "kevin.morfitt@fearnside-systems.co.uk" Date: Wed, 4 Nov 2009 17:49:31 +0900 Subject: Clean-up of s3c24x0 header files Cleans up the s3c24x0 header files: s4c24x0.h: removes the use of 'volatile' from the S3C24X0_REG8, S3C24X0_REG16 and S3C24X0_REG32 register typedef's. Registers are always accessed using the IO accessor functions which cast the register address as 'volatile' anyway so it isn't required here. s3c2400.h and s3c2410.h: insert a blank line between the static inline functions Signed-off-by: Kevin Morfitt --- include/asm-arm/arch-s3c24x0/s3c2400.h | 16 + include/asm-arm/arch-s3c24x0/s3c2410.h | 17 + include/asm-arm/arch-s3c24x0/s3c24x0.h | 904 ++++++++++++++++----------------- 3 files changed, 483 insertions(+), 454 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-s3c24x0/s3c2400.h b/include/asm-arm/arch-s3c24x0/s3c2400.h index 26bd4e49a1..2678be1548 100644 --- a/include/asm-arm/arch-s3c24x0/s3c2400.h +++ b/include/asm-arm/arch-s3c24x0/s3c2400.h @@ -67,67 +67,83 @@ static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) { return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; } + static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) { return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; } + static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) { return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; } + static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) { return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; } + static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) { return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; } + static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) { return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; } + static inline struct s3c24x0_uart *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) { return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); } + static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) { return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; } + static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) { return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; } + static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) { return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; } + static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) { return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; } + static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) { return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; } + static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) { return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; } + static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) { return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; } + static inline struct s3c2400_adc *s3c2400_get_base_adc(void) { return (struct s3c2400_adc *)S3C24X0_ADC_BASE; } + static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) { return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; } + static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void) { return (struct s3c2400_mmc *)S3C2400_MMC_BASE; diff --git a/include/asm-arm/arch-s3c24x0/s3c2410.h b/include/asm-arm/arch-s3c24x0/s3c2410.h index be2e76e5f2..0543fe1565 100644 --- a/include/asm-arm/arch-s3c24x0/s3c2410.h +++ b/include/asm-arm/arch-s3c24x0/s3c2410.h @@ -73,71 +73,88 @@ static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) { return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; } + static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) { return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; } + static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) { return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; } + static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) { return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; } + static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) { return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; } + static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) { return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; } + static inline struct s3c2410_nand *s3c2410_get_base_nand(void) { return (struct s3c2410_nand *)S3C2410_NAND_BASE; } + static inline struct s3c24x0_uart *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) { return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); } + static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) { return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; } + static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) { return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; } + static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) { return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; } + static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) { return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; } + static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) { return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; } + static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) { return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; } + static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) { return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; } + static inline struct s3c2410_adc *s3c2410_get_base_adc(void) { return (struct s3c2410_adc *)S3C2410_ADC_BASE; } + static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) { return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; } + static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void) { return (struct s3c2410_sdi *)S3C2410_SDI_BASE; diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0.h b/include/asm-arm/arch-s3c24x0/s3c24x0.h index 56a551aeb4..15f53dd35b 100644 --- a/include/asm-arm/arch-s3c24x0/s3c24x0.h +++ b/include/asm-arm/arch-s3c24x0/s3c24x0.h @@ -31,84 +31,80 @@ #ifndef __S3C24X0_H__ #define __S3C24X0_H__ -typedef volatile u8 S3C24X0_REG8; -typedef volatile u16 S3C24X0_REG16; -typedef volatile u32 S3C24X0_REG32; - /* Memory controller (see manual chapter 5) */ struct s3c24x0_memctl { - S3C24X0_REG32 BWSCON; - S3C24X0_REG32 BANKCON[8]; - S3C24X0_REG32 REFRESH; - S3C24X0_REG32 BANKSIZE; - S3C24X0_REG32 MRSRB6; - S3C24X0_REG32 MRSRB7; + u32 BWSCON; + u32 BANKCON[8]; + u32 REFRESH; + u32 BANKSIZE; + u32 MRSRB6; + u32 MRSRB7; }; /* USB HOST (see manual chapter 12) */ struct s3c24x0_usb_host { - S3C24X0_REG32 HcRevision; - S3C24X0_REG32 HcControl; - S3C24X0_REG32 HcCommonStatus; - S3C24X0_REG32 HcInterruptStatus; - S3C24X0_REG32 HcInterruptEnable; - S3C24X0_REG32 HcInterruptDisable; - S3C24X0_REG32 HcHCCA; - S3C24X0_REG32 HcPeriodCuttendED; - S3C24X0_REG32 HcControlHeadED; - S3C24X0_REG32 HcControlCurrentED; - S3C24X0_REG32 HcBulkHeadED; - S3C24X0_REG32 HcBuldCurrentED; - S3C24X0_REG32 HcDoneHead; - S3C24X0_REG32 HcRmInterval; - S3C24X0_REG32 HcFmRemaining; - S3C24X0_REG32 HcFmNumber; - S3C24X0_REG32 HcPeriodicStart; - S3C24X0_REG32 HcLSThreshold; - S3C24X0_REG32 HcRhDescriptorA; - S3C24X0_REG32 HcRhDescriptorB; - S3C24X0_REG32 HcRhStatus; - S3C24X0_REG32 HcRhPortStatus1; - S3C24X0_REG32 HcRhPortStatus2; + u32 HcRevision; + u32 HcControl; + u32 HcCommonStatus; + u32 HcInterruptStatus; + u32 HcInterruptEnable; + u32 HcInterruptDisable; + u32 HcHCCA; + u32 HcPeriodCuttendED; + u32 HcControlHeadED; + u32 HcControlCurrentED; + u32 HcBulkHeadED; + u32 HcBuldCurrentED; + u32 HcDoneHead; + u32 HcRmInterval; + u32 HcFmRemaining; + u32 HcFmNumber; + u32 HcPeriodicStart; + u32 HcLSThreshold; + u32 HcRhDescriptorA; + u32 HcRhDescriptorB; + u32 HcRhStatus; + u32 HcRhPortStatus1; + u32 HcRhPortStatus2; }; /* INTERRUPT (see manual chapter 14) */ struct s3c24x0_interrupt { - S3C24X0_REG32 SRCPND; - S3C24X0_REG32 INTMOD; - S3C24X0_REG32 INTMSK; - S3C24X0_REG32 PRIORITY; - S3C24X0_REG32 INTPND; - S3C24X0_REG32 INTOFFSET; + u32 SRCPND; + u32 INTMOD; + u32 INTMSK; + u32 PRIORITY; + u32 INTPND; + u32 INTOFFSET; #ifdef CONFIG_S3C2410 - S3C24X0_REG32 SUBSRCPND; - S3C24X0_REG32 INTSUBMSK; + u32 SUBSRCPND; + u32 INTSUBMSK; #endif }; /* DMAS (see manual chapter 8) */ struct s3c24x0_dma { - S3C24X0_REG32 DISRC; + u32 DISRC; #ifdef CONFIG_S3C2410 - S3C24X0_REG32 DISRCC; + u32 DISRCC; #endif - S3C24X0_REG32 DIDST; + u32 DIDST; #ifdef CONFIG_S3C2410 - S3C24X0_REG32 DIDSTC; + u32 DIDSTC; #endif - S3C24X0_REG32 DCON; - S3C24X0_REG32 DSTAT; - S3C24X0_REG32 DCSRC; - S3C24X0_REG32 DCDST; - S3C24X0_REG32 DMASKTRIG; + u32 DCON; + u32 DSTAT; + u32 DCSRC; + u32 DCDST; + u32 DMASKTRIG; #ifdef CONFIG_S3C2400 - S3C24X0_REG32 res[1]; + u32 res[1]; #endif #ifdef CONFIG_S3C2410 - S3C24X0_REG32 res[7]; + u32 res[7]; #endif }; @@ -120,201 +116,201 @@ struct s3c24x0_dmas { /* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ /* (see S3C2410 manual chapter 7) */ struct s3c24x0_clock_power { - S3C24X0_REG32 LOCKTIME; - S3C24X0_REG32 MPLLCON; - S3C24X0_REG32 UPLLCON; - S3C24X0_REG32 CLKCON; - S3C24X0_REG32 CLKSLOW; - S3C24X0_REG32 CLKDIVN; + u32 LOCKTIME; + u32 MPLLCON; + u32 UPLLCON; + u32 CLKCON; + u32 CLKSLOW; + u32 CLKDIVN; }; /* LCD CONTROLLER (see manual chapter 15) */ struct s3c24x0_lcd { - S3C24X0_REG32 LCDCON1; - S3C24X0_REG32 LCDCON2; - S3C24X0_REG32 LCDCON3; - S3C24X0_REG32 LCDCON4; - S3C24X0_REG32 LCDCON5; - S3C24X0_REG32 LCDSADDR1; - S3C24X0_REG32 LCDSADDR2; - S3C24X0_REG32 LCDSADDR3; - S3C24X0_REG32 REDLUT; - S3C24X0_REG32 GREENLUT; - S3C24X0_REG32 BLUELUT; - S3C24X0_REG32 res[8]; - S3C24X0_REG32 DITHMODE; - S3C24X0_REG32 TPAL; + u32 LCDCON1; + u32 LCDCON2; + u32 LCDCON3; + u32 LCDCON4; + u32 LCDCON5; + u32 LCDSADDR1; + u32 LCDSADDR2; + u32 LCDSADDR3; + u32 REDLUT; + u32 GREENLUT; + u32 BLUELUT; + u32 res[8]; + u32 DITHMODE; + u32 TPAL; #ifdef CONFIG_S3C2410 - S3C24X0_REG32 LCDINTPND; - S3C24X0_REG32 LCDSRCPND; - S3C24X0_REG32 LCDINTMSK; - S3C24X0_REG32 LPCSEL; + u32 LCDINTPND; + u32 LCDSRCPND; + u32 LCDINTMSK; + u32 LPCSEL; #endif }; /* NAND FLASH (see S3C2410 manual chapter 6) */ struct s3c2410_nand { - S3C24X0_REG32 NFCONF; - S3C24X0_REG32 NFCMD; - S3C24X0_REG32 NFADDR; - S3C24X0_REG32 NFDATA; - S3C24X0_REG32 NFSTAT; - S3C24X0_REG32 NFECC; + u32 NFCONF; + u32 NFCMD; + u32 NFADDR; + u32 NFDATA; + u32 NFSTAT; + u32 NFECC; }; /* UART (see manual chapter 11) */ struct s3c24x0_uart { - S3C24X0_REG32 ULCON; - S3C24X0_REG32 UCON; - S3C24X0_REG32 UFCON; - S3C24X0_REG32 UMCON; - S3C24X0_REG32 UTRSTAT; - S3C24X0_REG32 UERSTAT; - S3C24X0_REG32 UFSTAT; - S3C24X0_REG32 UMSTAT; + u32 ULCON; + u32 UCON; + u32 UFCON; + u32 UMCON; + u32 UTRSTAT; + u32 UERSTAT; + u32 UFSTAT; + u32 UMSTAT; #ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 UTXH; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 URXH; + u8 res1[3]; + u8 UTXH; + u8 res2[3]; + u8 URXH; #else /* Little Endian */ - S3C24X0_REG8 UTXH; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 URXH; - S3C24X0_REG8 res2[3]; + u8 UTXH; + u8 res1[3]; + u8 URXH; + u8 res2[3]; #endif - S3C24X0_REG32 UBRDIV; + u32 UBRDIV; }; /* PWM TIMER (see manual chapter 10) */ struct s3c24x0_timer { - S3C24X0_REG32 TCNTB; - S3C24X0_REG32 TCMPB; - S3C24X0_REG32 TCNTO; + u32 TCNTB; + u32 TCMPB; + u32 TCNTO; }; struct s3c24x0_timers { - S3C24X0_REG32 TCFG0; - S3C24X0_REG32 TCFG1; - S3C24X0_REG32 TCON; + u32 TCFG0; + u32 TCFG1; + u32 TCON; struct s3c24x0_timer ch[4]; - S3C24X0_REG32 TCNTB4; - S3C24X0_REG32 TCNTO4; + u32 TCNTB4; + u32 TCNTO4; }; /* USB DEVICE (see manual chapter 13) */ struct s3c24x0_usb_dev_fifos { #ifdef __BIG_ENDIAN - S3C24X0_REG8 res[3]; - S3C24X0_REG8 EP_FIFO_REG; + u8 res[3]; + u8 EP_FIFO_REG; #else /* little endian */ - S3C24X0_REG8 EP_FIFO_REG; - S3C24X0_REG8 res[3]; + u8 EP_FIFO_REG; + u8 res[3]; #endif }; struct s3c24x0_usb_dev_dmas { #ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 EP_DMA_CON; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 EP_DMA_UNIT; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 EP_DMA_FIFO; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 EP_DMA_TTC_L; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 EP_DMA_TTC_M; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 EP_DMA_TTC_H; + u8 res1[3]; + u8 EP_DMA_CON; + u8 res2[3]; + u8 EP_DMA_UNIT; + u8 res3[3]; + u8 EP_DMA_FIFO; + u8 res4[3]; + u8 EP_DMA_TTC_L; + u8 res5[3]; + u8 EP_DMA_TTC_M; + u8 res6[3]; + u8 EP_DMA_TTC_H; #else /* little endian */ - S3C24X0_REG8 EP_DMA_CON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 EP_DMA_UNIT; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 EP_DMA_FIFO; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 EP_DMA_TTC_L; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 EP_DMA_TTC_M; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 EP_DMA_TTC_H; - S3C24X0_REG8 res6[3]; + u8 EP_DMA_CON; + u8 res1[3]; + u8 EP_DMA_UNIT; + u8 res2[3]; + u8 EP_DMA_FIFO; + u8 res3[3]; + u8 EP_DMA_TTC_L; + u8 res4[3]; + u8 EP_DMA_TTC_M; + u8 res5[3]; + u8 EP_DMA_TTC_H; + u8 res6[3]; #endif }; struct s3c24x0_usb_device { #ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 FUNC_ADDR_REG; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 PWR_REG; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 EP_INT_REG; - S3C24X0_REG8 res4[15]; - S3C24X0_REG8 USB_INT_REG; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 EP_INT_EN_REG; - S3C24X0_REG8 res6[15]; - S3C24X0_REG8 USB_INT_EN_REG; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 FRAME_NUM1_REG; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 FRAME_NUM2_REG; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 INDEX_REG; - S3C24X0_REG8 res10[7]; - S3C24X0_REG8 MAXP_REG; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 EP0_CSR_IN_CSR1_REG; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 IN_CSR2_REG; - S3C24X0_REG8 res13[7]; - S3C24X0_REG8 OUT_CSR1_REG; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 OUT_CSR2_REG; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 OUT_FIFO_CNT1_REG; - S3C24X0_REG8 res16[3]; - S3C24X0_REG8 OUT_FIFO_CNT2_REG; + u8 res1[3]; + u8 FUNC_ADDR_REG; + u8 res2[3]; + u8 PWR_REG; + u8 res3[3]; + u8 EP_INT_REG; + u8 res4[15]; + u8 USB_INT_REG; + u8 res5[3]; + u8 EP_INT_EN_REG; + u8 res6[15]; + u8 USB_INT_EN_REG; + u8 res7[3]; + u8 FRAME_NUM1_REG; + u8 res8[3]; + u8 FRAME_NUM2_REG; + u8 res9[3]; + u8 INDEX_REG; + u8 res10[7]; + u8 MAXP_REG; + u8 res11[3]; + u8 EP0_CSR_IN_CSR1_REG; + u8 res12[3]; + u8 IN_CSR2_REG; + u8 res13[7]; + u8 OUT_CSR1_REG; + u8 res14[3]; + u8 OUT_CSR2_REG; + u8 res15[3]; + u8 OUT_FIFO_CNT1_REG; + u8 res16[3]; + u8 OUT_FIFO_CNT2_REG; #else /* little endian */ - S3C24X0_REG8 FUNC_ADDR_REG; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 PWR_REG; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 EP_INT_REG; - S3C24X0_REG8 res3[15]; - S3C24X0_REG8 USB_INT_REG; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 EP_INT_EN_REG; - S3C24X0_REG8 res5[15]; - S3C24X0_REG8 USB_INT_EN_REG; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 FRAME_NUM1_REG; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 FRAME_NUM2_REG; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 INDEX_REG; - S3C24X0_REG8 res9[7]; - S3C24X0_REG8 MAXP_REG; - S3C24X0_REG8 res10[7]; - S3C24X0_REG8 EP0_CSR_IN_CSR1_REG; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 IN_CSR2_REG; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 OUT_CSR1_REG; - S3C24X0_REG8 res13[7]; - S3C24X0_REG8 OUT_CSR2_REG; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 OUT_FIFO_CNT1_REG; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 OUT_FIFO_CNT2_REG; - S3C24X0_REG8 res16[3]; + u8 FUNC_ADDR_REG; + u8 res1[3]; + u8 PWR_REG; + u8 res2[3]; + u8 EP_INT_REG; + u8 res3[15]; + u8 USB_INT_REG; + u8 res4[3]; + u8 EP_INT_EN_REG; + u8 res5[15]; + u8 USB_INT_EN_REG; + u8 res6[3]; + u8 FRAME_NUM1_REG; + u8 res7[3]; + u8 FRAME_NUM2_REG; + u8 res8[3]; + u8 INDEX_REG; + u8 res9[7]; + u8 MAXP_REG; + u8 res10[7]; + u8 EP0_CSR_IN_CSR1_REG; + u8 res11[3]; + u8 IN_CSR2_REG; + u8 res12[3]; + u8 OUT_CSR1_REG; + u8 res13[7]; + u8 OUT_CSR2_REG; + u8 res14[3]; + u8 OUT_FIFO_CNT1_REG; + u8 res15[3]; + u8 OUT_FIFO_CNT2_REG; + u8 res16[3]; #endif /* __BIG_ENDIAN */ struct s3c24x0_usb_dev_fifos fifo[5]; struct s3c24x0_usb_dev_dmas dma[5]; @@ -323,45 +319,45 @@ struct s3c24x0_usb_device { /* WATCH DOG TIMER (see manual chapter 18) */ struct s3c24x0_watchdog { - S3C24X0_REG32 WTCON; - S3C24X0_REG32 WTDAT; - S3C24X0_REG32 WTCNT; + u32 WTCON; + u32 WTDAT; + u32 WTCNT; }; /* IIC (see manual chapter 20) */ struct s3c24x0_i2c { - S3C24X0_REG32 IICCON; - S3C24X0_REG32 IICSTAT; - S3C24X0_REG32 IICADD; - S3C24X0_REG32 IICDS; + u32 IICCON; + u32 IICSTAT; + u32 IICADD; + u32 IICDS; }; /* IIS (see manual chapter 21) */ struct s3c24x0_i2s { #ifdef __BIG_ENDIAN - S3C24X0_REG16 res1; - S3C24X0_REG16 IISCON; - S3C24X0_REG16 res2; - S3C24X0_REG16 IISMOD; - S3C24X0_REG16 res3; - S3C24X0_REG16 IISPSR; - S3C24X0_REG16 res4; - S3C24X0_REG16 IISFCON; - S3C24X0_REG16 res5; - S3C24X0_REG16 IISFIFO; + u16 res1; + u16 IISCON; + u16 res2; + u16 IISMOD; + u16 res3; + u16 IISPSR; + u16 res4; + u16 IISFCON; + u16 res5; + u16 IISFIFO; #else /* little endian */ - S3C24X0_REG16 IISCON; - S3C24X0_REG16 res1; - S3C24X0_REG16 IISMOD; - S3C24X0_REG16 res2; - S3C24X0_REG16 IISPSR; - S3C24X0_REG16 res3; - S3C24X0_REG16 IISFCON; - S3C24X0_REG16 res4; - S3C24X0_REG16 IISFIFO; - S3C24X0_REG16 res5; + u16 IISCON; + u16 res1; + u16 IISMOD; + u16 res2; + u16 IISPSR; + u16 res3; + u16 IISFCON; + u16 res4; + u16 IISFIFO; + u16 res5; #endif }; @@ -369,87 +365,87 @@ struct s3c24x0_i2s { /* I/O PORT (see manual chapter 9) */ struct s3c24x0_gpio { #ifdef CONFIG_S3C2400 - S3C24X0_REG32 PACON; - S3C24X0_REG32 PADAT; + u32 PACON; + u32 PADAT; - S3C24X0_REG32 PBCON; - S3C24X0_REG32 PBDAT; - S3C24X0_REG32 PBUP; + u32 PBCON; + u32 PBDAT; + u32 PBUP; - S3C24X0_REG32 PCCON; - S3C24X0_REG32 PCDAT; - S3C24X0_REG32 PCUP; + u32 PCCON; + u32 PCDAT; + u32 PCUP; - S3C24X0_REG32 PDCON; - S3C24X0_REG32 PDDAT; - S3C24X0_REG32 PDUP; + u32 PDCON; + u32 PDDAT; + u32 PDUP; - S3C24X0_REG32 PECON; - S3C24X0_REG32 PEDAT; - S3C24X0_REG32 PEUP; + u32 PECON; + u32 PEDAT; + u32 PEUP; - S3C24X0_REG32 PFCON; - S3C24X0_REG32 PFDAT; - S3C24X0_REG32 PFUP; + u32 PFCON; + u32 PFDAT; + u32 PFUP; - S3C24X0_REG32 PGCON; - S3C24X0_REG32 PGDAT; - S3C24X0_REG32 PGUP; + u32 PGCON; + u32 PGDAT; + u32 PGUP; - S3C24X0_REG32 OPENCR; + u32 OPENCR; - S3C24X0_REG32 MISCCR; - S3C24X0_REG32 EXTINT; + u32 MISCCR; + u32 EXTINT; #endif #ifdef CONFIG_S3C2410 - S3C24X0_REG32 GPACON; - S3C24X0_REG32 GPADAT; - S3C24X0_REG32 res1[2]; - S3C24X0_REG32 GPBCON; - S3C24X0_REG32 GPBDAT; - S3C24X0_REG32 GPBUP; - S3C24X0_REG32 res2; - S3C24X0_REG32 GPCCON; - S3C24X0_REG32 GPCDAT; - S3C24X0_REG32 GPCUP; - S3C24X0_REG32 res3; - S3C24X0_REG32 GPDCON; - S3C24X0_REG32 GPDDAT; - S3C24X0_REG32 GPDUP; - S3C24X0_REG32 res4; - S3C24X0_REG32 GPECON; - S3C24X0_REG32 GPEDAT; - S3C24X0_REG32 GPEUP; - S3C24X0_REG32 res5; - S3C24X0_REG32 GPFCON; - S3C24X0_REG32 GPFDAT; - S3C24X0_REG32 GPFUP; - S3C24X0_REG32 res6; - S3C24X0_REG32 GPGCON; - S3C24X0_REG32 GPGDAT; - S3C24X0_REG32 GPGUP; - S3C24X0_REG32 res7; - S3C24X0_REG32 GPHCON; - S3C24X0_REG32 GPHDAT; - S3C24X0_REG32 GPHUP; - S3C24X0_REG32 res8; - - S3C24X0_REG32 MISCCR; - S3C24X0_REG32 DCLKCON; - S3C24X0_REG32 EXTINT0; - S3C24X0_REG32 EXTINT1; - S3C24X0_REG32 EXTINT2; - S3C24X0_REG32 EINTFLT0; - S3C24X0_REG32 EINTFLT1; - S3C24X0_REG32 EINTFLT2; - S3C24X0_REG32 EINTFLT3; - S3C24X0_REG32 EINTMASK; - S3C24X0_REG32 EINTPEND; - S3C24X0_REG32 GSTATUS0; - S3C24X0_REG32 GSTATUS1; - S3C24X0_REG32 GSTATUS2; - S3C24X0_REG32 GSTATUS3; - S3C24X0_REG32 GSTATUS4; + u32 GPACON; + u32 GPADAT; + u32 res1[2]; + u32 GPBCON; + u32 GPBDAT; + u32 GPBUP; + u32 res2; + u32 GPCCON; + u32 GPCDAT; + u32 GPCUP; + u32 res3; + u32 GPDCON; + u32 GPDDAT; + u32 GPDUP; + u32 res4; + u32 GPECON; + u32 GPEDAT; + u32 GPEUP; + u32 res5; + u32 GPFCON; + u32 GPFDAT; + u32 GPFUP; + u32 res6; + u32 GPGCON; + u32 GPGDAT; + u32 GPGUP; + u32 res7; + u32 GPHCON; + u32 GPHDAT; + u32 GPHUP; + u32 res8; + + u32 MISCCR; + u32 DCLKCON; + u32 EXTINT0; + u32 EXTINT1; + u32 EXTINT2; + u32 EINTFLT0; + u32 EINTFLT1; + u32 EINTFLT2; + u32 EINTFLT3; + u32 EINTMASK; + u32 EINTPEND; + u32 GSTATUS0; + u32 GSTATUS1; + u32 GSTATUS2; + u32 GSTATUS3; + u32 GSTATUS4; #endif }; @@ -457,112 +453,112 @@ struct s3c24x0_gpio { /* RTC (see manual chapter 17) */ struct s3c24x0_rtc { #ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[67]; - S3C24X0_REG8 RTCCON; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 TICNT; - S3C24X0_REG8 res3[11]; - S3C24X0_REG8 RTCALM; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 ALMSEC; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 ALMMIN; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 ALMHOUR; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 ALMDATE; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 ALMMON; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 ALMYEAR; - S3C24X0_REG8 res10[3]; - S3C24X0_REG8 RTCRST; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 BCDSEC; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 BCDMIN; - S3C24X0_REG8 res13[3]; - S3C24X0_REG8 BCDHOUR; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 BCDDATE; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 BCDDAY; - S3C24X0_REG8 res16[3]; - S3C24X0_REG8 BCDMON; - S3C24X0_REG8 res17[3]; - S3C24X0_REG8 BCDYEAR; + u8 res1[67]; + u8 RTCCON; + u8 res2[3]; + u8 TICNT; + u8 res3[11]; + u8 RTCALM; + u8 res4[3]; + u8 ALMSEC; + u8 res5[3]; + u8 ALMMIN; + u8 res6[3]; + u8 ALMHOUR; + u8 res7[3]; + u8 ALMDATE; + u8 res8[3]; + u8 ALMMON; + u8 res9[3]; + u8 ALMYEAR; + u8 res10[3]; + u8 RTCRST; + u8 res11[3]; + u8 BCDSEC; + u8 res12[3]; + u8 BCDMIN; + u8 res13[3]; + u8 BCDHOUR; + u8 res14[3]; + u8 BCDDATE; + u8 res15[3]; + u8 BCDDAY; + u8 res16[3]; + u8 BCDMON; + u8 res17[3]; + u8 BCDYEAR; #else /* little endian */ - S3C24X0_REG8 res0[64]; - S3C24X0_REG8 RTCCON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 TICNT; - S3C24X0_REG8 res2[11]; - S3C24X0_REG8 RTCALM; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 ALMSEC; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 ALMMIN; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 ALMHOUR; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 ALMDATE; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 ALMMON; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 ALMYEAR; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 RTCRST; - S3C24X0_REG8 res10[3]; - S3C24X0_REG8 BCDSEC; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 BCDMIN; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 BCDHOUR; - S3C24X0_REG8 res13[3]; - S3C24X0_REG8 BCDDATE; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 BCDDAY; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 BCDMON; - S3C24X0_REG8 res16[3]; - S3C24X0_REG8 BCDYEAR; - S3C24X0_REG8 res17[3]; + u8 res0[64]; + u8 RTCCON; + u8 res1[3]; + u8 TICNT; + u8 res2[11]; + u8 RTCALM; + u8 res3[3]; + u8 ALMSEC; + u8 res4[3]; + u8 ALMMIN; + u8 res5[3]; + u8 ALMHOUR; + u8 res6[3]; + u8 ALMDATE; + u8 res7[3]; + u8 ALMMON; + u8 res8[3]; + u8 ALMYEAR; + u8 res9[3]; + u8 RTCRST; + u8 res10[3]; + u8 BCDSEC; + u8 res11[3]; + u8 BCDMIN; + u8 res12[3]; + u8 BCDHOUR; + u8 res13[3]; + u8 BCDDATE; + u8 res14[3]; + u8 BCDDAY; + u8 res15[3]; + u8 BCDMON; + u8 res16[3]; + u8 BCDYEAR; + u8 res17[3]; #endif }; /* ADC (see manual chapter 16) */ struct s3c2400_adc { - S3C24X0_REG32 ADCCON; - S3C24X0_REG32 ADCDAT; + u32 ADCCON; + u32 ADCDAT; }; /* ADC (see manual chapter 16) */ struct s3c2410_adc { - S3C24X0_REG32 ADCCON; - S3C24X0_REG32 ADCTSC; - S3C24X0_REG32 ADCDLY; - S3C24X0_REG32 ADCDAT0; - S3C24X0_REG32 ADCDAT1; + u32 ADCCON; + u32 ADCTSC; + u32 ADCDLY; + u32 ADCDAT0; + u32 ADCDAT1; }; /* SPI (see manual chapter 22) */ struct s3c24x0_spi_channel { - S3C24X0_REG8 SPCON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 SPSTA; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 SPPIN; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 SPPRE; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 SPTDAT; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 SPRDAT; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 res7[16]; + u8 SPCON; + u8 res1[3]; + u8 SPSTA; + u8 res2[3]; + u8 SPPIN; + u8 res3[3]; + u8 SPPRE; + u8 res4[3]; + u8 SPTDAT; + u8 res5[3]; + u8 SPRDAT; + u8 res6[3]; + u8 res7[16]; }; struct s3c24x0_spi { @@ -573,84 +569,84 @@ struct s3c24x0_spi { /* MMC INTERFACE (see S3C2400 manual chapter 19) */ struct s3c2400_mmc { #ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 MMCON; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 MMCRR; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 MMFCON; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 MMSTA; - S3C24X0_REG16 res5; - S3C24X0_REG16 MMFSTA; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 MMPRE; - S3C24X0_REG16 res7; - S3C24X0_REG16 MMLEN; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 MMCR7; - S3C24X0_REG32 MMRSP[4]; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 MMCMD0; - S3C24X0_REG32 MMCMD1; - S3C24X0_REG16 res10; - S3C24X0_REG16 MMCR16; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 MMDAT; + u8 res1[3]; + u8 MMCON; + u8 res2[3]; + u8 MMCRR; + u8 res3[3]; + u8 MMFCON; + u8 res4[3]; + u8 MMSTA; + u16 res5; + u16 MMFSTA; + u8 res6[3]; + u8 MMPRE; + u16 res7; + u16 MMLEN; + u8 res8[3]; + u8 MMCR7; + u32 MMRSP[4]; + u8 res9[3]; + u8 MMCMD0; + u32 MMCMD1; + u16 res10; + u16 MMCR16; + u8 res11[3]; + u8 MMDAT; #else - S3C24X0_REG8 MMCON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 MMCRR; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 MMFCON; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 MMSTA; - S3C24X0_REG8 res4[3]; - S3C24X0_REG16 MMFSTA; - S3C24X0_REG16 res5; - S3C24X0_REG8 MMPRE; - S3C24X0_REG8 res6[3]; - S3C24X0_REG16 MMLEN; - S3C24X0_REG16 res7; - S3C24X0_REG8 MMCR7; - S3C24X0_REG8 res8[3]; - S3C24X0_REG32 MMRSP[4]; - S3C24X0_REG8 MMCMD0; - S3C24X0_REG8 res9[3]; - S3C24X0_REG32 MMCMD1; - S3C24X0_REG16 MMCR16; - S3C24X0_REG16 res10; - S3C24X0_REG8 MMDAT; - S3C24X0_REG8 res11[3]; + u8 MMCON; + u8 res1[3]; + u8 MMCRR; + u8 res2[3]; + u8 MMFCON; + u8 res3[3]; + u8 MMSTA; + u8 res4[3]; + u16 MMFSTA; + u16 res5; + u8 MMPRE; + u8 res6[3]; + u16 MMLEN; + u16 res7; + u8 MMCR7; + u8 res8[3]; + u32 MMRSP[4]; + u8 MMCMD0; + u8 res9[3]; + u32 MMCMD1; + u16 MMCR16; + u16 res10; + u8 MMDAT; + u8 res11[3]; #endif }; /* SD INTERFACE (see S3C2410 manual chapter 19) */ struct s3c2410_sdi { - S3C24X0_REG32 SDICON; - S3C24X0_REG32 SDIPRE; - S3C24X0_REG32 SDICARG; - S3C24X0_REG32 SDICCON; - S3C24X0_REG32 SDICSTA; - S3C24X0_REG32 SDIRSP0; - S3C24X0_REG32 SDIRSP1; - S3C24X0_REG32 SDIRSP2; - S3C24X0_REG32 SDIRSP3; - S3C24X0_REG32 SDIDTIMER; - S3C24X0_REG32 SDIBSIZE; - S3C24X0_REG32 SDIDCON; - S3C24X0_REG32 SDIDCNT; - S3C24X0_REG32 SDIDSTA; - S3C24X0_REG32 SDIFSTA; + u32 SDICON; + u32 SDIPRE; + u32 SDICARG; + u32 SDICCON; + u32 SDICSTA; + u32 SDIRSP0; + u32 SDIRSP1; + u32 SDIRSP2; + u32 SDIRSP3; + u32 SDIDTIMER; + u32 SDIBSIZE; + u32 SDIDCON; + u32 SDIDCNT; + u32 SDIDSTA; + u32 SDIFSTA; #ifdef __BIG_ENDIAN - S3C24X0_REG8 res[3]; - S3C24X0_REG8 SDIDAT; + u8 res[3]; + u8 SDIDAT; #else - S3C24X0_REG8 SDIDAT; - S3C24X0_REG8 res[3]; + u8 SDIDAT; + u8 res[3]; #endif - S3C24X0_REG32 SDIIMSK; + u32 SDIIMSK; }; #endif /*__S3C24X0_H__*/ -- cgit v1.2.1 From a59a23d68ae4f4a1c07d105520c93e6e289d186f Mon Sep 17 00:00:00 2001 From: Seunghyeon Rhee Date: Fri, 13 Nov 2009 16:49:41 +0900 Subject: S3C6400/SMDK6400: fix stack_setup in start.S Fix stack_setup to place the stack on the correct address in DRAM accroding to U-Boot standard and remove conditional compilation by CONFIG_MEMORY_UPPER_CODE macro that is not necessry. This macro was introduced and used only by this board for some unclear reason. The definition of this macro is also removed because it's not referenced elsewhere. Signed-off-by: Seunghyeon Rhee Tested-by: Minkyu Kang --- include/configs/smdk6400.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index f6e1221294..f644cd2cda 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -49,8 +49,6 @@ #define CONFIG_ENABLE_MMU #endif -#define CONFIG_MEMORY_UPPER_CODE - #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG -- cgit v1.2.1 From ac67804fbb2d82a19170066c02af7053d474ce8d Mon Sep 17 00:00:00 2001 From: "kevin.morfitt@fearnside-systems.co.uk" Date: Tue, 17 Nov 2009 18:30:34 +0900 Subject: Add a unified s3c24x0 header file This patch adds a unified s3c24x0 cpu header file that selects the header file for the specific s3c24x0 cpu from the SOC and CPU configs defined in board config file. This removes the current chain of s3c24-type #ifdef's from the s3c24x0 code. Signed-off-by: Kevin Morfitt Signed-off-by: Minkyu Kang --- include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h | 27 +++++++++++++++++++++++++++ include/common.h | 5 +++-- include/configs/VCMA9.h | 7 ++++--- include/configs/sbc2410x.h | 7 ++++--- include/configs/smdk2400.h | 7 ++++--- include/configs/smdk2410.h | 7 ++++--- include/configs/trab.h | 9 +++++---- 7 files changed, 51 insertions(+), 18 deletions(-) create mode 100644 include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h (limited to 'include') diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h b/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h new file mode 100644 index 0000000000..c37d4a108d --- /dev/null +++ b/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifdef CONFIG_S3C2400 + #include +#elif defined CONFIG_S3C2410 + #include +#else + #error Please define the s3c24x0 cpu type +#endif diff --git a/include/common.h b/include/common.h index f7c93bf5a6..8ee80c1391 100644 --- a/include/common.h +++ b/include/common.h @@ -495,8 +495,9 @@ int prt_mpc8220_clks (void); ulong get_OPB_freq (void); ulong get_PCI_freq (void); #endif -#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \ - defined(CONFIG_LH7A40X) || defined(CONFIG_S3C6400) +#if defined(CONFIG_S3C24X0) || \ + defined(CONFIG_LH7A40X) || \ + defined(CONFIG_S3C6400) ulong get_FCLK (void); ulong get_HCLK (void); ulong get_PCLK (void); diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 618b7f0a7e..ebc81c4003 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -33,9 +33,10 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ -#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h index e6886cf7f6..025ad0953c 100644 --- a/include/configs/sbc2410x.h +++ b/include/configs/sbc2410x.h @@ -43,9 +43,10 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ -#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */ /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */ diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h index a1beb65d0e..fd51219af4 100644 --- a/include/configs/smdk2400.h +++ b/include/configs/smdk2400.h @@ -34,9 +34,10 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T core */ -#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */ -#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */ +#define CONFIG_ARM920T 1 /* This is an ARM920T core */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */ +#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */ /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000 /* SMDK2400 has 12 MHz input clock */ diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index c57751bf90..f9d1e55186 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -33,9 +33,10 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ -#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */ /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */ diff --git a/include/configs/trab.h b/include/configs/trab.h index 97f30cea75..9827195e8d 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -40,10 +40,11 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an arm920t CPU */ -#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */ -#define CONFIG_TRAB 1 /* on a TRAB Board */ -#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */ +#define CONFIG_ARM920T 1 /* This is an arm920t CPU */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */ +#define CONFIG_TRAB 1 /* on a TRAB Board */ +#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */ /* automatic software updates (see board/trab/auto_update.c) */ #define CONFIG_AUTO_UPDATE 1 -- cgit v1.2.1 From bbed056e550b26712edc173411c9d7ff9cb7e0e6 Mon Sep 17 00:00:00 2001 From: Nick Thompson Date: Thu, 12 Nov 2009 11:06:08 -0500 Subject: Add TI DA8xx support: DA8xx includes Provides initial support for TI OMAP-L1x/DA8xx SoC devices. See http://www.ti.com The DA8xx devices are similar to DaVinci devices but have a differing memory map and updated peripheral versions. Signed-off-by: Nick Thompson Signed-off-by: Sekhar Nori --- include/asm-arm/arch-davinci/hardware.h | 237 ++++++++++++++++++++++++++++++++ include/asm-arm/arch-davinci/i2c_defs.h | 5 + 2 files changed, 242 insertions(+) (limited to 'include') diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h index acf12ea7a2..81cc8ab157 100644 --- a/include/asm-arm/arch-davinci/hardware.h +++ b/include/asm-arm/arch-davinci/hardware.h @@ -49,6 +49,8 @@ typedef volatile unsigned int * dv_reg_p; * on other DaVinci chips. Double check them before you try * using the addresses ... or PSC module identifiers, etc. */ +#ifndef CONFIG_SOC_DA8XX + #define DAVINCI_DMA_3PCC_BASE (0x01c00000) #define DAVINCI_DMA_3PTC0_BASE (0x01c10000) #define DAVINCI_DMA_3PTC1_BASE (0x01c10400) @@ -116,10 +118,46 @@ typedef volatile unsigned int * dv_reg_p; #endif +#else /* CONFIG_SOC_DA8XX */ + +#define DAVINCI_UART0_BASE 0x01c42000 +#define DAVINCI_UART1_BASE 0x01d0c000 +#define DAVINCI_UART2_BASE 0x01d0d000 +#define DAVINCI_I2C0_BASE 0x01c22000 +#define DAVINCI_I2C1_BASE 0x01e28000 +#define DAVINCI_TIMER0_BASE 0x01c20000 +#define DAVINCI_TIMER1_BASE 0x01c21000 +#define DAVINCI_WDOG_BASE 0x01c21000 +#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000 +#define DAVINCI_PSC0_BASE 0x01c10000 +#define DAVINCI_PSC1_BASE 0x01e27000 +#define DAVINCI_SPI0_BASE 0x01c41000 +#define DAVINCI_USB_OTG_BASE 0x01e00000 +#define DAVINCI_SPI1_BASE 0x01e12000 +#define DAVINCI_GPIO_BASE 0x01e26000 +#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000 +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000 +#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000 +#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000 +#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000 +#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000 +#define DAVINCI_INTC_BASE 0xfffee000 +#define DAVINCI_BOOTCFG_BASE 0x01c14000 + +#endif /* CONFIG_SOC_DA8XX */ + /* Power and Sleep Controller (PSC) Domains */ #define DAVINCI_GPSC_ARMDOMAIN 0 #define DAVINCI_GPSC_DSPDOMAIN 1 +#ifndef CONFIG_SOC_DA8XX + #define DAVINCI_LPSC_VPSSMSTR 0 #define DAVINCI_LPSC_VPSSSLV 1 #define DAVINCI_LPSC_TPCC 2 @@ -166,6 +204,52 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_DM646X_LPSC_UART0 26 #define DAVINCI_DM646X_LPSC_I2C 31 +#else /* CONFIG_SOC_DA8XX */ + +enum davinci_lpsc_ids { + DAVINCI_LPSC_TPCC = 0, + DAVINCI_LPSC_TPTC0, + DAVINCI_LPSC_TPTC1, + DAVINCI_LPSC_AEMIF, + DAVINCI_LPSC_SPI0, + DAVINCI_LPSC_MMC_SD, + DAVINCI_LPSC_AINTC, + DAVINCI_LPSC_ARM_RAM_ROM, + DAVINCI_LPSC_SECCTL_KEYMGR, + DAVINCI_LPSC_UART0, + DAVINCI_LPSC_SCR0, + DAVINCI_LPSC_SCR1, + DAVINCI_LPSC_SCR2, + DAVINCI_LPSC_DMAX, + DAVINCI_LPSC_ARM, + DAVINCI_LPSC_GEM, + /* for LPSCs in PSC1, offset from 32 for differentiation */ + DAVINCI_LPSC_PSC1_BASE = 32, + DAVINCI_LPSC_USB11, + DAVINCI_LPSC_USB20, + DAVINCI_LPSC_GPIO, + DAVINCI_LPSC_UHPI, + DAVINCI_LPSC_EMAC, + DAVINCI_LPSC_DDR_EMIF, + DAVINCI_LPSC_McASP0, + DAVINCI_LPSC_McASP1, + DAVINCI_LPSC_McASP2, + DAVINCI_LPSC_SPI1, + DAVINCI_LPSC_I2C1, + DAVINCI_LPSC_UART1, + DAVINCI_LPSC_UART2, + DAVINCI_LPSC_LCDC, + DAVINCI_LPSC_ePWM, + DAVINCI_LPSC_eCAP, + DAVINCI_LPSC_eQEP, + DAVINCI_LPSC_SCR_P0, + DAVINCI_LPSC_SCR_P1, + DAVINCI_LPSC_CR_P3, + DAVINCI_LPSC_L3_CBA_RAM +}; + +#endif /* CONFIG_SOC_DA8XX */ + void lpsc_on(unsigned int id); void dsp_on(void); @@ -174,6 +258,8 @@ void davinci_enable_emac(void); void davinci_enable_i2c(void); void davinci_errata_workarounds(void); +#ifndef CONFIG_SOC_DA8XX + /* Some PSC defines */ #define PSC_CHP_SHRTSW (0x01c40038) #define PSC_GBLCTL (0x01c41010) @@ -194,6 +280,39 @@ void davinci_errata_workarounds(void); #define PSC_SILVER_BULLET (0x01c41a20) +#else /* CONFIG_SOC_DA8XX */ + +#define PSC_PSC0_MODULE_ID_CNT 16 +#define PSC_PSC1_MODULE_ID_CNT 32 + +struct davinci_psc_regs { + dv_reg revid; + dv_reg rsvd0[71]; + dv_reg ptcmd; + dv_reg rsvd1; + dv_reg ptstat; + dv_reg rsvd2[437]; + union { + struct { + dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT]; + dv_reg rsvd3[112]; + dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT]; + } psc0; + struct { + dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT]; + dv_reg rsvd3[96]; + dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT]; + } psc1; + }; +}; + +#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE) +#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE) + +#endif /* CONFIG_SOC_DA8XX */ + +#ifndef CONFIG_SOC_DA8XX + /* Miscellania... */ #define VBPR (0x20000020) @@ -206,4 +325,122 @@ void davinci_errata_workarounds(void); #define PINMUX3 0x01c4000c #define PINMUX4 0x01c40010 +#else /* CONFIG_SOC_DA8XX */ + +struct davinci_pllc_regs { + dv_reg revid; + dv_reg rsvd1[56]; + dv_reg rstype; + dv_reg rsvd2[6]; + dv_reg pllctl; + dv_reg ocsel; + dv_reg rsvd3[2]; + dv_reg pllm; + dv_reg prediv; + dv_reg plldiv1; + dv_reg plldiv2; + dv_reg plldiv3; + dv_reg oscdiv; + dv_reg postdiv; + dv_reg rsvd4[3]; + dv_reg pllcmd; + dv_reg pllstat; + dv_reg alnctl; + dv_reg dchange; + dv_reg cken; + dv_reg ckstat; + dv_reg systat; + dv_reg rsvd5[3]; + dv_reg plldiv4; + dv_reg plldiv5; + dv_reg plldiv6; + dv_reg plldiv7; + dv_reg rsvd6[32]; + dv_reg emucnt0; + dv_reg emucnt1; +}; + +#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE) +#define DAVINCI_PLLC_DIV_MASK 0x1f + +/* Clock IDs */ +enum davinci_clk_ids { + DAVINCI_SPI0_CLKID = 2, + DAVINCI_UART2_CLKID = 2, + DAVINCI_MDIO_CLKID = 4, + DAVINCI_ARM_CLKID = 6, + DAVINCI_PLLM_CLKID = 0xff, + DAVINCI_PLLC_CLKID = 0x100, + DAVINCI_AUXCLK_CLKID = 0x101 +}; + +int clk_get(enum davinci_clk_ids id); + +/* Boot config */ +struct davinci_syscfg_regs { + dv_reg revid; + dv_reg rsvd[71]; + dv_reg pinmux[20]; + dv_reg suspsrc; + dv_reg chipsig; + dv_reg chipsig_clr; + dv_reg cfgchip0; + dv_reg cfgchip1; + dv_reg cfgchip2; + dv_reg cfgchip3; + dv_reg cfgchip4; +}; + +#define davinci_syscfg_regs \ + ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE) + +/* Emulation suspend bits */ +#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5) +#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16) +#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21) +#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20) +#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27) + +/* Interrupt controller */ +struct davinci_aintc_regs { + dv_reg revid; + dv_reg cr; + dv_reg dummy0[2]; + dv_reg ger; + dv_reg dummy1[219]; + dv_reg ecr1; + dv_reg ecr2; + dv_reg ecr3; + dv_reg dummy2[1117]; + dv_reg hier; +}; + +#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE) + +struct davinci_uart_ctrl_regs { + dv_reg revid1; + dv_reg revid2; + dv_reg pwremu_mgmt; + dv_reg mdr; +}; + +#define DAVINCI_UART_CTRL_BASE 0x28 +#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE) +#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE) +#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE) + +#define davinci_uart0_ctrl_regs \ + ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR) +#define davinci_uart1_ctrl_regs \ + ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR) +#define davinci_uart2_ctrl_regs \ + ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR) + +/* UART PWREMU_MGMT definitions */ +#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0) +#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13) +#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14) + +#endif /* CONFIG_SOC_DA8XX */ + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-davinci/i2c_defs.h b/include/asm-arm/arch-davinci/i2c_defs.h index 2e902e17f8..24cd268b95 100644 --- a/include/asm-arm/arch-davinci/i2c_defs.h +++ b/include/asm-arm/arch-davinci/i2c_defs.h @@ -28,7 +28,11 @@ #define I2C_WRITE 0 #define I2C_READ 1 +#ifndef CONFIG_SOC_DA8XX #define I2C_BASE 0x01c21000 +#else +#define I2C_BASE 0x01c22000 +#endif #define I2C_OA (I2C_BASE + 0x00) #define I2C_IE (I2C_BASE + 0x04) @@ -88,6 +92,7 @@ #define I2C_CON_XA (1 << 8) /* Expand address */ #define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */ #define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */ +#define I2C_CON_FREE (1 << 14) /* Free run on emulation */ #define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */ -- cgit v1.2.1 From 2819e1365be0c81a0141ef5c6a7996b40888f6d8 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Thu, 12 Nov 2009 11:09:25 -0500 Subject: TI DA8xx: Integrate DA830 EVM support into U-Boot Integrate DA830 EVM support into U-Boot. Provides initial support for TI OMAP-L137/DA830 SoC devices on a Spectrum Digital EVM board. See http://www.spectrumdigital.com/ Signed-off-by: Nick Thompson --- include/common.h | 3 + include/configs/da830evm.h | 243 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 246 insertions(+) create mode 100644 include/configs/da830evm.h (limited to 'include') diff --git a/include/common.h b/include/common.h index 8ee80c1391..30a4b7affb 100644 --- a/include/common.h +++ b/include/common.h @@ -107,6 +107,9 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_BLACKFIN #include #endif +#ifdef CONFIG_SOC_DA8XX +#include +#endif #include #include diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h new file mode 100644 index 0000000000..38e2ce1f1c --- /dev/null +++ b/include/configs/da830evm.h @@ -0,0 +1,243 @@ +/* + * Copyright (C) 2008 Texas Instruments, Inc + * + * Based on davinci_dvevm.h. Original Copyrights follow: + * + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Board + */ + +/* + * SoC Configuration + */ +#define CONFIG_MACH_DAVINCI_DA830_EVM +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) +#define CONFIG_SYS_OSCIN_FREQ 24000000 +#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ + +/* + * Memory Info + */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ +#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* memtest start addr */ +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) /* 16MB test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ + +/* + * Serial Driver info + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ +#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ +#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * I2C Configuration + */ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CONFIG_SYS_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */ +#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ + +/* + * I2C EEPROM definitions for catalyst 24W256 EEPROM chip + */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 + +/* + * Network & Ethernet Configuration + */ +#ifdef CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#endif + +/* + * Flash & Environment + */ +#ifdef CONFIG_USE_NAND +#undef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define CONFIG_ENV_SIZE (128 << 10) +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_CS 3 +#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE +#define CONFIG_SYS_CLE_MASK 0x10 +#define CONFIG_SYS_ALE_MASK 0x8 +#define CONFIG_SYS_NAND_HW_ECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#define DEF_BOOTM "" +#endif + +#ifdef CONFIG_USE_NOR +#define CONFIG_ENV_IS_IN_FLASH +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CONFIG_SYS_FLASH_SECT_SZ (64 << 10) /* 64KB */ +#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3) +#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE +#define PHYS_FLASH_SIZE (32 << 20) /* Flash size 32MB */ +#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ +#define CONFIG_SYS_FLASH_SPL_ACCESS +#endif + +#ifdef CONFIG_USE_SPIFLASH +#undef CONFIG_ENV_IS_IN_FLASH +#undef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE (16 << 10) +#define CONFIG_ENV_OFFSET (256 << 10) +#define CONFIG_ENV_SECT_SIZE 4096 +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_DAVINCI_SPI +#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE +#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) +#define CONFIG_SF_DEFAULT_SPEED 50000000 +#define CONFIG_SYS_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + + +/* + * U-Boot general configuration + */ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#undef CONFIG_MISC_INIT_R +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "DA830-evm > " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + 0x700000) +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC + +/* + * Linux Information + */ +#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100) +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock/2 rw noinitrd ip=dhcp" +#define CONFIG_BOOTCOMMAND "" +#define CONFIG_BOOTDELAY 3 + +/* + * U-Boot commands + */ +#include +#define CONFIG_CMD_ENV +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MEMORY +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#define CONFIG_CMD_EEPROM + +#ifndef CONFIG_DRIVER_TI_EMAC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_PING +#endif + +#ifdef CONFIG_USE_NAND +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE +#endif + +#ifdef CONFIG_USE_SPIFLASH +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_FLASH +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SAVEENV +#endif + +#if !defined(CONFIG_USE_NAND) && \ + !defined(CONFIG_USE_NOR) && \ + !defined(CONFIG_USE_SPIFLASH) +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_SIZE (16 << 10) +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_ENV +#endif + +#ifdef CONFIG_USB_DA8XX +#define CONFIG_CMD_USB /* include support for usb */ +#define CONFIG_CMD_STORAGE /* include support for usb */ +#define CONFIG_CMD_FAT /* include support for FAT/storage*/ +#define CONFIG_DOS_PARTITION /* include support for FAT/storage*/ +#endif + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From 169a4c804dbaf11facb041b1333d394c6ceb8d68 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Sat, 7 Nov 2009 10:40:47 -0500 Subject: OMAP3:SDRC: Cleanup references to SDP Remove SDP referenced unused defines Signed-off-by: Nishanth Menon --- include/asm-arm/arch-omap3/mem.h | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h index 5b9ac753e8..5496a618c6 100644 --- a/include/asm-arm/arch-omap3/mem.h +++ b/include/asm-arm/arch-omap3/mem.h @@ -40,11 +40,8 @@ enum { #define EARLY_INIT 1 /* Slower full frequency range default timings for x32 operation*/ -#define SDP_SDRC_SHARING 0x00000100 -#define SDP_SDRC_MR_0_SDR 0x00000031 - -/* optimized timings good for current shipping parts */ -#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ +#define SDRC_SHARING 0x00000100 +#define SDRC_MR_0_SDR 0x00000031 #define DLL_OFFSET 0 #define DLL_WRITEDDRCLKX2DIS 1 @@ -91,10 +88,6 @@ enum { #define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \ (TXP_165 << 8) | (TWTR_165 << 16)) -#define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 -#define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165 -#define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz - /* * GPMC settings - * Definitions is as per the following format -- cgit v1.2.1 From 30563a04bff73fd4fbd840b846f4b6459759a839 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Sat, 7 Nov 2009 10:51:24 -0500 Subject: OMAP3:SDRC: introduce DDR types Micron DDR timings based on: http://www.sakoman.net/cgi-bin/gitweb.cgi?p=x-load-omap3.git;a=blob;f=include/asm/arch-omap3/mem.h;h=e6fbfe3947f5d0d85fea776e30821d4017316d86;hb=HEAD Introduce Micron DDR timings and provide CONFIG_OMAP3_INFINEON_DDR and CONFIG_OMAP3_MICRON_DDR config options to allow for platform files to setup their timings as per the type of DDR selected Reported-by: Steve Sakoman in http://www.nabble.com/forum/Permalink.jtp?root=25779518&post=25959734&page=y Signed-off-by: Nishanth Menon --- include/asm-arm/arch-omap3/mem.h | 91 +++++++++++++++++++++++++++++++--------- include/configs/devkit8000.h | 3 ++ include/configs/omap3_beagle.h | 3 ++ include/configs/omap3_evm.h | 3 ++ include/configs/omap3_overo.h | 3 ++ include/configs/omap3_pandora.h | 3 ++ include/configs/omap3_sdp3430.h | 3 ++ include/configs/omap3_zoom1.h | 3 ++ include/configs/omap3_zoom2.h | 3 ++ 9 files changed, 96 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h index 5496a618c6..9439758e4a 100644 --- a/include/asm-arm/arch-omap3/mem.h +++ b/include/asm-arm/arch-omap3/mem.h @@ -68,25 +68,78 @@ enum { * TCKE = 2 * XSR = 120/6 = 20 */ -#define TDAL_165 6 -#define TDPL_165 3 -#define TRRD_165 2 -#define TRCD_165 3 -#define TRP_165 3 -#define TRAS_165 7 -#define TRC_165 10 -#define TRFC_165 21 -#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \ - (TRAS_165 << 18) | (TRP_165 << 15) | \ - (TRCD_165 << 12) | (TRRD_165 << 9) | \ - (TDPL_165 << 6) | (TDAL_165)) - -#define TWTR_165 1 -#define TCKE_165 1 -#define TXP_165 5 -#define XSR_165 23 -#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \ - (TXP_165 << 8) | (TWTR_165 << 16)) +#define INFINEON_TDAL_165 6 +#define INFINEON_TDPL_165 3 +#define INFINEON_TRRD_165 2 +#define INFINEON_TRCD_165 3 +#define INFINEON_TRP_165 3 +#define INFINEON_TRAS_165 7 +#define INFINEON_TRC_165 10 +#define INFINEON_TRFC_165 12 +#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \ + (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \ + (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \ + (INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \ + (INFINEON_TDAL_165)) + +#define INFINEON_TWTR_165 1 +#define INFINEON_TCKE_165 2 +#define INFINEON_TXP_165 2 +#define INFINEON_XSR_165 20 +#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \ + (INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \ + (INFINEON_TWTR_165 << 16)) + +/* Micron part of 3430 EVM (165MHz optimized) 6.06ns + * ACTIMA + * TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6 + * TDPL (Twr) = 15/6 = 2.5 -> 3 + * TRRD = 12/6 = 2 + * TRCD = 18/6 = 3 + * TRP = 18/6 = 3 + * TRAS = 42/6 = 7 + * TRC = 60/6 = 10 + * TRFC = 125/6 = 21 + * ACTIMB + * TWTR = 1 + * TCKE = 1 + * TXSR = 138/6 = 23 + * TXP = 25/6 = 4.1 ~5 + */ +#define MICRON_TDAL_165 6 +#define MICRON_TDPL_165 3 +#define MICRON_TRRD_165 2 +#define MICRON_TRCD_165 3 +#define MICRON_TRP_165 3 +#define MICRON_TRAS_165 7 +#define MICRON_TRC_165 10 +#define MICRON_TRFC_165 21 +#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \ + (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \ + (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \ + (MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \ + (MICRON_TDAL_165)) + +#define MICRON_TWTR_165 1 +#define MICRON_TCKE_165 1 +#define MICRON_XSR_165 23 +#define MICRON_TXP_165 5 +#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \ + (MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \ + (MICRON_TWTR_165 << 16)) + +#ifdef CONFIG_OMAP3_INFINEON_DDR +#define V_ACTIMA_165 INFINEON_V_ACTIMA_165 +#define V_ACTIMB_165 INFINEON_V_ACTIMB_165 +#endif +#ifdef CONFIG_OMAP3_MICRON_DDR +#define V_ACTIMA_165 MICRON_V_ACTIMA_165 +#define V_ACTIMB_165 MICRON_V_ACTIMB_165 +#endif + +#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) +#error "Please choose the right DDR type in config header" +#endif /* * GPMC settings - diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index bd5037e910..1011770962 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -66,6 +66,9 @@ /* Hardware drivers */ +/* DDR - I use Micron DDR */ +#define CONFIG_OMAP3_MICRON_DDR 1 + /* DM9000 */ #define CONFIG_NET_MULTI 1 #define CONFIG_NET_RETRY_COUNT 20 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 19a5ec92ec..024b9b8334 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -97,6 +97,9 @@ #define CONFIG_OMAP3_MMC 1 #define CONFIG_DOS_PARTITION 1 +/* DDR - I use Micron DDR */ +#define CONFIG_OMAP3_MICRON_DDR 1 + /* commands to include */ #include diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index a5514aeb9b..6709edc863 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -101,6 +101,9 @@ #define CONFIG_OMAP3_MMC 1 #define CONFIG_DOS_PARTITION 1 +/* DDR - I use Micron DDR */ +#define CONFIG_OMAP3_MICRON_DDR 1 + /* commands to include */ #include diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index ffb515d322..0f812a7930 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -89,6 +89,9 @@ #define CONFIG_OMAP3_MMC 1 #define CONFIG_DOS_PARTITION 1 +/* DDR - I use Micron DDR */ +#define CONFIG_OMAP3_MICRON_DDR 1 + /* commands to include */ #include diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 6f21af3d13..0cafeb81c7 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -92,6 +92,9 @@ #define CONFIG_OMAP3_MMC 1 #define CONFIG_DOS_PARTITION 1 +/* DDR - I use Micron DDR */ +#define CONFIG_OMAP3_MICRON_DDR 1 + /* commands to include */ #include diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 229dc5e644..d91c8ffa84 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -137,6 +137,9 @@ #define CONFIG_SYS_I2C_BUS_SELECT 1 #define CONFIG_DRIVER_OMAP34XX_I2C 1 +/* DDR - I use Infineon DDR */ +#define CONFIG_OMAP3_INFINEON_DDR 1 + /* OMITTED: single 1 Gbit MT29F1G NAND flash */ /* diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index da4b677f93..2aef973bce 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -98,6 +98,9 @@ #define CONFIG_OMAP3_MMC 1 #define CONFIG_DOS_PARTITION 1 +/* DDR - I use Micron DDR */ +#define CONFIG_OMAP3_MICRON_DDR 1 + /* commands to include */ #include diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 32cd6fdb14..5b03fb6987 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -98,6 +98,9 @@ #define CONFIG_OMAP3_MMC 1 #define CONFIG_DOS_PARTITION 1 +/* DDR - I use Micron DDR */ +#define CONFIG_OMAP3_MICRON_DDR 1 + /* Status LED */ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ #define CONFIG_BOARD_SPECIFIC_LED 1 -- cgit v1.2.1 From d414aae552bc229dafcad92028effb4a8306c7a5 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 9 Nov 2009 09:29:34 -0500 Subject: OMAP3: Fix SDRC init Defaults are for Infineon DDR timings. Since none of the supported boards currently do XIP boot, these seem to be faulty. fix the values as per the calculations(ACTIMA,B), conf the sdrc power with pwdnen and wakeupproc bits Signed-off-by: Nishanth Menon --- include/asm-arm/arch-omap3/cpu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h index 8ab2e391bc..e51c4f3293 100644 --- a/include/asm-arm/arch-omap3/cpu.h +++ b/include/asm-arm/arch-omap3/cpu.h @@ -222,6 +222,7 @@ struct sdrc { #define PAGEPOLICY_HIGH (0x1 << 0) #define SRFRONRESET (0x1 << 7) +#define PWDNEN (0x1 << 2) #define WAKEUPPROC (0x1 << 26) #define DDR_SDRAM (0x1 << 0) -- cgit v1.2.1 From 43a5f0df2f2e3a2b5eab05d6742501c98d3c0d0c Mon Sep 17 00:00:00 2001 From: Po-Yu Chuang Date: Wed, 11 Nov 2009 17:27:30 +0800 Subject: arm: A320: Add support for Faraday A320 evaluation board This patch adds support for A320 evaluation board from Faraday. This board uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM. FA526 is an ARMv4 processor and uses the ARM920T source in this patch. Signed-off-by: Po-Yu Chuang --- include/asm-arm/arch-a320/a320.h | 35 ++++++ include/asm-arm/arch-a320/ftpmu010.h | 146 ++++++++++++++++++++++ include/asm-arm/arch-a320/ftsdmc020.h | 103 ++++++++++++++++ include/asm-arm/arch-a320/ftsmc020.h | 79 ++++++++++++ include/asm-arm/arch-a320/fttmr010.h | 73 +++++++++++ include/configs/a320evb.h | 222 ++++++++++++++++++++++++++++++++++ 6 files changed, 658 insertions(+) create mode 100644 include/asm-arm/arch-a320/a320.h create mode 100644 include/asm-arm/arch-a320/ftpmu010.h create mode 100644 include/asm-arm/arch-a320/ftsdmc020.h create mode 100644 include/asm-arm/arch-a320/ftsmc020.h create mode 100644 include/asm-arm/arch-a320/fttmr010.h create mode 100644 include/configs/a320evb.h (limited to 'include') diff --git a/include/asm-arm/arch-a320/a320.h b/include/asm-arm/arch-a320/a320.h new file mode 100644 index 0000000000..5c0a097507 --- /dev/null +++ b/include/asm-arm/arch-a320/a320.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __A320_H +#define __A320_H + +/* + * Hardware register bases + */ +#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */ +#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */ +#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */ +#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */ +#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */ +#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */ +#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/ + +#endif /* __A320_H */ + diff --git a/include/asm-arm/arch-a320/ftpmu010.h b/include/asm-arm/arch-a320/ftpmu010.h new file mode 100644 index 0000000000..8ef7a37148 --- /dev/null +++ b/include/asm-arm/arch-a320/ftpmu010.h @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Power Management Unit + */ +#ifndef __FTPMU010_H +#define __FTPMU010_H + +struct ftpmu010 { + unsigned int IDNMBR0; /* 0x00 */ + unsigned int reserved0; /* 0x04 */ + unsigned int OSCC; /* 0x08 */ + unsigned int PMODE; /* 0x0C */ + unsigned int PMCR; /* 0x10 */ + unsigned int PED; /* 0x14 */ + unsigned int PEDSR; /* 0x18 */ + unsigned int reserved1; /* 0x1C */ + unsigned int PMSR; /* 0x20 */ + unsigned int PGSR; /* 0x24 */ + unsigned int MFPSR; /* 0x28 */ + unsigned int MISC; /* 0x2C */ + unsigned int PDLLCR0; /* 0x30 */ + unsigned int PDLLCR1; /* 0x34 */ + unsigned int AHBMCLKOFF; /* 0x38 */ + unsigned int APBMCLKOFF; /* 0x3C */ + unsigned int DCSRCR0; /* 0x40 */ + unsigned int DCSRCR1; /* 0x44 */ + unsigned int DCSRCR2; /* 0x48 */ + unsigned int SDRAMHTC; /* 0x4C */ + unsigned int PSPR0; /* 0x50 */ + unsigned int PSPR1; /* 0x54 */ + unsigned int PSPR2; /* 0x58 */ + unsigned int PSPR3; /* 0x5C */ + unsigned int PSPR4; /* 0x60 */ + unsigned int PSPR5; /* 0x64 */ + unsigned int PSPR6; /* 0x68 */ + unsigned int PSPR7; /* 0x6C */ + unsigned int PSPR8; /* 0x70 */ + unsigned int PSPR9; /* 0x74 */ + unsigned int PSPR10; /* 0x78 */ + unsigned int PSPR11; /* 0x7C */ + unsigned int PSPR12; /* 0x80 */ + unsigned int PSPR13; /* 0x84 */ + unsigned int PSPR14; /* 0x88 */ + unsigned int PSPR15; /* 0x8C */ + unsigned int AHBDMA_RACCS; /* 0x90 */ + unsigned int reserved2; /* 0x94 */ + unsigned int reserved3; /* 0x98 */ + unsigned int JSS; /* 0x9C */ + unsigned int CFC_RACC; /* 0xA0 */ + unsigned int SSP1_RACC; /* 0xA4 */ + unsigned int UART1TX_RACC; /* 0xA8 */ + unsigned int UART1RX_RACC; /* 0xAC */ + unsigned int UART2TX_RACC; /* 0xB0 */ + unsigned int UART2RX_RACC; /* 0xB4 */ + unsigned int SDC_RACC; /* 0xB8 */ + unsigned int I2SAC97_RACC; /* 0xBC */ + unsigned int IRDATX_RACC; /* 0xC0 */ + unsigned int reserved4; /* 0xC4 */ + unsigned int USBD_RACC; /* 0xC8 */ + unsigned int IRDARX_RACC; /* 0xCC */ + unsigned int IRDA_RACC; /* 0xD0 */ + unsigned int ED0_RACC; /* 0xD4 */ + unsigned int ED1_RACC; /* 0xD8 */ +}; + +/* + * ID Number 0 Register + */ +#define FTPMU010_ID_A320A 0x03200000 +#define FTPMU010_ID_A320C 0x03200010 +#define FTPMU010_ID_A320D 0x03200030 + +/* + * OSC Control Register + */ +#define FTPMU010_OSCC_OSCH_TRI (1 << 11) +#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) +#define FTPMU010_OSCC_OSCH_OFF (1 << 8) + +#define FTPMU010_OSCC_OSCL_TRI (1 << 3) +#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) +#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) +#define FTPMU010_OSCC_OSCL_OFF (1 << 0) + +/* + * Power Mode Register + */ +#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) +#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) +#define FTPMU010_PMODE_FCS (1 << 2) +#define FTPMU010_PMODE_TURBO (1 << 1) +#define FTPMU010_PMODE_SLEEP (1 << 0) + +/* + * Power Manager Status Register + */ +#define FTPMU010_PMSR_SMR (1 << 10) + +#define FTPMU010_PMSR_RDH (1 << 2) +#define FTPMU010_PMSR_PH (1 << 1) +#define FTPMU010_PMSR_CKEHLOW (1 << 0) + +/* + * Multi-Function Port Setting Register + */ +#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) +#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) +#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) + +/* + * PLL/DLL Control Register 0 + */ +#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf) +#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19) +#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) +#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) +#define FTPMU010_PDLLCR0_DLLDIS (1 << 16) +#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff) +#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) +#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) +#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) + +#endif /* __FTPMU010_H */ diff --git a/include/asm-arm/arch-a320/ftsdmc020.h b/include/asm-arm/arch-a320/ftsdmc020.h new file mode 100644 index 0000000000..069977200b --- /dev/null +++ b/include/asm-arm/arch-a320/ftsdmc020.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * SDRAM Controller + */ +#ifndef __FTSDMC020_H +#define __FTSDMC020_H + +#define FTSDMC020_OFFSET_TP0 0x00 +#define FTSDMC020_OFFSET_TP1 0x04 +#define FTSDMC020_OFFSET_CR 0x08 +#define FTSDMC020_OFFSET_BANK0_BSR 0x0C +#define FTSDMC020_OFFSET_BANK1_BSR 0x10 +#define FTSDMC020_OFFSET_BANK2_BSR 0x14 +#define FTSDMC020_OFFSET_BANK3_BSR 0x18 +#define FTSDMC020_OFFSET_BANK4_BSR 0x1C +#define FTSDMC020_OFFSET_BANK5_BSR 0x20 +#define FTSDMC020_OFFSET_BANK6_BSR 0x24 +#define FTSDMC020_OFFSET_BANK7_BSR 0x28 +#define FTSDMC020_OFFSET_ACR 0x34 + +/* + * Timing Parametet 0 Register + */ +#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) +#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) +#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) +#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) +#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) + +/* + * Timing Parametet 1 Register + */ +#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) +#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) + +/* + * Configuration Register + */ +#define FTSDMC020_CR_SREF (1 << 0) +#define FTSDMC020_CR_PWDN (1 << 1) +#define FTSDMC020_CR_ISMR (1 << 2) +#define FTSDMC020_CR_IREF (1 << 3) +#define FTSDMC020_CR_IPREC (1 << 4) +#define FTSDMC020_CR_REFTYPE (1 << 5) + +/* + * SDRAM External Bank Base/Size Register + */ +#define FTSDMC020_BANK_ENABLE (1 << 28) + +#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) + +#define FTSDMC020_BANK_DDW_X4 (0 << 12) +#define FTSDMC020_BANK_DDW_X8 (1 << 12) +#define FTSDMC020_BANK_DDW_X16 (2 << 12) +#define FTSDMC020_BANK_DDW_X32 (3 << 12) + +#define FTSDMC020_BANK_DSZ_16M (0 << 8) +#define FTSDMC020_BANK_DSZ_64M (1 << 8) +#define FTSDMC020_BANK_DSZ_128M (2 << 8) +#define FTSDMC020_BANK_DSZ_256M (3 << 8) + +#define FTSDMC020_BANK_MBW_8 (0 << 4) +#define FTSDMC020_BANK_MBW_16 (1 << 4) +#define FTSDMC020_BANK_MBW_32 (2 << 4) + +#define FTSDMC020_BANK_SIZE_1M 0x0 +#define FTSDMC020_BANK_SIZE_2M 0x1 +#define FTSDMC020_BANK_SIZE_4M 0x2 +#define FTSDMC020_BANK_SIZE_8M 0x3 +#define FTSDMC020_BANK_SIZE_16M 0x4 +#define FTSDMC020_BANK_SIZE_32M 0x5 +#define FTSDMC020_BANK_SIZE_64M 0x6 +#define FTSDMC020_BANK_SIZE_128M 0x7 +#define FTSDMC020_BANK_SIZE_256M 0x8 + +/* + * Arbiter Control Register + */ +#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) +#define FTSDMC020_ACR_TOE (1 << 8) + +#endif /* __FTSDMC020_H */ diff --git a/include/asm-arm/arch-a320/ftsmc020.h b/include/asm-arm/arch-a320/ftsmc020.h new file mode 100644 index 0000000000..95d9500339 --- /dev/null +++ b/include/asm-arm/arch-a320/ftsmc020.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Static Memory Controller + */ +#ifndef __FTSMC020_H +#define __FTSMC020_H + +#ifndef __ASSEMBLY__ + +struct ftsmc020 { + struct { + unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */ + unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */ + } bank[4]; + unsigned int pad[8]; /* 0x20 - 0x3c */ + unsigned int ssr; /* 0x40 */ +}; + +void ftsmc020_init(void); + +#endif /* __ASSEMBLY__ */ + +/* + * Memory Bank Configuration Register + */ +#define FTSMC020_BANK_ENABLE (1 << 28) +#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) + +#define FTSMC020_BANK_WPROT (1 << 11) + +#define FTSMC020_BANK_SIZE_32K (0xb << 4) +#define FTSMC020_BANK_SIZE_64K (0xc << 4) +#define FTSMC020_BANK_SIZE_128K (0xd << 4) +#define FTSMC020_BANK_SIZE_256K (0xe << 4) +#define FTSMC020_BANK_SIZE_512K (0xf << 4) +#define FTSMC020_BANK_SIZE_1M (0x0 << 4) +#define FTSMC020_BANK_SIZE_2M (0x1 << 4) +#define FTSMC020_BANK_SIZE_4M (0x2 << 4) +#define FTSMC020_BANK_SIZE_8M (0x3 << 4) +#define FTSMC020_BANK_SIZE_16M (0x4 << 4) +#define FTSMC020_BANK_SIZE_32M (0x5 << 4) + +#define FTSMC020_BANK_MBW_8 (0x0 << 0) +#define FTSMC020_BANK_MBW_16 (0x1 << 0) +#define FTSMC020_BANK_MBW_32 (0x2 << 0) + +/* + * Memory Bank Timing Parameter Register + */ +#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) +#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) +#define FTSMC020_TPR_RBE (1 << 20) +#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) +#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) +#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) +#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) +#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) +#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) +#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) + +#endif /* __FTSMC020_H */ diff --git a/include/asm-arm/arch-a320/fttmr010.h b/include/asm-arm/arch-a320/fttmr010.h new file mode 100644 index 0000000000..72abcb365d --- /dev/null +++ b/include/asm-arm/arch-a320/fttmr010.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Timer + */ +#ifndef __FTTMR010_H +#define __FTTMR010_H + +struct fttmr010 { + unsigned int timer1_counter; /* 0x00 */ + unsigned int timer1_load; /* 0x04 */ + unsigned int timer1_match1; /* 0x08 */ + unsigned int timer1_match2; /* 0x0c */ + unsigned int timer2_counter; /* 0x10 */ + unsigned int timer2_load; /* 0x14 */ + unsigned int timer2_match1; /* 0x18 */ + unsigned int timer2_match2; /* 0x1c */ + unsigned int timer3_counter; /* 0x20 */ + unsigned int timer3_load; /* 0x24 */ + unsigned int timer3_match1; /* 0x28 */ + unsigned int timer3_match2; /* 0x2c */ + unsigned int cr; /* 0x30 */ + unsigned int interrupt_state; /* 0x34 */ + unsigned int interrupt_mask; /* 0x38 */ +}; + +/* + * Timer Control Register + */ +#define FTTMR010_TM3_UPDOWN (1 << 11) +#define FTTMR010_TM2_UPDOWN (1 << 10) +#define FTTMR010_TM1_UPDOWN (1 << 9) +#define FTTMR010_TM3_OFENABLE (1 << 8) +#define FTTMR010_TM3_CLOCK (1 << 7) +#define FTTMR010_TM3_ENABLE (1 << 6) +#define FTTMR010_TM2_OFENABLE (1 << 5) +#define FTTMR010_TM2_CLOCK (1 << 4) +#define FTTMR010_TM2_ENABLE (1 << 3) +#define FTTMR010_TM1_OFENABLE (1 << 2) +#define FTTMR010_TM1_CLOCK (1 << 1) +#define FTTMR010_TM1_ENABLE (1 << 0) + +/* + * Timer Interrupt State & Mask Registers + */ +#define FTTMR010_TM3_OVERFLOW (1 << 8) +#define FTTMR010_TM3_MATCH2 (1 << 7) +#define FTTMR010_TM3_MATCH1 (1 << 6) +#define FTTMR010_TM2_OVERFLOW (1 << 5) +#define FTTMR010_TM2_MATCH2 (1 << 4) +#define FTTMR010_TM2_MATCH1 (1 << 3) +#define FTTMR010_TM1_OVERFLOW (1 << 2) +#define FTTMR010_TM1_MATCH2 (1 << 1) +#define FTTMR010_TM1_MATCH1 (1 << 0) + +#endif /* __FTTMR010_H */ diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h new file mode 100644 index 0000000000..fcc556321b --- /dev/null +++ b/include/configs/a320evb.h @@ -0,0 +1,222 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang + * + * Configuation settings for the Faraday A320 board. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/*----------------------------------------------------------------------- + * CPU and Board Configuration Options + */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#undef CONFIG_SKIP_LOWLEVEL_INIT + +/*----------------------------------------------------------------------- + * Timer + */ +#define CONFIG_SYS_HZ 1000 /* timer ticks per second */ + +/*----------------------------------------------------------------------- + * Real Time Clock + */ +#define CONFIG_RTC_FTRTC010 + +/*----------------------------------------------------------------------- + * Serial console configuration + */ + +/* FTUART is a high speed NS 16C550A compatible UART */ +#define CONFIG_BAUDRATE 38400 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_COM1 0x98200000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK 18432000 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Ethernet + */ +#define CONFIG_NET_MULTI +#define CONFIG_FTMAC100 + +#define CONFIG_BOOTDELAY 3 + +/*----------------------------------------------------------------------- + * Command line configuration. + */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PING + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +/*----------------------------------------------------------------------- + * size in bytes reserved for initial data +*/ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/*----------------------------------------------------------------------- + * SDRAM controller configuration + */ +#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \ + FTSDMC020_TP0_TRP(1) | \ + FTSDMC020_TP0_TRCD(1) | \ + FTSDMC020_TP0_TRF(3) | \ + FTSDMC020_TP0_TWR(1) | \ + FTSDMC020_TP0_TCL(2)) + +#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \ + FTSDMC020_TP1_INI_REFT(8) | \ + FTSDMC020_TP1_REF_INTV(0x180)) + +#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \ + FTSDMC020_BANK_DDW_X16 | \ + FTSDMC020_BANK_DSZ_256M | \ + FTSDMC020_BANK_MBW_32 | \ + FTSDMC020_BANK_SIZE_64M) + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +/* + * Load address and memory test area should agree with + * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself. + */ +#define CONFIG_SYS_LOAD_ADDR 0x12000000 + +/* memtest works on 63 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x13F00000 + +/*----------------------------------------------------------------------- + * Static memory controller configuration + */ + +#include + +#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ + FTSMC020_BANK_SIZE_1M | \ + FTSMC020_BANK_MBW_8) + +#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \ + FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_2) | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define CONFIG_SYS_FTSMC020_CONFIGS { \ + { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ + { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ +} + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* use CFI framework */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +/* support JEDEC */ +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx8 + +#define PHYS_FLASH_1 0x00000000 +#define PHYS_FLASH_2 0x00400000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, } + +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +#undef CONFIG_SYS_FLASH_EMPTY_INFO + +/* environments */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR 0x00060000 +#define CONFIG_ENV_SIZE 0x20000 + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From 3f12f5217e8bdf8f6842bf1b8c5c5b98425ac3db Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Sat, 21 Nov 2009 13:24:17 -0500 Subject: NAND: Add config option for imx27lite We will get compilation warnings without "CONFIG_SYS_64BIT_VSPRINTF" being defined in the board config. Signed-off-by: Sandeep Paulraj --- include/configs/imx27lite.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/imx27lite.h b/include/configs/imx27lite.h index 8ebb0bbee6..e219cccc95 100644 --- a/include/configs/imx27lite.h +++ b/include/configs/imx27lite.h @@ -156,6 +156,7 @@ #define CONFIG_SYS_NAND_BASE 0xd8000000 #define CONFIG_JFFS2_NAND #define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ /* * SD/MMC -- cgit v1.2.1 From 71636fa7c3de63de29c0f514d5c725eccb011657 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Sun, 29 Nov 2009 17:56:36 -0600 Subject: ARM Update mach-types Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit 3fcca9ac6cbce35b3e81e247d375534117d5f4cd Signed-off-by: Tom Rix --- include/asm-arm/mach-types.h | 481 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 481 insertions(+) (limited to 'include') diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index c7ee24d018..f1f7d932ad 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -1772,6 +1772,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_WDG002 1785 #define MACH_TYPE_SG560ADSL 1786 #define MACH_TYPE_NEXTIO_N2800_ICA 1787 +#define MACH_TYPE_MACH_MARVELL_NEW1 1788 #define MACH_TYPE_MARVELL_NEWDB 1789 #define MACH_TYPE_VANDIHUD 1790 #define MACH_TYPE_MAGX_E8 1791 @@ -2510,6 +2511,42 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_SWARCO_ITC3 2528 #define MACH_TYPE_TX51 2529 #define MACH_TYPE_DOLBY_CAT1021 2530 +#define MACH_TYPE_MX28EVK 2531 +#define MACH_TYPE_PHOENIX260 2532 +#define MACH_TYPE_UVACA_STORK 2533 +#define MACH_TYPE_SMARTQ5 2534 +#define MACH_TYPE_ALL3078 2535 +#define MACH_TYPE_CTERA_2BAY_DS 2536 +#define MACH_TYPE_SIOGENTOO3 2537 +#define MACH_TYPE_EPB5000 2538 +#define MACH_TYPE_HY9263 2539 +#define MACH_TYPE_ACER_TEMPO_M900 2540 +#define MACH_TYPE_ACER_TEMPO_DX900 2541 +#define MACH_TYPE_ACER_TEMPO_X960 2542 +#define MACH_TYPE_ACER_ETEN_V900 2543 +#define MACH_TYPE_ACER_ETEN_X900 2544 +#define MACH_TYPE_BONNELL 2545 +#define MACH_TYPE_OHT_MX27 2546 +#define MACH_TYPE_HTCQUARTZ 2547 +#define MACH_TYPE_DAVINCI_DM6467TEVM 2548 +#define MACH_TYPE_C3AX03 2549 +#define MACH_TYPE_MXT_TD60 2550 +#define MACH_TYPE_ESYX 2551 +#define MACH_TYPE_DOVE_DB 2552 +#define MACH_TYPE_BULLDOG 2553 +#define MACH_TYPE_DERELL_ME2000 2554 +#define MACH_TYPE_BCMRING_BASE 2555 +#define MACH_TYPE_BCMRING_EVM 2556 +#define MACH_TYPE_BCMRING_EVM_JAZZ 2557 +#define MACH_TYPE_BCMRING_SP 2558 +#define MACH_TYPE_BCMRING_SV 2559 +#define MACH_TYPE_BCMRING_SV_JAZZ 2560 +#define MACH_TYPE_BCMRING_TABLET 2561 +#define MACH_TYPE_BCMRING_VP 2562 +#define MACH_TYPE_BCMRING_EVM_SEIKOR 2563 +#define MACH_TYPE_BCMRING_SP_WQVGA 2564 +#define MACH_TYPE_BCMRING_CUSTOM 2565 +#define MACH_TYPE_ACER_S200 2566 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -23631,6 +23668,18 @@ extern unsigned int __machine_arch_type; # define machine_is_nextio_n2800_ica() (0) #endif +#ifdef CONFIG_MACH_MACH_MARVELL_NEW1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MACH_MARVELL_NEW1 +# endif +# define machine_is_dove_db() (machine_arch_type == MACH_TYPE_MACH_MARVELL_NEW1) +#else +# define machine_is_dove_db() (0) +#endif + #ifdef CONFIG_MACH_MARVELL_NEWDB # ifdef machine_arch_type # undef machine_arch_type @@ -32487,6 +32536,438 @@ extern unsigned int __machine_arch_type; # define machine_is_dolby_cat1021() (0) #endif +#ifdef CONFIG_MACH_MX28EVK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX28EVK +# endif +# define machine_is_mx28evk() (machine_arch_type == MACH_TYPE_MX28EVK) +#else +# define machine_is_mx28evk() (0) +#endif + +#ifdef CONFIG_MACH_PHOENIX260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHOENIX260 +# endif +# define machine_is_phoenix260() (machine_arch_type == MACH_TYPE_PHOENIX260) +#else +# define machine_is_phoenix260() (0) +#endif + +#ifdef CONFIG_MACH_UVACA_STORK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UVACA_STORK +# endif +# define machine_is_uvaca_stork() (machine_arch_type == MACH_TYPE_UVACA_STORK) +#else +# define machine_is_uvaca_stork() (0) +#endif + +#ifdef CONFIG_MACH_SMARTQ5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTQ5 +# endif +# define machine_is_smartq5() (machine_arch_type == MACH_TYPE_SMARTQ5) +#else +# define machine_is_smartq5() (0) +#endif + +#ifdef CONFIG_MACH_ALL3078 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ALL3078 +# endif +# define machine_is_all3078() (machine_arch_type == MACH_TYPE_ALL3078) +#else +# define machine_is_all3078() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_2BAY_DS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_2BAY_DS +# endif +# define machine_is_ctera_2bay_ds() (machine_arch_type == MACH_TYPE_CTERA_2BAY_DS) +#else +# define machine_is_ctera_2bay_ds() (0) +#endif + +#ifdef CONFIG_MACH_SIOGENTOO3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIOGENTOO3 +# endif +# define machine_is_siogentoo3() (machine_arch_type == MACH_TYPE_SIOGENTOO3) +#else +# define machine_is_siogentoo3() (0) +#endif + +#ifdef CONFIG_MACH_EPB5000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPB5000 +# endif +# define machine_is_epb5000() (machine_arch_type == MACH_TYPE_EPB5000) +#else +# define machine_is_epb5000() (0) +#endif + +#ifdef CONFIG_MACH_HY9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HY9263 +# endif +# define machine_is_hy9263() (machine_arch_type == MACH_TYPE_HY9263) +#else +# define machine_is_hy9263() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_M900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_M900 +# endif +# define machine_is_acer_tempo_m900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_M900) +#else +# define machine_is_acer_tempo_m900() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_DX900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_DX900 +# endif +# define machine_is_acer_tempo_dx650() (machine_arch_type == MACH_TYPE_ACER_TEMPO_DX900) +#else +# define machine_is_acer_tempo_dx650() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_X960 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_X960 +# endif +# define machine_is_acer_tempo_x960() (machine_arch_type == MACH_TYPE_ACER_TEMPO_X960) +#else +# define machine_is_acer_tempo_x960() (0) +#endif + +#ifdef CONFIG_MACH_ACER_ETEN_V900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_ETEN_V900 +# endif +# define machine_is_acer_eten_v900() (machine_arch_type == MACH_TYPE_ACER_ETEN_V900) +#else +# define machine_is_acer_eten_v900() (0) +#endif + +#ifdef CONFIG_MACH_ACER_ETEN_X900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_ETEN_X900 +# endif +# define machine_is_acer_eten_x900() (machine_arch_type == MACH_TYPE_ACER_ETEN_X900) +#else +# define machine_is_acer_eten_x900() (0) +#endif + +#ifdef CONFIG_MACH_BONNELL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BONNELL +# endif +# define machine_is_bonnell() (machine_arch_type == MACH_TYPE_BONNELL) +#else +# define machine_is_bonnell() (0) +#endif + +#ifdef CONFIG_MACH_OHT_MX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OHT_MX27 +# endif +# define machine_is_oht_mx27() (machine_arch_type == MACH_TYPE_OHT_MX27) +#else +# define machine_is_oht_mx27() (0) +#endif + +#ifdef CONFIG_MACH_HTCQUARTZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCQUARTZ +# endif +# define machine_is_htcquartz() (machine_arch_type == MACH_TYPE_HTCQUARTZ) +#else +# define machine_is_htcquartz() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM6467TEVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM6467TEVM +# endif +# define machine_is_davinci_dm6467tevm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467TEVM) +#else +# define machine_is_davinci_dm6467tevm() (0) +#endif + +#ifdef CONFIG_MACH_C3AX03 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C3AX03 +# endif +# define machine_is_c3ax03() (machine_arch_type == MACH_TYPE_C3AX03) +#else +# define machine_is_c3ax03() (0) +#endif + +#ifdef CONFIG_MACH_MXT_TD60 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXT_TD60 +# endif +# define machine_is_mxt_td60() (machine_arch_type == MACH_TYPE_MXT_TD60) +#else +# define machine_is_mxt_td60() (0) +#endif + +#ifdef CONFIG_MACH_ESYX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESYX +# endif +# define machine_is_esyx() (machine_arch_type == MACH_TYPE_ESYX) +#else +# define machine_is_esyx() (0) +#endif + +#ifdef CONFIG_MACH_DOVE_DB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOVE_DB +# endif +# define machine_is_dove_db2() (machine_arch_type == MACH_TYPE_DOVE_DB) +#else +# define machine_is_dove_db2() (0) +#endif + +#ifdef CONFIG_MACH_BULLDOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BULLDOG +# endif +# define machine_is_bulldog() (machine_arch_type == MACH_TYPE_BULLDOG) +#else +# define machine_is_bulldog() (0) +#endif + +#ifdef CONFIG_MACH_DERELL_ME2000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DERELL_ME2000 +# endif +# define machine_is_derell_me2000() (machine_arch_type == MACH_TYPE_DERELL_ME2000) +#else +# define machine_is_derell_me2000() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_BASE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_BASE +# endif +# define machine_is_bcmring_base() (machine_arch_type == MACH_TYPE_BCMRING_BASE) +#else +# define machine_is_bcmring_base() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_EVM +# endif +# define machine_is_bcmring_evm() (machine_arch_type == MACH_TYPE_BCMRING_EVM) +#else +# define machine_is_bcmring_evm() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_EVM_JAZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_EVM_JAZZ +# endif +# define machine_is_bcmring_evm_jazz() (machine_arch_type == MACH_TYPE_BCMRING_EVM_JAZZ) +#else +# define machine_is_bcmring_evm_jazz() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SP +# endif +# define machine_is_bcmring_sp() (machine_arch_type == MACH_TYPE_BCMRING_SP) +#else +# define machine_is_bcmring_sp() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SV +# endif +# define machine_is_bcmring_sv() (machine_arch_type == MACH_TYPE_BCMRING_SV) +#else +# define machine_is_bcmring_sv() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SV_JAZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SV_JAZZ +# endif +# define machine_is_bcmring_sv_jazz() (machine_arch_type == MACH_TYPE_BCMRING_SV_JAZZ) +#else +# define machine_is_bcmring_sv_jazz() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_TABLET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_TABLET +# endif +# define machine_is_bcmring_tablet() (machine_arch_type == MACH_TYPE_BCMRING_TABLET) +#else +# define machine_is_bcmring_tablet() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_VP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_VP +# endif +# define machine_is_bcmring_vp() (machine_arch_type == MACH_TYPE_BCMRING_VP) +#else +# define machine_is_bcmring_vp() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_EVM_SEIKOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_EVM_SEIKOR +# endif +# define machine_is_bcmring_evm_seikor() (machine_arch_type == MACH_TYPE_BCMRING_EVM_SEIKOR) +#else +# define machine_is_bcmring_evm_seikor() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SP_WQVGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SP_WQVGA +# endif +# define machine_is_bcmring_sp_wqvga() (machine_arch_type == MACH_TYPE_BCMRING_SP_WQVGA) +#else +# define machine_is_bcmring_sp_wqvga() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_CUSTOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_CUSTOM +# endif +# define machine_is_bcmring_custom() (machine_arch_type == MACH_TYPE_BCMRING_CUSTOM) +#else +# define machine_is_bcmring_custom() (0) +#endif + +#ifdef CONFIG_MACH_ACER_S200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_S200 +# endif +# define machine_is_acer_s200() (machine_arch_type == MACH_TYPE_ACER_S200) +#else +# define machine_is_acer_s200() (0) +#endif + /* * These have not yet been registered */ -- cgit v1.2.1