From 0d79f4f490352f6e1500cdd12a3b0e8b17265bde Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 18 Jul 2013 12:13:40 -0700 Subject: ARM: tegra: Make cache line size SoC specific Currently all Tegra SoCs are assumed to have 32 byte cache lines. This isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and therefore uses a cache line size of 64 bytes. Move the cache line size setting to the per-SoC common configuration file. Signed-off-by: Thierry Reding Tested-by: Stephen Warren Reviewed-by: Stephen Warren Signed-off-by: Tom Warren --- include/configs/tegra-common.h | 2 -- include/configs/tegra114-common.h | 3 +++ include/configs/tegra20-common.h | 3 +++ include/configs/tegra30-common.h | 3 +++ 4 files changed, 9 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index ccd68a19fd..0aac14e1c3 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -17,8 +17,6 @@ #define CONFIG_TEGRA /* which is a Tegra generic machine */ #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - #include /* get chip and board defs */ /* diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 44e98e5019..c3de9a999e 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -18,6 +18,9 @@ #define _TEGRA114_COMMON_H_ #include "tegra-common.h" +/* Cortex-A15 uses a cache line size of 64 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* * NS16550 Configuration */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index d5e9ee4062..b009a316b1 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -9,6 +9,9 @@ #define _TEGRA20_COMMON_H_ #include "tegra-common.h" +/* Cortex-A9 uses a cache line size of 32 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* * Errata configuration */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 5ac8816504..99acbfd28b 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -9,6 +9,9 @@ #define _TEGRA30_COMMON_H_ #include "tegra-common.h" +/* Cortex-A9 uses a cache line size of 32 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* * Errata configuration */ -- cgit v1.2.1 From e94f0af969f8832fe9acd1af91fa08b88facbd58 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 18 Jul 2013 12:13:41 -0700 Subject: ARM: tegra: Enable data cache on Dalmore Disabling the data cache is no longer required to boot Dalmore, so enable it. This results in notably better performance when loading and booting the Linux kernel. Signed-off-by: Thierry Reding Signed-off-by: Tom Warren --- include/configs/dalmore.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 145e7ac926..bdf012b2b8 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -21,9 +21,6 @@ #include "tegra114-common.h" -/* Must be off for Dalmore to boot !?!? FIXME */ -#define CONFIG_SYS_DCACHE_OFF - /* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */ #define CONFIG_DEFAULT_DEVICE_TREE tegra114-dalmore #define CONFIG_OF_CONTROL -- cgit v1.2.1 From 8258c126143034bef2e35e01b2e14f2d90a7e0b5 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 14 Aug 2013 10:05:33 -0600 Subject: ARM: tegra: support raw ramdisks This way, we don't have to run mkimage on them. Signed-off-by: Stephen Warren Acked-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/tegra-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 0aac14e1c3..ba6c6bb9f5 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -133,6 +133,7 @@ #define CONFIG_CMD_GPIO #define CONFIG_CMD_ENTERRCM #define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD /* Defines for SPL */ #define CONFIG_SPL -- cgit v1.2.1