From b03a466d6ceb9dbfd1a1638f355e9c8b4833259f Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 1 Feb 2011 15:55:58 +0000 Subject: powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Kumar Gala --- include/pci.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/pci.h') diff --git a/include/pci.h b/include/pci.h index c6b264bdb5..1284c427b5 100644 --- a/include/pci.h +++ b/include/pci.h @@ -306,6 +306,7 @@ #define PCI_DCR 0x54 /* PCIe Device Control Register */ #define PCI_DSR 0x56 /* PCIe Device Status Register */ #define PCI_LSR 0x5e /* PCIe Link Status Register */ +#define PCI_LCR 0x5c /* PCIe Link Control Register */ #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ #define PCI_LTSSM_L0 0x16 /* L0 state */ -- cgit v1.2.1