From 32c8cfb23cd8beb814edd217c02e6aa5c7a64acf Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Wed, 9 Feb 2011 09:24:10 +0530 Subject: fsl_esdhc: Deal with watermark level register related changes P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain Signed-off-by: Poonam Aggrwal Tested-by: Stefano Babic Signed-off-by: Kumar Gala --- include/fsl_esdhc.h | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'include/fsl_esdhc.h') diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 477bbd792e..8418bf7f47 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -2,7 +2,7 @@ * FSL SD/MMC Defines *------------------------------------------------------------------- * - * Copyright 2007-2008,2010 Freescale Semiconductor, Inc + * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -135,8 +135,21 @@ #define WML 0x2e044 #define WML_WRITE 0x00010000 +#ifdef CONFIG_FSL_SDHC_V2_3 +#define WML_RD_WML_MAX 0x80 +#define WML_WR_WML_MAX 0x80 +#define WML_RD_WML_MAX_VAL 0x0 +#define WML_WR_WML_MAX_VAL 0x0 +#define WML_RD_WML_MASK 0x7f +#define WML_WR_WML_MASK 0x7f0000 +#else +#define WML_RD_WML_MAX 0x10 +#define WML_WR_WML_MAX 0x80 +#define WML_RD_WML_MAX_VAL 0x10 +#define WML_WR_WML_MAX_VAL 0x80 #define WML_RD_WML_MASK 0xff #define WML_WR_WML_MASK 0xff0000 +#endif #define BLKATTR 0x2e004 #define BLKATTR_CNT(x) ((x & 0xffff) << 16) -- cgit v1.2.1