From c0391111c33c22fabeddf8f4ca801ec7645b4f5c Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Sat, 27 Sep 2008 14:40:57 +0800 Subject: Fix the incorrect DDR clk freq reporting on 8536DS On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by: Jason Jin --- include/configs/MPC8536DS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 2578bef278..0d65b206ba 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -59,7 +59,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ -/* #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /\* ddrclk for MPC85xx *\/ FIXME-8536*/ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq from ICS307 instead of switches */ -- cgit v1.2.1