From 4d5723da57344cc8f41324fb18b039fb2ce83428 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 07:01:00 -0600 Subject: powerpc/85xx: Rework P2020DS pci_init_board to use common FSL PCIe code Remove duplicated code in P2020DS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Li Yang Signed-off-by: Kumar Gala --- include/configs/P2020DS.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/configs/P2020DS.h') diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 0af21528d9..24f2498d07 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -394,6 +394,7 @@ */ /* controller 3, Slot 1, tgtid 3, Base address b000 */ +#define CONFIG_SYS_PCIE3_NAME "Slot 1" #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 @@ -413,6 +414,7 @@ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "ULI" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 @@ -432,6 +434,7 @@ #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "Slot 2" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -- cgit v1.2.1